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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json
....@@ -1,284 +1,284 @@
11 [
22     {
3
-        "EventCode": "0x08",
4
-        "UMask": "0x1",
5
-        "BriefDescription": "Load misses in all DTLB levels that cause page walks",
3
+        "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
64         "Counter": "0,1,2,3",
7
-        "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
8
-        "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
5
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
6
+        "EventCode": "0x85",
7
+        "EventName": "ITLB_MISSES.STLB_HIT",
98         "SampleAfterValue": "100003",
10
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
9
+        "UMask": "0x20"
1110     },
1211     {
13
-        "EventCode": "0x08",
14
-        "UMask": "0x2",
15
-        "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
16
-        "Counter": "0,1,2,3",
17
-        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
18
-        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
19
-        "SampleAfterValue": "2000003",
20
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
21
-    },
22
-    {
23
-        "EventCode": "0x08",
24
-        "UMask": "0x4",
25
-        "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
26
-        "Counter": "0,1,2,3",
27
-        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
28
-        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page fault.",
29
-        "SampleAfterValue": "2000003",
30
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
31
-    },
32
-    {
33
-        "EventCode": "0x08",
34
-        "UMask": "0x8",
35
-        "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
36
-        "Counter": "0,1,2,3",
37
-        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
38
-        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
39
-        "SampleAfterValue": "2000003",
40
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
41
-    },
42
-    {
43
-        "EventCode": "0x08",
44
-        "UMask": "0xe",
45
-        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
46
-        "Counter": "0,1,2,3",
47
-        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
48
-        "PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
49
-        "SampleAfterValue": "100003",
50
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
51
-    },
52
-    {
53
-        "EventCode": "0x08",
54
-        "UMask": "0x10",
55
-        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
56
-        "Counter": "0,1,2,3",
57
-        "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
58
-        "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
59
-        "SampleAfterValue": "2000003",
60
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
61
-    },
62
-    {
63
-        "EventCode": "0x08",
64
-        "UMask": "0x10",
65
-        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
66
-        "Counter": "0,1,2,3",
67
-        "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
68
-        "CounterMask": "1",
69
-        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
70
-        "SampleAfterValue": "100003",
71
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
72
-    },
73
-    {
74
-        "EventCode": "0x08",
75
-        "UMask": "0x20",
76
-        "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
77
-        "Counter": "0,1,2,3",
78
-        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
79
-        "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
80
-        "SampleAfterValue": "2000003",
81
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
82
-    },
83
-    {
84
-        "EventCode": "0x49",
85
-        "UMask": "0x1",
8612         "BriefDescription": "Store misses in all DTLB levels that cause page walks",
8713         "Counter": "0,1,2,3",
14
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
15
+        "EventCode": "0x49",
8816         "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
8917         "PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
9018         "SampleAfterValue": "100003",
91
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
19
+        "UMask": "0x1"
9220     },
9321     {
94
-        "EventCode": "0x49",
95
-        "UMask": "0x2",
96
-        "BriefDescription": "Page walk completed due to a demand data store to a 4K page",
97
-        "Counter": "0,1,2,3",
98
-        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
99
-        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
100
-        "SampleAfterValue": "100003",
101
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
102
-    },
103
-    {
104
-        "EventCode": "0x49",
105
-        "UMask": "0x4",
10622         "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
10723         "Counter": "0,1,2,3",
24
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
25
+        "EventCode": "0x49",
10826         "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
10927         "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page fault.",
11028         "SampleAfterValue": "100003",
111
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
29
+        "UMask": "0x4"
11230     },
11331     {
114
-        "EventCode": "0x49",
115
-        "UMask": "0x8",
116
-        "BriefDescription": "Page walk completed due to a demand data store to a 1G page",
117
-        "Counter": "0,1,2,3",
118
-        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
119
-        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages.  The page walks can end with or without a page fault.",
120
-        "SampleAfterValue": "100003",
121
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
122
-    },
123
-    {
124
-        "EventCode": "0x49",
125
-        "UMask": "0xe",
126
-        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
127
-        "Counter": "0,1,2,3",
128
-        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
129
-        "PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
130
-        "SampleAfterValue": "100003",
131
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
132
-    },
133
-    {
134
-        "EventCode": "0x49",
135
-        "UMask": "0x10",
136
-        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
137
-        "Counter": "0,1,2,3",
138
-        "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
139
-        "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
140
-        "SampleAfterValue": "2000003",
141
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
142
-    },
143
-    {
144
-        "EventCode": "0x49",
145
-        "UMask": "0x10",
146
-        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
147
-        "Counter": "0,1,2,3",
148
-        "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
149
-        "CounterMask": "1",
150
-        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
151
-        "SampleAfterValue": "100003",
152
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
153
-    },
154
-    {
155
-        "EventCode": "0x49",
156
-        "UMask": "0x20",
157
-        "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
158
-        "Counter": "0,1,2,3",
159
-        "EventName": "DTLB_STORE_MISSES.STLB_HIT",
160
-        "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
161
-        "SampleAfterValue": "100003",
162
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
163
-    },
164
-    {
165
-        "EventCode": "0x4F",
166
-        "UMask": "0x10",
167
-        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
168
-        "Counter": "0,1,2,3",
169
-        "EventName": "EPT.WALK_PENDING",
170
-        "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
171
-        "SampleAfterValue": "2000003",
172
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
173
-    },
174
-    {
175
-        "EventCode": "0x85",
176
-        "UMask": "0x1",
177
-        "BriefDescription": "Misses at all ITLB levels that cause page walks",
178
-        "Counter": "0,1,2,3",
179
-        "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
180
-        "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
181
-        "SampleAfterValue": "100003",
182
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
183
-    },
184
-    {
185
-        "EventCode": "0x85",
186
-        "UMask": "0x2",
187
-        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
188
-        "Counter": "0,1,2,3",
189
-        "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
190
-        "PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
191
-        "SampleAfterValue": "100003",
192
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
193
-    },
194
-    {
195
-        "EventCode": "0x85",
196
-        "UMask": "0x4",
197
-        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
198
-        "Counter": "0,1,2,3",
199
-        "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
200
-        "PublicDescription": "Counts code misses in all ITLB levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
201
-        "SampleAfterValue": "100003",
202
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
203
-    },
204
-    {
205
-        "EventCode": "0x85",
206
-        "UMask": "0x8",
207
-        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
208
-        "Counter": "0,1,2,3",
209
-        "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
210
-        "PublicDescription": "Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
211
-        "SampleAfterValue": "100003",
212
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
213
-    },
214
-    {
215
-        "EventCode": "0x85",
216
-        "UMask": "0xe",
217
-        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
218
-        "Counter": "0,1,2,3",
219
-        "EventName": "ITLB_MISSES.WALK_COMPLETED",
220
-        "PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
221
-        "SampleAfterValue": "100003",
222
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
223
-    },
224
-    {
225
-        "EventCode": "0x85",
226
-        "UMask": "0x10",
22732         "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
22833         "Counter": "0,1,2,3",
34
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
35
+        "EventCode": "0x85",
22936         "EventName": "ITLB_MISSES.WALK_PENDING",
23037         "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
23138         "SampleAfterValue": "100003",
232
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
39
+        "UMask": "0x10"
23340     },
23441     {
235
-        "EventCode": "0x85",
236
-        "UMask": "0x10",
237
-        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
42
+        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
23843         "Counter": "0,1,2,3",
239
-        "EventName": "ITLB_MISSES.WALK_ACTIVE",
240
-        "CounterMask": "1",
241
-        "PublicDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture.",
242
-        "SampleAfterValue": "100003",
243
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
244
-    },
245
-    {
44
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
24645         "EventCode": "0x85",
247
-        "UMask": "0x20",
248
-        "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
249
-        "Counter": "0,1,2,3",
250
-        "EventName": "ITLB_MISSES.STLB_HIT",
46
+        "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
47
+        "PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
25148         "SampleAfterValue": "100003",
252
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
49
+        "UMask": "0x2"
25350     },
25451     {
255
-        "EventCode": "0xAE",
256
-        "UMask": "0x1",
25752         "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
25853         "Counter": "0,1,2,3",
54
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
55
+        "EventCode": "0xAE",
25956         "EventName": "ITLB.ITLB_FLUSH",
26057         "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
26158         "SampleAfterValue": "100007",
262
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
59
+        "UMask": "0x1"
26360     },
26461     {
265
-        "EventCode": "0xBD",
266
-        "UMask": "0x1",
62
+        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
63
+        "Counter": "0,1,2,3",
64
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
65
+        "CounterMask": "1",
66
+        "EventCode": "0x85",
67
+        "EventName": "ITLB_MISSES.WALK_ACTIVE",
68
+        "PublicDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture.",
69
+        "SampleAfterValue": "100003",
70
+        "UMask": "0x10"
71
+    },
72
+    {
73
+        "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
74
+        "Counter": "0,1,2,3",
75
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
76
+        "EventCode": "0x08",
77
+        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
78
+        "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
79
+        "SampleAfterValue": "2000003",
80
+        "UMask": "0x20"
81
+    },
82
+    {
83
+        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
84
+        "Counter": "0,1,2,3",
85
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
86
+        "EventCode": "0x49",
87
+        "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
88
+        "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
89
+        "SampleAfterValue": "2000003",
90
+        "UMask": "0x10"
91
+    },
92
+    {
26793         "BriefDescription": "DTLB flush attempts of the thread-specific entries",
26894         "Counter": "0,1,2,3",
95
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
96
+        "EventCode": "0xBD",
26997         "EventName": "TLB_FLUSH.DTLB_THREAD",
27098         "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
27199         "SampleAfterValue": "100007",
272
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
100
+        "UMask": "0x1"
273101     },
274102     {
275
-        "EventCode": "0xBD",
276
-        "UMask": "0x20",
103
+        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
104
+        "Counter": "0,1,2,3",
105
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
106
+        "EventCode": "0x08",
107
+        "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
108
+        "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
109
+        "SampleAfterValue": "2000003",
110
+        "UMask": "0x10"
111
+    },
112
+    {
113
+        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
114
+        "Counter": "0,1,2,3",
115
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
116
+        "CounterMask": "1",
117
+        "EventCode": "0x49",
118
+        "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
119
+        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
120
+        "SampleAfterValue": "100003",
121
+        "UMask": "0x10"
122
+    },
123
+    {
124
+        "BriefDescription": "Misses at all ITLB levels that cause page walks",
125
+        "Counter": "0,1,2,3",
126
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
127
+        "EventCode": "0x85",
128
+        "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
129
+        "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
130
+        "SampleAfterValue": "100003",
131
+        "UMask": "0x1"
132
+    },
133
+    {
134
+        "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
135
+        "Counter": "0,1,2,3",
136
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
137
+        "EventCode": "0x49",
138
+        "EventName": "DTLB_STORE_MISSES.STLB_HIT",
139
+        "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
140
+        "SampleAfterValue": "100003",
141
+        "UMask": "0x20"
142
+    },
143
+    {
144
+        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
145
+        "Counter": "0,1,2,3",
146
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
147
+        "EventCode": "0x49",
148
+        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
149
+        "PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
150
+        "SampleAfterValue": "100003",
151
+        "UMask": "0xe"
152
+    },
153
+    {
154
+        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
155
+        "Counter": "0,1,2,3",
156
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
157
+        "EventCode": "0x08",
158
+        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
159
+        "PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
160
+        "SampleAfterValue": "100003",
161
+        "UMask": "0xe"
162
+    },
163
+    {
164
+        "BriefDescription": "Page walk completed due to a demand data store to a 4K page",
165
+        "Counter": "0,1,2,3",
166
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
167
+        "EventCode": "0x49",
168
+        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
169
+        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
170
+        "SampleAfterValue": "100003",
171
+        "UMask": "0x2"
172
+    },
173
+    {
174
+        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
175
+        "Counter": "0,1,2,3",
176
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
177
+        "EventCode": "0x85",
178
+        "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
179
+        "PublicDescription": "Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
180
+        "SampleAfterValue": "100003",
181
+        "UMask": "0x8"
182
+    },
183
+    {
184
+        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
185
+        "Counter": "0,1,2,3",
186
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
187
+        "EventCode": "0x85",
188
+        "EventName": "ITLB_MISSES.WALK_COMPLETED",
189
+        "PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
190
+        "SampleAfterValue": "100003",
191
+        "UMask": "0xe"
192
+    },
193
+    {
194
+        "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
195
+        "Counter": "0,1,2,3",
196
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
197
+        "EventCode": "0x08",
198
+        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
199
+        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
200
+        "SampleAfterValue": "2000003",
201
+        "UMask": "0x2"
202
+    },
203
+    {
204
+        "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
205
+        "Counter": "0,1,2,3",
206
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
207
+        "EventCode": "0x08",
208
+        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
209
+        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page fault.",
210
+        "SampleAfterValue": "2000003",
211
+        "UMask": "0x4"
212
+    },
213
+    {
214
+        "BriefDescription": "Load misses in all DTLB levels that cause page walks",
215
+        "Counter": "0,1,2,3",
216
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
217
+        "EventCode": "0x08",
218
+        "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
219
+        "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
220
+        "SampleAfterValue": "100003",
221
+        "UMask": "0x1"
222
+    },
223
+    {
224
+        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
225
+        "Counter": "0,1,2,3",
226
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
227
+        "EventCode": "0x4F",
228
+        "EventName": "EPT.WALK_PENDING",
229
+        "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
230
+        "SampleAfterValue": "2000003",
231
+        "UMask": "0x10"
232
+    },
233
+    {
277234         "BriefDescription": "STLB flush attempts",
278235         "Counter": "0,1,2,3",
236
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
237
+        "EventCode": "0xBD",
279238         "EventName": "TLB_FLUSH.STLB_ANY",
280239         "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
281240         "SampleAfterValue": "100007",
282
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
241
+        "UMask": "0x20"
242
+    },
243
+    {
244
+        "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
245
+        "Counter": "0,1,2,3",
246
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
247
+        "EventCode": "0x08",
248
+        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
249
+        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
250
+        "SampleAfterValue": "2000003",
251
+        "UMask": "0x8"
252
+    },
253
+    {
254
+        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
255
+        "Counter": "0,1,2,3",
256
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
257
+        "CounterMask": "1",
258
+        "EventCode": "0x08",
259
+        "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
260
+        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
261
+        "SampleAfterValue": "100003",
262
+        "UMask": "0x10"
263
+    },
264
+    {
265
+        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
266
+        "Counter": "0,1,2,3",
267
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
268
+        "EventCode": "0x85",
269
+        "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
270
+        "PublicDescription": "Counts code misses in all ITLB levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
271
+        "SampleAfterValue": "100003",
272
+        "UMask": "0x4"
273
+    },
274
+    {
275
+        "BriefDescription": "Page walk completed due to a demand data store to a 1G page",
276
+        "Counter": "0,1,2,3",
277
+        "CounterHTOff": "0,1,2,3,4,5,6,7",
278
+        "EventCode": "0x49",
279
+        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
280
+        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages.  The page walks can end with or without a page fault.",
281
+        "SampleAfterValue": "100003",
282
+        "UMask": "0x8"
283283     }
284284 ]