~hc/RK356X_SDK_RELEASE.git

..	..	@@ -215,7 +215,7 @@
215	215	"UMask": "0x4",
216	216	"EventName": "HLE_RETIRED.ABORTED",
217	217	"SampleAfterValue": "2000003",
218		- "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ",
	218	+ "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
219	219	"CounterHTOff": "0,1,2,3,4,5,6,7"
220	220	},
221	221	{
..	..	@@ -237,6 +237,7 @@
237	237	"CounterHTOff": "0,1,2,3,4,5,6,7"
238	238	},
239	239	{
	240	+ "PublicDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
240	241	"EventCode": "0xC8",
241	242	"Counter": "0,1,2,3",
242	243	"UMask": "0x20",
..	..	@@ -292,7 +293,7 @@
292	293	"UMask": "0x4",
293	294	"EventName": "RTM_RETIRED.ABORTED",
294	295	"SampleAfterValue": "2000003",
295		- "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ",
	296	+ "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
296	297	"CounterHTOff": "0,1,2,3,4,5,6,7"
297	298	},
298	299	{
..	..	@@ -346,7 +347,7 @@
346	347	},
347	348	{
348	349	"PEBS": "2",
349		- "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
	350	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
350	351	"EventCode": "0xCD",
351	352	"MSRValue": "0x4",
352	353	"Counter": "0,1,2,3",
..	..	@@ -354,13 +355,13 @@
354	355	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
355	356	"MSRIndex": "0x3F6",
356	357	"SampleAfterValue": "100003",
357		- "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles.",
	358	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
358	359	"TakenAlone": "1",
359	360	"CounterHTOff": "0,1,2,3"
360	361	},
361	362	{
362	363	"PEBS": "2",
363		- "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
	364	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
364	365	"EventCode": "0xCD",
365	366	"MSRValue": "0x8",
366	367	"Counter": "0,1,2,3",
..	..	@@ -368,13 +369,13 @@
368	369	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
369	370	"MSRIndex": "0x3F6",
370	371	"SampleAfterValue": "50021",
371		- "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles.",
	372	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
372	373	"TakenAlone": "1",
373	374	"CounterHTOff": "0,1,2,3"
374	375	},
375	376	{
376	377	"PEBS": "2",
377		- "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
	378	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
378	379	"EventCode": "0xCD",
379	380	"MSRValue": "0x10",
380	381	"Counter": "0,1,2,3",
..	..	@@ -382,13 +383,13 @@
382	383	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
383	384	"MSRIndex": "0x3F6",
384	385	"SampleAfterValue": "20011",
385		- "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles.",
	386	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
386	387	"TakenAlone": "1",
387	388	"CounterHTOff": "0,1,2,3"
388	389	},
389	390	{
390	391	"PEBS": "2",
391		- "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
	392	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
392	393	"EventCode": "0xCD",
393	394	"MSRValue": "0x20",
394	395	"Counter": "0,1,2,3",
..	..	@@ -396,13 +397,13 @@
396	397	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
397	398	"MSRIndex": "0x3F6",
398	399	"SampleAfterValue": "100007",
399		- "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles.",
	400	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
400	401	"TakenAlone": "1",
401	402	"CounterHTOff": "0,1,2,3"
402	403	},
403	404	{
404	405	"PEBS": "2",
405		- "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
	406	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
406	407	"EventCode": "0xCD",
407	408	"MSRValue": "0x40",
408	409	"Counter": "0,1,2,3",
..	..	@@ -410,13 +411,13 @@
410	411	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
411	412	"MSRIndex": "0x3F6",
412	413	"SampleAfterValue": "2003",
413		- "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles.",
	414	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
414	415	"TakenAlone": "1",
415	416	"CounterHTOff": "0,1,2,3"
416	417	},
417	418	{
418	419	"PEBS": "2",
419		- "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
	420	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
420	421	"EventCode": "0xCD",
421	422	"MSRValue": "0x80",
422	423	"Counter": "0,1,2,3",
..	..	@@ -424,13 +425,13 @@
424	425	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
425	426	"MSRIndex": "0x3F6",
426	427	"SampleAfterValue": "1009",
427		- "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles.",
	428	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
428	429	"TakenAlone": "1",
429	430	"CounterHTOff": "0,1,2,3"
430	431	},
431	432	{
432	433	"PEBS": "2",
433		- "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
	434	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
434	435	"EventCode": "0xCD",
435	436	"MSRValue": "0x100",
436	437	"Counter": "0,1,2,3",
..	..	@@ -438,13 +439,13 @@
438	439	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
439	440	"MSRIndex": "0x3F6",
440	441	"SampleAfterValue": "503",
441		- "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles.",
	442	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
442	443	"TakenAlone": "1",
443	444	"CounterHTOff": "0,1,2,3"
444	445	},
445	446	{
446	447	"PEBS": "2",
447		- "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
	448	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
448	449	"EventCode": "0xCD",
449	450	"MSRValue": "0x200",
450	451	"Counter": "0,1,2,3",
..	..	@@ -452,163 +453,1151 @@
452	453	"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
453	454	"MSRIndex": "0x3F6",
454	455	"SampleAfterValue": "101",
455		- "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles.",
	456	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
456	457	"TakenAlone": "1",
457	458	"CounterHTOff": "0,1,2,3"
458	459	},
459	460	{
460		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	461	+ "PublicDescription": "Counts any other requests",
461	462	"EventCode": "0xB7, 0xBB",
462		- "MSRValue": "0x3ffc000001 ",
	463	+ "MSRValue": "0x3FFC408000",
	464	+ "Counter": "0,1,2,3",
	465	+ "UMask": "0x1",
	466	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",
	467	+ "MSRIndex": "0x1a6, 0x1a7",
	468	+ "SampleAfterValue": "100003",
	469	+ "BriefDescription": "Counts any other requests",
	470	+ "Offcore": "1",
	471	+ "CounterHTOff": "0,1,2,3"
	472	+ },
	473	+ {
	474	+ "PublicDescription": "Counts any other requests",
	475	+ "EventCode": "0xB7, 0xBB",
	476	+ "MSRValue": "0x203C408000",
	477	+ "Counter": "0,1,2,3",
	478	+ "UMask": "0x1",
	479	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM",
	480	+ "MSRIndex": "0x1a6, 0x1a7",
	481	+ "SampleAfterValue": "100003",
	482	+ "BriefDescription": "Counts any other requests",
	483	+ "Offcore": "1",
	484	+ "CounterHTOff": "0,1,2,3"
	485	+ },
	486	+ {
	487	+ "PublicDescription": "Counts any other requests",
	488	+ "EventCode": "0xB7, 0xBB",
	489	+ "MSRValue": "0x103C408000",
	490	+ "Counter": "0,1,2,3",
	491	+ "UMask": "0x1",
	492	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM",
	493	+ "MSRIndex": "0x1a6, 0x1a7",
	494	+ "SampleAfterValue": "100003",
	495	+ "BriefDescription": "Counts any other requests",
	496	+ "Offcore": "1",
	497	+ "CounterHTOff": "0,1,2,3"
	498	+ },
	499	+ {
	500	+ "PublicDescription": "Counts any other requests",
	501	+ "EventCode": "0xB7, 0xBB",
	502	+ "MSRValue": "0x043C408000",
	503	+ "Counter": "0,1,2,3",
	504	+ "UMask": "0x1",
	505	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",
	506	+ "MSRIndex": "0x1a6, 0x1a7",
	507	+ "SampleAfterValue": "100003",
	508	+ "BriefDescription": "Counts any other requests",
	509	+ "Offcore": "1",
	510	+ "CounterHTOff": "0,1,2,3"
	511	+ },
	512	+ {
	513	+ "PublicDescription": "Counts any other requests",
	514	+ "EventCode": "0xB7, 0xBB",
	515	+ "MSRValue": "0x023C408000",
	516	+ "Counter": "0,1,2,3",
	517	+ "UMask": "0x1",
	518	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
	519	+ "MSRIndex": "0x1a6, 0x1a7",
	520	+ "SampleAfterValue": "100003",
	521	+ "BriefDescription": "Counts any other requests",
	522	+ "Offcore": "1",
	523	+ "CounterHTOff": "0,1,2,3"
	524	+ },
	525	+ {
	526	+ "PublicDescription": "Counts any other requests",
	527	+ "EventCode": "0xB7, 0xBB",
	528	+ "MSRValue": "0x013C408000",
	529	+ "Counter": "0,1,2,3",
	530	+ "UMask": "0x1",
	531	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",
	532	+ "MSRIndex": "0x1a6, 0x1a7",
	533	+ "SampleAfterValue": "100003",
	534	+ "BriefDescription": "Counts any other requests",
	535	+ "Offcore": "1",
	536	+ "CounterHTOff": "0,1,2,3"
	537	+ },
	538	+ {
	539	+ "PublicDescription": "Counts any other requests",
	540	+ "EventCode": "0xB7, 0xBB",
	541	+ "MSRValue": "0x00BC408000",
	542	+ "Counter": "0,1,2,3",
	543	+ "UMask": "0x1",
	544	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
	545	+ "MSRIndex": "0x1a6, 0x1a7",
	546	+ "SampleAfterValue": "100003",
	547	+ "BriefDescription": "Counts any other requests",
	548	+ "Offcore": "1",
	549	+ "CounterHTOff": "0,1,2,3"
	550	+ },
	551	+ {
	552	+ "PublicDescription": "Counts any other requests",
	553	+ "EventCode": "0xB7, 0xBB",
	554	+ "MSRValue": "0x007C408000",
	555	+ "Counter": "0,1,2,3",
	556	+ "UMask": "0x1",
	557	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT",
	558	+ "MSRIndex": "0x1a6, 0x1a7",
	559	+ "SampleAfterValue": "100003",
	560	+ "BriefDescription": "Counts any other requests",
	561	+ "Offcore": "1",
	562	+ "CounterHTOff": "0,1,2,3"
	563	+ },
	564	+ {
	565	+ "PublicDescription": "Counts any other requests",
	566	+ "EventCode": "0xB7, 0xBB",
	567	+ "MSRValue": "0x3FC4008000",
	568	+ "Counter": "0,1,2,3",
	569	+ "UMask": "0x1",
	570	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
	571	+ "MSRIndex": "0x1a6, 0x1a7",
	572	+ "SampleAfterValue": "100003",
	573	+ "BriefDescription": "Counts any other requests",
	574	+ "Offcore": "1",
	575	+ "CounterHTOff": "0,1,2,3"
	576	+ },
	577	+ {
	578	+ "PublicDescription": "Counts any other requests",
	579	+ "EventCode": "0xB7, 0xBB",
	580	+ "MSRValue": "0x2004008000",
	581	+ "Counter": "0,1,2,3",
	582	+ "UMask": "0x1",
	583	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
	584	+ "MSRIndex": "0x1a6, 0x1a7",
	585	+ "SampleAfterValue": "100003",
	586	+ "BriefDescription": "Counts any other requests",
	587	+ "Offcore": "1",
	588	+ "CounterHTOff": "0,1,2,3"
	589	+ },
	590	+ {
	591	+ "PublicDescription": "Counts any other requests",
	592	+ "EventCode": "0xB7, 0xBB",
	593	+ "MSRValue": "0x1004008000",
	594	+ "Counter": "0,1,2,3",
	595	+ "UMask": "0x1",
	596	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
	597	+ "MSRIndex": "0x1a6, 0x1a7",
	598	+ "SampleAfterValue": "100003",
	599	+ "BriefDescription": "Counts any other requests",
	600	+ "Offcore": "1",
	601	+ "CounterHTOff": "0,1,2,3"
	602	+ },
	603	+ {
	604	+ "PublicDescription": "Counts any other requests",
	605	+ "EventCode": "0xB7, 0xBB",
	606	+ "MSRValue": "0x0404008000",
	607	+ "Counter": "0,1,2,3",
	608	+ "UMask": "0x1",
	609	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
	610	+ "MSRIndex": "0x1a6, 0x1a7",
	611	+ "SampleAfterValue": "100003",
	612	+ "BriefDescription": "Counts any other requests",
	613	+ "Offcore": "1",
	614	+ "CounterHTOff": "0,1,2,3"
	615	+ },
	616	+ {
	617	+ "PublicDescription": "Counts any other requests",
	618	+ "EventCode": "0xB7, 0xBB",
	619	+ "MSRValue": "0x0204008000",
	620	+ "Counter": "0,1,2,3",
	621	+ "UMask": "0x1",
	622	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
	623	+ "MSRIndex": "0x1a6, 0x1a7",
	624	+ "SampleAfterValue": "100003",
	625	+ "BriefDescription": "Counts any other requests",
	626	+ "Offcore": "1",
	627	+ "CounterHTOff": "0,1,2,3"
	628	+ },
	629	+ {
	630	+ "PublicDescription": "Counts any other requests",
	631	+ "EventCode": "0xB7, 0xBB",
	632	+ "MSRValue": "0x0104008000",
	633	+ "Counter": "0,1,2,3",
	634	+ "UMask": "0x1",
	635	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
	636	+ "MSRIndex": "0x1a6, 0x1a7",
	637	+ "SampleAfterValue": "100003",
	638	+ "BriefDescription": "Counts any other requests",
	639	+ "Offcore": "1",
	640	+ "CounterHTOff": "0,1,2,3"
	641	+ },
	642	+ {
	643	+ "PublicDescription": "Counts any other requests",
	644	+ "EventCode": "0xB7, 0xBB",
	645	+ "MSRValue": "0x0084008000",
	646	+ "Counter": "0,1,2,3",
	647	+ "UMask": "0x1",
	648	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
	649	+ "MSRIndex": "0x1a6, 0x1a7",
	650	+ "SampleAfterValue": "100003",
	651	+ "BriefDescription": "Counts any other requests",
	652	+ "Offcore": "1",
	653	+ "CounterHTOff": "0,1,2,3"
	654	+ },
	655	+ {
	656	+ "PublicDescription": "Counts any other requests",
	657	+ "EventCode": "0xB7, 0xBB",
	658	+ "MSRValue": "0x0044008000",
	659	+ "Counter": "0,1,2,3",
	660	+ "UMask": "0x1",
	661	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT",
	662	+ "MSRIndex": "0x1a6, 0x1a7",
	663	+ "SampleAfterValue": "100003",
	664	+ "BriefDescription": "Counts any other requests",
	665	+ "Offcore": "1",
	666	+ "CounterHTOff": "0,1,2,3"
	667	+ },
	668	+ {
	669	+ "PublicDescription": "Counts any other requests",
	670	+ "EventCode": "0xB7, 0xBB",
	671	+ "MSRValue": "0x2000408000",
	672	+ "Counter": "0,1,2,3",
	673	+ "UMask": "0x1",
	674	+ "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
	675	+ "MSRIndex": "0x1a6, 0x1a7",
	676	+ "SampleAfterValue": "100003",
	677	+ "BriefDescription": "Counts any other requests",
	678	+ "Offcore": "1",
	679	+ "CounterHTOff": "0,1,2,3"
	680	+ },
	681	+ {
	682	+ "PublicDescription": "Counts any other requests",
	683	+ "EventCode": "0xB7, 0xBB",
	684	+ "MSRValue": "0x20001C8000",
	685	+ "Counter": "0,1,2,3",
	686	+ "UMask": "0x1",
	687	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",
	688	+ "MSRIndex": "0x1a6, 0x1a7",
	689	+ "SampleAfterValue": "100003",
	690	+ "BriefDescription": "Counts any other requests",
	691	+ "Offcore": "1",
	692	+ "CounterHTOff": "0,1,2,3"
	693	+ },
	694	+ {
	695	+ "PublicDescription": "Counts any other requests",
	696	+ "EventCode": "0xB7, 0xBB",
	697	+ "MSRValue": "0x2000108000",
	698	+ "Counter": "0,1,2,3",
	699	+ "UMask": "0x1",
	700	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM",
	701	+ "MSRIndex": "0x1a6, 0x1a7",
	702	+ "SampleAfterValue": "100003",
	703	+ "BriefDescription": "Counts any other requests",
	704	+ "Offcore": "1",
	705	+ "CounterHTOff": "0,1,2,3"
	706	+ },
	707	+ {
	708	+ "PublicDescription": "Counts any other requests",
	709	+ "EventCode": "0xB7, 0xBB",
	710	+ "MSRValue": "0x2000088000",
	711	+ "Counter": "0,1,2,3",
	712	+ "UMask": "0x1",
	713	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM",
	714	+ "MSRIndex": "0x1a6, 0x1a7",
	715	+ "SampleAfterValue": "100003",
	716	+ "BriefDescription": "Counts any other requests",
	717	+ "Offcore": "1",
	718	+ "CounterHTOff": "0,1,2,3"
	719	+ },
	720	+ {
	721	+ "PublicDescription": "Counts any other requests",
	722	+ "EventCode": "0xB7, 0xBB",
	723	+ "MSRValue": "0x2000048000",
	724	+ "Counter": "0,1,2,3",
	725	+ "UMask": "0x1",
	726	+ "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM",
	727	+ "MSRIndex": "0x1a6, 0x1a7",
	728	+ "SampleAfterValue": "100003",
	729	+ "BriefDescription": "Counts any other requests",
	730	+ "Offcore": "1",
	731	+ "CounterHTOff": "0,1,2,3"
	732	+ },
	733	+ {
	734	+ "PublicDescription": "Counts any other requests",
	735	+ "EventCode": "0xB7, 0xBB",
	736	+ "MSRValue": "0x2000028000",
	737	+ "Counter": "0,1,2,3",
	738	+ "UMask": "0x1",
	739	+ "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM",
	740	+ "MSRIndex": "0x1a6, 0x1a7",
	741	+ "SampleAfterValue": "100003",
	742	+ "BriefDescription": "Counts any other requests",
	743	+ "Offcore": "1",
	744	+ "CounterHTOff": "0,1,2,3"
	745	+ },
	746	+ {
	747	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	749	+ "MSRValue": "0x3FFC400004",
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	752	+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
	753	+ "MSRIndex": "0x1a6, 0x1a7",
	754	+ "SampleAfterValue": "100003",
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	757	+ "CounterHTOff": "0,1,2,3"
	758	+ },
	759	+ {
	760	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	765	+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM",
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	767	+ "SampleAfterValue": "100003",
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	770	+ "CounterHTOff": "0,1,2,3"
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	772	+ {
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	775	+ "MSRValue": "0x103C400004",
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	779	+ "MSRIndex": "0x1a6, 0x1a7",
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	781	+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	783	+ "CounterHTOff": "0,1,2,3"
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	790	+ "UMask": "0x1",
	791	+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
	792	+ "MSRIndex": "0x1a6, 0x1a7",
	793	+ "SampleAfterValue": "100003",
	794	+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	796	+ "CounterHTOff": "0,1,2,3"
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	798	+ {
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	806	+ "SampleAfterValue": "100003",
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	809	+ "CounterHTOff": "0,1,2,3"
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	814	+ "MSRValue": "0x013C400004",
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	816	+ "UMask": "0x1",
	817	+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
	818	+ "MSRIndex": "0x1a6, 0x1a7",
	819	+ "SampleAfterValue": "100003",
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	822	+ "CounterHTOff": "0,1,2,3"
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	835	+ "CounterHTOff": "0,1,2,3"
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	848	+ "CounterHTOff": "0,1,2,3"
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	850	+ {
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	856	+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
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	861	+ "CounterHTOff": "0,1,2,3"
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	863	+ {
	864	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	870	+ "MSRIndex": "0x1a6, 0x1a7",
	871	+ "SampleAfterValue": "100003",
	872	+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	874	+ "CounterHTOff": "0,1,2,3"
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	876	+ {
	877	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	882	+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
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	884	+ "SampleAfterValue": "100003",
	885	+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	887	+ "CounterHTOff": "0,1,2,3"
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	889	+ {
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	897	+ "SampleAfterValue": "100003",
	898	+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	900	+ "CounterHTOff": "0,1,2,3"
	901	+ },
	902	+ {
	903	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	913	+ "CounterHTOff": "0,1,2,3"
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	923	+ "SampleAfterValue": "100003",
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	926	+ "CounterHTOff": "0,1,2,3"
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	928	+ {
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	935	+ "MSRIndex": "0x1a6, 0x1a7",
	936	+ "SampleAfterValue": "100003",
	937	+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	939	+ "CounterHTOff": "0,1,2,3"
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	941	+ {
	942	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	949	+ "SampleAfterValue": "100003",
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	952	+ "CounterHTOff": "0,1,2,3"
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	954	+ {
	955	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	959	+ "UMask": "0x1",
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	967	+ {
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	978	+ "CounterHTOff": "0,1,2,3"
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	980	+ {
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	991	+ "CounterHTOff": "0,1,2,3"
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	993	+ {
	994	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that",
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	1000	+ "MSRIndex": "0x1a6, 0x1a7",
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	1006	+ {
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	1014	+ "SampleAfterValue": "100003",
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	1017	+ "CounterHTOff": "0,1,2,3"
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	1136	+ {
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	1147	+ "CounterHTOff": "0,1,2,3"
	1148	+ },
	1149	+ {
	1150	+ "PublicDescription": "Counts all demand data writes (RFOs)",
	1151	+ "EventCode": "0xB7, 0xBB",
	1152	+ "MSRValue": "0x2004000002",
	1153	+ "Counter": "0,1,2,3",
	1154	+ "UMask": "0x1",
	1155	+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
	1156	+ "MSRIndex": "0x1a6, 0x1a7",
	1157	+ "SampleAfterValue": "100003",
	1158	+ "BriefDescription": "Counts all demand data writes (RFOs)",
	1159	+ "Offcore": "1",
	1160	+ "CounterHTOff": "0,1,2,3"
	1161	+ },
	1162	+ {
	1163	+ "PublicDescription": "Counts all demand data writes (RFOs)",
	1164	+ "EventCode": "0xB7, 0xBB",
	1165	+ "MSRValue": "0x1004000002",
	1166	+ "Counter": "0,1,2,3",
	1167	+ "UMask": "0x1",
	1168	+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
	1169	+ "MSRIndex": "0x1a6, 0x1a7",
	1170	+ "SampleAfterValue": "100003",
	1171	+ "BriefDescription": "Counts all demand data writes (RFOs)",
	1172	+ "Offcore": "1",
	1173	+ "CounterHTOff": "0,1,2,3"
	1174	+ },
	1175	+ {
	1176	+ "PublicDescription": "Counts all demand data writes (RFOs)",
	1177	+ "EventCode": "0xB7, 0xBB",
	1178	+ "MSRValue": "0x0404000002",
	1179	+ "Counter": "0,1,2,3",
	1180	+ "UMask": "0x1",
	1181	+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
	1182	+ "MSRIndex": "0x1a6, 0x1a7",
	1183	+ "SampleAfterValue": "100003",
	1184	+ "BriefDescription": "Counts all demand data writes (RFOs)",
	1185	+ "Offcore": "1",
	1186	+ "CounterHTOff": "0,1,2,3"
	1187	+ },
	1188	+ {
	1189	+ "PublicDescription": "Counts all demand data writes (RFOs)",
	1190	+ "EventCode": "0xB7, 0xBB",
	1191	+ "MSRValue": "0x0204000002",
	1192	+ "Counter": "0,1,2,3",
	1193	+ "UMask": "0x1",
	1194	+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
	1195	+ "MSRIndex": "0x1a6, 0x1a7",
	1196	+ "SampleAfterValue": "100003",
	1197	+ "BriefDescription": "Counts all demand data writes (RFOs)",
	1198	+ "Offcore": "1",
	1199	+ "CounterHTOff": "0,1,2,3"
	1200	+ },
	1201	+ {
	1202	+ "PublicDescription": "Counts all demand data writes (RFOs)",
	1203	+ "EventCode": "0xB7, 0xBB",
	1204	+ "MSRValue": "0x0104000002",
	1205	+ "Counter": "0,1,2,3",
	1206	+ "UMask": "0x1",
	1207	+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
	1208	+ "MSRIndex": "0x1a6, 0x1a7",
	1209	+ "SampleAfterValue": "100003",
	1210	+ "BriefDescription": "Counts all demand data writes (RFOs)",
	1211	+ "Offcore": "1",
	1212	+ "CounterHTOff": "0,1,2,3"
	1213	+ },
	1214	+ {
	1215	+ "PublicDescription": "Counts all demand data writes (RFOs)",
	1216	+ "EventCode": "0xB7, 0xBB",
	1217	+ "MSRValue": "0x0084000002",
	1218	+ "Counter": "0,1,2,3",
	1219	+ "UMask": "0x1",
	1220	+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
	1221	+ "MSRIndex": "0x1a6, 0x1a7",
	1222	+ "SampleAfterValue": "100003",
	1223	+ "BriefDescription": "Counts all demand data writes (RFOs)",
	1224	+ "Offcore": "1",
	1225	+ "CounterHTOff": "0,1,2,3"
	1226	+ },
	1227	+ {
	1228	+ "PublicDescription": "Counts all demand data writes (RFOs)",
	1229	+ "EventCode": "0xB7, 0xBB",
	1230	+ "MSRValue": "0x0044000002",
	1231	+ "Counter": "0,1,2,3",
	1232	+ "UMask": "0x1",
	1233	+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT",
	1234	+ "MSRIndex": "0x1a6, 0x1a7",
	1235	+ "SampleAfterValue": "100003",
	1236	+ "BriefDescription": "Counts all demand data writes (RFOs)",
	1237	+ "Offcore": "1",
	1238	+ "CounterHTOff": "0,1,2,3"
	1239	+ },
	1240	+ {
	1241	+ "PublicDescription": "Counts all demand data writes (RFOs)",
	1242	+ "EventCode": "0xB7, 0xBB",
	1243	+ "MSRValue": "0x2000400002",
	1244	+ "Counter": "0,1,2,3",
	1245	+ "UMask": "0x1",
	1246	+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
	1247	+ "MSRIndex": "0x1a6, 0x1a7",
	1248	+ "SampleAfterValue": "100003",
	1249	+ "BriefDescription": "Counts all demand data writes (RFOs)",
	1250	+ "Offcore": "1",
	1251	+ "CounterHTOff": "0,1,2,3"
	1252	+ },
	1253	+ {
	1254	+ "PublicDescription": "Counts all demand data writes (RFOs)",
	1255	+ "EventCode": "0xB7, 0xBB",
	1256	+ "MSRValue": "0x20001C0002",
	1257	+ "Counter": "0,1,2,3",
	1258	+ "UMask": "0x1",
	1259	+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM",
	1260	+ "MSRIndex": "0x1a6, 0x1a7",
	1261	+ "SampleAfterValue": "100003",
	1262	+ "BriefDescription": "Counts all demand data writes (RFOs)",
	1263	+ "Offcore": "1",
	1264	+ "CounterHTOff": "0,1,2,3"
	1265	+ },
	1266	+ {
	1267	+ "PublicDescription": "Counts all demand data writes (RFOs)",
	1268	+ "EventCode": "0xB7, 0xBB",
	1269	+ "MSRValue": "0x2000100002",
	1270	+ "Counter": "0,1,2,3",
	1271	+ "UMask": "0x1",
	1272	+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM",
	1273	+ "MSRIndex": "0x1a6, 0x1a7",
	1274	+ "SampleAfterValue": "100003",
	1275	+ "BriefDescription": "Counts all demand data writes (RFOs)",
	1276	+ "Offcore": "1",
	1277	+ "CounterHTOff": "0,1,2,3"
	1278	+ },
	1279	+ {
	1280	+ "PublicDescription": "Counts all demand data writes (RFOs)",
	1281	+ "EventCode": "0xB7, 0xBB",
	1282	+ "MSRValue": "0x2000080002",
	1283	+ "Counter": "0,1,2,3",
	1284	+ "UMask": "0x1",
	1285	+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM",
	1286	+ "MSRIndex": "0x1a6, 0x1a7",
	1287	+ "SampleAfterValue": "100003",
	1288	+ "BriefDescription": "Counts all demand data writes (RFOs)",
	1289	+ "Offcore": "1",
	1290	+ "CounterHTOff": "0,1,2,3"
	1291	+ },
	1292	+ {
	1293	+ "PublicDescription": "Counts all demand data writes (RFOs)",
	1294	+ "EventCode": "0xB7, 0xBB",
	1295	+ "MSRValue": "0x2000040002",
	1296	+ "Counter": "0,1,2,3",
	1297	+ "UMask": "0x1",
	1298	+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM",
	1299	+ "MSRIndex": "0x1a6, 0x1a7",
	1300	+ "SampleAfterValue": "100003",
	1301	+ "BriefDescription": "Counts all demand data writes (RFOs)",
	1302	+ "Offcore": "1",
	1303	+ "CounterHTOff": "0,1,2,3"
	1304	+ },
	1305	+ {
	1306	+ "PublicDescription": "Counts all demand data writes (RFOs)",
	1307	+ "EventCode": "0xB7, 0xBB",
	1308	+ "MSRValue": "0x2000020002",
	1309	+ "Counter": "0,1,2,3",
	1310	+ "UMask": "0x1",
	1311	+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
	1312	+ "MSRIndex": "0x1a6, 0x1a7",
	1313	+ "SampleAfterValue": "100003",
	1314	+ "BriefDescription": "Counts all demand data writes (RFOs)",
	1315	+ "Offcore": "1",
	1316	+ "CounterHTOff": "0,1,2,3"
	1317	+ },
	1318	+ {
	1319	+ "PublicDescription": "Counts demand data reads",
	1320	+ "EventCode": "0xB7, 0xBB",
	1321	+ "MSRValue": "0x3FFC400001",
463	1322	"Counter": "0,1,2,3",
464	1323	"UMask": "0x1",
465	1324	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
466		- "MSRIndex": "0x1a6,0x1a7",
	1325	+ "MSRIndex": "0x1a6, 0x1a7",
467	1326	"SampleAfterValue": "100003",
468		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS & ANY_SNOOP",
	1327	+ "BriefDescription": "Counts demand data reads",
469	1328	"Offcore": "1",
470	1329	"CounterHTOff": "0,1,2,3"
471	1330	},
472	1331	{
473		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1332	+ "PublicDescription": "Counts demand data reads",
474	1333	"EventCode": "0xB7, 0xBB",
475		- "MSRValue": "0x103c000001 ",
	1334	+ "MSRValue": "0x203C400001",
	1335	+ "Counter": "0,1,2,3",
	1336	+ "UMask": "0x1",
	1337	+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM",
	1338	+ "MSRIndex": "0x1a6, 0x1a7",
	1339	+ "SampleAfterValue": "100003",
	1340	+ "BriefDescription": "Counts demand data reads",
	1341	+ "Offcore": "1",
	1342	+ "CounterHTOff": "0,1,2,3"
	1343	+ },
	1344	+ {
	1345	+ "PublicDescription": "Counts demand data reads",
	1346	+ "EventCode": "0xB7, 0xBB",
	1347	+ "MSRValue": "0x103C400001",
476	1348	"Counter": "0,1,2,3",
477	1349	"UMask": "0x1",
478	1350	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM",
479		- "MSRIndex": "0x1a6,0x1a7",
	1351	+ "MSRIndex": "0x1a6, 0x1a7",
480	1352	"SampleAfterValue": "100003",
481		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_HITM",
	1353	+ "BriefDescription": "Counts demand data reads",
482	1354	"Offcore": "1",
483	1355	"CounterHTOff": "0,1,2,3"
484	1356	},
485	1357	{
486		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1358	+ "PublicDescription": "Counts demand data reads",
487	1359	"EventCode": "0xB7, 0xBB",
488		- "MSRValue": "0x043c000001 ",
	1360	+ "MSRValue": "0x043C400001",
489	1361	"Counter": "0,1,2,3",
490	1362	"UMask": "0x1",
491	1363	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
492		- "MSRIndex": "0x1a6,0x1a7",
	1364	+ "MSRIndex": "0x1a6, 0x1a7",
493	1365	"SampleAfterValue": "100003",
494		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD",
	1366	+ "BriefDescription": "Counts demand data reads",
495	1367	"Offcore": "1",
496	1368	"CounterHTOff": "0,1,2,3"
497	1369	},
498	1370	{
499		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1371	+ "PublicDescription": "Counts demand data reads",
500	1372	"EventCode": "0xB7, 0xBB",
501		- "MSRValue": "0x023c000001 ",
	1373	+ "MSRValue": "0x023C400001",
502	1374	"Counter": "0,1,2,3",
503	1375	"UMask": "0x1",
504	1376	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
505		- "MSRIndex": "0x1a6,0x1a7",
	1377	+ "MSRIndex": "0x1a6, 0x1a7",
506	1378	"SampleAfterValue": "100003",
507		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_MISS",
	1379	+ "BriefDescription": "Counts demand data reads",
508	1380	"Offcore": "1",
509	1381	"CounterHTOff": "0,1,2,3"
510	1382	},
511	1383	{
512		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1384	+ "PublicDescription": "Counts demand data reads",
513	1385	"EventCode": "0xB7, 0xBB",
514		- "MSRValue": "0x013c000001 ",
	1386	+ "MSRValue": "0x013C400001",
515	1387	"Counter": "0,1,2,3",
516	1388	"UMask": "0x1",
517	1389	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
518		- "MSRIndex": "0x1a6,0x1a7",
	1390	+ "MSRIndex": "0x1a6, 0x1a7",
519	1391	"SampleAfterValue": "100003",
520		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED",
	1392	+ "BriefDescription": "Counts demand data reads",
521	1393	"Offcore": "1",
522	1394	"CounterHTOff": "0,1,2,3"
523	1395	},
524	1396	{
525		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1397	+ "PublicDescription": "Counts demand data reads",
526	1398	"EventCode": "0xB7, 0xBB",
527		- "MSRValue": "0x00bc000001 ",
	1399	+ "MSRValue": "0x00BC400001",
528	1400	"Counter": "0,1,2,3",
529	1401	"UMask": "0x1",
530	1402	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
531		- "MSRIndex": "0x1a6,0x1a7",
	1403	+ "MSRIndex": "0x1a6, 0x1a7",
532	1404	"SampleAfterValue": "100003",
533		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_NONE",
	1405	+ "BriefDescription": "Counts demand data reads",
534	1406	"Offcore": "1",
535	1407	"CounterHTOff": "0,1,2,3"
536	1408	},
537	1409	{
538		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1410	+ "PublicDescription": "Counts demand data reads",
539	1411	"EventCode": "0xB7, 0xBB",
540		- "MSRValue": "0x3fc4000001 ",
	1412	+ "MSRValue": "0x007C400001",
	1413	+ "Counter": "0,1,2,3",
	1414	+ "UMask": "0x1",
	1415	+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT",
	1416	+ "MSRIndex": "0x1a6, 0x1a7",
	1417	+ "SampleAfterValue": "100003",
	1418	+ "BriefDescription": "Counts demand data reads",
	1419	+ "Offcore": "1",
	1420	+ "CounterHTOff": "0,1,2,3"
	1421	+ },
	1422	+ {
	1423	+ "PublicDescription": "Counts demand data reads",
	1424	+ "EventCode": "0xB7, 0xBB",
	1425	+ "MSRValue": "0x3FC4000001",
541	1426	"Counter": "0,1,2,3",
542	1427	"UMask": "0x1",
543	1428	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
544		- "MSRIndex": "0x1a6,0x1a7",
	1429	+ "MSRIndex": "0x1a6, 0x1a7",
545	1430	"SampleAfterValue": "100003",
546		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP",
	1431	+ "BriefDescription": "Counts demand data reads",
547	1432	"Offcore": "1",
548	1433	"CounterHTOff": "0,1,2,3"
549	1434	},
550	1435	{
551		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1436	+ "PublicDescription": "Counts demand data reads",
552	1437	"EventCode": "0xB7, 0xBB",
553		- "MSRValue": "0x1004000001 ",
	1438	+ "MSRValue": "0x2004000001",
	1439	+ "Counter": "0,1,2,3",
	1440	+ "UMask": "0x1",
	1441	+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
	1442	+ "MSRIndex": "0x1a6, 0x1a7",
	1443	+ "SampleAfterValue": "100003",
	1444	+ "BriefDescription": "Counts demand data reads",
	1445	+ "Offcore": "1",
	1446	+ "CounterHTOff": "0,1,2,3"
	1447	+ },
	1448	+ {
	1449	+ "PublicDescription": "Counts demand data reads",
	1450	+ "EventCode": "0xB7, 0xBB",
	1451	+ "MSRValue": "0x1004000001",
554	1452	"Counter": "0,1,2,3",
555	1453	"UMask": "0x1",
556	1454	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
557		- "MSRIndex": "0x1a6,0x1a7",
	1455	+ "MSRIndex": "0x1a6, 0x1a7",
558	1456	"SampleAfterValue": "100003",
559		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM",
	1457	+ "BriefDescription": "Counts demand data reads",
560	1458	"Offcore": "1",
561	1459	"CounterHTOff": "0,1,2,3"
562	1460	},
563	1461	{
564		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1462	+ "PublicDescription": "Counts demand data reads",
565	1463	"EventCode": "0xB7, 0xBB",
566		- "MSRValue": "0x0404000001 ",
	1464	+ "MSRValue": "0x0404000001",
567	1465	"Counter": "0,1,2,3",
568	1466	"UMask": "0x1",
569	1467	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
570		- "MSRIndex": "0x1a6,0x1a7",
	1468	+ "MSRIndex": "0x1a6, 0x1a7",
571	1469	"SampleAfterValue": "100003",
572		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD",
	1470	+ "BriefDescription": "Counts demand data reads",
573	1471	"Offcore": "1",
574	1472	"CounterHTOff": "0,1,2,3"
575	1473	},
576	1474	{
577		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1475	+ "PublicDescription": "Counts demand data reads",
578	1476	"EventCode": "0xB7, 0xBB",
579		- "MSRValue": "0x0204000001 ",
	1477	+ "MSRValue": "0x0204000001",
580	1478	"Counter": "0,1,2,3",
581	1479	"UMask": "0x1",
582	1480	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
583		- "MSRIndex": "0x1a6,0x1a7",
	1481	+ "MSRIndex": "0x1a6, 0x1a7",
584	1482	"SampleAfterValue": "100003",
585		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS",
	1483	+ "BriefDescription": "Counts demand data reads",
586	1484	"Offcore": "1",
587	1485	"CounterHTOff": "0,1,2,3"
588	1486	},
589	1487	{
590		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1488	+ "PublicDescription": "Counts demand data reads",
591	1489	"EventCode": "0xB7, 0xBB",
592		- "MSRValue": "0x0104000001 ",
	1490	+ "MSRValue": "0x0104000001",
593	1491	"Counter": "0,1,2,3",
594	1492	"UMask": "0x1",
595	1493	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
596		- "MSRIndex": "0x1a6,0x1a7",
	1494	+ "MSRIndex": "0x1a6, 0x1a7",
597	1495	"SampleAfterValue": "100003",
598		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED",
	1496	+ "BriefDescription": "Counts demand data reads",
599	1497	"Offcore": "1",
600	1498	"CounterHTOff": "0,1,2,3"
601	1499	},
602	1500	{
603		- "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
	1501	+ "PublicDescription": "Counts demand data reads",
604	1502	"EventCode": "0xB7, 0xBB",
605		- "MSRValue": "0x0084000001 ",
	1503	+ "MSRValue": "0x0084000001",
606	1504	"Counter": "0,1,2,3",
607	1505	"UMask": "0x1",
608	1506	"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
609		- "MSRIndex": "0x1a6,0x1a7",
	1507	+ "MSRIndex": "0x1a6, 0x1a7",
610	1508	"SampleAfterValue": "100003",
611		- "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE",
	1509	+ "BriefDescription": "Counts demand data reads",
	1510	+ "Offcore": "1",
	1511	+ "CounterHTOff": "0,1,2,3"
	1512	+ },
	1513	+ {
	1514	+ "PublicDescription": "Counts demand data reads",
	1515	+ "EventCode": "0xB7, 0xBB",
	1516	+ "MSRValue": "0x0044000001",
	1517	+ "Counter": "0,1,2,3",
	1518	+ "UMask": "0x1",
	1519	+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
	1520	+ "MSRIndex": "0x1a6, 0x1a7",
	1521	+ "SampleAfterValue": "100003",
	1522	+ "BriefDescription": "Counts demand data reads",
	1523	+ "Offcore": "1",
	1524	+ "CounterHTOff": "0,1,2,3"
	1525	+ },
	1526	+ {
	1527	+ "PublicDescription": "Counts demand data reads",
	1528	+ "EventCode": "0xB7, 0xBB",
	1529	+ "MSRValue": "0x2000400001",
	1530	+ "Counter": "0,1,2,3",
	1531	+ "UMask": "0x1",
	1532	+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
	1533	+ "MSRIndex": "0x1a6, 0x1a7",
	1534	+ "SampleAfterValue": "100003",
	1535	+ "BriefDescription": "Counts demand data reads",
	1536	+ "Offcore": "1",
	1537	+ "CounterHTOff": "0,1,2,3"
	1538	+ },
	1539	+ {
	1540	+ "PublicDescription": "Counts demand data reads",
	1541	+ "EventCode": "0xB7, 0xBB",
	1542	+ "MSRValue": "0x20001C0001",
	1543	+ "Counter": "0,1,2,3",
	1544	+ "UMask": "0x1",
	1545	+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
	1546	+ "MSRIndex": "0x1a6, 0x1a7",
	1547	+ "SampleAfterValue": "100003",
	1548	+ "BriefDescription": "Counts demand data reads",
	1549	+ "Offcore": "1",
	1550	+ "CounterHTOff": "0,1,2,3"
	1551	+ },
	1552	+ {
	1553	+ "PublicDescription": "Counts demand data reads",
	1554	+ "EventCode": "0xB7, 0xBB",
	1555	+ "MSRValue": "0x2000100001",
	1556	+ "Counter": "0,1,2,3",
	1557	+ "UMask": "0x1",
	1558	+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM",
	1559	+ "MSRIndex": "0x1a6, 0x1a7",
	1560	+ "SampleAfterValue": "100003",
	1561	+ "BriefDescription": "Counts demand data reads",
	1562	+ "Offcore": "1",
	1563	+ "CounterHTOff": "0,1,2,3"
	1564	+ },
	1565	+ {
	1566	+ "PublicDescription": "Counts demand data reads",
	1567	+ "EventCode": "0xB7, 0xBB",
	1568	+ "MSRValue": "0x2000080001",
	1569	+ "Counter": "0,1,2,3",
	1570	+ "UMask": "0x1",
	1571	+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM",
	1572	+ "MSRIndex": "0x1a6, 0x1a7",
	1573	+ "SampleAfterValue": "100003",
	1574	+ "BriefDescription": "Counts demand data reads",
	1575	+ "Offcore": "1",
	1576	+ "CounterHTOff": "0,1,2,3"
	1577	+ },
	1578	+ {
	1579	+ "PublicDescription": "Counts demand data reads",
	1580	+ "EventCode": "0xB7, 0xBB",
	1581	+ "MSRValue": "0x2000040001",
	1582	+ "Counter": "0,1,2,3",
	1583	+ "UMask": "0x1",
	1584	+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM",
	1585	+ "MSRIndex": "0x1a6, 0x1a7",
	1586	+ "SampleAfterValue": "100003",
	1587	+ "BriefDescription": "Counts demand data reads",
	1588	+ "Offcore": "1",
	1589	+ "CounterHTOff": "0,1,2,3"
	1590	+ },
	1591	+ {
	1592	+ "PublicDescription": "Counts demand data reads",
	1593	+ "EventCode": "0xB7, 0xBB",
	1594	+ "MSRValue": "0x2000020001",
	1595	+ "Counter": "0,1,2,3",
	1596	+ "UMask": "0x1",
	1597	+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
	1598	+ "MSRIndex": "0x1a6, 0x1a7",
	1599	+ "SampleAfterValue": "100003",
	1600	+ "BriefDescription": "Counts demand data reads",
612	1601	"Offcore": "1",
613	1602	"CounterHTOff": "0,1,2,3"
614	1603	}