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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json
....@@ -1,60 +1,5 @@
11 [
22     {
3
-        "EventCode": "0xAE",
4
-        "Counter": "0,1,2,3",
5
-        "UMask": "0x1",
6
-        "EventName": "ITLB.ITLB_FLUSH",
7
-        "SampleAfterValue": "100007",
8
-        "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
9
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
10
-    },
11
-    {
12
-        "EventCode": "0x4F",
13
-        "Counter": "0,1,2,3",
14
-        "UMask": "0x10",
15
-        "EventName": "EPT.WALK_CYCLES",
16
-        "SampleAfterValue": "2000003",
17
-        "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
18
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
19
-    },
20
-    {
21
-        "EventCode": "0x85",
22
-        "Counter": "0,1,2,3",
23
-        "UMask": "0x1",
24
-        "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
25
-        "SampleAfterValue": "100003",
26
-        "BriefDescription": "Misses at all ITLB levels that cause page walks.",
27
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
28
-    },
29
-    {
30
-        "EventCode": "0x85",
31
-        "Counter": "0,1,2,3",
32
-        "UMask": "0x2",
33
-        "EventName": "ITLB_MISSES.WALK_COMPLETED",
34
-        "SampleAfterValue": "100003",
35
-        "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
36
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
37
-    },
38
-    {
39
-        "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
40
-        "EventCode": "0x85",
41
-        "Counter": "0,1,2,3",
42
-        "UMask": "0x4",
43
-        "EventName": "ITLB_MISSES.WALK_DURATION",
44
-        "SampleAfterValue": "2000003",
45
-        "BriefDescription": "Cycles when PMH is busy with page walks.",
46
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
47
-    },
48
-    {
49
-        "EventCode": "0x85",
50
-        "Counter": "0,1,2,3",
51
-        "UMask": "0x10",
52
-        "EventName": "ITLB_MISSES.STLB_HIT",
53
-        "SampleAfterValue": "100003",
54
-        "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
55
-        "CounterHTOff": "0,1,2,3,4,5,6,7"
56
-    },
57
-    {
583         "EventCode": "0x08",
594         "Counter": "0,1,2,3",
605         "UMask": "0x1",
....@@ -129,6 +74,61 @@
12974         "CounterHTOff": "0,1,2,3,4,5,6,7"
13075     },
13176     {
77
+        "EventCode": "0x4F",
78
+        "Counter": "0,1,2,3",
79
+        "UMask": "0x10",
80
+        "EventName": "EPT.WALK_CYCLES",
81
+        "SampleAfterValue": "2000003",
82
+        "BriefDescription": "Cycle count for an Extended Page table walk.  The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
83
+        "CounterHTOff": "0,1,2,3,4,5,6,7"
84
+    },
85
+    {
86
+        "EventCode": "0x85",
87
+        "Counter": "0,1,2,3",
88
+        "UMask": "0x1",
89
+        "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
90
+        "SampleAfterValue": "100003",
91
+        "BriefDescription": "Misses at all ITLB levels that cause page walks.",
92
+        "CounterHTOff": "0,1,2,3,4,5,6,7"
93
+    },
94
+    {
95
+        "EventCode": "0x85",
96
+        "Counter": "0,1,2,3",
97
+        "UMask": "0x2",
98
+        "EventName": "ITLB_MISSES.WALK_COMPLETED",
99
+        "SampleAfterValue": "100003",
100
+        "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
101
+        "CounterHTOff": "0,1,2,3,4,5,6,7"
102
+    },
103
+    {
104
+        "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
105
+        "EventCode": "0x85",
106
+        "Counter": "0,1,2,3",
107
+        "UMask": "0x4",
108
+        "EventName": "ITLB_MISSES.WALK_DURATION",
109
+        "SampleAfterValue": "2000003",
110
+        "BriefDescription": "Cycles when PMH is busy with page walks.",
111
+        "CounterHTOff": "0,1,2,3,4,5,6,7"
112
+    },
113
+    {
114
+        "EventCode": "0x85",
115
+        "Counter": "0,1,2,3",
116
+        "UMask": "0x10",
117
+        "EventName": "ITLB_MISSES.STLB_HIT",
118
+        "SampleAfterValue": "100003",
119
+        "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
120
+        "CounterHTOff": "0,1,2,3,4,5,6,7"
121
+    },
122
+    {
123
+        "EventCode": "0xAE",
124
+        "Counter": "0,1,2,3",
125
+        "UMask": "0x1",
126
+        "EventName": "ITLB.ITLB_FLUSH",
127
+        "SampleAfterValue": "100007",
128
+        "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
129
+        "CounterHTOff": "0,1,2,3,4,5,6,7"
130
+    },
131
+    {
132132         "EventCode": "0xBD",
133133         "Counter": "0,1,2,3",
134134         "UMask": "0x1",