forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/tools/perf/pmu-events/arch/x86/haswellx/memory.json
....@@ -291,7 +291,7 @@
291291     {
292292         "EventCode": "0xCD",
293293         "UMask": "0x1",
294
-        "BriefDescription": "Loads with latency value being above 4.",
294
+        "BriefDescription": "Randomly selected loads with latency value being above 4.",
295295         "PEBS": "2",
296296         "MSRValue": "0x4",
297297         "Counter": "3",
....@@ -305,7 +305,7 @@
305305     {
306306         "EventCode": "0xCD",
307307         "UMask": "0x1",
308
-        "BriefDescription": "Loads with latency value being above 8.",
308
+        "BriefDescription": "Randomly selected loads with latency value being above 8.",
309309         "PEBS": "2",
310310         "MSRValue": "0x8",
311311         "Counter": "3",
....@@ -319,7 +319,7 @@
319319     {
320320         "EventCode": "0xCD",
321321         "UMask": "0x1",
322
-        "BriefDescription": "Loads with latency value being above 16.",
322
+        "BriefDescription": "Randomly selected loads with latency value being above 16.",
323323         "PEBS": "2",
324324         "MSRValue": "0x10",
325325         "Counter": "3",
....@@ -333,7 +333,7 @@
333333     {
334334         "EventCode": "0xCD",
335335         "UMask": "0x1",
336
-        "BriefDescription": "Loads with latency value being above 32.",
336
+        "BriefDescription": "Randomly selected loads with latency value being above 32.",
337337         "PEBS": "2",
338338         "MSRValue": "0x20",
339339         "Counter": "3",
....@@ -347,7 +347,7 @@
347347     {
348348         "EventCode": "0xCD",
349349         "UMask": "0x1",
350
-        "BriefDescription": "Loads with latency value being above 64.",
350
+        "BriefDescription": "Randomly selected loads with latency value being above 64.",
351351         "PEBS": "2",
352352         "MSRValue": "0x40",
353353         "Counter": "3",
....@@ -361,7 +361,7 @@
361361     {
362362         "EventCode": "0xCD",
363363         "UMask": "0x1",
364
-        "BriefDescription": "Loads with latency value being above 128.",
364
+        "BriefDescription": "Randomly selected loads with latency value being above 128.",
365365         "PEBS": "2",
366366         "MSRValue": "0x80",
367367         "Counter": "3",
....@@ -375,7 +375,7 @@
375375     {
376376         "EventCode": "0xCD",
377377         "UMask": "0x1",
378
-        "BriefDescription": "Loads with latency value being above 256.",
378
+        "BriefDescription": "Randomly selected loads with latency value being above 256.",
379379         "PEBS": "2",
380380         "MSRValue": "0x100",
381381         "Counter": "3",
....@@ -389,7 +389,7 @@
389389     {
390390         "EventCode": "0xCD",
391391         "UMask": "0x1",
392
-        "BriefDescription": "Loads with latency value being above 512.",
392
+        "BriefDescription": "Randomly selected loads with latency value being above 512.",
393393         "PEBS": "2",
394394         "MSRValue": "0x200",
395395         "Counter": "3",
....@@ -404,12 +404,12 @@
404404         "Offcore": "1",
405405         "EventCode": "0xB7, 0xBB",
406406         "UMask": "0x1",
407
-        "BriefDescription": "Counts demand data reads that miss in the L3",
408
-        "MSRValue": "0x3fbfc00001",
407
+        "BriefDescription": "Counts demand data reads miss in the L3",
408
+        "MSRValue": "0x3FBFC00001",
409409         "Counter": "0,1,2,3",
410410         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
411411         "MSRIndex": "0x1a6,0x1a7",
412
-        "PublicDescription": "Counts demand data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
412
+        "PublicDescription": "Counts demand data reads miss in the L3",
413413         "SampleAfterValue": "100003",
414414         "CounterHTOff": "0,1,2,3"
415415     },
....@@ -417,12 +417,12 @@
417417         "Offcore": "1",
418418         "EventCode": "0xB7, 0xBB",
419419         "UMask": "0x1",
420
-        "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram",
420
+        "BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram",
421421         "MSRValue": "0x0600400001",
422422         "Counter": "0,1,2,3",
423423         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
424424         "MSRIndex": "0x1a6,0x1a7",
425
-        "PublicDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
425
+        "PublicDescription": "Counts demand data reads miss the L3 and the data is returned from local dram",
426426         "SampleAfterValue": "100003",
427427         "CounterHTOff": "0,1,2,3"
428428     },
....@@ -430,12 +430,12 @@
430430         "Offcore": "1",
431431         "EventCode": "0xB7, 0xBB",
432432         "UMask": "0x1",
433
-        "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3",
434
-        "MSRValue": "0x3fbfc00002",
433
+        "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
434
+        "MSRValue": "0x3FBFC00002",
435435         "Counter": "0,1,2,3",
436436         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
437437         "MSRIndex": "0x1a6,0x1a7",
438
-        "PublicDescription": "Counts all demand data writes (RFOs) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
438
+        "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3",
439439         "SampleAfterValue": "100003",
440440         "CounterHTOff": "0,1,2,3"
441441     },
....@@ -443,12 +443,12 @@
443443         "Offcore": "1",
444444         "EventCode": "0xB7, 0xBB",
445445         "UMask": "0x1",
446
-        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram",
446
+        "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram",
447447         "MSRValue": "0x0600400002",
448448         "Counter": "0,1,2,3",
449449         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM",
450450         "MSRIndex": "0x1a6,0x1a7",
451
-        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
451
+        "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram",
452452         "SampleAfterValue": "100003",
453453         "CounterHTOff": "0,1,2,3"
454454     },
....@@ -456,12 +456,12 @@
456456         "Offcore": "1",
457457         "EventCode": "0xB7, 0xBB",
458458         "UMask": "0x1",
459
-        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache",
460
-        "MSRValue": "0x103fc00002",
459
+        "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
460
+        "MSRValue": "0x103FC00002",
461461         "Counter": "0,1,2,3",
462462         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
463463         "MSRIndex": "0x1a6,0x1a7",
464
-        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
464
+        "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
465465         "SampleAfterValue": "100003",
466466         "CounterHTOff": "0,1,2,3"
467467     },
....@@ -469,12 +469,12 @@
469469         "Offcore": "1",
470470         "EventCode": "0xB7, 0xBB",
471471         "UMask": "0x1",
472
-        "BriefDescription": "Counts all demand code reads that miss in the L3",
473
-        "MSRValue": "0x3fbfc00004",
472
+        "BriefDescription": "Counts all demand code reads miss in the L3",
473
+        "MSRValue": "0x3FBFC00004",
474474         "Counter": "0,1,2,3",
475475         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
476476         "MSRIndex": "0x1a6,0x1a7",
477
-        "PublicDescription": "Counts all demand code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
477
+        "PublicDescription": "Counts all demand code reads miss in the L3",
478478         "SampleAfterValue": "100003",
479479         "CounterHTOff": "0,1,2,3"
480480     },
....@@ -482,12 +482,12 @@
482482         "Offcore": "1",
483483         "EventCode": "0xB7, 0xBB",
484484         "UMask": "0x1",
485
-        "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram",
485
+        "BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram",
486486         "MSRValue": "0x0600400004",
487487         "Counter": "0,1,2,3",
488488         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
489489         "MSRIndex": "0x1a6,0x1a7",
490
-        "PublicDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
490
+        "PublicDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram",
491491         "SampleAfterValue": "100003",
492492         "CounterHTOff": "0,1,2,3"
493493     },
....@@ -495,12 +495,12 @@
495495         "Offcore": "1",
496496         "EventCode": "0xB7, 0xBB",
497497         "UMask": "0x1",
498
-        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3",
499
-        "MSRValue": "0x3fbfc00010",
498
+        "BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3",
499
+        "MSRValue": "0x3FBFC00010",
500500         "Counter": "0,1,2,3",
501501         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
502502         "MSRIndex": "0x1a6,0x1a7",
503
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
503
+        "PublicDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3",
504504         "SampleAfterValue": "100003",
505505         "CounterHTOff": "0,1,2,3"
506506     },
....@@ -508,12 +508,12 @@
508508         "Offcore": "1",
509509         "EventCode": "0xB7, 0xBB",
510510         "UMask": "0x1",
511
-        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3",
512
-        "MSRValue": "0x3fbfc00020",
511
+        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3",
512
+        "MSRValue": "0x3FBFC00020",
513513         "Counter": "0,1,2,3",
514514         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE",
515515         "MSRIndex": "0x1a6,0x1a7",
516
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
516
+        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3",
517517         "SampleAfterValue": "100003",
518518         "CounterHTOff": "0,1,2,3"
519519     },
....@@ -521,12 +521,12 @@
521521         "Offcore": "1",
522522         "EventCode": "0xB7, 0xBB",
523523         "UMask": "0x1",
524
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3",
525
-        "MSRValue": "0x3fbfc00040",
524
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3",
525
+        "MSRValue": "0x3FBFC00040",
526526         "Counter": "0,1,2,3",
527527         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
528528         "MSRIndex": "0x1a6,0x1a7",
529
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
529
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3",
530530         "SampleAfterValue": "100003",
531531         "CounterHTOff": "0,1,2,3"
532532     },
....@@ -534,12 +534,12 @@
534534         "Offcore": "1",
535535         "EventCode": "0xB7, 0xBB",
536536         "UMask": "0x1",
537
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3",
538
-        "MSRValue": "0x3fbfc00080",
537
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3",
538
+        "MSRValue": "0x3FBFC00080",
539539         "Counter": "0,1,2,3",
540540         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
541541         "MSRIndex": "0x1a6,0x1a7",
542
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
542
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3",
543543         "SampleAfterValue": "100003",
544544         "CounterHTOff": "0,1,2,3"
545545     },
....@@ -547,12 +547,12 @@
547547         "Offcore": "1",
548548         "EventCode": "0xB7, 0xBB",
549549         "UMask": "0x1",
550
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3",
551
-        "MSRValue": "0x3fbfc00100",
550
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
551
+        "MSRValue": "0x3FBFC00100",
552552         "Counter": "0,1,2,3",
553553         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
554554         "MSRIndex": "0x1a6,0x1a7",
555
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
555
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
556556         "SampleAfterValue": "100003",
557557         "CounterHTOff": "0,1,2,3"
558558     },
....@@ -560,12 +560,12 @@
560560         "Offcore": "1",
561561         "EventCode": "0xB7, 0xBB",
562562         "UMask": "0x1",
563
-        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3",
564
-        "MSRValue": "0x3fbfc00200",
563
+        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
564
+        "MSRValue": "0x3FBFC00200",
565565         "Counter": "0,1,2,3",
566566         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
567567         "MSRIndex": "0x1a6,0x1a7",
568
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
568
+        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
569569         "SampleAfterValue": "100003",
570570         "CounterHTOff": "0,1,2,3"
571571     },
....@@ -573,12 +573,12 @@
573573         "Offcore": "1",
574574         "EventCode": "0xB7, 0xBB",
575575         "UMask": "0x1",
576
-        "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3",
577
-        "MSRValue": "0x3fbfc00091",
576
+        "BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
577
+        "MSRValue": "0x3FBFC00091",
578578         "Counter": "0,1,2,3",
579579         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
580580         "MSRIndex": "0x1a6,0x1a7",
581
-        "PublicDescription": "Counts all demand & prefetch data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
581
+        "PublicDescription": "Counts all demand & prefetch data reads miss in the L3",
582582         "SampleAfterValue": "100003",
583583         "CounterHTOff": "0,1,2,3"
584584     },
....@@ -586,12 +586,12 @@
586586         "Offcore": "1",
587587         "EventCode": "0xB7, 0xBB",
588588         "UMask": "0x1",
589
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram",
589
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
590590         "MSRValue": "0x0600400091",
591591         "Counter": "0,1,2,3",
592592         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
593593         "MSRIndex": "0x1a6,0x1a7",
594
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
594
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
595595         "SampleAfterValue": "100003",
596596         "CounterHTOff": "0,1,2,3"
597597     },
....@@ -599,12 +599,12 @@
599599         "Offcore": "1",
600600         "EventCode": "0xB7, 0xBB",
601601         "UMask": "0x1",
602
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram",
603
-        "MSRValue": "0x063f800091",
602
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
603
+        "MSRValue": "0x063F800091",
604604         "Counter": "0,1,2,3",
605605         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
606606         "MSRIndex": "0x1a6,0x1a7",
607
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
607
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
608608         "SampleAfterValue": "100003",
609609         "CounterHTOff": "0,1,2,3"
610610     },
....@@ -612,12 +612,12 @@
612612         "Offcore": "1",
613613         "EventCode": "0xB7, 0xBB",
614614         "UMask": "0x1",
615
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache",
616
-        "MSRValue": "0x103fc00091",
615
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
616
+        "MSRValue": "0x103FC00091",
617617         "Counter": "0,1,2,3",
618618         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
619619         "MSRIndex": "0x1a6,0x1a7",
620
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
620
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
621621         "SampleAfterValue": "100003",
622622         "CounterHTOff": "0,1,2,3"
623623     },
....@@ -625,12 +625,12 @@
625625         "Offcore": "1",
626626         "EventCode": "0xB7, 0xBB",
627627         "UMask": "0x1",
628
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache",
629
-        "MSRValue": "0x083fc00091",
628
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
629
+        "MSRValue": "0x083FC00091",
630630         "Counter": "0,1,2,3",
631631         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
632632         "MSRIndex": "0x1a6,0x1a7",
633
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
633
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
634634         "SampleAfterValue": "100003",
635635         "CounterHTOff": "0,1,2,3"
636636     },
....@@ -638,12 +638,12 @@
638638         "Offcore": "1",
639639         "EventCode": "0xB7, 0xBB",
640640         "UMask": "0x1",
641
-        "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3",
642
-        "MSRValue": "0x3fbfc00122",
641
+        "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
642
+        "MSRValue": "0x3FBFC00122",
643643         "Counter": "0,1,2,3",
644644         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
645645         "MSRIndex": "0x1a6,0x1a7",
646
-        "PublicDescription": "Counts all demand & prefetch RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
646
+        "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3",
647647         "SampleAfterValue": "100003",
648648         "CounterHTOff": "0,1,2,3"
649649     },
....@@ -651,12 +651,12 @@
651651         "Offcore": "1",
652652         "EventCode": "0xB7, 0xBB",
653653         "UMask": "0x1",
654
-        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram",
654
+        "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
655655         "MSRValue": "0x0600400122",
656656         "Counter": "0,1,2,3",
657657         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
658658         "MSRIndex": "0x1a6,0x1a7",
659
-        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
659
+        "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
660660         "SampleAfterValue": "100003",
661661         "CounterHTOff": "0,1,2,3"
662662     },
....@@ -664,12 +664,12 @@
664664         "Offcore": "1",
665665         "EventCode": "0xB7, 0xBB",
666666         "UMask": "0x1",
667
-        "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3",
668
-        "MSRValue": "0x3fbfc00244",
667
+        "BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
668
+        "MSRValue": "0x3FBFC00244",
669669         "Counter": "0,1,2,3",
670670         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
671671         "MSRIndex": "0x1a6,0x1a7",
672
-        "PublicDescription": "Counts all demand & prefetch code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
672
+        "PublicDescription": "Counts all demand & prefetch code reads miss in the L3",
673673         "SampleAfterValue": "100003",
674674         "CounterHTOff": "0,1,2,3"
675675     },
....@@ -677,12 +677,12 @@
677677         "Offcore": "1",
678678         "EventCode": "0xB7, 0xBB",
679679         "UMask": "0x1",
680
-        "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram",
680
+        "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
681681         "MSRValue": "0x0600400244",
682682         "Counter": "0,1,2,3",
683683         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
684684         "MSRIndex": "0x1a6,0x1a7",
685
-        "PublicDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
685
+        "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
686686         "SampleAfterValue": "100003",
687687         "CounterHTOff": "0,1,2,3"
688688     },
....@@ -690,12 +690,12 @@
690690         "Offcore": "1",
691691         "EventCode": "0xB7, 0xBB",
692692         "UMask": "0x1",
693
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3",
694
-        "MSRValue": "0x3fbfc007f7",
693
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
694
+        "MSRValue": "0x3FBFC007F7",
695695         "Counter": "0,1,2,3",
696696         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
697697         "MSRIndex": "0x1a6,0x1a7",
698
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
698
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
699699         "SampleAfterValue": "100003",
700700         "CounterHTOff": "0,1,2,3"
701701     },
....@@ -703,12 +703,12 @@
703703         "Offcore": "1",
704704         "EventCode": "0xB7, 0xBB",
705705         "UMask": "0x1",
706
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram",
707
-        "MSRValue": "0x06004007f7",
706
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
707
+        "MSRValue": "0x06004007F7",
708708         "Counter": "0,1,2,3",
709709         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
710710         "MSRIndex": "0x1a6,0x1a7",
711
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
711
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
712712         "SampleAfterValue": "100003",
713713         "CounterHTOff": "0,1,2,3"
714714     },
....@@ -716,12 +716,12 @@
716716         "Offcore": "1",
717717         "EventCode": "0xB7, 0xBB",
718718         "UMask": "0x1",
719
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram",
720
-        "MSRValue": "0x063f8007f7",
719
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
720
+        "MSRValue": "0x063F8007F7",
721721         "Counter": "0,1,2,3",
722722         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
723723         "MSRIndex": "0x1a6,0x1a7",
724
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
724
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
725725         "SampleAfterValue": "100003",
726726         "CounterHTOff": "0,1,2,3"
727727     },
....@@ -729,12 +729,12 @@
729729         "Offcore": "1",
730730         "EventCode": "0xB7, 0xBB",
731731         "UMask": "0x1",
732
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache",
733
-        "MSRValue": "0x103fc007f7",
732
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
733
+        "MSRValue": "0x103FC007F7",
734734         "Counter": "0,1,2,3",
735735         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
736736         "MSRIndex": "0x1a6,0x1a7",
737
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
737
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
738738         "SampleAfterValue": "100003",
739739         "CounterHTOff": "0,1,2,3"
740740     },
....@@ -742,12 +742,12 @@
742742         "Offcore": "1",
743743         "EventCode": "0xB7, 0xBB",
744744         "UMask": "0x1",
745
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache",
746
-        "MSRValue": "0x083fc007f7",
745
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
746
+        "MSRValue": "0x083FC007F7",
747747         "Counter": "0,1,2,3",
748748         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
749749         "MSRIndex": "0x1a6,0x1a7",
750
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
750
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
751751         "SampleAfterValue": "100003",
752752         "CounterHTOff": "0,1,2,3"
753753     },
....@@ -755,12 +755,12 @@
755755         "Offcore": "1",
756756         "EventCode": "0xB7, 0xBB",
757757         "UMask": "0x1",
758
-        "BriefDescription": "Counts all requests that miss in the L3",
759
-        "MSRValue": "0x3fbfc08fff",
758
+        "BriefDescription": "Counts all requests miss in the L3",
759
+        "MSRValue": "0x3FBFC08FFF",
760760         "Counter": "0,1,2,3",
761761         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
762762         "MSRIndex": "0x1a6,0x1a7",
763
-        "PublicDescription": "Counts all requests that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
763
+        "PublicDescription": "Counts all requests miss in the L3",
764764         "SampleAfterValue": "100003",
765765         "CounterHTOff": "0,1,2,3"
766766     }