forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/tools/perf/pmu-events/arch/x86/haswellx/cache.json
....@@ -64,18 +64,18 @@
6464     },
6565     {
6666         "EventCode": "0x24",
67
-        "UMask": "0x41",
67
+        "UMask": "0xc1",
6868         "BriefDescription": "Demand Data Read requests that hit L2 cache",
6969         "Counter": "0,1,2,3",
7070         "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
7171         "Errata": "HSD78",
72
-        "PublicDescription": "Demand data read requests that hit L2 cache.",
72
+        "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
7373         "SampleAfterValue": "200003",
7474         "CounterHTOff": "0,1,2,3,4,5,6,7"
7575     },
7676     {
7777         "EventCode": "0x24",
78
-        "UMask": "0x42",
78
+        "UMask": "0xc2",
7979         "BriefDescription": "RFO requests that hit L2 cache",
8080         "Counter": "0,1,2,3",
8181         "EventName": "L2_RQSTS.RFO_HIT",
....@@ -85,7 +85,7 @@
8585     },
8686     {
8787         "EventCode": "0x24",
88
-        "UMask": "0x44",
88
+        "UMask": "0xc4",
8989         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
9090         "Counter": "0,1,2,3",
9191         "EventName": "L2_RQSTS.CODE_RD_HIT",
....@@ -95,7 +95,7 @@
9595     },
9696     {
9797         "EventCode": "0x24",
98
-        "UMask": "0x50",
98
+        "UMask": "0xd0",
9999         "BriefDescription": "L2 prefetch requests that hit L2 cache",
100100         "Counter": "0,1,2,3",
101101         "EventName": "L2_RQSTS.L2_PF_HIT",
....@@ -416,7 +416,7 @@
416416     {
417417         "EventCode": "0xD0",
418418         "UMask": "0x11",
419
-        "BriefDescription": "Retired load uops that miss the STLB. (precise Event)",
419
+        "BriefDescription": "Retired load uops that miss the STLB.",
420420         "Data_LA": "1",
421421         "PEBS": "1",
422422         "Counter": "0,1,2,3",
....@@ -428,7 +428,7 @@
428428     {
429429         "EventCode": "0xD0",
430430         "UMask": "0x12",
431
-        "BriefDescription": "Retired store uops that miss the STLB. (precise Event)",
431
+        "BriefDescription": "Retired store uops that miss the STLB.",
432432         "Data_LA": "1",
433433         "PEBS": "1",
434434         "Counter": "0,1,2,3",
....@@ -441,7 +441,7 @@
441441     {
442442         "EventCode": "0xD0",
443443         "UMask": "0x21",
444
-        "BriefDescription": "Retired load uops with locked access. (precise Event)",
444
+        "BriefDescription": "Retired load uops with locked access.",
445445         "Data_LA": "1",
446446         "PEBS": "1",
447447         "Counter": "0,1,2,3",
....@@ -453,34 +453,32 @@
453453     {
454454         "EventCode": "0xD0",
455455         "UMask": "0x41",
456
-        "BriefDescription": "Retired load uops that split across a cacheline boundary. (precise Event)",
456
+        "BriefDescription": "Retired load uops that split across a cacheline boundary.",
457457         "Data_LA": "1",
458458         "PEBS": "1",
459459         "Counter": "0,1,2,3",
460460         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
461461         "Errata": "HSD29, HSM30",
462
-        "PublicDescription": "This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.",
463462         "SampleAfterValue": "100003",
464463         "CounterHTOff": "0,1,2,3"
465464     },
466465     {
467466         "EventCode": "0xD0",
468467         "UMask": "0x42",
469
-        "BriefDescription": "Retired store uops that split across a cacheline boundary. (precise Event)",
468
+        "BriefDescription": "Retired store uops that split across a cacheline boundary.",
470469         "Data_LA": "1",
471470         "PEBS": "1",
472471         "Counter": "0,1,2,3",
473472         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
474473         "Errata": "HSD29, HSM30",
475474         "L1_Hit_Indication": "1",
476
-        "PublicDescription": "This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.",
477475         "SampleAfterValue": "100003",
478476         "CounterHTOff": "0,1,2,3"
479477     },
480478     {
481479         "EventCode": "0xD0",
482480         "UMask": "0x81",
483
-        "BriefDescription": "All retired load uops. (precise Event)",
481
+        "BriefDescription": "All retired load uops.",
484482         "Data_LA": "1",
485483         "PEBS": "1",
486484         "Counter": "0,1,2,3",
....@@ -492,14 +490,13 @@
492490     {
493491         "EventCode": "0xD0",
494492         "UMask": "0x82",
495
-        "BriefDescription": "All retired store uops. (precise Event)",
493
+        "BriefDescription": "All retired store uops.",
496494         "Data_LA": "1",
497495         "PEBS": "1",
498496         "Counter": "0,1,2,3",
499497         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
500498         "Errata": "HSD29, HSM30",
501499         "L1_Hit_Indication": "1",
502
-        "PublicDescription": "This event counts all store uops retired. This is a precise event.",
503500         "SampleAfterValue": "2000003",
504501         "CounterHTOff": "0,1,2,3"
505502     },
....@@ -530,13 +527,13 @@
530527     {
531528         "EventCode": "0xD1",
532529         "UMask": "0x4",
533
-        "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
530
+        "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
534531         "Data_LA": "1",
535532         "PEBS": "1",
536533         "Counter": "0,1,2,3",
537534         "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
538535         "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
539
-        "PublicDescription": "This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event.",
536
+        "PublicDescription": "Retired load uops with L3 cache hits as data sources.",
540537         "SampleAfterValue": "50021",
541538         "CounterHTOff": "0,1,2,3"
542539     },
....@@ -549,19 +546,20 @@
549546         "Counter": "0,1,2,3",
550547         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
551548         "Errata": "HSM30",
552
-        "PublicDescription": "This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event.",
549
+        "PublicDescription": "Retired load uops missed L1 cache as data sources.",
553550         "SampleAfterValue": "100003",
554551         "CounterHTOff": "0,1,2,3"
555552     },
556553     {
557554         "EventCode": "0xD1",
558555         "UMask": "0x10",
559
-        "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
556
+        "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
560557         "Data_LA": "1",
561558         "PEBS": "1",
562559         "Counter": "0,1,2,3",
563560         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
564561         "Errata": "HSD29, HSM30",
562
+        "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",
565563         "SampleAfterValue": "50021",
566564         "CounterHTOff": "0,1,2,3"
567565     },
....@@ -574,6 +572,7 @@
574572         "Counter": "0,1,2,3",
575573         "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
576574         "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
575
+        "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .",
577576         "SampleAfterValue": "100003",
578577         "CounterHTOff": "0,1,2,3"
579578     },
....@@ -604,26 +603,24 @@
604603     {
605604         "EventCode": "0xD2",
606605         "UMask": "0x2",
607
-        "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. ",
606
+        "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
608607         "Data_LA": "1",
609608         "PEBS": "1",
610609         "Counter": "0,1,2,3",
611610         "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
612611         "Errata": "HSD29, HSD25, HSM26, HSM30",
613
-        "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.",
614612         "SampleAfterValue": "20011",
615613         "CounterHTOff": "0,1,2,3"
616614     },
617615     {
618616         "EventCode": "0xD2",
619617         "UMask": "0x4",
620
-        "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. ",
618
+        "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
621619         "Data_LA": "1",
622620         "PEBS": "1",
623621         "Counter": "0,1,2,3",
624622         "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
625623         "Errata": "HSD29, HSD25, HSM26, HSM30",
626
-        "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.",
627624         "SampleAfterValue": "20011",
628625         "CounterHTOff": "0,1,2,3"
629626     },
....@@ -642,19 +639,20 @@
642639     {
643640         "EventCode": "0xD3",
644641         "UMask": "0x1",
642
+        "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
645643         "Data_LA": "1",
646644         "PEBS": "1",
647645         "Counter": "0,1,2,3",
648646         "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
649647         "Errata": "HSD74, HSD29, HSD25, HSM30",
650
-        "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.",
648
+        "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.",
651649         "SampleAfterValue": "100003",
652650         "CounterHTOff": "0,1,2,3"
653651     },
654652     {
655653         "EventCode": "0xD3",
656654         "UMask": "0x4",
657
-        "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)",
655
+        "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",
658656         "Data_LA": "1",
659657         "PEBS": "1",
660658         "Counter": "0,1,2,3",
....@@ -666,7 +664,7 @@
666664     {
667665         "EventCode": "0xD3",
668666         "UMask": "0x10",
669
-        "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)",
667
+        "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",
670668         "Data_LA": "1",
671669         "PEBS": "1",
672670         "Counter": "0,1,2,3",
....@@ -678,7 +676,7 @@
678676     {
679677         "EventCode": "0xD3",
680678         "UMask": "0x20",
681
-        "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)",
679
+        "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",
682680         "Data_LA": "1",
683681         "PEBS": "1",
684682         "Counter": "0,1,2,3",
....@@ -833,7 +831,6 @@
833831         "BriefDescription": "Split locks in SQ",
834832         "Counter": "0,1,2,3",
835833         "EventName": "SQ_MISC.SPLIT_LOCK",
836
-        "PublicDescription": "",
837834         "SampleAfterValue": "100003",
838835         "CounterHTOff": "0,1,2,3,4,5,6,7"
839836     },
....@@ -841,12 +838,12 @@
841838         "Offcore": "1",
842839         "EventCode": "0xB7, 0xBB",
843840         "UMask": "0x1",
844
-        "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
845
-        "MSRValue": "0x04003c0001",
841
+        "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
842
+        "MSRValue": "0x04003C0001",
846843         "Counter": "0,1,2,3",
847844         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
848845         "MSRIndex": "0x1a6,0x1a7",
849
-        "PublicDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
846
+        "PublicDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
850847         "SampleAfterValue": "100003",
851848         "CounterHTOff": "0,1,2,3"
852849     },
....@@ -854,12 +851,12 @@
854851         "Offcore": "1",
855852         "EventCode": "0xB7, 0xBB",
856853         "UMask": "0x1",
857
-        "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
858
-        "MSRValue": "0x10003c0001",
854
+        "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
855
+        "MSRValue": "0x10003C0001",
859856         "Counter": "0,1,2,3",
860857         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
861858         "MSRIndex": "0x1a6,0x1a7",
862
-        "PublicDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
859
+        "PublicDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
863860         "SampleAfterValue": "100003",
864861         "CounterHTOff": "0,1,2,3"
865862     },
....@@ -867,12 +864,12 @@
867864         "Offcore": "1",
868865         "EventCode": "0xB7, 0xBB",
869866         "UMask": "0x1",
870
-        "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
871
-        "MSRValue": "0x04003c0002",
867
+        "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
868
+        "MSRValue": "0x04003C0002",
872869         "Counter": "0,1,2,3",
873870         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
874871         "MSRIndex": "0x1a6,0x1a7",
875
-        "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
872
+        "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
876873         "SampleAfterValue": "100003",
877874         "CounterHTOff": "0,1,2,3"
878875     },
....@@ -880,12 +877,12 @@
880877         "Offcore": "1",
881878         "EventCode": "0xB7, 0xBB",
882879         "UMask": "0x1",
883
-        "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
884
-        "MSRValue": "0x10003c0002",
880
+        "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
881
+        "MSRValue": "0x10003C0002",
885882         "Counter": "0,1,2,3",
886883         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
887884         "MSRIndex": "0x1a6,0x1a7",
888
-        "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
885
+        "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
889886         "SampleAfterValue": "100003",
890887         "CounterHTOff": "0,1,2,3"
891888     },
....@@ -893,12 +890,12 @@
893890         "Offcore": "1",
894891         "EventCode": "0xB7, 0xBB",
895892         "UMask": "0x1",
896
-        "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
897
-        "MSRValue": "0x04003c0004",
893
+        "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
894
+        "MSRValue": "0x04003C0004",
898895         "Counter": "0,1,2,3",
899896         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
900897         "MSRIndex": "0x1a6,0x1a7",
901
-        "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
898
+        "PublicDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
902899         "SampleAfterValue": "100003",
903900         "CounterHTOff": "0,1,2,3"
904901     },
....@@ -906,12 +903,12 @@
906903         "Offcore": "1",
907904         "EventCode": "0xB7, 0xBB",
908905         "UMask": "0x1",
909
-        "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
910
-        "MSRValue": "0x10003c0004",
906
+        "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
907
+        "MSRValue": "0x10003C0004",
911908         "Counter": "0,1,2,3",
912909         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE",
913910         "MSRIndex": "0x1a6,0x1a7",
914
-        "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
911
+        "PublicDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
915912         "SampleAfterValue": "100003",
916913         "CounterHTOff": "0,1,2,3"
917914     },
....@@ -919,12 +916,12 @@
919916         "Offcore": "1",
920917         "EventCode": "0xB7, 0xBB",
921918         "UMask": "0x1",
922
-        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3",
923
-        "MSRValue": "0x3f803c0010",
919
+        "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
920
+        "MSRValue": "0x3F803C0010",
924921         "Counter": "0,1,2,3",
925922         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
926923         "MSRIndex": "0x1a6,0x1a7",
927
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
924
+        "PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
928925         "SampleAfterValue": "100003",
929926         "CounterHTOff": "0,1,2,3"
930927     },
....@@ -932,12 +929,12 @@
932929         "Offcore": "1",
933930         "EventCode": "0xB7, 0xBB",
934931         "UMask": "0x1",
935
-        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3",
936
-        "MSRValue": "0x3f803c0020",
932
+        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
933
+        "MSRValue": "0x3F803C0020",
937934         "Counter": "0,1,2,3",
938935         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE",
939936         "MSRIndex": "0x1a6,0x1a7",
940
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
937
+        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
941938         "SampleAfterValue": "100003",
942939         "CounterHTOff": "0,1,2,3"
943940     },
....@@ -945,12 +942,12 @@
945942         "Offcore": "1",
946943         "EventCode": "0xB7, 0xBB",
947944         "UMask": "0x1",
948
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3",
949
-        "MSRValue": "0x3f803c0040",
945
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
946
+        "MSRValue": "0x3F803C0040",
950947         "Counter": "0,1,2,3",
951948         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
952949         "MSRIndex": "0x1a6,0x1a7",
953
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
950
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
954951         "SampleAfterValue": "100003",
955952         "CounterHTOff": "0,1,2,3"
956953     },
....@@ -958,12 +955,12 @@
958955         "Offcore": "1",
959956         "EventCode": "0xB7, 0xBB",
960957         "UMask": "0x1",
961
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3",
962
-        "MSRValue": "0x3f803c0080",
958
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
959
+        "MSRValue": "0x3F803C0080",
963960         "Counter": "0,1,2,3",
964961         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
965962         "MSRIndex": "0x1a6,0x1a7",
966
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
963
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
967964         "SampleAfterValue": "100003",
968965         "CounterHTOff": "0,1,2,3"
969966     },
....@@ -971,12 +968,12 @@
971968         "Offcore": "1",
972969         "EventCode": "0xB7, 0xBB",
973970         "UMask": "0x1",
974
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3",
975
-        "MSRValue": "0x3f803c0100",
971
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
972
+        "MSRValue": "0x3F803C0100",
976973         "Counter": "0,1,2,3",
977974         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
978975         "MSRIndex": "0x1a6,0x1a7",
979
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
976
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
980977         "SampleAfterValue": "100003",
981978         "CounterHTOff": "0,1,2,3"
982979     },
....@@ -984,12 +981,12 @@
984981         "Offcore": "1",
985982         "EventCode": "0xB7, 0xBB",
986983         "UMask": "0x1",
987
-        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3",
988
-        "MSRValue": "0x3f803c0200",
984
+        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
985
+        "MSRValue": "0x3F803C0200",
989986         "Counter": "0,1,2,3",
990987         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
991988         "MSRIndex": "0x1a6,0x1a7",
992
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
989
+        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
993990         "SampleAfterValue": "100003",
994991         "CounterHTOff": "0,1,2,3"
995992     },
....@@ -997,12 +994,12 @@
997994         "Offcore": "1",
998995         "EventCode": "0xB7, 0xBB",
999996         "UMask": "0x1",
1000
-        "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1001
-        "MSRValue": "0x04003c0091",
997
+        "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
998
+        "MSRValue": "0x04003C0091",
1002999         "Counter": "0,1,2,3",
10031000         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
10041001         "MSRIndex": "0x1a6,0x1a7",
1005
-        "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1002
+        "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
10061003         "SampleAfterValue": "100003",
10071004         "CounterHTOff": "0,1,2,3"
10081005     },
....@@ -1010,12 +1007,12 @@
10101007         "Offcore": "1",
10111008         "EventCode": "0xB7, 0xBB",
10121009         "UMask": "0x1",
1013
-        "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1014
-        "MSRValue": "0x10003c0091",
1010
+        "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1011
+        "MSRValue": "0x10003C0091",
10151012         "Counter": "0,1,2,3",
10161013         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
10171014         "MSRIndex": "0x1a6,0x1a7",
1018
-        "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1015
+        "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
10191016         "SampleAfterValue": "100003",
10201017         "CounterHTOff": "0,1,2,3"
10211018     },
....@@ -1023,12 +1020,12 @@
10231020         "Offcore": "1",
10241021         "EventCode": "0xB7, 0xBB",
10251022         "UMask": "0x1",
1026
-        "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1027
-        "MSRValue": "0x04003c0122",
1023
+        "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1024
+        "MSRValue": "0x04003C0122",
10281025         "Counter": "0,1,2,3",
10291026         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
10301027         "MSRIndex": "0x1a6,0x1a7",
1031
-        "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1028
+        "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
10321029         "SampleAfterValue": "100003",
10331030         "CounterHTOff": "0,1,2,3"
10341031     },
....@@ -1036,12 +1033,12 @@
10361033         "Offcore": "1",
10371034         "EventCode": "0xB7, 0xBB",
10381035         "UMask": "0x1",
1039
-        "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1040
-        "MSRValue": "0x10003c0122",
1036
+        "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1037
+        "MSRValue": "0x10003C0122",
10411038         "Counter": "0,1,2,3",
10421039         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
10431040         "MSRIndex": "0x1a6,0x1a7",
1044
-        "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1041
+        "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
10451042         "SampleAfterValue": "100003",
10461043         "CounterHTOff": "0,1,2,3"
10471044     },
....@@ -1049,12 +1046,12 @@
10491046         "Offcore": "1",
10501047         "EventCode": "0xB7, 0xBB",
10511048         "UMask": "0x1",
1052
-        "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1053
-        "MSRValue": "0x04003c0244",
1049
+        "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1050
+        "MSRValue": "0x04003C0244",
10541051         "Counter": "0,1,2,3",
10551052         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
10561053         "MSRIndex": "0x1a6,0x1a7",
1057
-        "PublicDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1054
+        "PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
10581055         "SampleAfterValue": "100003",
10591056         "CounterHTOff": "0,1,2,3"
10601057     },
....@@ -1062,12 +1059,12 @@
10621059         "Offcore": "1",
10631060         "EventCode": "0xB7, 0xBB",
10641061         "UMask": "0x1",
1065
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1066
-        "MSRValue": "0x04003c07f7",
1062
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1063
+        "MSRValue": "0x04003C07F7",
10671064         "Counter": "0,1,2,3",
10681065         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
10691066         "MSRIndex": "0x1a6,0x1a7",
1070
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1067
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
10711068         "SampleAfterValue": "100003",
10721069         "CounterHTOff": "0,1,2,3"
10731070     },
....@@ -1075,12 +1072,12 @@
10751072         "Offcore": "1",
10761073         "EventCode": "0xB7, 0xBB",
10771074         "UMask": "0x1",
1078
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1079
-        "MSRValue": "0x10003c07f7",
1075
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1076
+        "MSRValue": "0x10003C07F7",
10801077         "Counter": "0,1,2,3",
10811078         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
10821079         "MSRIndex": "0x1a6,0x1a7",
1083
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1080
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
10841081         "SampleAfterValue": "100003",
10851082         "CounterHTOff": "0,1,2,3"
10861083     },
....@@ -1088,12 +1085,12 @@
10881085         "Offcore": "1",
10891086         "EventCode": "0xB7, 0xBB",
10901087         "UMask": "0x1",
1091
-        "BriefDescription": "Counts all requests that hit in the L3",
1092
-        "MSRValue": "0x3f803c8fff",
1088
+        "BriefDescription": "Counts all requests hit in the L3",
1089
+        "MSRValue": "0x3F803C8FFF",
10931090         "Counter": "0,1,2,3",
10941091         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",
10951092         "MSRIndex": "0x1a6,0x1a7",
1096
-        "PublicDescription": "Counts all requests that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1093
+        "PublicDescription": "Counts all requests hit in the L3",
10971094         "SampleAfterValue": "100003",
10981095         "CounterHTOff": "0,1,2,3"
10991096     }