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hc
2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/tools/perf/pmu-events/arch/x86/broadwellx/memory.json
....@@ -170,11 +170,11 @@
170170     {
171171         "EventCode": "0xc8",
172172         "UMask": "0x4",
173
-        "BriefDescription": "Number of times HLE abort was triggered (PEBS)",
173
+        "BriefDescription": "Number of times HLE abort was triggered",
174174         "PEBS": "1",
175175         "Counter": "0,1,2,3",
176176         "EventName": "HLE_RETIRED.ABORTED",
177
-        "PublicDescription": "Number of times HLE abort was triggered (PEBS).",
177
+        "PublicDescription": "Number of times HLE abort was triggered.",
178178         "SampleAfterValue": "2000003",
179179         "CounterHTOff": "0,1,2,3,4,5,6,7"
180180     },
....@@ -251,11 +251,11 @@
251251     {
252252         "EventCode": "0xc9",
253253         "UMask": "0x4",
254
-        "BriefDescription": "Number of times RTM abort was triggered (PEBS)",
254
+        "BriefDescription": "Number of times RTM abort was triggered",
255255         "PEBS": "1",
256256         "Counter": "0,1,2,3",
257257         "EventName": "RTM_RETIRED.ABORTED",
258
-        "PublicDescription": "Number of times RTM abort was triggered (PEBS).",
258
+        "PublicDescription": "Number of times RTM abort was triggered .",
259259         "SampleAfterValue": "2000003",
260260         "CounterHTOff": "0,1,2,3"
261261     },
....@@ -312,14 +312,14 @@
312312     {
313313         "EventCode": "0xCD",
314314         "UMask": "0x1",
315
-        "BriefDescription": "Loads with latency value being above 4",
315
+        "BriefDescription": "Randomly selected loads with latency value being above 4",
316316         "PEBS": "2",
317317         "MSRValue": "0x4",
318318         "Counter": "3",
319319         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
320320         "MSRIndex": "0x3F6",
321321         "Errata": "BDM100, BDM35",
322
-        "PublicDescription": "This event counts loads with latency value being above four.",
322
+        "PublicDescription": "Counts randomly selected loads with latency value being above four.",
323323         "TakenAlone": "1",
324324         "SampleAfterValue": "100003",
325325         "CounterHTOff": "3"
....@@ -327,14 +327,14 @@
327327     {
328328         "EventCode": "0xCD",
329329         "UMask": "0x1",
330
-        "BriefDescription": "Loads with latency value being above 8",
330
+        "BriefDescription": "Randomly selected loads with latency value being above 8",
331331         "PEBS": "2",
332332         "MSRValue": "0x8",
333333         "Counter": "3",
334334         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
335335         "MSRIndex": "0x3F6",
336336         "Errata": "BDM100, BDM35",
337
-        "PublicDescription": "This event counts loads with latency value being above eight.",
337
+        "PublicDescription": "Counts randomly selected loads with latency value being above eight.",
338338         "TakenAlone": "1",
339339         "SampleAfterValue": "50021",
340340         "CounterHTOff": "3"
....@@ -342,14 +342,14 @@
342342     {
343343         "EventCode": "0xCD",
344344         "UMask": "0x1",
345
-        "BriefDescription": "Loads with latency value being above 16",
345
+        "BriefDescription": "Randomly selected loads with latency value being above 16",
346346         "PEBS": "2",
347347         "MSRValue": "0x10",
348348         "Counter": "3",
349349         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
350350         "MSRIndex": "0x3F6",
351351         "Errata": "BDM100, BDM35",
352
-        "PublicDescription": "This event counts loads with latency value being above 16.",
352
+        "PublicDescription": "Counts randomly selected loads with latency value being above 16.",
353353         "TakenAlone": "1",
354354         "SampleAfterValue": "20011",
355355         "CounterHTOff": "3"
....@@ -357,14 +357,14 @@
357357     {
358358         "EventCode": "0xCD",
359359         "UMask": "0x1",
360
-        "BriefDescription": "Loads with latency value being above 32",
360
+        "BriefDescription": "Randomly selected loads with latency value being above 32",
361361         "PEBS": "2",
362362         "MSRValue": "0x20",
363363         "Counter": "3",
364364         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
365365         "MSRIndex": "0x3F6",
366366         "Errata": "BDM100, BDM35",
367
-        "PublicDescription": "This event counts loads with latency value being above 32.",
367
+        "PublicDescription": "Counts randomly selected loads with latency value being above 32.",
368368         "TakenAlone": "1",
369369         "SampleAfterValue": "100007",
370370         "CounterHTOff": "3"
....@@ -372,14 +372,14 @@
372372     {
373373         "EventCode": "0xCD",
374374         "UMask": "0x1",
375
-        "BriefDescription": "Loads with latency value being above 64",
375
+        "BriefDescription": "Randomly selected loads with latency value being above 64",
376376         "PEBS": "2",
377377         "MSRValue": "0x40",
378378         "Counter": "3",
379379         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
380380         "MSRIndex": "0x3F6",
381381         "Errata": "BDM100, BDM35",
382
-        "PublicDescription": "This event counts loads with latency value being above 64.",
382
+        "PublicDescription": "Counts randomly selected loads with latency value being above 64.",
383383         "TakenAlone": "1",
384384         "SampleAfterValue": "2003",
385385         "CounterHTOff": "3"
....@@ -387,14 +387,14 @@
387387     {
388388         "EventCode": "0xCD",
389389         "UMask": "0x1",
390
-        "BriefDescription": "Loads with latency value being above 128",
390
+        "BriefDescription": "Randomly selected loads with latency value being above 128",
391391         "PEBS": "2",
392392         "MSRValue": "0x80",
393393         "Counter": "3",
394394         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
395395         "MSRIndex": "0x3F6",
396396         "Errata": "BDM100, BDM35",
397
-        "PublicDescription": "This event counts loads with latency value being above 128.",
397
+        "PublicDescription": "Counts randomly selected loads with latency value being above 128.",
398398         "TakenAlone": "1",
399399         "SampleAfterValue": "1009",
400400         "CounterHTOff": "3"
....@@ -402,14 +402,14 @@
402402     {
403403         "EventCode": "0xCD",
404404         "UMask": "0x1",
405
-        "BriefDescription": "Loads with latency value being above 256",
405
+        "BriefDescription": "Randomly selected loads with latency value being above 256",
406406         "PEBS": "2",
407407         "MSRValue": "0x100",
408408         "Counter": "3",
409409         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
410410         "MSRIndex": "0x3F6",
411411         "Errata": "BDM100, BDM35",
412
-        "PublicDescription": "This event counts loads with latency value being above 256.",
412
+        "PublicDescription": "Counts randomly selected loads with latency value being above 256.",
413413         "TakenAlone": "1",
414414         "SampleAfterValue": "503",
415415         "CounterHTOff": "3"
....@@ -417,14 +417,14 @@
417417     {
418418         "EventCode": "0xCD",
419419         "UMask": "0x1",
420
-        "BriefDescription": "Loads with latency value being above 512",
420
+        "BriefDescription": "Randomly selected loads with latency value being above 512",
421421         "PEBS": "2",
422422         "MSRValue": "0x200",
423423         "Counter": "3",
424424         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
425425         "MSRIndex": "0x3F6",
426426         "Errata": "BDM100, BDM35",
427
-        "PublicDescription": "This event counts loads with latency value being above 512.",
427
+        "PublicDescription": "Counts randomly selected loads with latency value being above 512.",
428428         "TakenAlone": "1",
429429         "SampleAfterValue": "101",
430430         "CounterHTOff": "3"
....@@ -433,12 +433,12 @@
433433         "Offcore": "1",
434434         "EventCode": "0xB7, 0xBB",
435435         "UMask": "0x1",
436
-        "BriefDescription": "Counts all requests that miss in the L3",
437
-        "MSRValue": "0x3fbfc08fff",
436
+        "BriefDescription": "Counts all requests miss in the L3",
437
+        "MSRValue": "0x3FBFC08FFF",
438438         "Counter": "0,1,2,3",
439439         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
440440         "MSRIndex": "0x1a6,0x1a7",
441
-        "PublicDescription": "Counts all requests that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
441
+        "PublicDescription": "Counts all requests miss in the L3",
442442         "SampleAfterValue": "100003",
443443         "CounterHTOff": "0,1,2,3"
444444     },
....@@ -446,12 +446,12 @@
446446         "Offcore": "1",
447447         "EventCode": "0xB7, 0xBB",
448448         "UMask": "0x1",
449
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache",
450
-        "MSRValue": "0x087fc007f7",
449
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
450
+        "MSRValue": "0x087FC007F7",
451451         "Counter": "0,1,2,3",
452452         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
453453         "MSRIndex": "0x1a6,0x1a7",
454
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
454
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
455455         "SampleAfterValue": "100003",
456456         "CounterHTOff": "0,1,2,3"
457457     },
....@@ -459,12 +459,12 @@
459459         "Offcore": "1",
460460         "EventCode": "0xB7, 0xBB",
461461         "UMask": "0x1",
462
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache",
463
-        "MSRValue": "0x103fc007f7",
462
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
463
+        "MSRValue": "0x103FC007F7",
464464         "Counter": "0,1,2,3",
465465         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
466466         "MSRIndex": "0x1a6,0x1a7",
467
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
467
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
468468         "SampleAfterValue": "100003",
469469         "CounterHTOff": "0,1,2,3"
470470     },
....@@ -472,12 +472,12 @@
472472         "Offcore": "1",
473473         "EventCode": "0xB7, 0xBB",
474474         "UMask": "0x1",
475
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram",
476
-        "MSRValue": "0x063bc007f7",
475
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
476
+        "MSRValue": "0x063BC007F7",
477477         "Counter": "0,1,2,3",
478478         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
479479         "MSRIndex": "0x1a6,0x1a7",
480
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
480
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
481481         "SampleAfterValue": "100003",
482482         "CounterHTOff": "0,1,2,3"
483483     },
....@@ -485,12 +485,12 @@
485485         "Offcore": "1",
486486         "EventCode": "0xB7, 0xBB",
487487         "UMask": "0x1",
488
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram",
489
-        "MSRValue": "0x06040007f7",
488
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
489
+        "MSRValue": "0x06040007F7",
490490         "Counter": "0,1,2,3",
491491         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
492492         "MSRIndex": "0x1a6,0x1a7",
493
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
493
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
494494         "SampleAfterValue": "100003",
495495         "CounterHTOff": "0,1,2,3"
496496     },
....@@ -498,12 +498,12 @@
498498         "Offcore": "1",
499499         "EventCode": "0xB7, 0xBB",
500500         "UMask": "0x1",
501
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3",
502
-        "MSRValue": "0x3fbfc007f7",
501
+        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
502
+        "MSRValue": "0x3FBFC007F7",
503503         "Counter": "0,1,2,3",
504504         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
505505         "MSRIndex": "0x1a6,0x1a7",
506
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
506
+        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
507507         "SampleAfterValue": "100003",
508508         "CounterHTOff": "0,1,2,3"
509509     },
....@@ -511,12 +511,12 @@
511511         "Offcore": "1",
512512         "EventCode": "0xB7, 0xBB",
513513         "UMask": "0x1",
514
-        "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram",
514
+        "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
515515         "MSRValue": "0x0604000244",
516516         "Counter": "0,1,2,3",
517517         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
518518         "MSRIndex": "0x1a6,0x1a7",
519
-        "PublicDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
519
+        "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
520520         "SampleAfterValue": "100003",
521521         "CounterHTOff": "0,1,2,3"
522522     },
....@@ -524,12 +524,12 @@
524524         "Offcore": "1",
525525         "EventCode": "0xB7, 0xBB",
526526         "UMask": "0x1",
527
-        "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3",
528
-        "MSRValue": "0x3fbfc00244",
527
+        "BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
528
+        "MSRValue": "0x3FBFC00244",
529529         "Counter": "0,1,2,3",
530530         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
531531         "MSRIndex": "0x1a6,0x1a7",
532
-        "PublicDescription": "Counts all demand & prefetch code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
532
+        "PublicDescription": "Counts all demand & prefetch code reads miss in the L3",
533533         "SampleAfterValue": "100003",
534534         "CounterHTOff": "0,1,2,3"
535535     },
....@@ -537,12 +537,12 @@
537537         "Offcore": "1",
538538         "EventCode": "0xB7, 0xBB",
539539         "UMask": "0x1",
540
-        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram",
540
+        "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
541541         "MSRValue": "0x0604000122",
542542         "Counter": "0,1,2,3",
543543         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
544544         "MSRIndex": "0x1a6,0x1a7",
545
-        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
545
+        "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
546546         "SampleAfterValue": "100003",
547547         "CounterHTOff": "0,1,2,3"
548548     },
....@@ -550,12 +550,12 @@
550550         "Offcore": "1",
551551         "EventCode": "0xB7, 0xBB",
552552         "UMask": "0x1",
553
-        "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3",
554
-        "MSRValue": "0x3fbfc00122",
553
+        "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
554
+        "MSRValue": "0x3FBFC00122",
555555         "Counter": "0,1,2,3",
556556         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
557557         "MSRIndex": "0x1a6,0x1a7",
558
-        "PublicDescription": "Counts all demand & prefetch RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
558
+        "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3",
559559         "SampleAfterValue": "100003",
560560         "CounterHTOff": "0,1,2,3"
561561     },
....@@ -563,12 +563,12 @@
563563         "Offcore": "1",
564564         "EventCode": "0xB7, 0xBB",
565565         "UMask": "0x1",
566
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache",
567
-        "MSRValue": "0x087fc00091",
566
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
567
+        "MSRValue": "0x087FC00091",
568568         "Counter": "0,1,2,3",
569569         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
570570         "MSRIndex": "0x1a6,0x1a7",
571
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
571
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
572572         "SampleAfterValue": "100003",
573573         "CounterHTOff": "0,1,2,3"
574574     },
....@@ -576,12 +576,12 @@
576576         "Offcore": "1",
577577         "EventCode": "0xB7, 0xBB",
578578         "UMask": "0x1",
579
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache",
580
-        "MSRValue": "0x103fc00091",
579
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
580
+        "MSRValue": "0x103FC00091",
581581         "Counter": "0,1,2,3",
582582         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
583583         "MSRIndex": "0x1a6,0x1a7",
584
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
584
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
585585         "SampleAfterValue": "100003",
586586         "CounterHTOff": "0,1,2,3"
587587     },
....@@ -589,12 +589,12 @@
589589         "Offcore": "1",
590590         "EventCode": "0xB7, 0xBB",
591591         "UMask": "0x1",
592
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram",
593
-        "MSRValue": "0x063bc00091",
592
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
593
+        "MSRValue": "0x063BC00091",
594594         "Counter": "0,1,2,3",
595595         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
596596         "MSRIndex": "0x1a6,0x1a7",
597
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
597
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
598598         "SampleAfterValue": "100003",
599599         "CounterHTOff": "0,1,2,3"
600600     },
....@@ -602,12 +602,12 @@
602602         "Offcore": "1",
603603         "EventCode": "0xB7, 0xBB",
604604         "UMask": "0x1",
605
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram",
605
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
606606         "MSRValue": "0x0604000091",
607607         "Counter": "0,1,2,3",
608608         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
609609         "MSRIndex": "0x1a6,0x1a7",
610
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
610
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
611611         "SampleAfterValue": "100003",
612612         "CounterHTOff": "0,1,2,3"
613613     },
....@@ -615,12 +615,12 @@
615615         "Offcore": "1",
616616         "EventCode": "0xB7, 0xBB",
617617         "UMask": "0x1",
618
-        "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3",
619
-        "MSRValue": "0x3fbfc00091",
618
+        "BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
619
+        "MSRValue": "0x3FBFC00091",
620620         "Counter": "0,1,2,3",
621621         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
622622         "MSRIndex": "0x1a6,0x1a7",
623
-        "PublicDescription": "Counts all demand & prefetch data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
623
+        "PublicDescription": "Counts all demand & prefetch data reads miss in the L3",
624624         "SampleAfterValue": "100003",
625625         "CounterHTOff": "0,1,2,3"
626626     },
....@@ -628,12 +628,12 @@
628628         "Offcore": "1",
629629         "EventCode": "0xB7, 0xBB",
630630         "UMask": "0x1",
631
-        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3",
632
-        "MSRValue": "0x3fbfc00200",
631
+        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
632
+        "MSRValue": "0x3FBFC00200",
633633         "Counter": "0,1,2,3",
634634         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
635635         "MSRIndex": "0x1a6,0x1a7",
636
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
636
+        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
637637         "SampleAfterValue": "100003",
638638         "CounterHTOff": "0,1,2,3"
639639     },
....@@ -641,12 +641,12 @@
641641         "Offcore": "1",
642642         "EventCode": "0xB7, 0xBB",
643643         "UMask": "0x1",
644
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3",
645
-        "MSRValue": "0x3fbfc00100",
644
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
645
+        "MSRValue": "0x3FBFC00100",
646646         "Counter": "0,1,2,3",
647647         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
648648         "MSRIndex": "0x1a6,0x1a7",
649
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
649
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
650650         "SampleAfterValue": "100003",
651651         "CounterHTOff": "0,1,2,3"
652652     },
....@@ -654,12 +654,12 @@
654654         "Offcore": "1",
655655         "EventCode": "0xB7, 0xBB",
656656         "UMask": "0x1",
657
-        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache",
658
-        "MSRValue": "0x103fc00002",
657
+        "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
658
+        "MSRValue": "0x103FC00002",
659659         "Counter": "0,1,2,3",
660660         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
661661         "MSRIndex": "0x1a6,0x1a7",
662
-        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
662
+        "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
663663         "SampleAfterValue": "100003",
664664         "CounterHTOff": "0,1,2,3"
665665     },
....@@ -667,12 +667,12 @@
667667         "Offcore": "1",
668668         "EventCode": "0xB7, 0xBB",
669669         "UMask": "0x1",
670
-        "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3",
671
-        "MSRValue": "0x3fbfc00002",
670
+        "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
671
+        "MSRValue": "0x3FBFC00002",
672672         "Counter": "0,1,2,3",
673673         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
674674         "MSRIndex": "0x1a6,0x1a7",
675
-        "PublicDescription": "Counts all demand data writes (RFOs) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
675
+        "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3",
676676         "SampleAfterValue": "100003",
677677         "CounterHTOff": "0,1,2,3"
678678     }