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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/include/uapi/gpu/arm/bifrost/gpu/mali_kbase_gpu_regmap.h
....@@ -1,7 +1,7 @@
11 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
22 /*
33  *
4
- * (C) COPYRIGHT 2021 ARM Limited. All rights reserved.
4
+ * (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved.
55  *
66  * This program is free software and is provided to you under the terms of the
77  * GNU General Public License version 2 as published by the Free Software
....@@ -22,83 +22,22 @@
2222 #ifndef _UAPI_KBASE_GPU_REGMAP_H_
2323 #define _UAPI_KBASE_GPU_REGMAP_H_
2424 
25
-#include "mali_kbase_gpu_coherency.h"
26
-#include "mali_kbase_gpu_id.h"
2725 #if MALI_USE_CSF
2826 #include "backend/mali_kbase_gpu_regmap_csf.h"
2927 #else
3028 #include "backend/mali_kbase_gpu_regmap_jm.h"
31
-#endif
29
+#endif /* !MALI_USE_CSF */
3230 
3331 /* Begin Register Offsets */
3432 /* GPU control registers */
3533 
3634 #define GPU_CONTROL_BASE        0x0000
3735 #define GPU_CONTROL_REG(r)      (GPU_CONTROL_BASE + (r))
36
+
3837 #define GPU_ID                  0x000   /* (RO) GPU and revision identifier */
39
-#define L2_FEATURES             0x004   /* (RO) Level 2 cache features */
40
-#define TILER_FEATURES          0x00C   /* (RO) Tiler Features */
41
-#define MEM_FEATURES            0x010   /* (RO) Memory system features */
42
-#define MMU_FEATURES            0x014   /* (RO) MMU features */
43
-#define AS_PRESENT              0x018   /* (RO) Address space slots present */
44
-#define GPU_IRQ_RAWSTAT         0x020   /* (RW) */
38
+
4539 #define GPU_IRQ_CLEAR           0x024   /* (WO) */
46
-#define GPU_IRQ_MASK            0x028   /* (RW) */
4740 #define GPU_IRQ_STATUS          0x02C   /* (RO) */
48
-
49
-#define GPU_COMMAND             0x030   /* (WO) */
50
-#define GPU_STATUS              0x034   /* (RO) */
51
-
52
-#define GPU_DBGEN               (1 << 8)    /* DBGEN wire status */
53
-
54
-#define GPU_FAULTSTATUS         0x03C   /* (RO) GPU exception type and fault status */
55
-#define GPU_FAULTADDRESS_LO     0x040   /* (RO) GPU exception fault address, low word */
56
-#define GPU_FAULTADDRESS_HI     0x044   /* (RO) GPU exception fault address, high word */
57
-
58
-#define L2_CONFIG               0x048   /* (RW) Level 2 cache configuration */
59
-
60
-#define GROUPS_L2_COHERENT      (1 << 0) /* Cores groups are l2 coherent */
61
-#define SUPER_L2_COHERENT       (1 << 1) /* Shader cores within a core
62
-					  * supergroup are l2 coherent
63
-					  */
64
-
65
-#define PWR_KEY                 0x050   /* (WO) Power manager key register */
66
-#define PWR_OVERRIDE0           0x054   /* (RW) Power manager override settings */
67
-#define PWR_OVERRIDE1           0x058   /* (RW) Power manager override settings */
68
-#define GPU_FEATURES_LO         0x060   /* (RO) GPU features, low word */
69
-#define GPU_FEATURES_HI         0x064   /* (RO) GPU features, high word */
70
-#define PRFCNT_FEATURES         0x068   /* (RO) Performance counter features */
71
-#define TIMESTAMP_OFFSET_LO     0x088   /* (RW) Global time stamp offset, low word */
72
-#define TIMESTAMP_OFFSET_HI     0x08C   /* (RW) Global time stamp offset, high word */
73
-#define CYCLE_COUNT_LO          0x090   /* (RO) Cycle counter, low word */
74
-#define CYCLE_COUNT_HI          0x094   /* (RO) Cycle counter, high word */
75
-#define TIMESTAMP_LO            0x098   /* (RO) Global time stamp counter, low word */
76
-#define TIMESTAMP_HI            0x09C   /* (RO) Global time stamp counter, high word */
77
-
78
-#define THREAD_MAX_THREADS      0x0A0   /* (RO) Maximum number of threads per core */
79
-#define THREAD_MAX_WORKGROUP_SIZE 0x0A4 /* (RO) Maximum workgroup size */
80
-#define THREAD_MAX_BARRIER_SIZE 0x0A8   /* (RO) Maximum threads waiting at a barrier */
81
-#define THREAD_FEATURES         0x0AC   /* (RO) Thread features */
82
-#define THREAD_TLS_ALLOC        0x310   /* (RO) Number of threads per core that TLS must be allocated for */
83
-
84
-#define TEXTURE_FEATURES_0      0x0B0   /* (RO) Support flags for indexed texture formats 0..31 */
85
-#define TEXTURE_FEATURES_1      0x0B4   /* (RO) Support flags for indexed texture formats 32..63 */
86
-#define TEXTURE_FEATURES_2      0x0B8   /* (RO) Support flags for indexed texture formats 64..95 */
87
-#define TEXTURE_FEATURES_3      0x0BC   /* (RO) Support flags for texture order */
88
-
89
-#define TEXTURE_FEATURES_REG(n) GPU_CONTROL_REG(TEXTURE_FEATURES_0 + ((n) << 2))
90
-
91
-#define SHADER_PRESENT_LO       0x100   /* (RO) Shader core present bitmap, low word */
92
-#define SHADER_PRESENT_HI       0x104   /* (RO) Shader core present bitmap, high word */
93
-
94
-#define TILER_PRESENT_LO        0x110   /* (RO) Tiler core present bitmap, low word */
95
-#define TILER_PRESENT_HI        0x114   /* (RO) Tiler core present bitmap, high word */
96
-
97
-#define L2_PRESENT_LO           0x120   /* (RO) Level 2 cache present bitmap, low word */
98
-#define L2_PRESENT_HI           0x124   /* (RO) Level 2 cache present bitmap, high word */
99
-
100
-#define STACK_PRESENT_LO        0xE00   /* (RO) Core stack present bitmap, low word */
101
-#define STACK_PRESENT_HI        0xE04   /* (RO) Core stack present bitmap, high word */
10241 
10342 #define SHADER_READY_LO         0x140   /* (RO) Shader core ready bitmap, low word */
10443 #define SHADER_READY_HI         0x144   /* (RO) Shader core ready bitmap, high word */
....@@ -109,9 +48,6 @@
10948 #define L2_READY_LO             0x160   /* (RO) Level 2 cache ready bitmap, low word */
11049 #define L2_READY_HI             0x164   /* (RO) Level 2 cache ready bitmap, high word */
11150 
112
-#define STACK_READY_LO          0xE10   /* (RO) Core stack ready bitmap, low word */
113
-#define STACK_READY_HI          0xE14   /* (RO) Core stack ready bitmap, high word */
114
-
11551 #define SHADER_PWRON_LO         0x180   /* (WO) Shader core power on bitmap, low word */
11652 #define SHADER_PWRON_HI         0x184   /* (WO) Shader core power on bitmap, high word */
11753 
....@@ -121,60 +57,12 @@
12157 #define L2_PWRON_LO             0x1A0   /* (WO) Level 2 cache power on bitmap, low word */
12258 #define L2_PWRON_HI             0x1A4   /* (WO) Level 2 cache power on bitmap, high word */
12359 
124
-#define STACK_PWRON_LO          0xE20   /* (RO) Core stack power on bitmap, low word */
125
-#define STACK_PWRON_HI          0xE24   /* (RO) Core stack power on bitmap, high word */
126
-
127
-#define SHADER_PWROFF_LO        0x1C0   /* (WO) Shader core power off bitmap, low word */
128
-#define SHADER_PWROFF_HI        0x1C4   /* (WO) Shader core power off bitmap, high word */
129
-
130
-#define TILER_PWROFF_LO         0x1D0   /* (WO) Tiler core power off bitmap, low word */
131
-#define TILER_PWROFF_HI         0x1D4   /* (WO) Tiler core power off bitmap, high word */
132
-
133
-#define L2_PWROFF_LO            0x1E0   /* (WO) Level 2 cache power off bitmap, low word */
134
-#define L2_PWROFF_HI            0x1E4   /* (WO) Level 2 cache power off bitmap, high word */
135
-
136
-#define STACK_PWROFF_LO         0xE30   /* (RO) Core stack power off bitmap, low word */
137
-#define STACK_PWROFF_HI         0xE34   /* (RO) Core stack power off bitmap, high word */
138
-
139
-#define SHADER_PWRTRANS_LO      0x200   /* (RO) Shader core power transition bitmap, low word */
140
-#define SHADER_PWRTRANS_HI      0x204   /* (RO) Shader core power transition bitmap, high word */
141
-
142
-#define TILER_PWRTRANS_LO       0x210   /* (RO) Tiler core power transition bitmap, low word */
143
-#define TILER_PWRTRANS_HI       0x214   /* (RO) Tiler core power transition bitmap, high word */
144
-
145
-#define L2_PWRTRANS_LO          0x220   /* (RO) Level 2 cache power transition bitmap, low word */
146
-#define L2_PWRTRANS_HI          0x224   /* (RO) Level 2 cache power transition bitmap, high word */
147
-
148
-#define ASN_HASH_0              0x02C0 /* (RW) ASN hash function argument 0 */
149
-#define ASN_HASH(n)             (ASN_HASH_0 + (n)*4)
150
-#define ASN_HASH_COUNT          3
151
-
152
-#define STACK_PWRTRANS_LO       0xE40   /* (RO) Core stack power transition bitmap, low word */
153
-#define STACK_PWRTRANS_HI       0xE44   /* (RO) Core stack power transition bitmap, high word */
154
-
155
-#define SHADER_PWRACTIVE_LO     0x240   /* (RO) Shader core active bitmap, low word */
156
-#define SHADER_PWRACTIVE_HI     0x244   /* (RO) Shader core active bitmap, high word */
157
-
158
-#define TILER_PWRACTIVE_LO      0x250   /* (RO) Tiler core active bitmap, low word */
159
-#define TILER_PWRACTIVE_HI      0x254   /* (RO) Tiler core active bitmap, high word */
160
-
161
-#define L2_PWRACTIVE_LO         0x260   /* (RO) Level 2 cache active bitmap, low word */
162
-#define L2_PWRACTIVE_HI         0x264   /* (RO) Level 2 cache active bitmap, high word */
163
-
164
-#define COHERENCY_FEATURES      0x300   /* (RO) Coherency features present */
165
-#define COHERENCY_ENABLE        0x304   /* (RW) Coherency enable */
166
-
167
-#define SHADER_CONFIG           0xF04   /* (RW) Shader core configuration (implementation-specific) */
168
-#define TILER_CONFIG            0xF08   /* (RW) Tiler core configuration (implementation-specific) */
169
-#define L2_MMU_CONFIG           0xF0C   /* (RW) L2 cache and MMU configuration (implementation-specific) */
170
-
17160 /* Job control registers */
17261 
17362 #define JOB_CONTROL_BASE        0x1000
17463 
17564 #define JOB_CONTROL_REG(r)      (JOB_CONTROL_BASE + (r))
17665 
177
-#define JOB_IRQ_RAWSTAT         0x000   /* Raw interrupt status register */
17866 #define JOB_IRQ_CLEAR           0x004   /* Interrupt clear register */
17967 #define JOB_IRQ_MASK            0x008   /* Interrupt mask register */
18068 #define JOB_IRQ_STATUS          0x00C   /* Interrupt status register */
....@@ -182,6 +70,7 @@
18270 /* MMU control registers */
18371 
18472 #define MEMORY_MANAGEMENT_BASE  0x2000
73
+
18574 #define MMU_REG(r)              (MEMORY_MANAGEMENT_BASE + (r))
18675 
18776 #define MMU_IRQ_RAWSTAT         0x000   /* (RW) Raw interrupt status register */
....@@ -190,21 +79,6 @@
19079 #define MMU_IRQ_STATUS          0x00C   /* (RO) Interrupt status register */
19180 
19281 #define MMU_AS0                 0x400   /* Configuration registers for address space 0 */
193
-#define MMU_AS1                 0x440   /* Configuration registers for address space 1 */
194
-#define MMU_AS2                 0x480   /* Configuration registers for address space 2 */
195
-#define MMU_AS3                 0x4C0   /* Configuration registers for address space 3 */
196
-#define MMU_AS4                 0x500   /* Configuration registers for address space 4 */
197
-#define MMU_AS5                 0x540   /* Configuration registers for address space 5 */
198
-#define MMU_AS6                 0x580   /* Configuration registers for address space 6 */
199
-#define MMU_AS7                 0x5C0   /* Configuration registers for address space 7 */
200
-#define MMU_AS8                 0x600   /* Configuration registers for address space 8 */
201
-#define MMU_AS9                 0x640   /* Configuration registers for address space 9 */
202
-#define MMU_AS10                0x680   /* Configuration registers for address space 10 */
203
-#define MMU_AS11                0x6C0   /* Configuration registers for address space 11 */
204
-#define MMU_AS12                0x700   /* Configuration registers for address space 12 */
205
-#define MMU_AS13                0x740   /* Configuration registers for address space 13 */
206
-#define MMU_AS14                0x780   /* Configuration registers for address space 14 */
207
-#define MMU_AS15                0x7C0   /* Configuration registers for address space 15 */
20882 
20983 /* MMU address space control registers */
21084 
....@@ -214,221 +88,11 @@
21488 #define AS_TRANSTAB_HI         0x04	/* (RW) Translation Table Base Address for address space n, high word */
21589 #define AS_MEMATTR_LO          0x08	/* (RW) Memory attributes for address space n, low word. */
21690 #define AS_MEMATTR_HI          0x0C	/* (RW) Memory attributes for address space n, high word. */
217
-#define AS_LOCKADDR_LO         0x10	/* (RW) Lock region address for address space n, low word */
218
-#define AS_LOCKADDR_HI         0x14	/* (RW) Lock region address for address space n, high word */
21991 #define AS_COMMAND             0x18	/* (WO) MMU command register for address space n */
220
-#define AS_FAULTSTATUS         0x1C	/* (RO) MMU fault status register for address space n */
221
-#define AS_FAULTADDRESS_LO     0x20	/* (RO) Fault Address for address space n, low word */
222
-#define AS_FAULTADDRESS_HI     0x24	/* (RO) Fault Address for address space n, high word */
223
-#define AS_STATUS              0x28	/* (RO) Status flags for address space n */
22492 
22593 /* (RW) Translation table configuration for address space n, low word */
22694 #define AS_TRANSCFG_LO         0x30
22795 /* (RW) Translation table configuration for address space n, high word */
22896 #define AS_TRANSCFG_HI         0x34
229
-/* (RO) Secondary fault address for address space n, low word */
230
-#define AS_FAULTEXTRA_LO       0x38
231
-/* (RO) Secondary fault address for address space n, high word */
232
-#define AS_FAULTEXTRA_HI       0x3C
233
-
234
-/* End Register Offsets */
235
-
236
-#define GPU_IRQ_REG_ALL (GPU_IRQ_REG_COMMON)
237
-
238
-/*
239
- * MMU_IRQ_RAWSTAT register values. Values are valid also for
240
- * MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
241
- */
242
-
243
-#define MMU_PAGE_FAULT_FLAGS    16
244
-
245
-/* Macros returning a bitmask to retrieve page fault or bus error flags from
246
- * MMU registers
247
- */
248
-#define MMU_PAGE_FAULT(n)       (1UL << (n))
249
-#define MMU_BUS_ERROR(n)        (1UL << ((n) + MMU_PAGE_FAULT_FLAGS))
250
-
251
-/*
252
- * Begin AARCH64 MMU TRANSTAB register values
253
- */
254
-#define MMU_HW_OUTA_BITS 40
255
-#define AS_TRANSTAB_BASE_MASK ((1ULL << MMU_HW_OUTA_BITS) - (1ULL << 4))
256
-
257
-/*
258
- * Begin MMU STATUS register values
259
- */
260
-#define AS_STATUS_AS_ACTIVE 0x01
261
-
262
-#define AS_FAULTSTATUS_EXCEPTION_CODE_MASK                      (0x7<<3)
263
-#define AS_FAULTSTATUS_EXCEPTION_CODE_TRANSLATION_FAULT         (0x0<<3)
264
-#define AS_FAULTSTATUS_EXCEPTION_CODE_PERMISSION_FAULT          (0x1<<3)
265
-#define AS_FAULTSTATUS_EXCEPTION_CODE_TRANSTAB_BUS_FAULT        (0x2<<3)
266
-#define AS_FAULTSTATUS_EXCEPTION_CODE_ACCESS_FLAG               (0x3<<3)
267
-#define AS_FAULTSTATUS_EXCEPTION_CODE_ADDRESS_SIZE_FAULT        (0x4<<3)
268
-#define AS_FAULTSTATUS_EXCEPTION_CODE_MEMORY_ATTRIBUTES_FAULT   (0x5<<3)
269
-
270
-#define AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT 0
271
-#define AS_FAULTSTATUS_EXCEPTION_TYPE_MASK (0xFF << AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)
272
-#define AS_FAULTSTATUS_EXCEPTION_TYPE_GET(reg_val) \
273
-	(((reg_val)&AS_FAULTSTATUS_EXCEPTION_TYPE_MASK) >> AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)
274
-#define AS_FAULTSTATUS_EXCEPTION_TYPE_TRANSLATION_FAULT_0 0xC0
275
-
276
-#define AS_FAULTSTATUS_ACCESS_TYPE_SHIFT 8
277
-#define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << AS_FAULTSTATUS_ACCESS_TYPE_SHIFT)
278
-#define AS_FAULTSTATUS_ACCESS_TYPE_GET(reg_val) \
279
-	(((reg_val)&AS_FAULTSTATUS_ACCESS_TYPE_MASK) >> AS_FAULTSTATUS_ACCESS_TYPE_SHIFT)
280
-
281
-#define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC       (0x0)
282
-#define AS_FAULTSTATUS_ACCESS_TYPE_EX           (0x1)
283
-#define AS_FAULTSTATUS_ACCESS_TYPE_READ         (0x2)
284
-#define AS_FAULTSTATUS_ACCESS_TYPE_WRITE        (0x3)
285
-
286
-#define AS_FAULTSTATUS_SOURCE_ID_SHIFT 16
287
-#define AS_FAULTSTATUS_SOURCE_ID_MASK (0xFFFF << AS_FAULTSTATUS_SOURCE_ID_SHIFT)
288
-#define AS_FAULTSTATUS_SOURCE_ID_GET(reg_val) \
289
-	(((reg_val)&AS_FAULTSTATUS_SOURCE_ID_MASK) >> AS_FAULTSTATUS_SOURCE_ID_SHIFT)
290
-
291
-#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT (0)
292
-#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK                                \
293
-	((0xFF) << PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT)
294
-#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_GET(reg_val)                        \
295
-	(((reg_val)&PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK) >>                \
296
-	 PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT)
297
-
298
-/*
299
- * Begin MMU TRANSCFG register values
300
- */
301
-#define AS_TRANSCFG_ADRMODE_LEGACY      0
302
-#define AS_TRANSCFG_ADRMODE_UNMAPPED    1
303
-#define AS_TRANSCFG_ADRMODE_IDENTITY    2
304
-#define AS_TRANSCFG_ADRMODE_AARCH64_4K  6
305
-#define AS_TRANSCFG_ADRMODE_AARCH64_64K 8
306
-
307
-#define AS_TRANSCFG_ADRMODE_MASK        0xF
308
-
309
-/*
310
- * Begin TRANSCFG register values
311
- */
312
-#define AS_TRANSCFG_PTW_MEMATTR_MASK (3ull << 24)
313
-#define AS_TRANSCFG_PTW_MEMATTR_NON_CACHEABLE (1ull << 24)
314
-#define AS_TRANSCFG_PTW_MEMATTR_WRITE_BACK (2ull << 24)
315
-
316
-#define AS_TRANSCFG_PTW_SH_MASK ((3ull << 28))
317
-#define AS_TRANSCFG_PTW_SH_OS (2ull << 28)
318
-#define AS_TRANSCFG_PTW_SH_IS (3ull << 28)
319
-#define AS_TRANSCFG_R_ALLOCATE (1ull << 30)
320
-
321
-/*
322
- * Begin Command Values
323
- */
324
-
325
-/* AS_COMMAND register commands */
326
-#define AS_COMMAND_NOP         0x00	/* NOP Operation */
327
-#define AS_COMMAND_UPDATE      0x01	/* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs */
328
-#define AS_COMMAND_LOCK        0x02	/* Issue a lock region command to all MMUs */
329
-#define AS_COMMAND_UNLOCK      0x03	/* Issue a flush region command to all MMUs */
330
-/* Flush all L2 caches then issue a flush region command to all MMUs
331
- * (deprecated - only for use with T60x)
332
- */
333
-#define AS_COMMAND_FLUSH 0x04
334
-/* Flush all L2 caches then issue a flush region command to all MMUs */
335
-#define AS_COMMAND_FLUSH_PT 0x04
336
-/* Wait for memory accesses to complete, flush all the L1s cache then flush all
337
- * L2 caches then issue a flush region command to all MMUs
338
- */
339
-#define AS_COMMAND_FLUSH_MEM 0x05
340
-
341
-/* GPU_STATUS values */
342
-#define GPU_STATUS_PRFCNT_ACTIVE            (1 << 2)    /* Set if the performance counters are active. */
343
-#define GPU_STATUS_CYCLE_COUNT_ACTIVE       (1 << 6)    /* Set if the cycle counter is active. */
344
-#define GPU_STATUS_PROTECTED_MODE_ACTIVE    (1 << 7)    /* Set if protected mode is active */
345
-
346
-/* PRFCNT_CONFIG register values */
347
-#define PRFCNT_CONFIG_MODE_SHIFT        0 /* Counter mode position. */
348
-#define PRFCNT_CONFIG_AS_SHIFT          4 /* Address space bitmap position. */
349
-#define PRFCNT_CONFIG_SETSELECT_SHIFT   8 /* Set select position. */
350
-
351
-/* The performance counters are disabled. */
352
-#define PRFCNT_CONFIG_MODE_OFF          0
353
-/* The performance counters are enabled, but are only written out when a
354
- * PRFCNT_SAMPLE command is issued using the GPU_COMMAND register.
355
- */
356
-#define PRFCNT_CONFIG_MODE_MANUAL       1
357
-/* The performance counters are enabled, and are written out each time a tile
358
- * finishes rendering.
359
- */
360
-#define PRFCNT_CONFIG_MODE_TILE         2
361
-
362
-/* AS<n>_MEMATTR values from MMU_MEMATTR_STAGE1: */
363
-/* Use GPU implementation-defined caching policy. */
364
-#define AS_MEMATTR_IMPL_DEF_CACHE_POLICY 0x88ull
365
-/* The attribute set to force all resources to be cached. */
366
-#define AS_MEMATTR_FORCE_TO_CACHE_ALL    0x8Full
367
-/* Inner write-alloc cache setup, no outer caching */
368
-#define AS_MEMATTR_WRITE_ALLOC           0x8Dull
369
-
370
-/* Use GPU implementation-defined  caching policy. */
371
-#define AS_MEMATTR_LPAE_IMPL_DEF_CACHE_POLICY 0x48ull
372
-/* The attribute set to force all resources to be cached. */
373
-#define AS_MEMATTR_LPAE_FORCE_TO_CACHE_ALL    0x4Full
374
-/* Inner write-alloc cache setup, no outer caching */
375
-#define AS_MEMATTR_LPAE_WRITE_ALLOC           0x4Dull
376
-/* Set to implementation defined, outer caching */
377
-#define AS_MEMATTR_LPAE_OUTER_IMPL_DEF        0x88ull
378
-/* Set to write back memory, outer caching */
379
-#define AS_MEMATTR_LPAE_OUTER_WA              0x8Dull
380
-/* There is no LPAE support for non-cacheable, since the memory type is always
381
- * write-back.
382
- * Marking this setting as reserved for LPAE
383
- */
384
-#define AS_MEMATTR_LPAE_NON_CACHEABLE_RESERVED
385
-
386
-/* L2_MMU_CONFIG register */
387
-#define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT       (23)
388
-#define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY             (0x1 << L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT)
389
-
390
-/* End L2_MMU_CONFIG register */
391
-
392
-/* THREAD_* registers */
393
-
394
-/* THREAD_FEATURES IMPLEMENTATION_TECHNOLOGY values */
395
-#define IMPLEMENTATION_UNSPECIFIED  0
396
-#define IMPLEMENTATION_SILICON      1
397
-#define IMPLEMENTATION_FPGA         2
398
-#define IMPLEMENTATION_MODEL        3
399
-
400
-/* Default values when registers are not supported by the implemented hardware */
401
-#define THREAD_MT_DEFAULT     256
402
-#define THREAD_MWS_DEFAULT    256
403
-#define THREAD_MBS_DEFAULT    256
404
-#define THREAD_MR_DEFAULT     1024
405
-#define THREAD_MTQ_DEFAULT    4
406
-#define THREAD_MTGS_DEFAULT   10
407
-
408
-/* End THREAD_* registers */
409
-
410
-/* SHADER_CONFIG register */
411
-#define SC_LS_ALLOW_ATTR_TYPES      (1ul << 16)
412
-#define SC_TLS_HASH_ENABLE          (1ul << 17)
413
-#define SC_LS_ATTR_CHECK_DISABLE    (1ul << 18)
414
-#define SC_VAR_ALGORITHM            (1ul << 29)
415
-/* End SHADER_CONFIG register */
416
-
417
-/* TILER_CONFIG register */
418
-#define TC_CLOCK_GATE_OVERRIDE      (1ul << 0)
419
-/* End TILER_CONFIG register */
420
-
421
-/* L2_CONFIG register */
422
-#define L2_CONFIG_SIZE_SHIFT        16
423
-#define L2_CONFIG_SIZE_MASK         (0xFFul << L2_CONFIG_SIZE_SHIFT)
424
-#define L2_CONFIG_HASH_SHIFT        24
425
-#define L2_CONFIG_HASH_MASK         (0xFFul << L2_CONFIG_HASH_SHIFT)
426
-#define L2_CONFIG_ASN_HASH_ENABLE_SHIFT        24
427
-#define L2_CONFIG_ASN_HASH_ENABLE_MASK         (1ul << L2_CONFIG_ASN_HASH_ENABLE_SHIFT)
428
-/* End L2_CONFIG register */
429
-
430
-/* IDVS_GROUP register */
431
-#define IDVS_GROUP_SIZE_SHIFT (16)
432
-#define IDVS_GROUP_MAX_SIZE (0x3F)
43397 
43498 #endif /* _UAPI_KBASE_GPU_REGMAP_H_ */