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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 1 | 2 | /* |
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| 2 | 3 | * mv643xx.h - MV-643XX Internal registers definition file. |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright 2002 Momentum Computer, Inc. |
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| 5 | 6 | * Author: Matthew Dharm <mdharm@momenco.com> |
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| 6 | 7 | * Copyright 2002 GALILEO TECHNOLOGY, LTD. |
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| 7 | | - * |
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| 8 | | - * This program is free software; you can redistribute it and/or modify it |
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| 9 | | - * under the terms of the GNU General Public License as published by the |
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| 10 | | - * Free Software Foundation; either version 2 of the License, or (at your |
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| 11 | | - * option) any later version. |
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| 12 | 8 | */ |
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| 13 | 9 | #ifndef __ASM_MV643XX_H |
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| 14 | 10 | #define __ASM_MV643XX_H |
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| .. | .. |
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| 921 | 917 | #define MV64340_SERIAL_INIT_STATUS 0xf32c |
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| 922 | 918 | |
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| 923 | 919 | extern void mv64340_irq_init(unsigned int base); |
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| 924 | | - |
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| 925 | | -/* MPSC Platform Device, Driver Data (Shared register regions) */ |
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| 926 | | -#define MPSC_SHARED_NAME "mpsc_shared" |
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| 927 | | - |
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| 928 | | -#define MPSC_ROUTING_BASE_ORDER 0 |
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| 929 | | -#define MPSC_SDMA_INTR_BASE_ORDER 1 |
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| 930 | | - |
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| 931 | | -#define MPSC_ROUTING_REG_BLOCK_SIZE 0x000c |
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| 932 | | -#define MPSC_SDMA_INTR_REG_BLOCK_SIZE 0x0084 |
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| 933 | | - |
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| 934 | | -struct mpsc_shared_pdata { |
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| 935 | | - u32 mrr_val; |
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| 936 | | - u32 rcrr_val; |
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| 937 | | - u32 tcrr_val; |
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| 938 | | - u32 intr_cause_val; |
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| 939 | | - u32 intr_mask_val; |
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| 940 | | -}; |
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| 941 | | - |
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| 942 | | -/* MPSC Platform Device, Driver Data */ |
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| 943 | | -#define MPSC_CTLR_NAME "mpsc" |
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| 944 | | - |
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| 945 | | -#define MPSC_BASE_ORDER 0 |
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| 946 | | -#define MPSC_SDMA_BASE_ORDER 1 |
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| 947 | | -#define MPSC_BRG_BASE_ORDER 2 |
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| 948 | | - |
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| 949 | | -#define MPSC_REG_BLOCK_SIZE 0x0038 |
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| 950 | | -#define MPSC_SDMA_REG_BLOCK_SIZE 0x0c18 |
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| 951 | | -#define MPSC_BRG_REG_BLOCK_SIZE 0x0008 |
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| 952 | | - |
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| 953 | | -struct mpsc_pdata { |
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| 954 | | - u8 mirror_regs; |
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| 955 | | - u8 cache_mgmt; |
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| 956 | | - u8 max_idle; |
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| 957 | | - int default_baud; |
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| 958 | | - int default_bits; |
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| 959 | | - int default_parity; |
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| 960 | | - int default_flow; |
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| 961 | | - u32 chr_1_val; |
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| 962 | | - u32 chr_2_val; |
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| 963 | | - u32 chr_10_val; |
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| 964 | | - u32 mpcr_val; |
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| 965 | | - u32 bcr_val; |
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| 966 | | - u8 brg_can_tune; |
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| 967 | | - u8 brg_clk_src; |
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| 968 | | - u32 brg_clk_freq; |
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| 969 | | -}; |
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| 970 | 920 | |
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| 971 | 921 | /* Watchdog Platform Device, Driver Data */ |
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| 972 | 922 | #define MV64x60_WDT_NAME "mv64x60_wdt" |
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