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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/include/linux/irqchip/arm-gic-v3.h
....@@ -1,19 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
34  * Author: Marc Zyngier <marc.zyngier@arm.com>
4
- *
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License version 2 as
8
- * published by the Free Software Foundation.
9
- *
10
- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
- * GNU General Public License for more details.
14
- *
15
- * You should have received a copy of the GNU General Public License
16
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
175  */
186 #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
197 #define __LINUX_IRQCHIP_ARM_GIC_V3_H
....@@ -25,12 +13,12 @@
2513 #define GICD_CTLR			0x0000
2614 #define GICD_TYPER			0x0004
2715 #define GICD_IIDR			0x0008
16
+#define GICD_TYPER2			0x000C
2817 #define GICD_STATUSR			0x0010
2918 #define GICD_SETSPI_NSR			0x0040
3019 #define GICD_CLRSPI_NSR			0x0048
3120 #define GICD_SETSPI_SR			0x0050
3221 #define GICD_CLRSPI_SR			0x0058
33
-#define GICD_SEIR			0x0068
3422 #define GICD_IGROUPR			0x0080
3523 #define GICD_ISENABLER			0x0100
3624 #define GICD_ICENABLER			0x0180
....@@ -42,9 +30,21 @@
4230 #define GICD_ICFGR			0x0C00
4331 #define GICD_IGRPMODR			0x0D00
4432 #define GICD_NSACR			0x0E00
33
+#define GICD_IGROUPRnE			0x1000
34
+#define GICD_ISENABLERnE		0x1200
35
+#define GICD_ICENABLERnE		0x1400
36
+#define GICD_ISPENDRnE			0x1600
37
+#define GICD_ICPENDRnE			0x1800
38
+#define GICD_ISACTIVERnE		0x1A00
39
+#define GICD_ICACTIVERnE		0x1C00
40
+#define GICD_IPRIORITYRnE		0x2000
41
+#define GICD_ICFGRnE			0x3000
4542 #define GICD_IROUTER			0x6000
43
+#define GICD_IROUTERnE			0x8000
4644 #define GICD_IDREGS			0xFFD0
4745 #define GICD_PIDR2			0xFFE8
46
+
47
+#define ESPI_BASE_INTID			4096
4848 
4949 /*
5050  * Those registers are actually from GICv2, but the spec demands that they
....@@ -56,6 +56,7 @@
5656 #define GICD_SPENDSGIR			0x0F20
5757 
5858 #define GICD_CTLR_RWP			(1U << 31)
59
+#define GICD_CTLR_nASSGIreq		(1U << 8)
5960 #define GICD_CTLR_DS			(1U << 6)
6061 #define GICD_CTLR_ARE_NS		(1U << 4)
6162 #define GICD_CTLR_ENABLE_G1A		(1U << 1)
....@@ -81,10 +82,17 @@
8182 #define GICD_TYPER_RSS			(1U << 26)
8283 #define GICD_TYPER_LPIS			(1U << 17)
8384 #define GICD_TYPER_MBIS			(1U << 16)
85
+#define GICD_TYPER_ESPI			(1U << 8)
8486 
8587 #define GICD_TYPER_ID_BITS(typer)	((((typer) >> 19) & 0x1f) + 1)
8688 #define GICD_TYPER_NUM_LPIS(typer)	((((typer) >> 11) & 0x1f) + 1)
87
-#define GICD_TYPER_IRQS(typer)		((((typer) & 0x1f) + 1) * 32)
89
+#define GICD_TYPER_SPIS(typer)		((((typer) & 0x1f) + 1) * 32)
90
+#define GICD_TYPER_ESPIS(typer)						\
91
+	(((typer) & GICD_TYPER_ESPI) ? GICD_TYPER_SPIS((typer) >> 27) : 0)
92
+
93
+#define GICD_TYPER2_nASSGIcap		(1U << 8)
94
+#define GICD_TYPER2_VIL			(1U << 7)
95
+#define GICD_TYPER2_VID			GENMASK(4, 0)
8896 
8997 #define GICD_IROUTER_SPI_MODE_ONE	(0U << 31)
9098 #define GICD_IROUTER_SPI_MODE_ANY	(1U << 31)
....@@ -94,6 +102,11 @@
94102 #define GIC_PIDR2_ARCH_GICv4		0x40
95103 
96104 #define GIC_V3_DIST_SIZE		0x10000
105
+
106
+#define GIC_PAGE_SIZE_4K		0ULL
107
+#define GIC_PAGE_SIZE_16K		1ULL
108
+#define GIC_PAGE_SIZE_64K		2ULL
109
+#define GIC_PAGE_SIZE_MASK		3ULL
97110 
98111 /*
99112  * Re-Distributor registers, offsets from RD_base
....@@ -105,14 +118,11 @@
105118 #define GICR_WAKER			0x0014
106119 #define GICR_SETLPIR			0x0040
107120 #define GICR_CLRLPIR			0x0048
108
-#define GICR_SEIR			GICD_SEIR
109121 #define GICR_PROPBASER			0x0070
110122 #define GICR_PENDBASER			0x0078
111123 #define GICR_INVLPIR			0x00A0
112124 #define GICR_INVALLR			0x00B0
113125 #define GICR_SYNCR			0x00C0
114
-#define GICR_MOVLPIR			0x0100
115
-#define GICR_MOVALLR			0x0110
116126 #define GICR_IDREGS			GICD_IDREGS
117127 #define GICR_PIDR2			GICD_PIDR2
118128 
....@@ -120,6 +130,18 @@
120130 #define GICR_CTLR_RWP			(1UL << 3)
121131 
122132 #define GICR_TYPER_CPU_NUMBER(r)	(((r) >> 8) & 0xffff)
133
+
134
+#define EPPI_BASE_INTID			1056
135
+
136
+#define GICR_TYPER_NR_PPIS(r)						\
137
+	({								\
138
+		unsigned int __ppinum = ((r) >> 27) & 0x1f;		\
139
+		unsigned int __nr_ppis = 16;				\
140
+		if (__ppinum == 1 || __ppinum == 2)			\
141
+			__nr_ppis +=  __ppinum * 32;			\
142
+									\
143
+		__nr_ppis;						\
144
+	 })
123145 
124146 #define GICR_WAKER_ProcessorSleep	(1U << 1)
125147 #define GICR_WAKER_ChildrenAsleep	(1U << 2)
....@@ -217,8 +239,19 @@
217239 
218240 #define GICR_TYPER_PLPIS		(1U << 0)
219241 #define GICR_TYPER_VLPIS		(1U << 1)
242
+#define GICR_TYPER_DIRTY		(1U << 2)
220243 #define GICR_TYPER_DirectLPIS		(1U << 3)
221244 #define GICR_TYPER_LAST			(1U << 4)
245
+#define GICR_TYPER_RVPEID		(1U << 7)
246
+#define GICR_TYPER_COMMON_LPI_AFF	GENMASK_ULL(25, 24)
247
+#define GICR_TYPER_AFFINITY		GENMASK_ULL(63, 32)
248
+
249
+#define GICR_INVLPIR_INTID		GENMASK_ULL(31, 0)
250
+#define GICR_INVLPIR_VPEID		GENMASK_ULL(47, 32)
251
+#define GICR_INVLPIR_V			GENMASK_ULL(63, 63)
252
+
253
+#define GICR_INVALLR_VPEID		GICR_INVLPIR_VPEID
254
+#define GICR_INVALLR_V			GICR_INVLPIR_V
222255 
223256 #define GIC_V3_REDIST_SIZE		0x20000
224257 
....@@ -257,6 +290,18 @@
257290 #define GICR_VPROPBASER_RaWaWt	GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWt)
258291 #define GICR_VPROPBASER_RaWaWb	GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWb)
259292 
293
+/*
294
+ * GICv4.1 VPROPBASER reinvention. A subtle mix between the old
295
+ * VPROPBASER and ITS_BASER. Just not quite any of the two.
296
+ */
297
+#define GICR_VPROPBASER_4_1_VALID	(1ULL << 63)
298
+#define GICR_VPROPBASER_4_1_ENTRY_SIZE	GENMASK_ULL(61, 59)
299
+#define GICR_VPROPBASER_4_1_INDIRECT	(1ULL << 55)
300
+#define GICR_VPROPBASER_4_1_PAGE_SIZE	GENMASK_ULL(54, 53)
301
+#define GICR_VPROPBASER_4_1_Z		(1ULL << 52)
302
+#define GICR_VPROPBASER_4_1_ADDR	GENMASK_ULL(51, 12)
303
+#define GICR_VPROPBASER_4_1_SIZE	GENMASK_ULL(6, 0)
304
+
260305 #define GICR_VPENDBASER			0x0078
261306 
262307 #define GICR_VPENDBASER_SHAREABILITY_SHIFT		(10)
....@@ -274,6 +319,9 @@
274319 #define GICR_VPENDBASER_NonShareable					\
275320 	GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable)
276321 
322
+#define GICR_VPENDBASER_InnerShareable					\
323
+	GIC_BASER_SHAREABILITY(GICR_VPENDBASER, InnerShareable)
324
+
277325 #define GICR_VPENDBASER_nCnB	GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB)
278326 #define GICR_VPENDBASER_nC 	GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC)
279327 #define GICR_VPENDBASER_RaWt	GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
....@@ -289,11 +337,30 @@
289337 #define GICR_VPENDBASER_Valid		(1ULL << 63)
290338 
291339 /*
340
+ * GICv4.1 VPENDBASER, used for VPE residency. On top of these fields,
341
+ * also use the above Valid, PendingLast and Dirty.
342
+ */
343
+#define GICR_VPENDBASER_4_1_DB		(1ULL << 62)
344
+#define GICR_VPENDBASER_4_1_VGRP0EN	(1ULL << 59)
345
+#define GICR_VPENDBASER_4_1_VGRP1EN	(1ULL << 58)
346
+#define GICR_VPENDBASER_4_1_VPEID	GENMASK_ULL(15, 0)
347
+
348
+#define GICR_VSGIR			0x0080
349
+
350
+#define GICR_VSGIR_VPEID		GENMASK(15, 0)
351
+
352
+#define GICR_VSGIPENDR			0x0088
353
+
354
+#define GICR_VSGIPENDR_BUSY		(1U << 31)
355
+#define GICR_VSGIPENDR_PENDING		GENMASK(15, 0)
356
+
357
+/*
292358  * ITS registers, offsets from ITS_base
293359  */
294360 #define GITS_CTLR			0x0000
295361 #define GITS_IIDR			0x0004
296362 #define GITS_TYPER			0x0008
363
+#define GITS_MPIDR			0x0018
297364 #define GITS_CBASER			0x0080
298365 #define GITS_CWRITER			0x0088
299366 #define GITS_CREADR			0x0090
....@@ -310,6 +377,11 @@
310377 
311378 #define GITS_TRANSLATER			0x10040
312379 
380
+#define GITS_SGIR			0x20020
381
+
382
+#define GITS_SGIR_VPEID			GENMASK_ULL(47, 32)
383
+#define GITS_SGIR_VINTID		GENMASK_ULL(3, 0)
384
+
313385 #define GITS_CTLR_ENABLE		(1U << 0)
314386 #define GITS_CTLR_ImDe			(1U << 1)
315387 #define	GITS_CTLR_ITS_NUMBER_SHIFT	4
....@@ -319,14 +391,16 @@
319391 #define GITS_TYPER_PLPIS		(1UL << 0)
320392 #define GITS_TYPER_VLPIS		(1UL << 1)
321393 #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT	4
322
-#define GITS_TYPER_ITT_ENTRY_SIZE(r)	((((r) >> GITS_TYPER_ITT_ENTRY_SIZE_SHIFT) & 0xf) + 1)
394
+#define GITS_TYPER_ITT_ENTRY_SIZE	GENMASK_ULL(7, 4)
323395 #define GITS_TYPER_IDBITS_SHIFT		8
324396 #define GITS_TYPER_DEVBITS_SHIFT	13
325
-#define GITS_TYPER_DEVBITS(r)		((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
397
+#define GITS_TYPER_DEVBITS		GENMASK_ULL(17, 13)
326398 #define GITS_TYPER_PTA			(1UL << 19)
327399 #define GITS_TYPER_HCC_SHIFT		24
328400 #define GITS_TYPER_HCC(r)		(((r) >> GITS_TYPER_HCC_SHIFT) & 0xff)
329401 #define GITS_TYPER_VMOVP		(1ULL << 37)
402
+#define GITS_TYPER_VMAPP		(1ULL << 40)
403
+#define GITS_TYPER_SVPET		GENMASK_ULL(42, 41)
330404 
331405 #define GITS_IIDR_REV_SHIFT		12
332406 #define GITS_IIDR_REV_MASK		(0xf << GITS_IIDR_REV_SHIFT)
....@@ -356,6 +430,8 @@
356430 #define GITS_CBASER_WaWb	GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
357431 #define GITS_CBASER_RaWaWt	GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
358432 #define GITS_CBASER_RaWaWb	GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
433
+
434
+#define GITS_CBASER_ADDRESS(cbaser)	((cbaser) & GENMASK_ULL(51, 12))
359435 
360436 #define GITS_BASER_NR_REGS		8
361437 
....@@ -388,14 +464,18 @@
388464 #define GITS_BASER_ENTRY_SIZE_MASK	GENMASK_ULL(52, 48)
389465 #define GITS_BASER_PHYS_52_to_48(phys)					\
390466 	(((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12)
467
+#define GITS_BASER_ADDR_48_to_52(baser)					\
468
+	(((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48)
469
+
391470 #define GITS_BASER_SHAREABILITY_SHIFT	(10)
392471 #define GITS_BASER_InnerShareable					\
393472 	GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
394473 #define GITS_BASER_PAGE_SIZE_SHIFT	(8)
395
-#define GITS_BASER_PAGE_SIZE_4K		(0ULL << GITS_BASER_PAGE_SIZE_SHIFT)
396
-#define GITS_BASER_PAGE_SIZE_16K	(1ULL << GITS_BASER_PAGE_SIZE_SHIFT)
397
-#define GITS_BASER_PAGE_SIZE_64K	(2ULL << GITS_BASER_PAGE_SIZE_SHIFT)
398
-#define GITS_BASER_PAGE_SIZE_MASK	(3ULL << GITS_BASER_PAGE_SIZE_SHIFT)
474
+#define __GITS_BASER_PSZ(sz)		(GIC_PAGE_SIZE_ ## sz << GITS_BASER_PAGE_SIZE_SHIFT)
475
+#define GITS_BASER_PAGE_SIZE_4K		__GITS_BASER_PSZ(4K)
476
+#define GITS_BASER_PAGE_SIZE_16K	__GITS_BASER_PSZ(16K)
477
+#define GITS_BASER_PAGE_SIZE_64K	__GITS_BASER_PSZ(64K)
478
+#define GITS_BASER_PAGE_SIZE_MASK	__GITS_BASER_PSZ(MASK)
399479 #define GITS_BASER_PAGES_MAX		256
400480 #define GITS_BASER_PAGES_SHIFT		(0)
401481 #define GITS_BASER_NR_PAGES(r)		(((r) & 0xff) + 1)
....@@ -436,8 +516,10 @@
436516 #define GITS_CMD_VMAPTI			GITS_CMD_GICv4(GITS_CMD_MAPTI)
437517 #define GITS_CMD_VMOVI			GITS_CMD_GICv4(GITS_CMD_MOVI)
438518 #define GITS_CMD_VSYNC			GITS_CMD_GICv4(GITS_CMD_SYNC)
439
-/* VMOVP is the odd one, as it doesn't have a physical counterpart */
519
+/* VMOVP, VSGI and INVDB are the odd ones, as they dont have a physical counterpart */
440520 #define GITS_CMD_VMOVP			GITS_CMD_GICv4(2)
521
+#define GITS_CMD_VSGI			GITS_CMD_GICv4(3)
522
+#define GITS_CMD_INVDB			GITS_CMD_GICv4(0xe)
441523 
442524 /*
443525  * ITS error numbers
....@@ -467,6 +549,8 @@
467549 #define ICC_CTLR_EL1_EOImode_MASK	(1 << ICC_CTLR_EL1_EOImode_SHIFT)
468550 #define ICC_CTLR_EL1_CBPR_SHIFT		0
469551 #define ICC_CTLR_EL1_CBPR_MASK		(1 << ICC_CTLR_EL1_CBPR_SHIFT)
552
+#define ICC_CTLR_EL1_PMHE_SHIFT		6
553
+#define ICC_CTLR_EL1_PMHE_MASK		(1 << ICC_CTLR_EL1_PMHE_SHIFT)
470554 #define ICC_CTLR_EL1_PRI_BITS_SHIFT	8
471555 #define ICC_CTLR_EL1_PRI_BITS_MASK	(0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
472556 #define ICC_CTLR_EL1_ID_BITS_SHIFT	11
....@@ -476,6 +560,7 @@
476560 #define ICC_CTLR_EL1_A3V_SHIFT		15
477561 #define ICC_CTLR_EL1_A3V_MASK		(0x1 << ICC_CTLR_EL1_A3V_SHIFT)
478562 #define ICC_CTLR_EL1_RSS		(0x1 << 18)
563
+#define ICC_CTLR_EL1_ExtRange		(0x1 << 19)
479564 #define ICC_PMR_EL1_SHIFT		0
480565 #define ICC_PMR_EL1_MASK		(0xff << ICC_PMR_EL1_SHIFT)
481566 #define ICC_BPR0_EL1_SHIFT		0
....@@ -582,16 +667,23 @@
582667 
583668 struct rdists {
584669 	struct {
670
+		raw_spinlock_t	rd_lock;
585671 		void __iomem	*rd_base;
586672 		struct page	*pend_page;
587673 		phys_addr_t	phys_base;
588674 		bool		lpi_enabled;
675
+		cpumask_t	*vpe_table_mask;
676
+		void		*vpe_l1_base;
589677 	} __percpu		*rdist;
590
-	struct page		*prop_page;
678
+	phys_addr_t		prop_table_pa;
679
+	void			*prop_table_va;
591680 	u64			flags;
592681 	u32			gicd_typer;
682
+	u32			gicd_typer2;
593683 	bool			has_vlpis;
684
+	bool			has_rvpeid;
594685 	bool			has_direct_lpi;
686
+	bool			has_vpend_valid_dirty;
595687 };
596688 
597689 struct irq_domain;
....@@ -600,6 +692,20 @@
600692 int its_init(struct fwnode_handle *handle, struct rdists *rdists,
601693 	     struct irq_domain *domain);
602694 int mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent);
695
+
696
+struct gic_chip_data {
697
+	struct fwnode_handle	*fwnode;
698
+	void __iomem		*dist_base;
699
+	struct redist_region	*redist_regions;
700
+	struct rdists		rdists;
701
+	struct irq_domain	*domain;
702
+	u64			redist_stride;
703
+	u32			nr_redist_regions;
704
+	u64			flags;
705
+	bool			has_rss;
706
+	unsigned int		ppi_nr;
707
+	struct partition_desc	**ppi_descs;
708
+};
603709 
604710 static inline bool gic_enable_sre(void)
605711 {
....@@ -616,6 +722,8 @@
616722 	return !!(val & ICC_SRE_EL1_SRE);
617723 }
618724 
725
+void gic_resume(void);
726
+
619727 #endif
620728 
621729 #endif