hc
2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5
kernel/include/linux/coresight-pmu.h
....@@ -10,17 +10,27 @@
1010 #define CORESIGHT_ETM_PMU_NAME "cs_etm"
1111 #define CORESIGHT_ETM_PMU_SEED 0x10
1212
13
-/* ETMv3.5/PTM's ETMCR config bit */
14
-#define ETM_OPT_CYCACC 12
15
-#define ETM_OPT_CTXTID 14
16
-#define ETM_OPT_TS 28
17
-#define ETM_OPT_RETSTK 29
13
+/*
14
+ * Below are the definition of bit offsets for perf option, and works as
15
+ * arbitrary values for all ETM versions.
16
+ *
17
+ * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore,
18
+ * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
19
+ * directly use below macros as config bits.
20
+ */
21
+#define ETM_OPT_CYCACC 12
22
+#define ETM_OPT_CTXTID 14
23
+#define ETM_OPT_CTXTID2 15
24
+#define ETM_OPT_TS 28
25
+#define ETM_OPT_RETSTK 29
1826
1927 /* ETMv4 CONFIGR programming bits for the ETM OPTs */
2028 #define ETM4_CFG_BIT_CYCACC 4
2129 #define ETM4_CFG_BIT_CTXTID 6
30
+#define ETM4_CFG_BIT_VMID 7
2231 #define ETM4_CFG_BIT_TS 11
2332 #define ETM4_CFG_BIT_RETSTK 12
33
+#define ETM4_CFG_BIT_VMID_OPT 15
2434
2535 static inline int coresight_get_trace_id(int cpu)
2636 {