.. | .. |
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10 | 10 | #define CORESIGHT_ETM_PMU_NAME "cs_etm" |
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11 | 11 | #define CORESIGHT_ETM_PMU_SEED 0x10 |
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12 | 12 | |
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13 | | -/* ETMv3.5/PTM's ETMCR config bit */ |
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14 | | -#define ETM_OPT_CYCACC 12 |
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15 | | -#define ETM_OPT_CTXTID 14 |
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16 | | -#define ETM_OPT_TS 28 |
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17 | | -#define ETM_OPT_RETSTK 29 |
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| 13 | +/* |
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| 14 | + * Below are the definition of bit offsets for perf option, and works as |
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| 15 | + * arbitrary values for all ETM versions. |
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| 16 | + * |
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| 17 | + * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, |
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| 18 | + * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and |
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| 19 | + * directly use below macros as config bits. |
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| 20 | + */ |
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| 21 | +#define ETM_OPT_CYCACC 12 |
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| 22 | +#define ETM_OPT_CTXTID 14 |
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| 23 | +#define ETM_OPT_CTXTID2 15 |
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| 24 | +#define ETM_OPT_TS 28 |
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| 25 | +#define ETM_OPT_RETSTK 29 |
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18 | 26 | |
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19 | 27 | /* ETMv4 CONFIGR programming bits for the ETM OPTs */ |
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20 | 28 | #define ETM4_CFG_BIT_CYCACC 4 |
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21 | 29 | #define ETM4_CFG_BIT_CTXTID 6 |
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| 30 | +#define ETM4_CFG_BIT_VMID 7 |
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22 | 31 | #define ETM4_CFG_BIT_TS 11 |
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23 | 32 | #define ETM4_CFG_BIT_RETSTK 12 |
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| 33 | +#define ETM4_CFG_BIT_VMID_OPT 15 |
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24 | 34 | |
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25 | 35 | static inline int coresight_get_trace_id(int cpu) |
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26 | 36 | { |
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