~hc/RK356X_SDK_RELEASE.git

..	..	@@ -5,11 +5,10 @@
5	5	* it under the terms of the GNU General Public License as published by
6	6	* the Free Software Foundation; either version 2 of the License, or
7	7	* (at your option) any later version.
8		- * date: 2020-09-23
	8	+ * date: 2021-07-26
9	9	* function: rk ftl v5 for rockchip soc base on arm v7 to support MLC NAND.
10	10	*/
11	11	.arch armv7-a
12		- .fpu softvfp
13	12	.eabi_attribute 20, 1
14	13	.eabi_attribute 21, 1
15	14	.eabi_attribute 23, 3
..	..	@@ -18,139 +17,245 @@
18	17	.eabi_attribute 26, 2
19	18	.eabi_attribute 30, 4
20	19	.eabi_attribute 34, 1
21		- .eabi_attribute 18, 4
22	20	.file "rk_ftlv5_arm_v8.c"
23		-#APP
24		- .syntax unified
25	21	.text
26	22	.align 2
	23	+ .fpu softvfp
	24	+ .type ndelay, %function
	25	+ndelay:
	26	+ .fnstart
	27	+ @ args = 0, pretend = 0, frame = 0
	28	+ @ frame_needed = 0, uses_anonymous_args = 0
	29	+ @ link register save eliminated.
	30	+ ldr r3, .L2
	31	+ add r0, r0, #996
	32	+ add r0, r0, #3
	33	+ umull r0, r1, r0, r3
	34	+ ldr r3, .L2+4
	35	+ ldr r3, [r3, #8]
	36	+ lsr r0, r1, #6
	37	+ bx r3 @ indirect register sibling call
	38	+.L3:
	39	+ .align 2
	40	+.L2:
	41	+ .word 274877907
	42	+ .word arm_delay_ops
	43	+ .fnend
	44	+ .size ndelay, .-ndelay
	45	+ .align 2
	46	+ .syntax unified
	47	+ .arm
	48	+ .fpu softvfp
	49	+ .type flash_read_ecc, %function
	50	+flash_read_ecc:
	51	+ .fnstart
	52	+ @ args = 0, pretend = 0, frame = 0
	53	+ @ frame_needed = 0, uses_anonymous_args = 0
	54	+ ldr r3, .L6
	55	+ push {r4, lr}
	56	+ .save {r4, lr}
	57	+ ldr r4, [r3, r0, lsl #3]
	58	+ add r3, r3, r0, lsl #3
	59	+ mov r0, #80
	60	+ ldrb r3, [r3, #4] @ zero_extendqisi2
	61	+ add r4, r4, r3, lsl #8
	62	+ mov r3, #122
	63	+ str r3, [r4, #2056]
	64	+ bl ndelay
	65	+ ldr r3, [r4, #2048]
	66	+ ldr r0, [r4, #2048]
	67	+ and r3, r3, #15
	68	+ and r0, r0, #15
	69	+ cmp r0, r3
	70	+ movcc r0, r3
	71	+ ldr r3, [r4, #2048]
	72	+ and r3, r3, #15
	73	+ cmp r3, r0
	74	+ movcc r3, r0
	75	+ ldr r0, [r4, #2048]
	76	+ and r0, r0, #15
	77	+ cmp r0, r3
	78	+ movcc r0, r3
	79	+ pop {r4, pc}
	80	+.L7:
	81	+ .align 2
	82	+.L6:
	83	+ .word .LANCHOR0
	84	+ .fnend
	85	+ .size flash_read_ecc, .-flash_read_ecc
	86	+ .align 2
	87	+ .syntax unified
	88	+ .arm
	89	+ .fpu softvfp
	90	+ .type ftl_set_blk_mode.part.17, %function
	91	+ftl_set_blk_mode.part.17:
	92	+ .fnstart
	93	+ @ args = 0, pretend = 0, frame = 0
	94	+ @ frame_needed = 0, uses_anonymous_args = 0
	95	+ @ link register save eliminated.
	96	+ ldr r3, .L9
	97	+ lsr r1, r0, #5
	98	+ mov ip, #1
	99	+ and r0, r0, #31
	100	+ ldr r2, [r3, #32]
	101	+ ldr r3, [r2, r1, lsl #2]
	102	+ orr r0, r3, ip, lsl r0
	103	+ str r0, [r2, r1, lsl #2]
	104	+ bx lr
	105	+.L10:
	106	+ .align 2
	107	+.L9:
	108	+ .word .LANCHOR0
	109	+ .fnend
	110	+ .size ftl_set_blk_mode.part.17, .-ftl_set_blk_mode.part.17
	111	+ .align 2
27	112	.global FlashMemCmp8
	113	+ .syntax unified
	114	+ .arm
	115	+ .fpu softvfp
28	116	.type FlashMemCmp8, %function
29	117	FlashMemCmp8:
30	118	.fnstart
31	119	@ args = 0, pretend = 0, frame = 0
32	120	@ frame_needed = 0, uses_anonymous_args = 0
33		- ldr r3, .L11
34		- str lr, [sp, #-4]!
35		- .save {lr}
36		- ldrb r3, [r3] @ zero_extendqisi2
	121	+ ldr r3, .L25
	122	+ ldrb r3, [r3, #36] @ zero_extendqisi2
37	123	cmp r3, #0
38		- beq .L4
	124	+ beq .L20
39	125	ldrb r3, [r1, #1] @ zero_extendqisi2
40	126	ldrb ip, [r0, #1] @ zero_extendqisi2
41	127	cmp ip, r3
42	128	movne r3, #0
43		- beq .L8
44		-.L4:
	129	+ bne .L20
	130	+.L24:
	131	+ mov r0, #0
	132	+ bx lr
	133	+.L14:
45	134	cmp r3, r2
46		- beq .L8
	135	+ bne .L16
	136	+ mov r0, #0
	137	+ ldr pc, [sp], #4
	138	+.L20:
	139	+ cmp r3, r2
	140	+ beq .L24
	141	+ str lr, [sp, #-4]!
	142	+ .save {lr}
	143	+.L16:
47	144	ldrb lr, [r0, r3] @ zero_extendqisi2
48	145	ldrb ip, [r1, r3] @ zero_extendqisi2
49	146	add r3, r3, #1
50	147	cmp lr, ip
51		- beq .L4
	148	+ beq .L14
52	149	mov r0, r3
53	150	ldr pc, [sp], #4
54		-.L8:
55		- mov r0, #0
56		- ldr pc, [sp], #4
57		-.L12:
	151	+.L26:
58	152	.align 2
59		-.L11:
	153	+.L25:
60	154	.word .LANCHOR0
61	155	.fnend
62	156	.size FlashMemCmp8, .-FlashMemCmp8
63	157	.align 2
64	158	.global FlashRsvdBlkChk
	159	+ .syntax unified
	160	+ .arm
	161	+ .fpu softvfp
65	162	.type FlashRsvdBlkChk, %function
66	163	FlashRsvdBlkChk:
67	164	.fnstart
68	165	@ args = 0, pretend = 0, frame = 0
69	166	@ frame_needed = 0, uses_anonymous_args = 0
70	167	@ link register save eliminated.
71		- ldr r3, .L14
72		- ldrb r2, [r3, #1] @ zero_extendqisi2
73		- ldr r3, [r3, #4]
74		- mul r3, r3, r2
75		- cmp r1, r3
76		- movcs r2, #0
77		- movcc r2, #1
	168	+ ldr r2, .L28
	169	+ ldrb ip, [r2, #37] @ zero_extendqisi2
	170	+ ldr r3, [r2, #40]
	171	+ mul r3, r3, ip
	172	+ cmp r3, r1
	173	+ movls r2, #0
	174	+ movhi r2, #1
78	175	cmp r0, #0
79	176	movne r2, #0
80	177	eor r0, r2, #1
81	178	bx lr
82		-.L15:
	179	+.L29:
83	180	.align 2
84		-.L14:
	181	+.L28:
85	182	.word .LANCHOR0
86	183	.fnend
87	184	.size FlashRsvdBlkChk, .-FlashRsvdBlkChk
88	185	.align 2
89	186	.global FlashGetRandomizer
	187	+ .syntax unified
	188	+ .arm
	189	+ .fpu softvfp
90	190	.type FlashGetRandomizer, %function
91	191	FlashGetRandomizer:
92	192	.fnstart
93	193	@ args = 0, pretend = 0, frame = 0
94	194	@ frame_needed = 0, uses_anonymous_args = 0
95	195	and r3, r1, #127
96		- ldr r2, .L25
97		- stmfd sp!, {r4, lr}
	196	+ ldr r2, .L39
	197	+ lsl r3, r3, #1
	198	+ push {r4, lr}
98	199	.save {r4, lr}
99		- mov r3, r3, asl #1
100	200	ldrh r4, [r2, r3]
101		- ldr r3, .L25+4
102		- ldrb r3, [r3, #8] @ zero_extendqisi2
	201	+ ldr r3, .L39+4
	202	+ ldrb r3, [r3, #44] @ zero_extendqisi2
103	203	cmp r3, #0
104		- beq .L17
	204	+ beq .L30
105	205	bl FlashRsvdBlkChk
106	206	cmp r0, #0
107	207	orrne r4, r4, #-1073741824
108		-.L17:
	208	+.L30:
109	209	mov r0, r4
110		- ldmfd sp!, {r4, pc}
111		-.L26:
	210	+ pop {r4, pc}
	211	+.L40:
112	212	.align 2
113		-.L25:
	213	+.L39:
114	214	.word .LANCHOR1
115	215	.word .LANCHOR0
116	216	.fnend
117	217	.size FlashGetRandomizer, .-FlashGetRandomizer
118	218	.align 2
119	219	.global FlashSetRandomizer
	220	+ .syntax unified
	221	+ .arm
	222	+ .fpu softvfp
120	223	.type FlashSetRandomizer, %function
121	224	FlashSetRandomizer:
122	225	.fnstart
123	226	@ args = 0, pretend = 0, frame = 0
124	227	@ frame_needed = 0, uses_anonymous_args = 0
	228	+ ldr r2, .L50
125	229	and r3, r1, #127
126		- ldr r2, .L36
127		- stmfd sp!, {r4, r5, r6, lr}
	230	+ lsl r3, r3, #1
	231	+ push {r4, r5, r6, lr}
128	232	.save {r4, r5, r6, lr}
129		- mov r3, r3, asl #1
130	233	mov r6, r0
131	234	ldrh r5, [r2, r3]
132		- ldr r3, .L36+4
133		- ldrb r2, [r3, #8] @ zero_extendqisi2
	235	+ ldr r3, .L50+4
	236	+ ldrb r2, [r3, #44] @ zero_extendqisi2
134	237	mov r4, r3
135	238	cmp r2, #0
136		- beq .L28
	239	+ beq .L42
137	240	bl FlashRsvdBlkChk
138	241	cmp r0, #0
139	242	orrne r5, r5, #-1073741824
140		-.L28:
141		- add r4, r4, r6, asl #3
142		- ldr r3, [r4, #12]
	243	+.L42:
	244	+ ldr r3, [r4, r6, lsl #3]
143	245	str r5, [r3, #336]
144		- ldmfd sp!, {r4, r5, r6, pc}
145		-.L37:
	246	+ pop {r4, r5, r6, pc}
	247	+.L51:
146	248	.align 2
147		-.L36:
	249	+.L50:
148	250	.word .LANCHOR1
149	251	.word .LANCHOR0
150	252	.fnend
151	253	.size FlashSetRandomizer, .-FlashSetRandomizer
152	254	.align 2
153	255	.global FlashBlockAlignInit
	256	+ .syntax unified
	257	+ .arm
	258	+ .fpu softvfp
154	259	.type FlashBlockAlignInit, %function
155	260	FlashBlockAlignInit:
156	261	.fnstart
..	..	@@ -158,45 +263,49 @@
158	263	@ frame_needed = 0, uses_anonymous_args = 0
159	264	@ link register save eliminated.
160	265	cmp r0, #512
161		- ldr r3, .L44
	266	+ ldr r3, .L58
162	267	movhi r2, #1024
163		- bhi .L43
	268	+ bhi .L57
164	269	cmp r0, #256
165	270	movhi r2, #512
166		- bhi .L43
	271	+ bhi .L57
167	272	cmp r0, #128
168		- strls r0, [r3, #4]
169		- bxls lr
170		- mov r2, #256
171		-.L43:
172		- str r2, [r3, #4]
	273	+ movhi r2, #256
	274	+ bhi .L57
	275	+ str r0, [r3, #40]
173	276	bx lr
174		-.L45:
	277	+.L57:
	278	+ str r2, [r3, #40]
	279	+ bx lr
	280	+.L59:
175	281	.align 2
176		-.L44:
	282	+.L58:
177	283	.word .LANCHOR0
178	284	.fnend
179	285	.size FlashBlockAlignInit, .-FlashBlockAlignInit
180	286	.align 2
181	287	.global FlashReadCmd
	288	+ .syntax unified
	289	+ .arm
	290	+ .fpu softvfp
182	291	.type FlashReadCmd, %function
183	292	FlashReadCmd:
184	293	.fnstart
185	294	@ args = 0, pretend = 0, frame = 0
186	295	@ frame_needed = 0, uses_anonymous_args = 0
187		- ldr ip, .L49
	296	+ ldr ip, .L63
188	297	str lr, [sp, #-4]!
189	298	.save {lr}
190		- add r3, ip, r0, asl #3
191		- ldr ip, [ip, #44]
192		- ldr r2, [r3, #12]
193		- ldrb r3, [r3, #16] @ zero_extendqisi2
	299	+ add r2, ip, r0, lsl #3
	300	+ ldr r3, [ip, r0, lsl #3]
	301	+ ldr ip, [ip, #48]
	302	+ ldrb r2, [r2, #4] @ zero_extendqisi2
194	303	ldrb ip, [ip, #7] @ zero_extendqisi2
195		- mov r3, r3, asl #8
	304	+ lsl r2, r2, #8
196	305	cmp ip, #1
197		- addeq ip, r2, r3
198		- add r3, r2, r3
	306	+ addeq ip, r3, r2
199	307	moveq lr, #38
	308	+ add r3, r3, r2
200	309	mov r2, #0
201	310	streq lr, [ip, #2056]
202	311	str r2, [r3, #2056]
..	..	@@ -204,41 +313,44 @@
204	313	str r2, [r3, #2052]
205	314	uxtb r2, r1
206	315	str r2, [r3, #2052]
207		- mov r2, r1, lsr #8
	316	+ lsr r2, r1, #8
208	317	str r2, [r3, #2052]
209		- mov r2, r1, lsr #16
	318	+ lsr r2, r1, #16
210	319	str r2, [r3, #2052]
211	320	mov r2, #48
212	321	str r2, [r3, #2056]
213	322	ldr lr, [sp], #4
214	323	b FlashSetRandomizer
215		-.L50:
	324	+.L64:
216	325	.align 2
217		-.L49:
	326	+.L63:
218	327	.word .LANCHOR0
219	328	.fnend
220	329	.size FlashReadCmd, .-FlashReadCmd
221	330	.align 2
222	331	.global FlashReadDpDataOutCmd
	332	+ .syntax unified
	333	+ .arm
	334	+ .fpu softvfp
223	335	.type FlashReadDpDataOutCmd, %function
224	336	FlashReadDpDataOutCmd:
225	337	.fnstart
226	338	@ args = 0, pretend = 0, frame = 0
227	339	@ frame_needed = 0, uses_anonymous_args = 0
228		- ldr ip, .L56
229		- stmfd sp!, {r4, lr}
	340	+ ldr ip, .L70
	341	+ push {r4, lr}
230	342	.save {r4, lr}
231		- add r3, ip, r0, asl #3
232		- ldrb ip, [ip, #64] @ zero_extendqisi2
233	343	uxtb r4, r1
234		- ldr r2, [r3, #12]
235		- mov lr, r1, lsr #8
236		- ldrb r3, [r3, #16] @ zero_extendqisi2
	344	+ lsr lr, r1, #8
	345	+ add r2, ip, r0, lsl #3
	346	+ ldr r3, [ip, r0, lsl #3]
	347	+ ldrb ip, [ip, #68] @ zero_extendqisi2
	348	+ ldrb r2, [r2, #4] @ zero_extendqisi2
237	349	cmp ip, #1
238		- mov ip, r1, lsr #16
239		- mov r3, r3, asl #8
240		- add r3, r2, r3
241		- bne .L52
	350	+ lsr ip, r1, #16
	351	+ lsl r2, r2, #8
	352	+ add r3, r3, r2
	353	+ bne .L66
242	354	mov r2, #6
243	355	str r2, [r3, #2056]
244	356	mov r2, #0
..	..	@@ -247,8 +359,12 @@
247	359	str r4, [r3, #2052]
248	360	str lr, [r3, #2052]
249	361	str ip, [r3, #2052]
250		- b .L55
251		-.L52:
	362	+.L69:
	363	+ mov r2, #224
	364	+ str r2, [r3, #2056]
	365	+ pop {r4, lr}
	366	+ b FlashSetRandomizer
	367	+.L66:
252	368	mov r2, #0
253	369	str r2, [r3, #2056]
254	370	str r2, [r3, #2052]
..	..	@@ -260,31 +376,31 @@
260	376	str ip, [r3, #2056]
261	377	str r2, [r3, #2052]
262	378	str r2, [r3, #2052]
263		-.L55:
264		- mov r2, #224
265		- str r2, [r3, #2056]
266		- ldmfd sp!, {r4, lr}
267		- b FlashSetRandomizer
268		-.L57:
	379	+ b .L69
	380	+.L71:
269	381	.align 2
270		-.L56:
	382	+.L70:
271	383	.word .LANCHOR0
272	384	.fnend
273	385	.size FlashReadDpDataOutCmd, .-FlashReadDpDataOutCmd
274	386	.align 2
275	387	.global FlashProgFirstCmd
	388	+ .syntax unified
	389	+ .arm
	390	+ .fpu softvfp
276	391	.type FlashProgFirstCmd, %function
277	392	FlashProgFirstCmd:
278	393	.fnstart
279	394	@ args = 0, pretend = 0, frame = 0
280	395	@ frame_needed = 0, uses_anonymous_args = 0
281		- @ link register save eliminated.
282		- ldr ip, .L59
283		- mov r2, r1, lsr #16
284		- add ip, ip, r0, asl #3
285		- ldr r3, [ip, #12]
286		- ldrb ip, [ip, #16] @ zero_extendqisi2
287		- add r3, r3, ip, asl #8
	396	+ ldr ip, .L74
	397	+ lsr r2, r1, #16
	398	+ str lr, [sp, #-4]!
	399	+ .save {lr}
	400	+ ldr r3, [ip, r0, lsl #3]
	401	+ add ip, ip, r0, lsl #3
	402	+ ldrb ip, [ip, #4] @ zero_extendqisi2
	403	+ add r3, r3, ip, lsl #8
288	404	mov ip, #128
289	405	str ip, [r3, #2056]
290	406	mov ip, #0
..	..	@@ -292,176 +408,225 @@
292	408	str ip, [r3, #2052]
293	409	uxtb ip, r1
294	410	str ip, [r3, #2052]
295		- mov ip, r1, lsr #8
	411	+ lsr ip, r1, #8
296	412	str ip, [r3, #2052]
297	413	str r2, [r3, #2052]
	414	+ ldr lr, [sp], #4
298	415	b FlashSetRandomizer
299		-.L60:
	416	+.L75:
300	417	.align 2
301		-.L59:
	418	+.L74:
302	419	.word .LANCHOR0
303	420	.fnend
304	421	.size FlashProgFirstCmd, .-FlashProgFirstCmd
305	422	.align 2
306	423	.global FlashEraseCmd
	424	+ .syntax unified
	425	+ .arm
	426	+ .fpu softvfp
307	427	.type FlashEraseCmd, %function
308	428	FlashEraseCmd:
309	429	.fnstart
310	430	@ args = 0, pretend = 0, frame = 0
311	431	@ frame_needed = 0, uses_anonymous_args = 0
	432	+ ldr ip, .L82
	433	+ cmp r2, #0
312	434	str lr, [sp, #-4]!
313	435	.save {lr}
314		- cmp r2, #0
315		- ldr lr, .L67
316		- add r0, lr, r0, asl #3
317		- ldrb r3, [r0, #16] @ zero_extendqisi2
318		- ldr ip, [r0, #12]
319		- mov r3, r3, asl #8
320		- beq .L62
321		- add r2, ip, r3
322		- mov r0, #96
323		- str r0, [r2, #2056]
324		- uxtb r0, r1
325		- str r0, [r2, #2052]
326		- mov r0, r1, lsr #8
327		- str r0, [r2, #2052]
328		- mov r0, r1, lsr #16
329		- str r0, [r2, #2052]
330		- ldr r2, [lr, #4]
	436	+ ldr r3, [ip, r0, lsl #3]
	437	+ add r0, ip, r0, lsl #3
	438	+ ldrb r0, [r0, #4] @ zero_extendqisi2
	439	+ lsl r0, r0, #8
	440	+ beq .L77
	441	+ add r2, r3, r0
	442	+ mov lr, #96
	443	+ str lr, [r2, #2056]
	444	+ uxtb lr, r1
	445	+ str lr, [r2, #2052]
	446	+ lsr lr, r1, #8
	447	+ str lr, [r2, #2052]
	448	+ lsr lr, r1, #16
	449	+ str lr, [r2, #2052]
	450	+ ldr r2, [ip, #40]
331	451	add r1, r1, r2
332		-.L62:
333		- add r3, ip, r3
	452	+.L77:
	453	+ add r3, r3, r0
334	454	mov r2, #96
335	455	str r2, [r3, #2056]
336	456	uxtb r2, r1
337	457	str r2, [r3, #2052]
338		- mov r2, r1, lsr #8
339		- mov r1, r1, lsr #16
	458	+ lsr r2, r1, #8
	459	+ lsr r1, r1, #16
340	460	str r2, [r3, #2052]
341		- str r1, [r3, #2052]
342	461	mov r2, #208
	462	+ str r1, [r3, #2052]
343	463	str r2, [r3, #2056]
344	464	ldr pc, [sp], #4
345		-.L68:
	465	+.L83:
346	466	.align 2
347		-.L67:
	467	+.L82:
348	468	.word .LANCHOR0
349	469	.fnend
350	470	.size FlashEraseCmd, .-FlashEraseCmd
351	471	.align 2
352	472	.global FlashProgDpSecondCmd
	473	+ .syntax unified
	474	+ .arm
	475	+ .fpu softvfp
353	476	.type FlashProgDpSecondCmd, %function
354	477	FlashProgDpSecondCmd:
355	478	.fnstart
356	479	@ args = 0, pretend = 0, frame = 0
357	480	@ frame_needed = 0, uses_anonymous_args = 0
358		- ldr ip, .L71
359		- mov r2, r1, lsr #16
360		- str lr, [sp, #-4]!
361		- .save {lr}
362		- add lr, ip, r0, asl #3
363		- ldrb ip, [ip, #59] @ zero_extendqisi2
364		- ldr r3, [lr, #12]
365		- ldrb lr, [lr, #16] @ zero_extendqisi2
366		- add r3, r3, lr, asl #8
	481	+ push {r4, lr}
	482	+ .save {r4, lr}
	483	+ lsr r2, r1, #16
	484	+ ldr lr, .L86
	485	+ ldr r3, [lr, r0, lsl #3]
	486	+ add ip, lr, r0, lsl #3
	487	+ ldrb r4, [ip, #4] @ zero_extendqisi2
	488	+ ldrb ip, [lr, #63] @ zero_extendqisi2
	489	+ add r3, r3, r4, lsl #8
367	490	str ip, [r3, #2056]
368	491	mov ip, #0
369	492	str ip, [r3, #2052]
370	493	str ip, [r3, #2052]
371	494	uxtb ip, r1
372	495	str ip, [r3, #2052]
373		- mov ip, r1, lsr #8
	496	+ lsr ip, r1, #8
374	497	str ip, [r3, #2052]
375	498	str r2, [r3, #2052]
376		- ldr lr, [sp], #4
	499	+ pop {r4, lr}
377	500	b FlashSetRandomizer
378		-.L72:
	501	+.L87:
379	502	.align 2
380		-.L71:
	503	+.L86:
381	504	.word .LANCHOR0
382	505	.fnend
383	506	.size FlashProgDpSecondCmd, .-FlashProgDpSecondCmd
384	507	.align 2
385	508	.global FlashProgSecondCmd
	509	+ .syntax unified
	510	+ .arm
	511	+ .fpu softvfp
386	512	.type FlashProgSecondCmd, %function
387	513	FlashProgSecondCmd:
388	514	.fnstart
389	515	@ args = 0, pretend = 0, frame = 0
390	516	@ frame_needed = 0, uses_anonymous_args = 0
391		- stmfd sp!, {r3, r4, r5, lr}
392		- .save {r3, r4, r5, lr}
393		- ldr r3, .L75
394		- add r0, r3, r0, asl #3
395		- ldr r3, .L75+4
396		- ldrb r5, [r0, #16] @ zero_extendqisi2
397		- ldr r4, [r0, #12]
	517	+ ldr r3, .L90
	518	+ push {r4, r5, r6, lr}
	519	+ .save {r4, r5, r6, lr}
	520	+ ldr r4, [r3, r0, lsl #3]
	521	+ add r3, r3, r0, lsl #3
	522	+ ldr r0, .L90+4
	523	+ ldrb r5, [r3, #4] @ zero_extendqisi2
	524	+ ldr r3, .L90+8
	525	+ add r4, r4, r5, lsl #8
398	526	ldr r3, [r3, #4]
399		- add r4, r4, r5, asl #8
400		- ldr r0, .L75+8
401	527	blx r3
402	528	mov r3, #16
403	529	str r3, [r4, #2056]
404		- ldmfd sp!, {r3, r4, r5, pc}
405		-.L76:
	530	+ pop {r4, r5, r6, pc}
	531	+.L91:
406	532	.align 2
407		-.L75:
	533	+.L90:
408	534	.word .LANCHOR0
	535	+ .word 64424500
409	536	.word arm_delay_ops
410		- .word 214748300
411	537	.fnend
412	538	.size FlashProgSecondCmd, .-FlashProgSecondCmd
413	539	.align 2
414	540	.global FlashProgDpFirstCmd
	541	+ .syntax unified
	542	+ .arm
	543	+ .fpu softvfp
415	544	.type FlashProgDpFirstCmd, %function
416	545	FlashProgDpFirstCmd:
417	546	.fnstart
418	547	@ args = 0, pretend = 0, frame = 0
419	548	@ frame_needed = 0, uses_anonymous_args = 0
420	549	@ link register save eliminated.
421		- ldr r2, .L78
422		- add r0, r2, r0, asl #3
423		- ldrb r2, [r2, #58] @ zero_extendqisi2
424		- ldrb r1, [r0, #16] @ zero_extendqisi2
425		- ldr r3, [r0, #12]
426		- add r3, r3, r1, asl #8
	550	+ ldr r2, .L93
	551	+ ldr r3, [r2, r0, lsl #3]
	552	+ add r0, r2, r0, lsl #3
	553	+ ldrb r2, [r2, #62] @ zero_extendqisi2
	554	+ ldrb r1, [r0, #4] @ zero_extendqisi2
	555	+ add r3, r3, r1, lsl #8
427	556	str r2, [r3, #2056]
428	557	bx lr
429		-.L79:
	558	+.L94:
430	559	.align 2
431		-.L78:
	560	+.L93:
432	561	.word .LANCHOR0
433	562	.fnend
434	563	.size FlashProgDpFirstCmd, .-FlashProgDpFirstCmd
435	564	.align 2
	565	+ .global FlashReadStatus
	566	+ .syntax unified
	567	+ .arm
	568	+ .fpu softvfp
	569	+ .type FlashReadStatus, %function
	570	+FlashReadStatus:
	571	+ .fnstart
	572	+ @ args = 0, pretend = 0, frame = 0
	573	+ @ frame_needed = 0, uses_anonymous_args = 0
	574	+ ldr r3, .L97
	575	+ mov r2, #112
	576	+ push {r4, r5, r6, lr}
	577	+ .save {r4, r5, r6, lr}
	578	+ ldr r5, [r3, r0, lsl #3]
	579	+ add r3, r3, r0, lsl #3
	580	+ mov r0, #80
	581	+ ldrb r4, [r3, #4] @ zero_extendqisi2
	582	+ add r3, r5, r4, lsl #8
	583	+ add r4, r4, #8
	584	+ str r2, [r3, #2056]
	585	+ bl ndelay
	586	+ ldr r0, [r5, r4, lsl #8]
	587	+ pop {r4, r5, r6, pc}
	588	+.L98:
	589	+ .align 2
	590	+.L97:
	591	+ .word .LANCHOR0
	592	+ .fnend
	593	+ .size FlashReadStatus, .-FlashReadStatus
	594	+ .align 2
436	595	.global js_hash
	596	+ .syntax unified
	597	+ .arm
	598	+ .fpu softvfp
437	599	.type js_hash, %function
438	600	js_hash:
439	601	.fnstart
440	602	@ args = 0, pretend = 0, frame = 0
441	603	@ frame_needed = 0, uses_anonymous_args = 0
442	604	@ link register save eliminated.
443		- ldr r3, .L84
	605	+ ldr r3, .L102
444	606	add r1, r0, r1
445		-.L81:
	607	+.L100:
446	608	cmp r0, r1
447		- beq .L83
448		- mov r2, r3, asl #5
449		- ldrb ip, [r0], #1 @ zero_extendqisi2
450		- add r2, r2, r3, lsr #2
451		- add r2, r2, ip
452		- eor r3, r3, r2
453		- b .L81
454		-.L83:
	609	+ bne .L101
455	610	mov r0, r3
456	611	bx lr
457		-.L85:
	612	+.L101:
	613	+ lsr r2, r3, #2
	614	+ ldrb ip, [r0], #1 @ zero_extendqisi2
	615	+ add r2, r2, r3, lsl #5
	616	+ add r2, r2, ip
	617	+ eor r3, r3, r2
	618	+ b .L100
	619	+.L103:
458	620	.align 2
459		-.L84:
	621	+.L102:
460	622	.word 1204201446
461	623	.fnend
462	624	.size js_hash, .-js_hash
463	625	.align 2
464	626	.global FlashLoadIdbInfo
	627	+ .syntax unified
	628	+ .arm
	629	+ .fpu softvfp
465	630	.type FlashLoadIdbInfo, %function
466	631	FlashLoadIdbInfo:
467	632	.fnstart
..	..	@@ -474,270 +639,276 @@
474	639	.size FlashLoadIdbInfo, .-FlashLoadIdbInfo
475	640	.align 2
476	641	.global BuildFlashLsbPageTable
	642	+ .syntax unified
	643	+ .arm
	644	+ .fpu softvfp
477	645	.type BuildFlashLsbPageTable, %function
478	646	BuildFlashLsbPageTable:
479	647	.fnstart
480	648	@ args = 0, pretend = 0, frame = 0
481	649	@ frame_needed = 0, uses_anonymous_args = 0
482	650	cmp r0, #0
483		- stmfd sp!, {r4, lr}
	651	+ push {r4, lr}
484	652	.save {r4, lr}
485	653	mov r4, r1
486		- bne .L88
487		- ldr r3, .L131
488		-.L89:
489		- mov r2, r0, asl #1
	654	+ bne .L106
	655	+ ldr r3, .L162
	656	+.L107:
	657	+ lsl r2, r0, #1
490	658	strh r0, [r2, r3] @ movhi
491	659	add r0, r0, #1
492	660	cmp r0, #512
493		- bne .L89
494		-.L93:
	661	+ bne .L107
	662	+.L113:
495	663	mov r2, #2048
496		- ldr r0, .L131+4
497	664	mov r1, #255
	665	+ ldr r0, .L162+4
498	666	uxth r4, r4
499	667	bl ftl_memset
500		- ldr r2, .L131
	668	+ ldr r2, .L162
501	669	mov r3, #0
502	670	add r0, r2, #1024
503		- b .L90
504		-.L88:
	671	+.L108:
	672	+ uxth r1, r3
	673	+ cmp r4, r1
	674	+ bhi .L141
	675	+ pop {r4, pc}
	676	+.L106:
505	677	cmp r0, #1
506		- bne .L91
507		- ldr ip, .L131
	678	+ bne .L109
	679	+ ldr r1, .L162
508	680	mov r3, #0
509		-.L92:
	681	+.L112:
	682	+ cmp r3, #3
510	683	uxth r2, r3
511		- mov lr, r3, asl #1
512		- cmp r2, #3
513		- movls r0, #0
514		- movhi r0, #1
515		- bics r1, r0, r3
	684	+ bls .L110
	685	+ tst r2, #1
	686	+ movne r0, #3
	687	+ moveq r0, #2
	688	+ rsb r2, r0, r2, lsl #1
	689	+ uxth r2, r2
	690	+.L110:
	691	+ lsl r0, r3, #1
516	692	add r3, r3, #1
517		- movne r1, #2
518		- moveq r1, #3
519		- cmp r0, #0
520		- rsb r1, r1, r2, asl #1
521		- movne r2, r1
522		- cmp r3, #512
523		- strh r2, [lr, ip] @ movhi
524		- bne .L92
525		- b .L93
526		-.L91:
527		- cmp r0, #2
528		- bne .L94
529		- ldr r1, .L131
530		- mov r3, #0
531		-.L95:
532		- uxth r2, r3
533		- mov r0, r3, asl #1
534		- cmp r2, #1
535		- add r3, r3, #1
536		- mov ip, r2, asl #1
537		- subhi r2, ip, #1
538	693	cmp r3, #512
539	694	strh r2, [r0, r1] @ movhi
540		- bne .L95
541		- b .L93
542		-.L94:
	695	+ bne .L112
	696	+ b .L113
	697	+.L109:
	698	+ cmp r0, #2
	699	+ bne .L114
	700	+ ldr r1, .L162
	701	+ mov r2, #0
	702	+.L116:
	703	+ uxth r3, r2
	704	+ cmp r2, #1
	705	+ lsl r0, r2, #1
	706	+ add r2, r2, #1
	707	+ lslhi r3, r3, #1
	708	+ subhi r3, r3, #1
	709	+ uxthhi r3, r3
	710	+ cmp r2, #512
	711	+ strh r3, [r0, r1] @ movhi
	712	+ bne .L116
	713	+ b .L113
	714	+.L114:
543	715	cmp r0, #3
544		- bne .L96
545		- ldr ip, .L131
	716	+ bne .L117
	717	+ ldr r1, .L162
546	718	mov r3, #0
547		-.L97:
	719	+.L120:
	720	+ cmp r3, #5
548	721	uxth r2, r3
549		- mov lr, r3, asl #1
550		- cmp r2, #5
551		- movls r0, #0
552		- movhi r0, #1
553		- bics r1, r0, r3
	722	+ bls .L118
	723	+ tst r2, #1
	724	+ movne r0, #5
	725	+ moveq r0, #4
	726	+ rsb r2, r0, r2, lsl #1
	727	+ uxth r2, r2
	728	+.L118:
	729	+ lsl r0, r3, #1
554	730	add r3, r3, #1
555		- movne r1, #4
556		- moveq r1, #5
557		- cmp r0, #0
558		- rsb r1, r1, r2, asl #1
559		- movne r2, r1
560	731	cmp r3, #512
561		- strh r2, [lr, ip] @ movhi
562		- bne .L97
563		- b .L93
564		-.L96:
	732	+ strh r2, [r0, r1] @ movhi
	733	+ bne .L120
	734	+ b .L113
	735	+.L117:
565	736	cmp r0, #4
566	737	mov r3, #0
567		- bne .L98
568		- ldr r2, .L131+8
569		- strh r3, [r2, #80] @ movhi
570		- mov r3, #1
571		- strh r0, [r2, #88] @ movhi
572		- strh r3, [r2, #82] @ movhi
573		- mov r3, #2
	738	+ bne .L121
	739	+ ldr r2, .L162+8
574	740	strh r3, [r2, #84] @ movhi
575		- mov r3, #3
	741	+ mov r3, #1
576	742	strh r3, [r2, #86] @ movhi
577		- mov r3, #5
	743	+ mov r3, #2
	744	+ strh r3, [r2, #88] @ movhi
	745	+ mov r3, #3
578	746	strh r3, [r2, #90] @ movhi
	747	+ mov r3, #5
	748	+ strh r3, [r2, #94] @ movhi
579	749	mov r3, #7
580		- strh r3, [r2, #92] @ movhi
	750	+ strh r3, [r2, #96] @ movhi
581	751	mov r3, #8
582		- strh r3, [r2, #94]! @ movhi
583		-.L99:
	752	+ strh r0, [r2, #92] @ movhi
	753	+ strh r3, [r2, #98]! @ movhi
	754	+.L123:
584	755	tst r3, #1
585	756	movne r1, #7
586	757	moveq r1, #6
587		- rsb r1, r1, r3, asl #1
	758	+ rsb r1, r1, r3, lsl #1
588	759	add r3, r3, #1
589		- strh r1, [r2, #2]! @ movhi
590	760	uxth r3, r3
	761	+ strh r1, [r2, #2]! @ movhi
591	762	cmp r3, #512
592		- bne .L99
593		- b .L93
594		-.L98:
	763	+ bne .L123
	764	+ b .L113
	765	+.L121:
595	766	cmp r0, #5
596		- bne .L100
597		- ldr r2, .L131
598		-.L101:
599		- mov r1, r3, asl #1
600		- strh r3, [r1, r2] @ movhi
	767	+ bne .L124
	768	+ ldr r2, .L162+8
	769	+ add r1, r2, #84
	770	+.L125:
	771	+ lsl r0, r3, #1
	772	+ strh r3, [r0, r1] @ movhi
601	773	add r3, r3, #1
602	774	cmp r3, #16
603		- bne .L101
604		- ldr r2, .L131+12
605		-.L102:
	775	+ bne .L125
	776	+ add r2, r2, #114
	777	+.L126:
606	778	strh r3, [r2, #2]! @ movhi
607	779	add r3, r3, #2
608	780	uxth r3, r3
609	781	cmp r3, #1008
610		- bne .L102
611		- b .L93
612		-.L100:
	782	+ bne .L126
	783	+ b .L113
	784	+.L124:
613	785	cmp r0, #6
614		- bne .L103
615		- ldr r1, .L131+16
616		-.L104:
617		- cmp r3, #5
618		- add r2, r3, r3, asl #1
619		- movls r0, #0
620		- movhi r0, #1
621		- bics ip, r0, r3
622		- movne ip, #10
623		- moveq ip, #12
624		- cmp r0, #0
625		- subne r2, r2, ip
626		- moveq r2, r3
627		- add r3, r3, #1
628		- strh r2, [r1, #2]! @ movhi
	786	+ bne .L127
	787	+ ldr r0, .L162
	788	+ mov r1, r3
	789	+.L130:
	790	+ cmp r1, #5
	791	+ uxth r2, r1
	792	+ bls .L128
	793	+ tst r2, #1
	794	+ movne r2, #12
	795	+ moveq r2, #10
	796	+ sub r2, r3, r2
	797	+ uxth r2, r2
	798	+.L128:
	799	+ lsl ip, r1, #1
	800	+ add r1, r1, #1
	801	+ cmp r1, #512
	802	+ add r3, r3, #3
	803	+ strh r2, [ip, r0] @ movhi
629	804	uxth r3, r3
630		- cmp r3, #512
631		- bne .L104
632		- b .L93
633		-.L103:
	805	+ bne .L130
	806	+ b .L113
	807	+.L127:
634	808	cmp r0, #9
635		- bne .L105
636		- ldr r2, .L131+8
	809	+ bne .L131
	810	+ ldr r2, .L162+8
637	811	movw r1, #1021
638		- strh r3, [r2, #80] @ movhi
	812	+ strh r3, [r2, #84] @ movhi
639	813	mov r3, #1
640		- strh r3, [r2, #82] @ movhi
641		- mov r3, #2
642		- strh r3, [r2, #84]! @ movhi
643		- mov r3, #3
644		-.L106:
645		- strh r3, [r2, #2]! @ movhi
646		- add r3, r3, #2
647		- uxth r3, r3
648		- cmp r3, r1
649		- bne .L106
650		- b .L93
651		-.L105:
	814	+ strh r3, [r2, #86] @ movhi
	815	+ mov r3, r2
	816	+ mov r2, #2
	817	+ strh r2, [r3, #88]! @ movhi
	818	+ mov r2, #3
	819	+.L132:
	820	+ strh r2, [r3, #2]! @ movhi
	821	+ add r2, r2, #2
	822	+ uxth r2, r2
	823	+ cmp r2, r1
	824	+ bne .L132
	825	+ b .L113
	826	+.L131:
652	827	cmp r0, #10
653		- bne .L107
654		- ldr r2, .L131
655		-.L108:
656		- mov r1, r3, asl #1
657		- strh r3, [r1, r2] @ movhi
	828	+ bne .L133
	829	+ ldr r2, .L162+8
	830	+ add r1, r2, #84
	831	+.L134:
	832	+ lsl r0, r3, #1
	833	+ strh r3, [r0, r1] @ movhi
658	834	add r3, r3, #1
659	835	cmp r3, #63
660		- bne .L108
661		- ldr r2, .L131+20
	836	+ bne .L134
	837	+ add r2, r2, #208
662	838	movw r1, #961
663		-.L109:
	839	+.L135:
664	840	strh r3, [r2, #2]! @ movhi
665	841	add r3, r3, #2
666	842	uxth r3, r3
667	843	cmp r3, r1
668		- bne .L109
669		- b .L93
670		-.L107:
	844	+ bne .L135
	845	+ b .L113
	846	+.L133:
671	847	cmp r0, #11
672		- bne .L110
673		- ldr r2, .L131
	848	+ bne .L136
	849	+ ldr r2, .L162+8
674	850	mov r3, #0
675		-.L111:
676		- mov r1, r3, asl #1
677		- strh r3, [r1, r2] @ movhi
	851	+ add r1, r2, #84
	852	+.L137:
	853	+ lsl r0, r3, #1
	854	+ strh r3, [r0, r1] @ movhi
678	855	add r3, r3, #1
679	856	cmp r3, #8
680		- bne .L111
681		- ldr r1, .L131+24
682		-.L112:
	857	+ bne .L137
	858	+ add r2, r2, #98
	859	+.L139:
683	860	tst r3, #1
684		- movne r2, #7
685		- moveq r2, #6
686		- rsb r2, r2, r3, asl #1
	861	+ movne r1, #7
	862	+ moveq r1, #6
	863	+ rsb r1, r1, r3, lsl #1
687	864	add r3, r3, #1
688		- strh r2, [r1, #2]! @ movhi
689	865	uxth r3, r3
	866	+ strh r1, [r2, #2]! @ movhi
690	867	cmp r3, #512
691		- bne .L112
692		- b .L93
693		-.L110:
	868	+ bne .L139
	869	+ b .L113
	870	+.L136:
694	871	cmp r0, #12
695		- bne .L93
696		- ldr r3, .L131+8
	872	+ bne .L113
	873	+ ldr r3, .L162+8
697	874	mov r2, #0
698		- strh r2, [r3, #80] @ movhi
699		- mov r2, #1
700		- strh r2, [r3, #82] @ movhi
701		- mov r2, #2
702	875	strh r2, [r3, #84] @ movhi
	876	+ mov r2, #1
	877	+ strh r2, [r3, #86] @ movhi
	878	+ mov r2, #2
	879	+ strh r2, [r3, #88] @ movhi
703	880	mov r2, #3
704		- strh r2, [r3, #86]! @ movhi
	881	+ strh r2, [r3, #90]! @ movhi
705	882	mov r2, #4
706		-.L113:
	883	+.L140:
707	884	sub r1, r2, #1
708	885	add r1, r1, r2, lsr #1
709	886	add r2, r2, #1
710		- strh r1, [r3, #2]! @ movhi
711	887	uxth r2, r2
	888	+ strh r1, [r3, #2]! @ movhi
712	889	cmp r2, #512
713		- bne .L113
714		- b .L93
715		-.L90:
716		- uxth r1, r3
717		- cmp r1, r4
718		- bcs .L130
719		- mov r1, r3, asl #1
	890	+ bne .L140
	891	+ b .L113
	892	+.L141:
	893	+ lsl r1, r3, #1
720	894	add r3, r3, #1
721	895	ldrh r1, [r1, r2]
722		- mov ip, r1, asl #1
	896	+ lsl ip, r1, #1
723	897	strh r1, [r0, ip] @ movhi
724		- b .L90
725		-.L130:
726		- ldmfd sp!, {r4, pc}
727		-.L132:
	898	+ b .L108
	899	+.L163:
728	900	.align 2
729		-.L131:
730		- .word .LANCHOR0+80
731		- .word .LANCHOR0+1104
	901	+.L162:
	902	+ .word .LANCHOR0+84
	903	+ .word .LANCHOR0+1108
732	904	.word .LANCHOR0
733		- .word .LANCHOR0+110
734		- .word .LANCHOR0+78
735		- .word .LANCHOR0+204
736		- .word .LANCHOR0+94
737	905	.fnend
738	906	.size BuildFlashLsbPageTable, .-BuildFlashLsbPageTable
739	907	.align 2
740	908	.global FlashPrintInfo
	909	+ .syntax unified
	910	+ .arm
	911	+ .fpu softvfp
741	912	.type FlashPrintInfo, %function
742	913	FlashPrintInfo:
743	914	.fnstart
..	..	@@ -748,405 +919,615 @@
748	919	.fnend
749	920	.size FlashPrintInfo, .-FlashPrintInfo
750	921	.align 2
	922	+ .global ToshibaSetRRPara
	923	+ .syntax unified
	924	+ .arm
	925	+ .fpu softvfp
	926	+ .type ToshibaSetRRPara, %function
	927	+ToshibaSetRRPara:
	928	+ .fnstart
	929	+ @ args = 0, pretend = 0, frame = 0
	930	+ @ frame_needed = 0, uses_anonymous_args = 0
	931	+ push {r4, r5, r6, r7, r8, lr}
	932	+ .save {r4, r5, r6, r7, r8, lr}
	933	+ add r8, r1, r1, lsl #2
	934	+ ldr r7, .L173
	935	+ mov r6, r0
	936	+ mov r5, #0
	937	+ add r7, r1, r7
	938	+.L166:
	939	+ ldr r3, .L173+4
	940	+ ldrb r3, [r3] @ zero_extendqisi2
	941	+ cmp r5, r3
	942	+ bcc .L170
	943	+ pop {r4, r5, r6, r7, r8, pc}
	944	+.L170:
	945	+ ldr r4, .L173+8
	946	+ mov r3, #85
	947	+ str r3, [r6, #8]
	948	+ mov r0, #200
	949	+ ldrsb r3, [r5, r4]
	950	+ str r3, [r6, #4]
	951	+ bl ndelay
	952	+ ldr r3, .L173+12
	953	+ ldrb r3, [r3] @ zero_extendqisi2
	954	+ cmp r3, #34
	955	+ addeq r3, r5, r8
	956	+ addeq r4, r4, r3
	957	+ ldrsbeq r3, [r4, #5]
	958	+ beq .L172
	959	+ cmp r3, #35
	960	+ addeq r3, r5, r8
	961	+ ldrsbne r3, [r7]
	962	+ addeq r4, r4, r3
	963	+ ldrsbeq r3, [r4, #50]
	964	+.L172:
	965	+ str r3, [r6]
	966	+ add r5, r5, #1
	967	+ b .L166
	968	+.L174:
	969	+ .align 2
	970	+.L173:
	971	+ .word .LANCHOR1+396
	972	+ .word g_maxRegNum
	973	+ .word .LANCHOR1+256
	974	+ .word g_retryMode
	975	+ .fnend
	976	+ .size ToshibaSetRRPara, .-ToshibaSetRRPara
	977	+ .align 2
	978	+ .global SamsungSetRRPara
	979	+ .syntax unified
	980	+ .arm
	981	+ .fpu softvfp
	982	+ .type SamsungSetRRPara, %function
	983	+SamsungSetRRPara:
	984	+ .fnstart
	985	+ @ args = 0, pretend = 0, frame = 0
	986	+ @ frame_needed = 0, uses_anonymous_args = 0
	987	+ ldr r3, .L179
	988	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
	989	+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
	990	+ mov r4, #0
	991	+ ldr r8, .L179+4
	992	+ mov r6, r0
	993	+ mov r7, r3
	994	+ mov r9, #161
	995	+ add r1, r3, r1, lsl #2
	996	+ mov r10, r4
	997	+ add r5, r1, #3
	998	+.L176:
	999	+ ldrb r3, [r8] @ zero_extendqisi2
	1000	+ cmp r4, r3
	1001	+ bcc .L177
	1002	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	1003	+.L177:
	1004	+ str r9, [r6, #8]
	1005	+ mov r0, #300
	1006	+ str r10, [r6]
	1007	+ ldrsb r3, [r7, r4]
	1008	+ add r4, r4, #1
	1009	+ str r3, [r6]
	1010	+ ldrsb r3, [r5, #1]!
	1011	+ str r3, [r6]
	1012	+ bl ndelay
	1013	+ b .L176
	1014	+.L180:
	1015	+ .align 2
	1016	+.L179:
	1017	+ .word .LANCHOR1+404
	1018	+ .word g_maxRegNum
	1019	+ .fnend
	1020	+ .size SamsungSetRRPara, .-SamsungSetRRPara
	1021	+ .align 2
751	1022	.global FlashDieInfoInit
	1023	+ .syntax unified
	1024	+ .arm
	1025	+ .fpu softvfp
752	1026	.type FlashDieInfoInit, %function
753	1027	FlashDieInfoInit:
754	1028	.fnstart
755	1029	@ args = 0, pretend = 0, frame = 0
756	1030	@ frame_needed = 0, uses_anonymous_args = 0
757		- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
758		- .save {r3, r4, r5, r6, r7, r8, r9, lr}
759		- mov r5, #0
760		- ldr r3, .L149
761		- ldr r4, .L149+4
762		- ldr r9, .L149+8
	1031	+ ldr r3, .L196
	1032	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
	1033	+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
	1034	+ mov r6, #0
	1035	+ ldr r4, .L196+4
763	1036	ldrh r0, [r3, #10]
764		- strb r5, [r4, #3152]
765		- strb r5, [r4, #3153]
	1037	+ strb r6, [r4, #3156]
	1038	+ strb r6, [r4, #3157]
766	1039	bl FlashBlockAlignInit
767		- mov r1, r5
768	1040	mov r2, #8
769		- ldr r0, .L149+12
	1041	+ mov r1, r6
	1042	+ ldr r0, .L196+8
770	1043	bl ftl_memset
771		- mov r1, r5
772	1044	mov r2, #32
773		- ldr r0, .L149+16
	1045	+ mov r1, r6
	1046	+ add r0, r4, #3168
	1047	+ ldr r9, .L196+12
774	1048	bl ftl_memset
775		- ldr r0, .L149+20
776		- mov r1, r5
777	1049	mov r2, #128
	1050	+ mov r1, r6
	1051	+ add r0, r4, #3200
	1052	+ mov r8, r9
778	1053	bl ftl_memset
779		- ldr r7, [r4, #44]
780		- add r6, r7, #1
781		-.L136:
782		- mov r0, r6
783		- add r1, r9, r5, asl #3
784		- ldrb r2, [r7] @ zero_extendqisi2
	1054	+ ldr r5, [r4, #48]
	1055	+ add r7, r5, #1
	1056	+.L183:
	1057	+ ldrb r2, [r5] @ zero_extendqisi2
	1058	+ add r1, r9, r6, lsl #3
	1059	+ mov r0, r7
785	1060	bl FlashMemCmp8
786		- ldr r8, .L149+8
787	1061	cmp r0, #0
788		- bne .L135
789		- ldrb r3, [r4, #3152] @ zero_extendqisi2
790		- add r2, r4, r3, asl #2
791		- str r0, [r2, #3164]
	1062	+ bne .L182
	1063	+ ldrb r3, [r4, #3156] @ zero_extendqisi2
	1064	+ add r2, r4, r3, lsl #2
	1065	+ str r0, [r2, #3168]
792	1066	add r2, r3, #1
793	1067	add r3, r4, r3
794		- strb r2, [r4, #3152]
795		- strb r5, [r3, #3156]
796		-.L135:
797		- add r5, r5, #1
798		- cmp r5, #4
799		- bne .L136
800		- ldrb r3, [r4, #3152] @ zero_extendqisi2
801		- strb r3, [r4, #3153]
802		- ldrb r3, [r7, #8] @ zero_extendqisi2
	1068	+ strb r2, [r4, #3156]
	1069	+ strb r6, [r3, #3160]
	1070	+.L182:
	1071	+ add r6, r6, #1
	1072	+ cmp r6, #4
	1073	+ bne .L183
	1074	+ ldrb r3, [r4, #3156] @ zero_extendqisi2
	1075	+ strb r3, [r4, #3157]
	1076	+ ldrb r3, [r5, #8] @ zero_extendqisi2
803	1077	cmp r3, #2
804		- beq .L137
805		-.L141:
806		- ldrb r3, [r7, #13] @ zero_extendqisi2
807		- ldrb r2, [r4, #3152] @ zero_extendqisi2
808		- smulbb r2, r2, r3
809		- ldrh r3, [r7, #14]
810		- smulbb r3, r2, r3
811		- movw r2, #3324
812		- strh r3, [r4, r2] @ movhi
813		- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
814		-.L137:
815		- ldr r3, .L149+4
816		- mov r5, #0
817		- ldr r9, [r3, #4]
818		-.L140:
819		- mov r0, r6
820		- add r1, r8, r5, asl #3
821		- ldrb r2, [r7] @ zero_extendqisi2
	1078	+ beq .L184
	1079	+.L188:
	1080	+ ldrh r2, [r5, #14]
	1081	+ ldrb r3, [r4, #3156] @ zero_extendqisi2
	1082	+ smulbb r3, r3, r2
	1083	+ ldrb r2, [r5, #13] @ zero_extendqisi2
	1084	+ smulbb r3, r3, r2
	1085	+ ldr r2, .L196+16
	1086	+ strh r3, [r2] @ movhi
	1087	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	1088	+.L184:
	1089	+ ldr r9, [r4, #40]
	1090	+ mov r6, #0
	1091	+.L187:
	1092	+ ldrb r2, [r5] @ zero_extendqisi2
	1093	+ add r1, r8, r6, lsl #3
	1094	+ mov r0, r7
822	1095	bl FlashMemCmp8
823	1096	cmp r0, #0
824		- bne .L138
825		- ldrb r1, [r7, #13] @ zero_extendqisi2
826		- ldrh r3, [r7, #14]
827		- ldrb r2, [r4, #3152] @ zero_extendqisi2
828		- mul r1, r9, r1
829		- and r3, r3, #65280
830		- add r0, r4, r2, asl #2
	1097	+ bne .L185
	1098	+ ldrh r3, [r5, #14]
	1099	+ ldrb r2, [r4, #3156] @ zero_extendqisi2
	1100	+ and r1, r3, #65280
	1101	+ ldrb r3, [r5, #13] @ zero_extendqisi2
	1102	+ mul r3, r9, r3
831	1103	mul r3, r3, r1
832		- str r3, [r0, #3164]
833		- ldrb r1, [r7, #23] @ zero_extendqisi2
834		- cmp r1, #0
835		- movne r3, r3, asl #1
836		- strne r3, [r0, #3164]
	1104	+ add r1, r4, r2, lsl #2
	1105	+ str r3, [r1, #3168]
	1106	+ ldrb r0, [r5, #23] @ zero_extendqisi2
	1107	+ cmp r0, #0
	1108	+ lslne r3, r3, #1
	1109	+ strne r3, [r1, #3168]
837	1110	add r3, r2, #1
838	1111	add r2, r4, r2
839		- strb r3, [r4, #3152]
840		- strb r5, [r2, #3156]
841		-.L138:
842		- add r5, r5, #1
843		- cmp r5, #4
844		- bne .L140
845		- b .L141
846		-.L150:
	1112	+ strb r3, [r4, #3156]
	1113	+ strb r6, [r2, #3160]
	1114	+.L185:
	1115	+ add r6, r6, #1
	1116	+ cmp r6, #4
	1117	+ bne .L187
	1118	+ b .L188
	1119	+.L197:
847	1120	.align 2
848		-.L149:
849		- .word .LANCHOR1+256
	1121	+.L196:
	1122	+ .word .LANCHOR1+468
850	1123	.word .LANCHOR0
	1124	+ .word .LANCHOR0+3160
851	1125	.word IDByte
852		- .word .LANCHOR0+3156
853		- .word .LANCHOR0+3164
854		- .word .LANCHOR0+3196
	1126	+ .word .LANCHOR0+3328
855	1127	.fnend
856	1128	.size FlashDieInfoInit, .-FlashDieInfoInit
857	1129	.align 2
858	1130	.global FlashReadIdbData
	1131	+ .syntax unified
	1132	+ .arm
	1133	+ .fpu softvfp
859	1134	.type FlashReadIdbData, %function
860	1135	FlashReadIdbData:
861	1136	.fnstart
862	1137	@ args = 0, pretend = 0, frame = 0
863	1138	@ frame_needed = 0, uses_anonymous_args = 0
864		- stmfd sp!, {r3, lr}
865		- .save {r3, lr}
	1139	+ push {r4, lr}
	1140	+ .save {r4, lr}
866	1141	mov r2, #2048
867		- ldr r1, .L153
	1142	+ ldr r1, .L200
868	1143	bl ftl_memcpy
869	1144	mov r0, #0
870		- ldmfd sp!, {r3, pc}
871		-.L154:
	1145	+ pop {r4, pc}
	1146	+.L201:
872	1147	.align 2
873		-.L153:
874		- .word .LANCHOR0+3328
	1148	+.L200:
	1149	+ .word .LANCHOR0+3332
875	1150	.fnend
876	1151	.size FlashReadIdbData, .-FlashReadIdbData
877	1152	.align 2
878	1153	.global FlashLoadPhyInfoInRam
	1154	+ .syntax unified
	1155	+ .arm
	1156	+ .fpu softvfp
879	1157	.type FlashLoadPhyInfoInRam, %function
880	1158	FlashLoadPhyInfoInRam:
881	1159	.fnstart
882	1160	@ args = 0, pretend = 0, frame = 0
883	1161	@ frame_needed = 0, uses_anonymous_args = 0
884		- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
885		- .save {r3, r4, r5, r6, r7, r8, r9, lr}
886		- mov r6, #0
887		- ldr r8, .L168
888		-.L159:
889		- mov r4, r6, asl #5
890		- ldr r1, .L168+4
891		- add r0, r4, #1
892		- ldrb r2, [r8, r6, asl #5] @ zero_extendqisi2
893		- add r0, r8, r0
894		- ldr r5, .L168+8
895		- bl FlashMemCmp8
896		- add r9, r5, #288
897		- subs r7, r0, #0
898		- bne .L156
899		- adds r9, r9, r4
900		- beq .L162
901		- add r4, r5, r4
902		- add r5, r5, #3040
903		- ldrb r3, [r4, #310] @ zero_extendqisi2
904		- mov r4, r7
905		- b .L161
906		-.L156:
907		- add r6, r6, #1
908		- cmp r6, #86
909		- bne .L159
910		- b .L162
911		-.L167:
912		- add r4, r4, #1
913		- cmp r4, #4
914		- beq .L160
915		-.L161:
916		- ldrb r2, [r5, r4, asl #5] @ zero_extendqisi2
917		- cmp r2, r3
918		- bne .L167
919		-.L160:
920		- ldr r6, .L168+12
921		- mov r2, #32
922		- ldr r1, .L168+16
923		- ldr r0, .L168+20
924		- add r1, r1, r4, asl #5
925		- bl ftl_memcpy
926		- mov r0, r6
	1162	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
	1163	+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
	1164	+ mov r4, #0
	1165	+ ldr r5, .L211
	1166	+ ldr r9, .L211+4
	1167	+ add r6, r5, #500
	1168	+.L205:
	1169	+ lsl r8, r4, #5
	1170	+ ldrb r2, [r6, r4, lsl #5] @ zero_extendqisi2
927	1171	mov r1, r9
	1172	+ add r0, r8, #1
	1173	+ add r0, r6, r0
	1174	+ bl FlashMemCmp8
	1175	+ subs r7, r0, #0
	1176	+ bne .L203
	1177	+ add r5, r5, r8
	1178	+ ldr r2, .L211+8
	1179	+ ldrb r0, [r5, #522] @ zero_extendqisi2
	1180	+ add r6, r6, r8
	1181	+ mov r3, r7
	1182	+ mov r1, r2
	1183	+.L204:
	1184	+ ldrb ip, [r2, r3, lsl #5] @ zero_extendqisi2
	1185	+ cmp ip, r0
	1186	+ beq .L207
	1187	+ add r3, r3, #1
	1188	+ cmp r3, #4
	1189	+ bne .L204
	1190	+.L207:
	1191	+ ldr r4, .L211+12
	1192	+ add r1, r1, r3, lsl #5
928	1193	mov r2, #32
	1194	+ ldr r0, .L211+16
929	1195	bl ftl_memcpy
930		- ldrh r0, [r6, #10]
	1196	+ mov r2, #32
	1197	+ mov r1, r6
	1198	+ mov r0, r4
	1199	+ bl ftl_memcpy
	1200	+ ldrh r0, [r4, #10]
931	1201	bl FlashBlockAlignInit
932		- b .L157
933		-.L162:
	1202	+ b .L202
	1203	+.L203:
	1204	+ add r4, r4, #1
	1205	+ cmp r4, #86
	1206	+ bne .L205
934	1207	mvn r7, #0
935		-.L157:
	1208	+.L202:
936	1209	mov r0, r7
937		- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
938		-.L169:
	1210	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	1211	+.L212:
939	1212	.align 2
940		-.L168:
941		- .word .LANCHOR1+288
942		- .word IDByte
	1213	+.L211:
943	1214	.word .LANCHOR1
944		- .word .LANCHOR1+256
945		- .word .LANCHOR1+3040
946		- .word .LANCHOR0+48
	1215	+ .word IDByte
	1216	+ .word .LANCHOR1+3252
	1217	+ .word .LANCHOR1+468
	1218	+ .word .LANCHOR0+52
947	1219	.fnend
948	1220	.size FlashLoadPhyInfoInRam, .-FlashLoadPhyInfoInRam
949	1221	.align 2
950	1222	.global ftl_flash_suspend
	1223	+ .syntax unified
	1224	+ .arm
	1225	+ .fpu softvfp
951	1226	.type ftl_flash_suspend, %function
952	1227	ftl_flash_suspend:
953	1228	.fnstart
954	1229	@ args = 0, pretend = 0, frame = 0
955	1230	@ frame_needed = 0, uses_anonymous_args = 0
956	1231	@ link register save eliminated.
957		- ldr r3, .L171
958		- ldr r2, [r3, #-2808]
	1232	+ ldr r3, .L214
	1233	+ ldr r2, [r3, #-2804]
959	1234	ldr r1, [r2]
960		- str r1, [r3, #-2804]
961		- ldr r1, [r2, #4]
962	1235	str r1, [r3, #-2800]
963		- ldr r1, [r2, #8]
	1236	+ ldr r1, [r2, #4]
964	1237	str r1, [r3, #-2796]
965		- ldr r1, [r2, #12]
	1238	+ ldr r1, [r2, #8]
966	1239	str r1, [r3, #-2792]
967		- ldr r1, [r2, #304]
	1240	+ ldr r1, [r2, #12]
968	1241	str r1, [r3, #-2788]
969		- ldr r1, [r2, #308]
	1242	+ ldr r1, [r2, #304]
970	1243	str r1, [r3, #-2784]
	1244	+ ldr r1, [r2, #308]
	1245	+ str r1, [r3, #-2780]
971	1246	ldr r1, [r2, #336]
972	1247	ldr r2, [r2, #344]
973		- str r1, [r3, #-2780]
974		- str r2, [r3, #-2776]
	1248	+ str r1, [r3, #-2776]
	1249	+ str r2, [r3, #-2772]
975	1250	bx lr
976		-.L172:
	1251	+.L215:
977	1252	.align 2
978		-.L171:
	1253	+.L214:
979	1254	.word .LANCHOR2
980	1255	.fnend
981	1256	.size ftl_flash_suspend, .-ftl_flash_suspend
982	1257	.global __aeabi_uidiv
	1258	+ .global __aeabi_uidivmod
983	1259	.align 2
984	1260	.global LogAddr2PhyAddr
	1261	+ .syntax unified
	1262	+ .arm
	1263	+ .fpu softvfp
985	1264	.type LogAddr2PhyAddr, %function
986	1265	LogAddr2PhyAddr:
987	1266	.fnstart
988	1267	@ args = 4, pretend = 0, frame = 8
989	1268	@ frame_needed = 0, uses_anonymous_args = 0
990		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	1269	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
991	1270	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
992	1271	.pad #12
993		- mov r9, r3
994		- ldr r3, .L179
995		- mov fp, r1
996		- ldr r7, .L179+4
997		- mov r5, r0
998		- mov r8, r2
999		- ldrh r4, [r3, #12]
1000		- ldrh r3, [r3, #14]
1001		- ldrh r10, [r7, #4]
1002		- smulbb r4, r4, r3
1003		- ldrb r3, [r7] @ zero_extendqisi2
1004		- cmp r3, #1
1005		- ldr r3, [r0, #4]
1006		- moveq r10, r10, asl #1
1007		- bic r3, r3, #-2147483648
	1272	+ mov r9, r2
	1273	+ ldr r2, .L222
	1274	+ mov fp, r3
	1275	+ mov r10, r1
	1276	+ mov r7, r0
	1277	+ ldr r5, .L222+4
	1278	+ ldrh r3, [r2, #14]
	1279	+ ldrh r2, [r2, #12]
	1280	+ ldrh r6, [r5, #40]
	1281	+ ldr r4, [r0, #4]
	1282	+ smulbb r3, r3, r2
	1283	+ ldrb r2, [r5, #36] @ zero_extendqisi2
	1284	+ uxth r3, r3
	1285	+ cmp r2, #1
	1286	+ lsleq r6, r6, #1
	1287	+ ubfx r2, r4, #10, #16
	1288	+ mov r1, r3
1008	1289	str r3, [sp, #4]
1009		- ubfx r6, r3, #10, #16
1010		- uxth r4, r4
1011		- uxtheq r10, r10
1012		- mov r1, r4
1013		- mov r0, r6
	1290	+ mov r0, r2
	1291	+ uxtheq r6, r6
	1292	+ str r2, [sp]
1014	1293	bl __aeabi_uidiv
1015		- cmp fp, #1
1016		- uxth r0, r0
1017	1294	ldr r3, [sp, #4]
1018		- smulbb r4, r0, r4
1019		- ubfx r1, r3, #0, #10
1020		- rsb r6, r4, r6
1021		- uxth r6, r6
1022		- bne .L175
1023		- ldr r3, .L179+8
1024		- ldrb r3, [r3, #-2744] @ zero_extendqisi2
	1295	+ uxth r8, r0
	1296	+ ldr r2, [sp]
	1297	+ mov r1, r3
	1298	+ mov r0, r2
	1299	+ bl __aeabi_uidivmod
	1300	+ cmp r10, #1
	1301	+ uxth r1, r1
	1302	+ ubfx r0, r4, #0, #10
	1303	+ bne .L218
	1304	+ ldr r3, .L222+8
	1305	+ ldrb r3, [r3, #-2740] @ zero_extendqisi2
1025	1306	cmp r3, #0
1026		- addeq r1, r7, r1, asl #1
1027		- ldreqh r1, [r1, #80]
1028		-.L175:
1029		- add lr, r7, r0, asl #2
	1307	+ addeq r0, r5, r0, lsl #1
	1308	+ ldrheq r0, [r0, #84]
	1309	+.L218:
	1310	+ add r5, r5, r8, lsl #2
	1311	+ ldr r3, [r5, #3168]
	1312	+ mla r6, r6, r1, r3
1030	1313	ldrb r3, [sp, #48] @ zero_extendqisi2
1031		- ldr ip, [lr, #3164]
1032	1314	cmp r3, #1
1033		- mla ip, r10, r6, ip
1034		- add r1, ip, r1
1035		- str r1, [r8]
	1315	+ add r0, r6, r0
1036	1316	str r0, [r9]
1037	1317	movls r0, #0
1038		- ldrhi r0, [r5, #4]
1039		- ldrhi r3, [r5, #40]
	1318	+ str r8, [fp]
	1319	+ ldrhi r0, [r7, #4]
	1320	+ ldrhi r3, [r7, #40]
1040	1321	addhi r0, r0, #1024
1041		- rsbhi r0, r3, r0
	1322	+ subhi r0, r0, r3
1042	1323	clzhi r0, r0
1043		- movhi r0, r0, lsr #5
	1324	+ lsrhi r0, r0, #5
1044	1325	add sp, sp, #12
1045	1326	@ sp needed
1046		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
1047		-.L180:
	1327	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	1328	+.L223:
1048	1329	.align 2
1049		-.L179:
1050		- .word .LANCHOR2-2772
	1330	+.L222:
	1331	+ .word .LANCHOR2-2768
1051	1332	.word .LANCHOR0
1052	1333	.word .LANCHOR2
1053	1334	.fnend
1054	1335	.size LogAddr2PhyAddr, .-LogAddr2PhyAddr
1055	1336	.align 2
	1337	+ .global FlashReadStatusEN
	1338	+ .syntax unified
	1339	+ .arm
	1340	+ .fpu softvfp
	1341	+ .type FlashReadStatusEN, %function
	1342	+FlashReadStatusEN:
	1343	+ .fnstart
	1344	+ @ args = 0, pretend = 0, frame = 0
	1345	+ @ frame_needed = 0, uses_anonymous_args = 0
	1346	+ ldr r3, .L237
	1347	+ push {r4, r5, r6, lr}
	1348	+ .save {r4, r5, r6, lr}
	1349	+ ldr r4, [r3, r0, lsl #3]
	1350	+ add r0, r3, r0, lsl #3
	1351	+ ldrb r5, [r0, #4] @ zero_extendqisi2
	1352	+ ldr r0, [r3, #48]
	1353	+ ldrb r0, [r0, #8] @ zero_extendqisi2
	1354	+ cmp r0, #2
	1355	+ mov r0, r3
	1356	+ lsl r3, r5, #8
	1357	+ movne r2, #112
	1358	+ add r5, r5, #8
	1359	+ addne r3, r4, r3
	1360	+ strne r2, [r3, #2056]
	1361	+ bne .L230
	1362	+ cmp r2, #0
	1363	+ add r3, r4, r3
	1364	+ ldrbne r2, [r0, #66] @ zero_extendqisi2
	1365	+ ldrbeq r2, [r0, #65] @ zero_extendqisi2
	1366	+ str r2, [r3, #2056]
	1367	+ ldrb r0, [r0, #67] @ zero_extendqisi2
	1368	+ cmp r0, #0
	1369	+ movne r2, #0
	1370	+ addne ip, r4, r5, lsl #8
	1371	+ bne .L229
	1372	+.L230:
	1373	+ mov r0, #80
	1374	+ bl ndelay
	1375	+ ldr r0, [r4, r5, lsl #8]
	1376	+ uxtb r0, r0
	1377	+ pop {r4, r5, r6, pc}
	1378	+.L231:
	1379	+ lsl r3, r2, #3
	1380	+ add r2, r2, #1
	1381	+ lsr r3, r1, r3
	1382	+ uxtb r3, r3
	1383	+ str r3, [ip, #4]
	1384	+.L229:
	1385	+ cmp r2, r0
	1386	+ bcc .L231
	1387	+ b .L230
	1388	+.L238:
	1389	+ .align 2
	1390	+.L237:
	1391	+ .word .LANCHOR0
	1392	+ .fnend
	1393	+ .size FlashReadStatusEN, .-FlashReadStatusEN
	1394	+ .align 2
	1395	+ .global FlashWaitReadyEN
	1396	+ .syntax unified
	1397	+ .arm
	1398	+ .fpu softvfp
	1399	+ .type FlashWaitReadyEN, %function
	1400	+FlashWaitReadyEN:
	1401	+ .fnstart
	1402	+ @ args = 0, pretend = 0, frame = 0
	1403	+ @ frame_needed = 0, uses_anonymous_args = 0
	1404	+ push {r4, r5, r6, lr}
	1405	+ .save {r4, r5, r6, lr}
	1406	+ mov r4, r0
	1407	+ mov r5, r1
	1408	+ mov r6, r2
	1409	+.L240:
	1410	+ mov r2, r6
	1411	+ mov r1, r5
	1412	+ mov r0, r4
	1413	+ bl FlashReadStatusEN
	1414	+ cmp r0, #255
	1415	+ beq .L240
	1416	+ tst r0, #64
	1417	+ popne {r4, r5, r6, pc}
	1418	+ mov r1, #3
	1419	+ mov r0, #1
	1420	+ bl usleep_range
	1421	+ b .L240
	1422	+ .fnend
	1423	+ .size FlashWaitReadyEN, .-FlashWaitReadyEN
	1424	+ .align 2
1056	1425	.global ftl_read_flash_info
	1426	+ .syntax unified
	1427	+ .arm
	1428	+ .fpu softvfp
1057	1429	.type ftl_read_flash_info, %function
1058	1430	ftl_read_flash_info:
1059	1431	.fnstart
1060	1432	@ args = 0, pretend = 0, frame = 0
1061	1433	@ frame_needed = 0, uses_anonymous_args = 0
1062		- stmfd sp!, {r4, lr}
	1434	+ push {r4, lr}
1063	1435	.save {r4, lr}
1064		- mov r1, #0
1065	1436	mov r2, #11
	1437	+ mov r1, #0
1066	1438	mov r4, r0
1067	1439	bl ftl_memset
1068		- ldr r2, .L186
1069		- ldr r0, .L186+4
	1440	+ ldr r2, .L250
1070	1441	mov ip, #1
1071		- ldr r3, [r2, #44]
1072		- ldrb r1, [r3, #9] @ zero_extendqisi2
1073		- ldr r3, [r2, #4]
1074		- smulbb r3, r1, r3
	1442	+ ldr r0, .L250+4
	1443	+ ldr r3, [r2, #48]
	1444	+ ldr r1, [r2, #40]
	1445	+ ldrb r3, [r3, #9] @ zero_extendqisi2
	1446	+ smulbb r3, r3, r1
1075	1447	strh r3, [r4, #4] @ unaligned
1076		- ldr r3, .L186+8
1077		- ldrb r1, [r3, #-2743] @ zero_extendqisi2
1078		- ldr r3, [r3, #-2740]
	1448	+ ldr r3, .L250+8
	1449	+ ldrb r1, [r3, #-2739] @ zero_extendqisi2
	1450	+ ldr r3, [r3, #-2736]
1079	1451	strb r1, [r4, #7]
1080	1452	str r3, [r4] @ unaligned
1081		- ldr r3, [r2, #44]
	1453	+ ldr r3, [r2, #48]
1082	1454	ldrb r1, [r3, #9] @ zero_extendqisi2
1083	1455	strb r1, [r4, #6]
1084	1456	mov r1, #32
1085	1457	strb r1, [r4, #8]
1086		- ldrb r1, [r2, #3152] @ zero_extendqisi2
	1458	+ ldrb r1, [r2, #3156] @ zero_extendqisi2
1087	1459	ldrb r3, [r3, #7] @ zero_extendqisi2
1088	1460	strb r3, [r4, #9]
1089	1461	mov r3, #0
1090	1462	strb r3, [r4, #10]
1091		-.L182:
	1463	+.L247:
1092	1464	uxtb r2, r3
1093		- cmp r2, r1
1094		- bcs .L185
	1465	+ cmp r1, r2
	1466	+ bhi .L248
	1467	+ pop {r4, pc}
	1468	+.L248:
1095	1469	ldrb lr, [r3, r0] @ zero_extendqisi2
1096	1470	add r3, r3, #1
1097	1471	ldrb r2, [r4, #10] @ zero_extendqisi2
1098		- orr r2, r2, ip, asl lr
	1472	+ orr r2, r2, ip, lsl lr
1099	1473	strb r2, [r4, #10]
1100		- b .L182
1101		-.L185:
1102		- ldmfd sp!, {r4, pc}
1103		-.L187:
	1474	+ b .L247
	1475	+.L251:
1104	1476	.align 2
1105		-.L186:
	1477	+.L250:
1106	1478	.word .LANCHOR0
1107		- .word .LANCHOR0+3156
	1479	+ .word .LANCHOR0+3160
1108	1480	.word .LANCHOR2
1109	1481	.fnend
1110	1482	.size ftl_read_flash_info, .-ftl_read_flash_info
1111	1483	.align 2
1112	1484	.global FlashScheduleEnSet
	1485	+ .syntax unified
	1486	+ .arm
	1487	+ .fpu softvfp
1113	1488	.type FlashScheduleEnSet, %function
1114	1489	FlashScheduleEnSet:
1115	1490	.fnstart
1116	1491	@ args = 0, pretend = 0, frame = 0
1117	1492	@ frame_needed = 0, uses_anonymous_args = 0
1118	1493	@ link register save eliminated.
1119		- ldr r3, .L189
1120		- ldr r2, [r3, #-2736]
1121		- str r0, [r3, #-2736]
	1494	+ ldr r3, .L253
	1495	+ ldr r2, [r3, #-2732]
	1496	+ str r0, [r3, #-2732]
1122	1497	mov r0, r2
1123	1498	bx lr
1124		-.L190:
	1499	+.L254:
1125	1500	.align 2
1126		-.L189:
	1501	+.L253:
1127	1502	.word .LANCHOR2
1128	1503	.fnend
1129	1504	.size FlashScheduleEnSet, .-FlashScheduleEnSet
1130	1505	.align 2
1131	1506	.global FlashGetPageSize
	1507	+ .syntax unified
	1508	+ .arm
	1509	+ .fpu softvfp
1132	1510	.type FlashGetPageSize, %function
1133	1511	FlashGetPageSize:
1134	1512	.fnstart
1135	1513	@ args = 0, pretend = 0, frame = 0
1136	1514	@ frame_needed = 0, uses_anonymous_args = 0
1137	1515	@ link register save eliminated.
1138		- ldr r3, .L192
1139		- ldr r3, [r3, #44]
	1516	+ ldr r3, .L256
	1517	+ ldr r3, [r3, #48]
1140	1518	ldrb r0, [r3, #9] @ zero_extendqisi2
1141	1519	bx lr
1142		-.L193:
	1520	+.L257:
1143	1521	.align 2
1144		-.L192:
	1522	+.L256:
1145	1523	.word .LANCHOR0
1146	1524	.fnend
1147	1525	.size FlashGetPageSize, .-FlashGetPageSize
1148	1526	.align 2
1149	1527	.global NandcReadDontCaseBusyEn
	1528	+ .syntax unified
	1529	+ .arm
	1530	+ .fpu softvfp
1150	1531	.type NandcReadDontCaseBusyEn, %function
1151	1532	NandcReadDontCaseBusyEn:
1152	1533	.fnstart
..	..	@@ -1158,107 +1539,122 @@
1158	1539	.size NandcReadDontCaseBusyEn, .-NandcReadDontCaseBusyEn
1159	1540	.align 2
1160	1541	.global NandcGetChipIf
	1542	+ .syntax unified
	1543	+ .arm
	1544	+ .fpu softvfp
1161	1545	.type NandcGetChipIf, %function
1162	1546	NandcGetChipIf:
1163	1547	.fnstart
1164	1548	@ args = 0, pretend = 0, frame = 0
1165	1549	@ frame_needed = 0, uses_anonymous_args = 0
1166	1550	@ link register save eliminated.
1167		- ldr r3, .L196
1168		- add r0, r3, r0, asl #3
1169		- ldrb r2, [r0, #16] @ zero_extendqisi2
1170		- ldr r0, [r0, #12]
1171		- add r2, r2, #8
1172		- add r0, r0, r2, asl #8
	1551	+ ldr r2, .L260
	1552	+ add r3, r2, r0, lsl #3
	1553	+ ldr r0, [r2, r0, lsl #3]
	1554	+ ldrb r3, [r3, #4] @ zero_extendqisi2
	1555	+ add r3, r3, #8
	1556	+ add r0, r0, r3, lsl #8
1173	1557	bx lr
1174		-.L197:
	1558	+.L261:
1175	1559	.align 2
1176		-.L196:
	1560	+.L260:
1177	1561	.word .LANCHOR0
1178	1562	.fnend
1179	1563	.size NandcGetChipIf, .-NandcGetChipIf
1180	1564	.align 2
1181	1565	.global NandcSetDdrPara
	1566	+ .syntax unified
	1567	+ .arm
	1568	+ .fpu softvfp
1182	1569	.type NandcSetDdrPara, %function
1183	1570	NandcSetDdrPara:
1184	1571	.fnstart
1185	1572	@ args = 0, pretend = 0, frame = 0
1186	1573	@ frame_needed = 0, uses_anonymous_args = 0
1187	1574	@ link register save eliminated.
1188		- ldr r3, .L199
1189		- ldr r2, [r3, #-2808]
1190		- mov r3, r0, asl #8
1191		- orr r0, r3, r0, asl #16
1192		- orr r3, r0, #1
1193		- str r3, [r2, #304]
	1575	+ ldr r3, .L263
	1576	+ ldr r2, [r3, #-2804]
	1577	+ lsl r3, r0, #8
	1578	+ orr r0, r3, r0, lsl #16
	1579	+ orr r0, r0, #1
	1580	+ str r0, [r2, #304]
1194	1581	bx lr
1195		-.L200:
	1582	+.L264:
1196	1583	.align 2
1197		-.L199:
	1584	+.L263:
1198	1585	.word .LANCHOR2
1199	1586	.fnend
1200	1587	.size NandcSetDdrPara, .-NandcSetDdrPara
1201	1588	.align 2
1202	1589	.global NandcSetDdrDiv
	1590	+ .syntax unified
	1591	+ .arm
	1592	+ .fpu softvfp
1203	1593	.type NandcSetDdrDiv, %function
1204	1594	NandcSetDdrDiv:
1205	1595	.fnstart
1206	1596	@ args = 0, pretend = 0, frame = 0
1207	1597	@ frame_needed = 0, uses_anonymous_args = 0
1208	1598	@ link register save eliminated.
1209		- ldr r3, .L202
	1599	+ ldr r3, .L266
1210	1600	orr r0, r0, #16640
1211		- ldr r3, [r3, #-2808]
	1601	+ ldr r3, [r3, #-2804]
1212	1602	str r0, [r3, #344]
1213	1603	bx lr
1214		-.L203:
	1604	+.L267:
1215	1605	.align 2
1216		-.L202:
	1606	+.L266:
1217	1607	.word .LANCHOR2
1218	1608	.fnend
1219	1609	.size NandcSetDdrDiv, .-NandcSetDdrDiv
1220	1610	.align 2
1221	1611	.global NandcSetDdrMode
	1612	+ .syntax unified
	1613	+ .arm
	1614	+ .fpu softvfp
1222	1615	.type NandcSetDdrMode, %function
1223	1616	NandcSetDdrMode:
1224	1617	.fnstart
1225	1618	@ args = 0, pretend = 0, frame = 0
1226	1619	@ frame_needed = 0, uses_anonymous_args = 0
1227	1620	@ link register save eliminated.
1228		- ldr r3, .L207
	1621	+ ldr r3, .L271
1229	1622	cmp r0, #0
1230		- ldr r2, [r3, #-2808]
	1623	+ ldr r2, [r3, #-2804]
1231	1624	ldr r3, [r2]
1232	1625	bfieq r3, r0, #13, #1
1233	1626	orrne r3, r3, #253952
1234	1627	str r3, [r2]
1235	1628	bx lr
1236		-.L208:
	1629	+.L272:
1237	1630	.align 2
1238		-.L207:
	1631	+.L271:
1239	1632	.word .LANCHOR2
1240	1633	.fnend
1241	1634	.size NandcSetDdrMode, .-NandcSetDdrMode
1242	1635	.align 2
1243	1636	.global NandcSetMode
	1637	+ .syntax unified
	1638	+ .arm
	1639	+ .fpu softvfp
1244	1640	.type NandcSetMode, %function
1245	1641	NandcSetMode:
1246	1642	.fnstart
1247	1643	@ args = 0, pretend = 0, frame = 0
1248	1644	@ frame_needed = 0, uses_anonymous_args = 0
1249	1645	@ link register save eliminated.
1250		- ldr r3, .L216
	1646	+ ldr r3, .L280
1251	1647	ands r1, r0, #6
1252		- ldr r2, [r3, #-2808]
	1648	+ ldr r2, [r3, #-2804]
1253	1649	ldr r3, [r2]
1254	1650	bfieq r3, r1, #13, #1
1255		- beq .L212
1256		- orr r3, r3, #24576
	1651	+ beq .L276
1257	1652	movw r1, #8322
1258		- bfc r3, #15, #1
	1653	+ orr r3, r3, #24576
1259	1654	str r1, [r2, #344]
	1655	+ bfc r3, #15, #1
	1656	+ ldr r1, .L280+4
1260	1657	orr r3, r3, #196608
1261		- ldr r1, .L216+4
1262	1658	tst r0, #4
1263	1659	orrne r3, r3, #32768
1264	1660	str r1, [r2, #304]
..	..	@@ -1266,650 +1662,425 @@
1266	1662	str r1, [r2, #308]
1267	1663	mov r1, #39
1268	1664	str r1, [r2, #308]
1269		-.L212:
	1665	+.L276:
1270	1666	str r3, [r2]
1271	1667	mov r0, #0
1272	1668	bx lr
1273		-.L217:
	1669	+.L281:
1274	1670	.align 2
1275		-.L216:
	1671	+.L280:
1276	1672	.word .LANCHOR2
1277	1673	.word 1052675
1278	1674	.fnend
1279	1675	.size NandcSetMode, .-NandcSetMode
1280	1676	.align 2
1281	1677	.global NandcFlashCs
	1678	+ .syntax unified
	1679	+ .arm
	1680	+ .fpu softvfp
1282	1681	.type NandcFlashCs, %function
1283	1682	NandcFlashCs:
1284	1683	.fnstart
1285	1684	@ args = 0, pretend = 0, frame = 0
1286	1685	@ frame_needed = 0, uses_anonymous_args = 0
1287	1686	@ link register save eliminated.
1288		- ldr r2, .L219
1289		- add r0, r2, r0, asl #3
	1687	+ ldr r3, .L283
1290	1688	mov r2, #1
1291		- ldr r1, [r0, #12]
1292		- ldrb r0, [r0, #16] @ zero_extendqisi2
	1689	+ ldr r1, [r3, r0, lsl #3]
	1690	+ add r0, r3, r0, lsl #3
	1691	+ ldrb r0, [r0, #4] @ zero_extendqisi2
1293	1692	ldr r3, [r1]
1294		- mov r2, r2, asl r0
	1693	+ lsl r2, r2, r0
1295	1694	bfi r3, r2, #0, #8
1296	1695	str r3, [r1]
1297	1696	bx lr
1298		-.L220:
	1697	+.L284:
1299	1698	.align 2
1300		-.L219:
	1699	+.L283:
1301	1700	.word .LANCHOR0
1302	1701	.fnend
1303	1702	.size NandcFlashCs, .-NandcFlashCs
1304	1703	.align 2
1305	1704	.global NandcFlashDeCs
	1705	+ .syntax unified
	1706	+ .arm
	1707	+ .fpu softvfp
1306	1708	.type NandcFlashDeCs, %function
1307	1709	NandcFlashDeCs:
1308	1710	.fnstart
1309	1711	@ args = 0, pretend = 0, frame = 0
1310	1712	@ frame_needed = 0, uses_anonymous_args = 0
1311	1713	@ link register save eliminated.
1312		- ldr r3, .L222
1313		- add r0, r3, r0, asl #3
1314		- ldr r2, [r0, #12]
	1714	+ ldr r3, .L286
	1715	+ ldr r2, [r3, r0, lsl #3]
1315	1716	ldr r3, [r2]
1316	1717	bfc r3, #0, #8
1317	1718	bfc r3, #17, #1
1318	1719	str r3, [r2]
1319	1720	bx lr
1320		-.L223:
	1721	+.L287:
1321	1722	.align 2
1322		-.L222:
	1723	+.L286:
1323	1724	.word .LANCHOR0
1324	1725	.fnend
1325	1726	.size NandcFlashDeCs, .-NandcFlashDeCs
1326	1727	.align 2
1327		- .global NandcDelayns
1328		- .type NandcDelayns, %function
1329		-NandcDelayns:
1330		- .fnstart
1331		- @ args = 0, pretend = 0, frame = 0
1332		- @ frame_needed = 0, uses_anonymous_args = 0
1333		- stmfd sp!, {r3, lr}
1334		- .save {r3, lr}
1335		- add r0, r0, #996
1336		- ldr r3, .L226
1337		- add r0, r0, #3
1338		- umull r0, r1, r0, r3
1339		- ldr r3, .L226+4
1340		- ldr r3, [r3, #8]
1341		- mov r0, r1, lsr #6
1342		- blx r3
1343		- mov r0, #0
1344		- ldmfd sp!, {r3, pc}
1345		-.L227:
1346		- .align 2
1347		-.L226:
1348		- .word 274877907
1349		- .word arm_delay_ops
1350		- .fnend
1351		- .size NandcDelayns, .-NandcDelayns
1352		- .align 2
1353		- .global FlashReadStatus
1354		- .type FlashReadStatus, %function
1355		-FlashReadStatus:
1356		- .fnstart
1357		- @ args = 0, pretend = 0, frame = 0
1358		- @ frame_needed = 0, uses_anonymous_args = 0
1359		- stmfd sp!, {r3, r4, r5, lr}
1360		- .save {r3, r4, r5, lr}
1361		- mov r2, #112
1362		- ldr r3, .L230
1363		- add r0, r3, r0, asl #3
1364		- ldrb r4, [r0, #16] @ zero_extendqisi2
1365		- ldr r5, [r0, #12]
1366		- mov r0, #80
1367		- add r3, r5, r4, asl #8
1368		- add r4, r4, #8
1369		- str r2, [r3, #2056]
1370		- bl NandcDelayns
1371		- ldr r0, [r5, r4, asl #8]
1372		- ldmfd sp!, {r3, r4, r5, pc}
1373		-.L231:
1374		- .align 2
1375		-.L230:
1376		- .word .LANCHOR0
1377		- .fnend
1378		- .size FlashReadStatus, .-FlashReadStatus
1379		- .align 2
1380		- .global ToshibaSetRRPara
1381		- .type ToshibaSetRRPara, %function
1382		-ToshibaSetRRPara:
1383		- .fnstart
1384		- @ args = 0, pretend = 0, frame = 0
1385		- @ frame_needed = 0, uses_anonymous_args = 0
1386		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
1387		- .save {r4, r5, r6, r7, r8, r9, r10, lr}
1388		- add r7, r1, r1, asl #2
1389		- ldr r8, .L242
1390		- mov r5, r0
1391		- ldr r10, .L242+4
1392		- mov r6, r1
1393		- add r9, r8, #3168
1394		- mov r4, #0
1395		-.L233:
1396		- ldrb r3, [r10] @ zero_extendqisi2
1397		- cmp r4, r3
1398		- bcs .L241
1399		- mov r3, #85
1400		- str r3, [r5, #8]
1401		- ldrsb r3, [r4, r9]
1402		- mov r0, #200
1403		- str r3, [r5, #4]
1404		- bl NandcDelayns
1405		- ldr r3, .L242+8
1406		- ldrb r3, [r3] @ zero_extendqisi2
1407		- cmp r3, #34
1408		- addeq r3, r4, r7
1409		- addeq r3, r9, r3
1410		- beq .L240
1411		- cmp r3, #35
1412		- addne r3, r8, r6
1413		- addne r3, r3, #3312
1414		- ldrnesb r3, [r3]
1415		- bne .L239
1416		- ldr r3, .L242+12
1417		- add r2, r4, r7
1418		- add r3, r3, r2
1419		-.L240:
1420		- ldrsb r3, [r3, #5]
1421		-.L239:
1422		- str r3, [r5]
1423		- add r4, r4, #1
1424		- b .L233
1425		-.L241:
1426		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
1427		-.L243:
1428		- .align 2
1429		-.L242:
1430		- .word .LANCHOR1
1431		- .word g_maxRegNum
1432		- .word g_retryMode
1433		- .word .LANCHOR1+3216
1434		- .fnend
1435		- .size ToshibaSetRRPara, .-ToshibaSetRRPara
1436		- .align 2
1437		- .global SamsungSetRRPara
1438		- .type SamsungSetRRPara, %function
1439		-SamsungSetRRPara:
1440		- .fnstart
1441		- @ args = 0, pretend = 0, frame = 0
1442		- @ frame_needed = 0, uses_anonymous_args = 0
1443		- ldr r3, .L249
1444		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
1445		- .save {r4, r5, r6, r7, r8, r9, r10, lr}
1446		- add r1, r3, r1, asl #2
1447		- ldr r8, .L249+4
1448		- mov r4, #0
1449		- add r5, r1, #3
1450		- mov r6, r0
1451		- mov r7, r3
1452		- mov r9, #161
1453		- mov r10, r4
1454		-.L245:
1455		- ldrb r3, [r8] @ zero_extendqisi2
1456		- cmp r4, r3
1457		- bcs .L248
1458		- str r9, [r6, #8]
1459		- mov r0, #300
1460		- str r10, [r6]
1461		- ldrsb r3, [r4, r7]
1462		- add r4, r4, #1
1463		- str r3, [r6]
1464		- ldrsb r3, [r5, #1]!
1465		- str r3, [r6]
1466		- bl NandcDelayns
1467		- b .L245
1468		-.L248:
1469		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
1470		-.L250:
1471		- .align 2
1472		-.L249:
1473		- .word .LANCHOR1+3320
1474		- .word g_maxRegNum
1475		- .fnend
1476		- .size SamsungSetRRPara, .-SamsungSetRRPara
1477		- .align 2
1478	1728	.global HynixSetRRPara
	1729	+ .syntax unified
	1730	+ .arm
	1731	+ .fpu softvfp
1479	1732	.type HynixSetRRPara, %function
1480	1733	HynixSetRRPara:
1481	1734	.fnstart
1482	1735	@ args = 0, pretend = 0, frame = 8
1483	1736	@ frame_needed = 0, uses_anonymous_args = 0
1484		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	1737	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
1485	1738	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
1486	1739	.pad #12
1487		- mov r6, r3
1488		- ldr r3, .L260
1489		- mov r10, r2
1490		- mov r7, r0
1491		- mov r9, r1
1492		- ldr r2, [r3, #44]
1493		- ldrb r4, [r2, #19] @ zero_extendqisi2
1494		- mov r2, r0, asl #3
1495		- cmp r4, #6
1496		- ldreq r4, .L260+4
1497		- addeq r4, r4, r0, asl #6
1498		- addeq r4, r4, #20
1499		- addeq r4, r4, r6, asl #2
1500		- beq .L253
1501		-.L252:
1502		- cmp r4, #7
1503		- bne .L254
1504		- ldr r1, .L260+4
1505		- mov r4, #160
1506		- mla r4, r4, r0, r1
1507		- add r1, r6, r6, asl #2
1508		- add r4, r4, #28
1509		- add r4, r4, r1, asl #1
1510		- b .L253
1511		-.L254:
1512		- cmp r4, #8
1513		- addne r4, r6, r2
1514		- addeq r1, r6, r6, asl #2
1515		- ldrne r1, .L260+4
1516		- ldreq r4, .L260+8
1517		- addne r4, r1, r4, asl #3
1518		- addeq r4, r4, r1
1519		- addne r4, r4, #20
1520		-.L253:
1521		- add r3, r3, r2
1522		- mov r0, r7
1523		- sub r9, r9, #1
1524		- sub r4, r4, #1
1525		- ldrb fp, [r3, #16] @ zero_extendqisi2
1526		- ldr r8, [r3, #12]
	1740	+ mov r8, r3
	1741	+ ldr r3, .L297
	1742	+ mov r7, r2
	1743	+ mov r5, r0
	1744	+ mov r6, r1
	1745	+ ldr r4, .L297+4
	1746	+ ldr r2, [r3, #48]
	1747	+ ldrb r2, [r2, #19] @ zero_extendqisi2
	1748	+ cmp r2, #6
	1749	+ bne .L289
	1750	+ mov r2, #20
	1751	+ sub r4, r4, #8
	1752	+ add r2, r2, r0, lsl #6
	1753	+ add r2, r2, r8, lsl #2
	1754	+.L296:
	1755	+ add r4, r4, r2
	1756	+.L290:
	1757	+ ldr r9, [r3, r5, lsl #3]
	1758	+ add r3, r3, r5, lsl #3
	1759	+ mov r0, r5
	1760	+ ldrb fp, [r3, #4] @ zero_extendqisi2
	1761	+ sub r6, r6, #1
1527	1762	bl NandcFlashCs
1528		- sub r2, r10, #1
1529		- add r10, r10, r9
1530		- mov fp, fp, asl #8
1531	1763	mov r3, #54
1532		- add r5, r8, fp
1533		- str r3, [r5, #2056]
1534		-.L256:
1535		- cmp r2, r10
1536		- beq .L259
1537		- ldrb r3, [r2, #1]! @ zero_extendqisi2
1538		- mov r0, #200
1539		- str r3, [r5, #2052]
1540		- str r2, [sp, #4]
1541		- bl NandcDelayns
1542		- ldrsb r3, [r4, #1]!
1543		- str r3, [r5, #2048]
1544		- ldr r2, [sp, #4]
1545		- b .L256
1546		-.L259:
1547		- add r8, r8, fp
	1764	+ sub r4, r4, #1
	1765	+ lsl fp, fp, #8
	1766	+ add r10, r9, fp
	1767	+ str r3, [r10, #2056]
	1768	+ sub r3, r7, #1
	1769	+ add r7, r7, r6
	1770	+.L293:
	1771	+ cmp r3, r7
	1772	+ bne .L294
1548	1773	mov r3, #22
1549		- mov r0, r7
1550		- str r3, [r8, #2056]
	1774	+ add r9, r9, fp
	1775	+ str r3, [r9, #2056]
	1776	+ mov r0, r5
1551	1777	bl NandcFlashDeCs
1552		- ldr r3, .L260+12
1553		- add r7, r3, r7
1554		- strb r6, [r7, #-1880]
	1778	+ ldr r3, .L297+8
	1779	+ add r5, r3, r5
	1780	+ strb r8, [r5, #-1876]
1555	1781	add sp, sp, #12
1556	1782	@ sp needed
1557		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
1558		-.L261:
	1783	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	1784	+.L289:
	1785	+ cmp r2, #7
	1786	+ bne .L291
	1787	+ mov r2, #160
	1788	+ mov r1, #28
	1789	+ smlabb r1, r2, r0, r1
	1790	+ mov r2, #10
	1791	+ sub r4, r4, #8
	1792	+ smlabb r2, r2, r8, r1
	1793	+ b .L296
	1794	+.L291:
	1795	+ cmp r2, #8
	1796	+ addeq r4, r4, #20
	1797	+ addeq r2, r8, r8, lsl #2
	1798	+ beq .L296
	1799	+ add r2, r8, #2
	1800	+ add r2, r2, r0, lsl #3
	1801	+ add r4, r4, r2, lsl #3
	1802	+ sub r4, r4, #4
	1803	+ b .L290
	1804	+.L294:
	1805	+ ldrb r2, [r3, #1]! @ zero_extendqisi2
	1806	+ mov r0, #200
	1807	+ str r2, [r10, #2052]
	1808	+ str r3, [sp, #4]
	1809	+ bl ndelay
	1810	+ ldrsb r2, [r4, #1]!
	1811	+ ldr r3, [sp, #4]
	1812	+ str r2, [r10, #2048]
	1813	+ b .L293
	1814	+.L298:
1559	1815	.align 2
1560		-.L260:
	1816	+.L297:
1561	1817	.word .LANCHOR0
1562		- .word .LANCHOR2-2732
1563		- .word .LANCHOR2-2704
	1818	+ .word .LANCHOR2-2720
1564	1819	.word .LANCHOR2
1565	1820	.fnend
1566	1821	.size HynixSetRRPara, .-HynixSetRRPara
1567	1822	.align 2
1568	1823	.global FlashSetReadRetryDefault
	1824	+ .syntax unified
	1825	+ .arm
	1826	+ .fpu softvfp
1569	1827	.type FlashSetReadRetryDefault, %function
1570	1828	FlashSetReadRetryDefault:
1571	1829	.fnstart
1572	1830	@ args = 0, pretend = 0, frame = 0
1573	1831	@ frame_needed = 0, uses_anonymous_args = 0
1574		- ldr r3, .L270
1575		- ldr r3, [r3, #44]
	1832	+ ldr r3, .L309
	1833	+ ldr r3, [r3, #48]
1576	1834	ldrb r3, [r3, #19] @ zero_extendqisi2
1577	1835	sub r3, r3, #1
1578	1836	cmp r3, #7
1579	1837	bxhi lr
1580		- stmfd sp!, {r4, r5, r6, lr}
	1838	+ push {r4, r5, r6, lr}
1581	1839	.save {r4, r5, r6, lr}
1582	1840	mov r4, #0
1583		- ldr r5, .L270+4
1584		- ldr r6, .L270+8
1585		-.L263:
1586		- ldrb r3, [r5, r4, asl #3] @ zero_extendqisi2
	1841	+ ldr r6, .L309+4
	1842	+ sub r5, r6, #2720
	1843	+ sub r5, r5, #4
	1844	+.L302:
	1845	+ ldr r3, .L309+8
1587	1846	uxtb r0, r4
	1847	+ ldrb r3, [r3, r4, lsl #3] @ zero_extendqisi2
1588	1848	cmp r3, #173
1589		- bne .L264
1590		- ldrb r1, [r6, #-2731] @ zero_extendqisi2
	1849	+ bne .L301
1591	1850	mov r3, #0
1592		- ldr r2, .L270+12
	1851	+ mov r2, r5
	1852	+ ldrb r1, [r6, #-2727] @ zero_extendqisi2
1593	1853	bl HynixSetRRPara
1594		-.L264:
	1854	+.L301:
1595	1855	add r4, r4, #1
1596	1856	cmp r4, #4
1597		- bne .L263
1598		- ldmfd sp!, {r4, r5, r6, pc}
1599		-.L271:
	1857	+ bne .L302
	1858	+ pop {r4, r5, r6, pc}
	1859	+.L310:
1600	1860	.align 2
1601		-.L270:
	1861	+.L309:
1602	1862	.word .LANCHOR0
1603		- .word IDByte
1604	1863	.word .LANCHOR2
1605		- .word .LANCHOR2-2728
	1864	+ .word IDByte
1606	1865	.fnend
1607	1866	.size FlashSetReadRetryDefault, .-FlashSetReadRetryDefault
1608	1867	.align 2
1609		- .global FlashReadStatusEN
1610		- .type FlashReadStatusEN, %function
1611		-FlashReadStatusEN:
1612		- .fnstart
1613		- @ args = 0, pretend = 0, frame = 0
1614		- @ frame_needed = 0, uses_anonymous_args = 0
1615		- ldr ip, .L283
1616		- stmfd sp!, {r3, r4, r5, lr}
1617		- .save {r3, r4, r5, lr}
1618		- add r0, ip, r0, asl #3
1619		- ldr r3, [ip, #44]
1620		- ldrb r5, [r0, #16] @ zero_extendqisi2
1621		- ldr r4, [r0, #12]
1622		- ldrb r3, [r3, #8] @ zero_extendqisi2
1623		- cmp r3, #2
1624		- mov r3, r5, asl #8
1625		- addne r3, r4, r3
1626		- add r5, r5, #8
1627		- movne r2, #112
1628		- strne r2, [r3, #2056]
1629		- bne .L277
1630		- cmp r2, #0
1631		- add r3, r4, r3
1632		- ldrneb r2, [ip, #62] @ zero_extendqisi2
1633		- ldreqb r2, [ip, #61] @ zero_extendqisi2
1634		- str r2, [r3, #2056]
1635		- ldrb r0, [ip, #63] @ zero_extendqisi2
1636		- cmp r0, #0
1637		- addne ip, r4, r5, asl #8
1638		- movne r2, #0
1639		- beq .L277
1640		-.L276:
1641		- cmp r2, r0
1642		- bcs .L277
1643		- mov r3, r2, asl #3
1644		- add r2, r2, #1
1645		- mov r3, r1, lsr r3
1646		- uxtb r3, r3
1647		- str r3, [ip, #4]
1648		- b .L276
1649		-.L277:
1650		- mov r0, #80
1651		- bl NandcDelayns
1652		- ldr r0, [r4, r5, asl #8]
1653		- uxtb r0, r0
1654		- ldmfd sp!, {r3, r4, r5, pc}
1655		-.L284:
1656		- .align 2
1657		-.L283:
1658		- .word .LANCHOR0
1659		- .fnend
1660		- .size FlashReadStatusEN, .-FlashReadStatusEN
1661		- .align 2
1662		- .global FlashWaitReadyEN
1663		- .type FlashWaitReadyEN, %function
1664		-FlashWaitReadyEN:
1665		- .fnstart
1666		- @ args = 0, pretend = 0, frame = 0
1667		- @ frame_needed = 0, uses_anonymous_args = 0
1668		- stmfd sp!, {r4, r5, r6, lr}
1669		- .save {r4, r5, r6, lr}
1670		- mov r4, r0
1671		- mov r5, r1
1672		- mov r6, r2
1673		-.L286:
1674		- mov r0, r4
1675		- mov r1, r5
1676		- mov r2, r6
1677		- bl FlashReadStatusEN
1678		- cmp r0, #255
1679		- beq .L286
1680		- tst r0, #64
1681		- ldmnefd sp!, {r4, r5, r6, pc}
1682		- mov r0, #1
1683		- mov r1, #3
1684		- bl usleep_range
1685		- b .L286
1686		- .fnend
1687		- .size FlashWaitReadyEN, .-FlashWaitReadyEN
1688		- .align 2
1689	1868	.global FlashWaitCmdDone
	1869	+ .syntax unified
	1870	+ .arm
	1871	+ .fpu softvfp
1690	1872	.type FlashWaitCmdDone, %function
1691	1873	FlashWaitCmdDone:
1692	1874	.fnstart
1693	1875	@ args = 0, pretend = 0, frame = 0
1694	1876	@ frame_needed = 0, uses_anonymous_args = 0
1695		- stmfd sp!, {r3, r4, r5, r6, r7, lr}
1696		- .save {r3, r4, r5, r6, r7, lr}
1697		- ldr r5, .L300
1698		- add r4, r5, r0, asl #4
1699		- ldr r3, [r4, #3204]
1700		- ldrb r7, [r4, #3196] @ zero_extendqisi2
	1877	+ push {r4, r5, r6, r7, r8, lr}
	1878	+ .save {r4, r5, r6, r7, r8, lr}
	1879	+ ldr r5, .L319
	1880	+ add r4, r5, r0, lsl #4
	1881	+ ldr r3, [r4, #3208]
1701	1882	cmp r3, #0
1702		- beq .L294
	1883	+ beq .L313
	1884	+ ldrb r7, [r4, #3200] @ zero_extendqisi2
1703	1885	mov r6, r0
	1886	+ add r5, r5, r6, lsl #2
1704	1887	mov r0, r7
1705		- add r5, r5, r6, asl #2
1706	1888	bl NandcFlashCs
1707		- ldr r1, [r4, #3200]
	1889	+ ldr r2, [r5, #3168]
1708	1890	mov r0, r7
1709		- ldr r2, [r5, #3164]
	1891	+ ldr r1, [r4, #3204]
1710	1892	adds r2, r2, #0
1711	1893	movne r2, #1
1712	1894	bl FlashWaitReadyEN
1713		- mov r5, r0
	1895	+ mov r1, r0
1714	1896	mov r0, r7
1715	1897	bl NandcFlashDeCs
1716		- ldr r2, [r4, #3204]
1717		- sbfx r3, r5, #0, #1
1718		- str r3, [r2]
1719		- mov r2, #0
1720		- ldr r1, [r4, #3208]
1721		- str r2, [r4, #3204]
1722		- cmp r1, r2
1723		- strne r3, [r1]
1724		- strne r2, [r4, #3208]
1725		-.L294:
	1898	+ ldr r3, [r4, #3208]
	1899	+ sbfx r0, r1, #0, #1
	1900	+ str r0, [r3]
	1901	+ mov r3, #0
	1902	+ ldr r2, [r4, #3212]
	1903	+ str r3, [r4, #3208]
	1904	+ cmp r2, r3
	1905	+ strne r0, [r2]
	1906	+ strne r3, [r4, #3212]
	1907	+.L313:
1726	1908	mov r0, #0
1727		- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
1728		-.L301:
	1909	+ pop {r4, r5, r6, r7, r8, pc}
	1910	+.L320:
1729	1911	.align 2
1730		-.L300:
	1912	+.L319:
1731	1913	.word .LANCHOR0
1732	1914	.fnend
1733	1915	.size FlashWaitCmdDone, .-FlashWaitCmdDone
1734	1916	.align 2
1735		- .type flash_read_ecc, %function
1736		-flash_read_ecc:
	1917	+ .global NandcDelayns
	1918	+ .syntax unified
	1919	+ .arm
	1920	+ .fpu softvfp
	1921	+ .type NandcDelayns, %function
	1922	+NandcDelayns:
1737	1923	.fnstart
1738	1924	@ args = 0, pretend = 0, frame = 0
1739	1925	@ frame_needed = 0, uses_anonymous_args = 0
1740		- ldr r2, .L304
1741		- stmfd sp!, {r4, lr}
	1926	+ push {r4, lr}
1742	1927	.save {r4, lr}
1743		- add r0, r2, r0, asl #3
1744		- ldrb r4, [r0, #16] @ zero_extendqisi2
1745		- ldr r3, [r0, #12]
1746		- mov r0, #80
1747		- add r4, r3, r4, asl #8
1748		- mov r3, #122
1749		- str r3, [r4, #2056]
1750		- bl NandcDelayns
1751		- ldr r3, [r4, #2048]
1752		- ldr r0, [r4, #2048]
1753		- and r3, r3, #15
1754		- and r0, r0, #15
1755		- cmp r0, r3
1756		- movcc r0, r3
1757		- ldr r3, [r4, #2048]
1758		- and r3, r3, #15
1759		- cmp r0, r3
1760		- movcc r0, r3
1761		- ldr r3, [r4, #2048]
1762		- and r3, r3, #15
1763		- cmp r0, r3
1764		- movcc r0, r3
1765		- ldmfd sp!, {r4, pc}
1766		-.L305:
1767		- .align 2
1768		-.L304:
1769		- .word .LANCHOR0
	1928	+ bl ndelay
	1929	+ mov r0, #0
	1930	+ pop {r4, pc}
1770	1931	.fnend
1771		- .size flash_read_ecc, .-flash_read_ecc
	1932	+ .size NandcDelayns, .-NandcDelayns
1772	1933	.align 2
1773	1934	.global NandcWaitFlashReadyNoDelay
	1935	+ .syntax unified
	1936	+ .arm
	1937	+ .fpu softvfp
1774	1938	.type NandcWaitFlashReadyNoDelay, %function
1775	1939	NandcWaitFlashReadyNoDelay:
1776	1940	.fnstart
1777	1941	@ args = 0, pretend = 0, frame = 8
1778	1942	@ frame_needed = 0, uses_anonymous_args = 0
1779		- ldr r3, .L312
1780		- stmfd sp!, {r0, r1, r2, r4, r5, lr}
	1943	+ ldr r3, .L329
	1944	+ push {r0, r1, r2, r4, r5, lr}
1781	1945	.save {r4, r5, lr}
1782	1946	.pad #12
1783		- add r0, r3, r0, asl #3
1784		- ldr r4, .L312+4
1785		- ldr r5, [r0, #12]
1786		-.L308:
	1947	+ ldr r4, .L329+4
	1948	+ ldr r5, [r3, r0, lsl #3]
	1949	+.L325:
1787	1950	ldr r3, [r5]
1788	1951	str r3, [sp, #4]
1789	1952	ldr r3, [sp, #4]
1790	1953	tst r3, #512
1791		- bne .L309
	1954	+ bne .L326
1792	1955	mov r0, #10
1793		- bl NandcDelayns
	1956	+ bl ndelay
1794	1957	subs r4, r4, #1
1795		- bne .L308
	1958	+ bne .L325
1796	1959	mvn r0, #0
1797		- b .L307
1798		-.L309:
1799		- mov r0, #0
1800		-.L307:
	1960	+.L323:
1801	1961	add sp, sp, #12
1802	1962	@ sp needed
1803		- ldmfd sp!, {r4, r5, pc}
1804		-.L313:
	1963	+ pop {r4, r5, pc}
	1964	+.L326:
	1965	+ mov r0, #0
	1966	+ b .L323
	1967	+.L330:
1805	1968	.align 2
1806		-.L312:
	1969	+.L329:
1807	1970	.word .LANCHOR0
1808	1971	.word 100000
1809	1972	.fnend
1810	1973	.size NandcWaitFlashReadyNoDelay, .-NandcWaitFlashReadyNoDelay
1811	1974	.align 2
1812	1975	.global NandcWaitFlashReady
	1976	+ .syntax unified
	1977	+ .arm
	1978	+ .fpu softvfp
1813	1979	.type NandcWaitFlashReady, %function
1814	1980	NandcWaitFlashReady:
1815	1981	.fnstart
1816	1982	@ args = 0, pretend = 0, frame = 8
1817	1983	@ frame_needed = 0, uses_anonymous_args = 0
1818		- ldr r3, .L320
1819		- stmfd sp!, {r0, r1, r2, r4, r5, lr}
	1984	+ push {r0, r1, r2, r4, r5, lr}
1820	1985	.save {r4, r5, lr}
1821	1986	.pad #12
1822		- add r0, r3, r0, asl #3
1823		- ldr r4, .L320+4
1824		- ldr r5, [r0, #12]
	1987	+ ldr r3, .L337
	1988	+ ldr r4, .L337+4
	1989	+ ldr r5, [r3, r0, lsl #3]
1825	1990	mov r0, #130
1826		- bl NandcDelayns
1827		-.L316:
	1991	+ bl ndelay
	1992	+.L333:
1828	1993	ldr r3, [r5]
1829	1994	str r3, [sp, #4]
1830	1995	ldr r3, [sp, #4]
1831	1996	tst r3, #512
1832		- bne .L317
1833		- mov r0, #1
	1997	+ bne .L334
1834	1998	mov r1, #2
	1999	+ mov r0, #1
1835	2000	bl usleep_range
1836	2001	subs r4, r4, #1
1837		- bne .L316
	2002	+ bne .L333
1838	2003	mvn r0, #0
1839		- b .L315
1840		-.L317:
1841		- mov r0, #0
1842		-.L315:
	2004	+.L331:
1843	2005	add sp, sp, #12
1844	2006	@ sp needed
1845		- ldmfd sp!, {r4, r5, pc}
1846		-.L321:
	2007	+ pop {r4, r5, pc}
	2008	+.L334:
	2009	+ mov r0, #0
	2010	+ b .L331
	2011	+.L338:
1847	2012	.align 2
1848		-.L320:
	2013	+.L337:
1849	2014	.word .LANCHOR0
1850	2015	.word 100000
1851	2016	.fnend
1852	2017	.size NandcWaitFlashReady, .-NandcWaitFlashReady
1853	2018	.align 2
1854	2019	.global FlashReset
	2020	+ .syntax unified
	2021	+ .arm
	2022	+ .fpu softvfp
1855	2023	.type FlashReset, %function
1856	2024	FlashReset:
1857	2025	.fnstart
1858	2026	@ args = 0, pretend = 0, frame = 0
1859	2027	@ frame_needed = 0, uses_anonymous_args = 0
1860		- ldr r3, .L324
1861		- stmfd sp!, {r4, r5, r6, lr}
	2028	+ ldr r3, .L341
	2029	+ push {r4, r5, r6, lr}
1862	2030	.save {r4, r5, r6, lr}
1863		- add r3, r3, r0, asl #3
1864	2031	mov r4, r0
1865		- ldrb r6, [r3, #16] @ zero_extendqisi2
1866		- ldr r5, [r3, #12]
	2032	+ ldr r5, [r3, r0, lsl #3]
	2033	+ add r3, r3, r0, lsl #3
	2034	+ ldrb r6, [r3, #4] @ zero_extendqisi2
1867	2035	bl NandcFlashCs
1868	2036	mov r3, #255
1869	2037	mov r0, r4
1870		- add r5, r5, r6, asl #8
	2038	+ add r5, r5, r6, lsl #8
1871	2039	str r3, [r5, #2056]
1872	2040	bl NandcWaitFlashReady
1873	2041	mov r0, r4
1874		- ldmfd sp!, {r4, r5, r6, lr}
	2042	+ pop {r4, r5, r6, lr}
1875	2043	b NandcFlashDeCs
1876		-.L325:
	2044	+.L342:
1877	2045	.align 2
1878		-.L324:
	2046	+.L341:
1879	2047	.word .LANCHOR0
1880	2048	.fnend
1881	2049	.size FlashReset, .-FlashReset
1882	2050	.align 2
1883	2051	.global flash_enter_slc_mode
	2052	+ .syntax unified
	2053	+ .arm
	2054	+ .fpu softvfp
1884	2055	.type flash_enter_slc_mode, %function
1885	2056	flash_enter_slc_mode:
1886	2057	.fnstart
1887	2058	@ args = 0, pretend = 0, frame = 0
1888	2059	@ frame_needed = 0, uses_anonymous_args = 0
1889		- stmfd sp!, {r4, r5, r6, r7, r8, lr}
	2060	+ push {r4, r5, r6, r7, r8, lr}
1890	2061	.save {r4, r5, r6, r7, r8, lr}
1891		- ldr r6, .L333
1892		- ldrb r3, [r6, #-2744] @ zero_extendqisi2
	2062	+ ldr r6, .L350
	2063	+ ldrb r3, [r6, #-2740] @ zero_extendqisi2
1893	2064	cmp r3, #0
1894		- ldmeqfd sp!, {r4, r5, r6, r7, r8, pc}
	2065	+ popeq {r4, r5, r6, r7, r8, pc}
1895	2066	mov r5, r0
1896	2067	bl NandcFlashCs
1897		- ldr r3, .L333+4
1898		- add r3, r3, r5, asl #3
1899		- ldrb r8, [r3, #16] @ zero_extendqisi2
1900		- ldr r7, [r3, #12]
1901		- ldr r3, .L333+8
1902		- mov r8, r8, asl #8
1903		- ldrb r3, [r3, r5, asl #3] @ zero_extendqisi2
	2068	+ ldr r3, .L350+4
	2069	+ ldr r7, [r3, r5, lsl #3]
	2070	+ add r3, r3, r5, lsl #3
	2071	+ ldrb r8, [r3, #4] @ zero_extendqisi2
	2072	+ ldr r3, .L350+8
	2073	+ ldrb r3, [r3, r5, lsl #3] @ zero_extendqisi2
	2074	+ lsl r8, r8, #8
1904	2075	cmp r3, #44
1905		- bne .L328
	2076	+ bne .L345
1906	2077	add r4, r7, r8
1907	2078	mov r3, #239
1908		- mov r0, #50
1909	2079	str r3, [r4, #2056]
1910	2080	mov r3, #145
1911	2081	str r3, [r4, #2052]
1912		- bl NandcDelayns
	2082	+ mov r0, #50
	2083	+ bl ndelay
1913	2084	mov r3, #0
1914	2085	mov r2, #1
1915	2086	str r3, [r4, #2048]
..	..	@@ -1917,21 +2088,21 @@
1917	2088	str r2, [r4, #2048]
1918	2089	str r3, [r4, #2048]
1919	2090	str r3, [r4, #2048]
1920		- bl NandcDelayns
1921		-.L328:
1922		- add r7, r7, r8
	2091	+ bl ndelay
	2092	+.L345:
1923	2093	mov r0, r5
	2094	+ add r7, r7, r8
1924	2095	bl NandcWaitFlashReadyNoDelay
1925	2096	mov r3, #218
1926	2097	mov r0, r5
1927	2098	str r3, [r7, #2056]
1928	2099	bl NandcWaitFlashReady
1929	2100	mov r3, #2
1930		- strb r3, [r6, #-1876]
1931		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
1932		-.L334:
	2101	+ strb r3, [r6, #-1872]
	2102	+ pop {r4, r5, r6, r7, r8, pc}
	2103	+.L351:
1933	2104	.align 2
1934		-.L333:
	2105	+.L350:
1935	2106	.word .LANCHOR2
1936	2107	.word .LANCHOR0
1937	2108	.word IDByte
..	..	@@ -1939,35 +2110,38 @@
1939	2110	.size flash_enter_slc_mode, .-flash_enter_slc_mode
1940	2111	.align 2
1941	2112	.global flash_exit_slc_mode
	2113	+ .syntax unified
	2114	+ .arm
	2115	+ .fpu softvfp
1942	2116	.type flash_exit_slc_mode, %function
1943	2117	flash_exit_slc_mode:
1944	2118	.fnstart
1945	2119	@ args = 0, pretend = 0, frame = 0
1946	2120	@ frame_needed = 0, uses_anonymous_args = 0
1947		- stmfd sp!, {r4, r5, r6, r7, r8, lr}
	2121	+ push {r4, r5, r6, r7, r8, lr}
1948	2122	.save {r4, r5, r6, r7, r8, lr}
1949		- ldr r6, .L342
1950		- ldrb r3, [r6, #-2744] @ zero_extendqisi2
	2123	+ ldr r6, .L359
	2124	+ ldrb r3, [r6, #-2740] @ zero_extendqisi2
1951	2125	cmp r3, #0
1952		- ldmeqfd sp!, {r4, r5, r6, r7, r8, pc}
	2126	+ popeq {r4, r5, r6, r7, r8, pc}
1953	2127	mov r5, r0
1954	2128	bl NandcFlashCs
1955		- ldr r3, .L342+4
1956		- add r3, r3, r5, asl #3
1957		- ldrb r8, [r3, #16] @ zero_extendqisi2
1958		- ldr r7, [r3, #12]
1959		- ldr r3, .L342+8
1960		- mov r8, r8, asl #8
1961		- ldrb r3, [r3, r5, asl #3] @ zero_extendqisi2
	2129	+ ldr r3, .L359+4
	2130	+ ldr r7, [r3, r5, lsl #3]
	2131	+ add r3, r3, r5, lsl #3
	2132	+ ldrb r8, [r3, #4] @ zero_extendqisi2
	2133	+ ldr r3, .L359+8
	2134	+ ldrb r3, [r3, r5, lsl #3] @ zero_extendqisi2
	2135	+ lsl r8, r8, #8
1962	2136	cmp r3, #44
1963		- bne .L337
	2137	+ bne .L354
1964	2138	add r4, r7, r8
1965	2139	mov r3, #239
1966		- mov r0, #50
1967	2140	str r3, [r4, #2056]
1968	2141	mov r3, #145
1969	2142	str r3, [r4, #2052]
1970		- bl NandcDelayns
	2143	+ mov r0, #50
	2144	+ bl ndelay
1971	2145	mov r3, #2
1972	2146	mov r0, #100
1973	2147	str r3, [r4, #2048]
..	..	@@ -1976,21 +2150,21 @@
1976	2150	mov r3, #0
1977	2151	str r3, [r4, #2048]
1978	2152	str r3, [r4, #2048]
1979		- bl NandcDelayns
1980		-.L337:
1981		- add r7, r7, r8
	2153	+ bl ndelay
	2154	+.L354:
1982	2155	mov r0, r5
	2156	+ add r7, r7, r8
1983	2157	bl NandcWaitFlashReadyNoDelay
1984	2158	mov r3, #223
1985	2159	mov r0, r5
1986	2160	str r3, [r7, #2056]
1987	2161	bl NandcWaitFlashReady
1988	2162	mov r3, #0
1989		- strb r3, [r6, #-1876]
1990		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
1991		-.L343:
	2163	+ strb r3, [r6, #-1872]
	2164	+ pop {r4, r5, r6, r7, r8, pc}
	2165	+.L360:
1992	2166	.align 2
1993		-.L342:
	2167	+.L359:
1994	2168	.word .LANCHOR2
1995	2169	.word .LANCHOR0
1996	2170	.word IDByte
..	..	@@ -1998,12 +2172,15 @@
1998	2172	.size flash_exit_slc_mode, .-flash_exit_slc_mode
1999	2173	.align 2
2000	2174	.global FlashEraseBlock
	2175	+ .syntax unified
	2176	+ .arm
	2177	+ .fpu softvfp
2001	2178	.type FlashEraseBlock, %function
2002	2179	FlashEraseBlock:
2003	2180	.fnstart
2004	2181	@ args = 0, pretend = 0, frame = 0
2005	2182	@ frame_needed = 0, uses_anonymous_args = 0
2006		- stmfd sp!, {r4, r5, r6, lr}
	2183	+ push {r4, r5, r6, lr}
2007	2184	.save {r4, r5, r6, lr}
2008	2185	mov r4, r0
2009	2186	mov r5, r1
..	..	@@ -2020,136 +2197,143 @@
2020	2197	mov r1, r5
2021	2198	mov r0, r4
2022	2199	bl FlashReadStatus
2023		- mov r5, r0
	2200	+ mov r1, r0
2024	2201	mov r0, r4
2025	2202	bl NandcFlashDeCs
2026		- and r0, r5, #1
2027		- ldmfd sp!, {r4, r5, r6, pc}
	2203	+ and r0, r1, #1
	2204	+ pop {r4, r5, r6, pc}
2028	2205	.fnend
2029	2206	.size FlashEraseBlock, .-FlashEraseBlock
2030	2207	.align 2
2031	2208	.global FlashSetInterfaceMode
	2209	+ .syntax unified
	2210	+ .arm
	2211	+ .fpu softvfp
2032	2212	.type FlashSetInterfaceMode, %function
2033	2213	FlashSetInterfaceMode:
2034	2214	.fnstart
2035	2215	@ args = 0, pretend = 0, frame = 8
2036	2216	@ frame_needed = 0, uses_anonymous_args = 0
2037		- ldr r3, .L369
2038		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	2217	+ ldr r3, .L386
	2218	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
2039	2219	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
2040	2220	.pad #12
2041	2221	mov lr, #0
2042		- ldrb r2, [r3, #-1875] @ zero_extendqisi2
2043		- mov r4, #239
2044		- ldr r7, .L369+4
2045		- mov r5, #128
2046		- and r3, r2, #1
2047		- and r2, r2, #4
2048		- str r3, [sp, #4]
2049		- mov r6, #1
2050		- uxtb r3, r2
2051		- mov r8, #35
	2222	+ ldr r4, .L386+4
	2223	+ mov r5, #239
	2224	+ mov r6, #128
	2225	+ mov r7, #1
	2226	+ ldrb r3, [r3, #-1871] @ zero_extendqisi2
	2227	+ mov r9, #35
	2228	+ mov r8, r4
	2229	+ mov r10, #32
	2230	+ and r2, r3, #4
	2231	+ and r3, r3, #1
	2232	+ str r2, [sp, #4]
2052	2233	mov r2, lr
2053		- mov r9, #32
2054		- mov r10, #5
2055	2234	str r3, [sp]
2056		-.L356:
2057		- ldr r3, .L369+8
2058		- ldrb ip, [lr, r7] @ zero_extendqisi2
2059		- ldr r1, [r3, lr]!
	2235	+.L373:
	2236	+ ldr r1, .L386+8
	2237	+ add r3, r4, lr
	2238	+ ldrb r3, [r3, #4] @ zero_extendqisi2
	2239	+ ldrb ip, [lr, r1] @ zero_extendqisi2
2060	2240	cmp ip, #69
2061	2241	cmpne ip, #152
2062		- ldrb r3, [r3, #4] @ zero_extendqisi2
2063		- beq .L347
	2242	+ beq .L364
2064	2243	cmp ip, #44
2065	2244	cmpne ip, #173
2066		- bne .L348
2067		-.L347:
	2245	+ bne .L365
	2246	+.L364:
2068	2247	cmp r0, #1
2069		- bne .L349
2070		- ldr fp, [sp, #4]
2071		- cmp fp, #0
2072		- beq .L348
2073		- mov r3, r3, asl #8
2074		- cmp ip, #173
2075		- add fp, r1, r3
2076		- str r4, [fp, #2056]
2077		- streq r0, [fp, #2052]
2078		- beq .L368
2079		- cmp ip, #44
2080		- streq r0, [fp, #2052]
2081		- strne r5, [fp, #2052]
2082		- streq r10, [fp, #2048]
2083		- strne r0, [fp, #2048]
2084		- b .L354
2085		-.L349:
	2248	+ ldr r1, [r8, lr]
	2249	+ bne .L366
2086	2250	ldr fp, [sp]
2087	2251	cmp fp, #0
2088		- beq .L348
2089		- mov r3, r3, asl #8
	2252	+ beq .L365
	2253	+ lsl r3, r3, #8
2090	2254	cmp ip, #173
2091	2255	add fp, r1, r3
2092		- str r4, [fp, #2056]
2093		- streq r6, [fp, #2052]
2094		- streq r9, [fp, #2048]
2095		- beq .L354
	2256	+ str r5, [fp, #2056]
	2257	+ streq r0, [fp, #2052]
	2258	+ beq .L385
2096	2259	cmp ip, #44
2097		- streq r6, [fp, #2052]
2098		- streq r8, [fp, #2048]
2099		- beq .L354
2100		- str r5, [fp, #2052]
2101		-.L368:
2102		- str r2, [fp, #2048]
2103		-.L354:
	2260	+ moveq ip, #5
	2261	+ streq r0, [fp, #2052]
	2262	+ strne r6, [fp, #2052]
	2263	+ streq ip, [fp, #2048]
	2264	+ strne r0, [fp, #2048]
	2265	+.L371:
2104	2266	add r3, r1, r3
2105	2267	str r2, [r3, #2048]
2106	2268	str r2, [r3, #2048]
2107	2269	str r2, [r3, #2048]
2108		-.L348:
	2270	+.L365:
2109	2271	add lr, lr, #8
2110	2272	cmp lr, #32
2111		- bne .L356
	2273	+ bne .L373
2112	2274	mov r0, #0
2113	2275	bl NandcWaitFlashReady
2114	2276	mov r0, #0
2115	2277	add sp, sp, #12
2116	2278	@ sp needed
2117		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
2118		-.L370:
	2279	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	2280	+.L366:
	2281	+ ldr fp, [sp, #4]
	2282	+ cmp fp, #0
	2283	+ beq .L365
	2284	+ lsl r3, r3, #8
	2285	+ cmp ip, #173
	2286	+ add fp, r1, r3
	2287	+ str r5, [fp, #2056]
	2288	+ streq r7, [fp, #2052]
	2289	+ streq r10, [fp, #2048]
	2290	+ beq .L371
	2291	+ cmp ip, #44
	2292	+ streq r7, [fp, #2052]
	2293	+ streq r9, [fp, #2048]
	2294	+ beq .L371
	2295	+ str r6, [fp, #2052]
	2296	+.L385:
	2297	+ str r2, [fp, #2048]
	2298	+ b .L371
	2299	+.L387:
2119	2300	.align 2
2120		-.L369:
	2301	+.L386:
2121	2302	.word .LANCHOR2
	2303	+ .word .LANCHOR0
2122	2304	.word IDByte
2123		- .word .LANCHOR0+12
2124	2305	.fnend
2125	2306	.size FlashSetInterfaceMode, .-FlashSetInterfaceMode
2126	2307	.align 2
2127	2308	.global FlashReadSpare
	2309	+ .syntax unified
	2310	+ .arm
	2311	+ .fpu softvfp
2128	2312	.type FlashReadSpare, %function
2129	2313	FlashReadSpare:
2130	2314	.fnstart
2131	2315	@ args = 0, pretend = 0, frame = 0
2132	2316	@ frame_needed = 0, uses_anonymous_args = 0
2133		- ldr ip, .L373
2134		- stmfd sp!, {r3, r4, r5, lr}
2135		- .save {r3, r4, r5, lr}
2136		- add ip, ip, r0, asl #3
2137		- ldr r3, .L373+4
	2317	+ ldr ip, .L390
	2318	+ ldr r3, .L390+4
	2319	+ push {r4, r5, r6, lr}
	2320	+ .save {r4, r5, r6, lr}
2138	2321	mov r5, r2
2139		- ldrb r2, [ip, #16] @ zero_extendqisi2
2140		- ldr r4, [ip, #12]
2141		- ldrb r3, [r3, #265] @ zero_extendqisi2
2142		- add r4, r4, r2, asl #8
	2322	+ ldr r4, [ip, r0, lsl #3]
	2323	+ add ip, ip, r0, lsl #3
	2324	+ ldrb r3, [r3, #477] @ zero_extendqisi2
	2325	+ ldrb r2, [ip, #4] @ zero_extendqisi2
	2326	+ lsl r3, r3, #9
	2327	+ add r4, r4, r2, lsl #8
2143	2328	mov r2, #0
2144		- mov r3, r3, asl #9
2145	2329	str r2, [r4, #2056]
2146	2330	str r3, [r4, #2052]
2147		- mov r3, r3, lsr #8
	2331	+ lsr r3, r3, #8
2148	2332	str r3, [r4, #2052]
2149	2333	uxtb r3, r1
2150	2334	str r3, [r4, #2052]
2151		- mov r3, r1, lsr #8
2152		- mov r1, r1, lsr #16
	2335	+ lsr r3, r1, #8
	2336	+ lsr r1, r1, #16
2153	2337	str r3, [r4, #2052]
2154	2338	mov r3, #48
2155	2339	str r1, [r4, #2052]
..	..	@@ -2157,28 +2341,31 @@
2157	2341	bl NandcWaitFlashReady
2158	2342	ldr r3, [r4, #2048]
2159	2343	strb r3, [r5]
2160		- ldmfd sp!, {r3, r4, r5, pc}
2161		-.L374:
	2344	+ pop {r4, r5, r6, pc}
	2345	+.L391:
2162	2346	.align 2
2163		-.L373:
	2347	+.L390:
2164	2348	.word .LANCHOR0
2165	2349	.word .LANCHOR1
2166	2350	.fnend
2167	2351	.size FlashReadSpare, .-FlashReadSpare
2168	2352	.align 2
2169	2353	.global SandiskProgTestBadBlock
	2354	+ .syntax unified
	2355	+ .arm
	2356	+ .fpu softvfp
2170	2357	.type SandiskProgTestBadBlock, %function
2171	2358	SandiskProgTestBadBlock:
2172	2359	.fnstart
2173	2360	@ args = 0, pretend = 0, frame = 0
2174	2361	@ frame_needed = 0, uses_anonymous_args = 0
2175		- ldr r2, .L377
2176		- stmfd sp!, {r4, lr}
	2362	+ ldr r3, .L394
	2363	+ push {r4, lr}
2177	2364	.save {r4, lr}
2178		- add r2, r2, r0, asl #3
2179		- ldrb r4, [r2, #16] @ zero_extendqisi2
2180		- ldr r3, [r2, #12]
2181		- add r4, r3, r4, asl #8
	2365	+ ldr r4, [r3, r0, lsl #3]
	2366	+ add r3, r3, r0, lsl #3
	2367	+ ldrb r3, [r3, #4] @ zero_extendqisi2
	2368	+ add r4, r4, r3, lsl #8
2182	2369	mov r3, #162
2183	2370	str r3, [r4, #2056]
2184	2371	mov r3, #128
..	..	@@ -2188,165 +2375,179 @@
2188	2375	str r3, [r4, #2052]
2189	2376	uxtb r3, r1
2190	2377	str r3, [r4, #2052]
2191		- mov r3, r1, lsr #8
2192		- mov r1, r1, lsr #16
	2378	+ lsr r3, r1, #8
	2379	+ lsr r1, r1, #16
2193	2380	str r3, [r4, #2052]
2194		- str r1, [r4, #2052]
2195	2381	mov r3, #16
	2382	+ str r1, [r4, #2052]
2196	2383	str r3, [r4, #2056]
2197	2384	bl NandcWaitFlashReady
2198	2385	mov r3, #112
2199	2386	mov r0, #80
2200	2387	str r3, [r4, #2056]
2201		- bl NandcDelayns
	2388	+ bl ndelay
2202	2389	ldr r0, [r4, #2048]
2203	2390	and r0, r0, #1
2204		- ldmfd sp!, {r4, pc}
2205		-.L378:
	2391	+ pop {r4, pc}
	2392	+.L395:
2206	2393	.align 2
2207		-.L377:
	2394	+.L394:
2208	2395	.word .LANCHOR0
2209	2396	.fnend
2210	2397	.size SandiskProgTestBadBlock, .-SandiskProgTestBadBlock
2211	2398	.align 2
2212	2399	.global SandiskSetRRPara
	2400	+ .syntax unified
	2401	+ .arm
	2402	+ .fpu softvfp
2213	2403	.type SandiskSetRRPara, %function
2214	2404	SandiskSetRRPara:
2215	2405	.fnstart
2216	2406	@ args = 0, pretend = 0, frame = 0
2217	2407	@ frame_needed = 0, uses_anonymous_args = 0
2218		- stmfd sp!, {r3, r4, r5, lr}
2219		- .save {r3, r4, r5, lr}
2220	2408	mov r3, #239
2221		- mov r5, r0
	2409	+ push {r4, r5, r6, lr}
	2410	+ .save {r4, r5, r6, lr}
2222	2411	str r3, [r0, #8]
2223	2412	mov r3, #17
	2413	+ mov r5, r0
	2414	+ mov r4, r1
2224	2415	str r3, [r0, #4]
2225	2416	mov r0, #200
2226		- mov r4, r1
2227		- bl NandcDelayns
2228		- ldr r1, .L387
2229		- ldr r0, .L387+4
2230		- add r4, r4, r4, asl #2
2231		- ldr ip, .L387+8
2232		- sub lr, r1, #48
	2417	+ bl ndelay
	2418	+ ldr r1, .L403
	2419	+ add r4, r4, r4, lsl #2
	2420	+ ldr r0, .L403+4
2233	2421	mov r2, #0
2234		-.L380:
	2422	+ ldr ip, .L403+8
	2423	+ sub lr, r1, #45
	2424	+.L397:
2235	2425	ldrb r3, [r0] @ zero_extendqisi2
2236	2426	cmp r2, r3
2237		- bcs .L386
	2427	+ bcc .L400
	2428	+ mov r0, #0
	2429	+ pop {r4, r5, r6, lr}
	2430	+ b NandcWaitFlashReady
	2431	+.L400:
2238	2432	ldrb r3, [ip] @ zero_extendqisi2
2239	2433	cmp r3, #67
2240	2434	add r3, r2, r4
2241	2435	addeq r3, lr, r3
2242	2436	addne r3, r1, r3
2243		- add r2, r2, #1
2244	2437	ldrsb r3, [r3, #5]
	2438	+ add r2, r2, #1
2245	2439	str r3, [r5]
2246		- b .L380
2247		-.L386:
2248		- mov r0, #0
2249		- ldmfd sp!, {r3, r4, r5, lr}
2250		- b NandcWaitFlashReady
2251		-.L388:
	2440	+ b .L397
	2441	+.L404:
2252	2442	.align 2
2253		-.L387:
2254		- .word .LANCHOR1+3216
	2443	+.L403:
	2444	+ .word .LANCHOR1+301
2255	2445	.word g_maxRegNum
2256	2446	.word g_retryMode
2257	2447	.fnend
2258	2448	.size SandiskSetRRPara, .-SandiskSetRRPara
2259	2449	.align 2
2260	2450	.global micron_auto_read_calibration_config
	2451	+ .syntax unified
	2452	+ .arm
	2453	+ .fpu softvfp
2261	2454	.type micron_auto_read_calibration_config, %function
2262	2455	micron_auto_read_calibration_config:
2263	2456	.fnstart
2264	2457	@ args = 0, pretend = 0, frame = 0
2265	2458	@ frame_needed = 0, uses_anonymous_args = 0
2266		- stmfd sp!, {r3, r4, r5, lr}
2267		- .save {r3, r4, r5, lr}
2268		- mov r4, r0
2269		- mov r5, r1
	2459	+ push {r4, r5, r6, lr}
	2460	+ .save {r4, r5, r6, lr}
	2461	+ mov r5, r0
	2462	+ mov r6, r1
2270	2463	bl NandcWaitFlashReady
2271		- ldr r3, .L391
	2464	+ ldr r0, .L407
	2465	+ ldr r4, [r0, r5, lsl #3]
	2466	+ add r0, r0, r5, lsl #3
	2467	+ ldrb r3, [r0, #4] @ zero_extendqisi2
2272	2468	mov r0, #200
2273		- add r2, r3, r4, asl #3
2274		- ldrb r4, [r2, #16] @ zero_extendqisi2
2275		- ldr r3, [r2, #12]
2276		- add r4, r3, r4, asl #8
	2469	+ add r4, r4, r3, lsl #8
2277	2470	mov r3, #239
2278	2471	str r3, [r4, #2056]
2279	2472	mov r3, #150
2280	2473	str r3, [r4, #2052]
2281		- bl NandcDelayns
2282		- str r5, [r4, #2048]
	2474	+ bl ndelay
2283	2475	mov r3, #0
	2476	+ str r6, [r4, #2048]
2284	2477	str r3, [r4, #2048]
2285	2478	str r3, [r4, #2048]
2286	2479	str r3, [r4, #2048]
2287		- ldmfd sp!, {r3, r4, r5, pc}
2288		-.L392:
	2480	+ pop {r4, r5, r6, pc}
	2481	+.L408:
2289	2482	.align 2
2290		-.L391:
	2483	+.L407:
2291	2484	.word .LANCHOR0
2292	2485	.fnend
2293	2486	.size micron_auto_read_calibration_config, .-micron_auto_read_calibration_config
2294	2487	.align 2
2295	2488	.global FlashEraseSLc2KBlocks
	2489	+ .syntax unified
	2490	+ .arm
	2491	+ .fpu softvfp
2296	2492	.type FlashEraseSLc2KBlocks, %function
2297	2493	FlashEraseSLc2KBlocks:
2298	2494	.fnstart
2299	2495	@ args = 0, pretend = 0, frame = 8
2300	2496	@ frame_needed = 0, uses_anonymous_args = 0
2301		- stmfd sp!, {r4, r5, r6, r7, r8, r9, lr}
2302		- .save {r4, r5, r6, r7, r8, r9, lr}
	2497	+ push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, lr}
	2498	+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
	2499	+ .pad #16
2303	2500	mov r5, #0
2304		- ldr r8, .L405
2305		- .pad #20
2306		- sub sp, sp, #20
	2501	+ ldr r8, .L420
2307	2502	mov r6, r0
2308	2503	mov r9, r1
2309	2504	mov r7, r5
2310		-.L394:
	2505	+ ldr r10, .L420+4
	2506	+.L410:
2311	2507	cmp r7, r9
2312		- beq .L404
2313		- rsb r3, r7, r9
	2508	+ bne .L415
	2509	+ mov r0, #0
	2510	+ add sp, sp, #16
	2511	+ @ sp needed
	2512	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	2513	+.L415:
	2514	+ sub r3, r9, r7
2314	2515	add r2, sp, #8
2315		- add r0, r6, r5
2316		- mov r1, #0
2317	2516	uxtb r3, r3
	2517	+ mov r1, #0
	2518	+ add r0, r6, r5
2318	2519	str r3, [sp]
2319	2520	add r3, sp, #12
2320	2521	bl LogAddr2PhyAddr
2321		- ldrb r2, [r8, #3152] @ zero_extendqisi2
	2522	+ ldrb r2, [r8, #3156] @ zero_extendqisi2
2322	2523	ldr r3, [sp, #12]
2323		- cmp r3, r2
2324		- mvncs r3, #0
2325		- strcs r3, [r6, r5]
2326		- bcs .L396
	2524	+ cmp r2, r3
	2525	+ mvnls r3, #0
	2526	+ strls r3, [r6, r5]
	2527	+ bls .L412
2327	2528	add r2, r8, r3
2328		- add r3, r8, r3, asl #4
2329		- ldrb r4, [r2, #3156] @ zero_extendqisi2
2330		- strb r4, [r3, #3196]
	2529	+ add r3, r8, r3, lsl #4
	2530	+ ldrb r4, [r2, #3160] @ zero_extendqisi2
	2531	+ strb r4, [r3, #3200]
2331	2532	mov r0, r4
2332	2533	bl NandcWaitFlashReady
2333	2534	mov r0, r4
2334	2535	bl NandcFlashCs
2335	2536	mov r2, #0
2336		- mov r0, r4
2337	2537	ldr r1, [sp, #8]
	2538	+ mov r0, r4
2338	2539	bl FlashEraseCmd
2339	2540	mov r0, r4
2340	2541	bl NandcWaitFlashReady
2341	2542	mov r0, r4
2342	2543	ldr r1, [sp, #8]
2343	2544	bl FlashReadStatus
2344		- mov r2, #0
2345		- ldr r3, [sp, #8]
2346	2545	sbfx r0, r0, #0, #1
	2546	+ ldr r1, [sp, #8]
2347	2547	str r0, [r6, r5]
	2548	+ mov r2, #0
	2549	+ ldr r3, [r8, #40]
2348	2550	mov r0, r4
2349		- ldr r1, [r8, #4]
2350	2551	add r1, r1, r3
2351	2552	bl FlashEraseCmd
2352	2553	mov r0, r4
..	..	@@ -2359,387 +2560,431 @@
2359	2560	strne r3, [r6, r5]
2360	2561	ldr r3, [r6, r5]
2361	2562	cmn r3, #1
2362		- bne .L398
2363		- ldr r0, .L405+4
	2563	+ bne .L414
2364	2564	ldr r1, [sp, #8]
	2565	+ mov r0, r10
2365	2566	bl printk
2366		-.L398:
	2567	+.L414:
2367	2568	mov r0, r4
2368	2569	bl NandcFlashDeCs
2369		-.L396:
	2570	+.L412:
2370	2571	add r7, r7, #1
2371	2572	add r5, r5, #36
2372		- b .L394
2373		-.L404:
2374		- mov r0, #0
2375		- add sp, sp, #20
2376		- @ sp needed
2377		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, pc}
2378		-.L406:
	2573	+ b .L410
	2574	+.L421:
2379	2575	.align 2
2380		-.L405:
	2576	+.L420:
2381	2577	.word .LANCHOR0
2382	2578	.word .LC1
2383	2579	.fnend
2384	2580	.size FlashEraseSLc2KBlocks, .-FlashEraseSLc2KBlocks
2385	2581	.align 2
2386	2582	.global FlashEraseBlocks
	2583	+ .syntax unified
	2584	+ .arm
	2585	+ .fpu softvfp
2387	2586	.type FlashEraseBlocks, %function
2388	2587	FlashEraseBlocks:
2389	2588	.fnstart
2390		- @ args = 0, pretend = 0, frame = 16
	2589	+ @ args = 0, pretend = 0, frame = 8
2391	2590	@ frame_needed = 0, uses_anonymous_args = 0
2392		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	2591	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
2393	2592	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
2394	2593	mov r8, r2
2395		- ldr r4, .L442
2396		- .pad #28
2397		- sub sp, sp, #28
2398		- ldrb r5, [r4] @ zero_extendqisi2
	2594	+ ldr r4, .L455
	2595	+ .pad #20
	2596	+ sub sp, sp, #20
	2597	+ ldrb r5, [r4, #36] @ zero_extendqisi2
2399	2598	cmp r5, #0
2400		- beq .L425
	2599	+ moveq r9, r0
	2600	+ moveq r10, r1
	2601	+ beq .L424
2401	2602	mov r1, r2
2402	2603	bl FlashEraseSLc2KBlocks
2403		- b .L409
2404		-.L425:
2405		- ldr fp, .L442+4
2406		- mov r9, r0
2407		- mov r10, r1
2408		-.L408:
2409		- cmp r5, r8
2410		- bcs .L440
	2604	+.L422:
	2605	+ add sp, sp, #20
	2606	+ @ sp needed
	2607	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	2608	+.L433:
2411	2609	mov r3, #36
2412		- mov r1, #0
	2610	+ add r2, sp, #8
2413	2611	mul r6, r3, r5
2414		- add r2, sp, #16
2415		- add r3, r9, r6
2416		- str r3, [sp, #12]
2417		- rsb r3, r5, r8
2418		- ldr r0, [sp, #12]
	2612	+ sub r3, r8, r5
2419	2613	uxtb r3, r3
	2614	+ mov r1, #0
2420	2615	str r3, [sp]
2421		- add r3, sp, #20
	2616	+ add r3, sp, #12
	2617	+ add fp, r9, r6
	2618	+ mov r0, fp
2422	2619	bl LogAddr2PhyAddr
2423		- ldrb r3, [r4, #3152] @ zero_extendqisi2
	2620	+ ldrb r3, [r4, #3156] @ zero_extendqisi2
2424	2621	mov r7, r0
2425		- ldr r0, [sp, #20]
2426		- cmp r0, r3
2427		- mvncs r3, #0
2428		- strcs r3, [r9, r6]
2429		- bcs .L411
2430		- ldrb r3, [fp, #-1874] @ zero_extendqisi2
	2622	+ ldr r0, [sp, #12]
	2623	+ cmp r3, r0
	2624	+ mvnls r3, #0
	2625	+ strls r3, [r9, r6]
	2626	+ bls .L427
	2627	+ ldr r3, .L455+4
	2628	+ ldrb r3, [r3, #-1870] @ zero_extendqisi2
2431	2629	cmp r3, #0
2432		- add r3, r4, r0, asl #4
2433		- ldr r3, [r3, #3204]
	2630	+ add r3, r4, r0, lsl #4
2434	2631	moveq r7, #0
	2632	+ ldr r3, [r3, #3208]
2435	2633	cmp r3, #0
2436		- beq .L413
	2634	+ beq .L429
2437	2635	uxtb r0, r0
2438	2636	bl FlashWaitCmdDone
2439		-.L413:
2440		- ldr r2, [sp, #20]
	2637	+.L429:
	2638	+ ldr r2, [sp, #12]
2441	2639	cmp r7, #0
2442		- ldr r0, [sp, #12]
2443		- addne ip, r6, #36
2444		- addne ip, r9, ip
2445		- mov r3, r2, asl #4
	2640	+ addne r6, r6, #36
	2641	+ mov r0, #0
	2642	+ addne r6, r9, r6
	2643	+ lsl r3, r2, #4
2446	2644	add r2, r4, r2
2447	2645	add r1, r4, r3
2448	2646	add r3, r4, r3
2449		- ldrb r6, [r2, #3156] @ zero_extendqisi2
	2647	+ str r0, [r1, #3212]
	2648	+ ldr r0, [sp, #8]
	2649	+ strne r6, [r1, #3212]
	2650	+ ldrb r6, [r2, #3160] @ zero_extendqisi2
2450	2651	str r0, [r1, #3204]
2451		- mov r0, #0
2452		- str r0, [r1, #3208]
2453		- ldr r0, [sp, #16]
2454		- strne ip, [r1, #3208]
2455		- strb r6, [r3, #3196]
2456		- str r0, [r1, #3200]
	2652	+ str fp, [r1, #3208]
2457	2653	mov r0, r6
	2654	+ strb r6, [r3, #3200]
2458	2655	bl NandcFlashCs
2459	2656	cmp r10, #1
2460	2657	mov r0, r6
2461		- bne .L415
2462		- ldr r3, .L442+4
2463		- ldrb r3, [r3, #-2744] @ zero_extendqisi2
	2658	+ bne .L431
	2659	+ ldr r3, .L455+4
	2660	+ ldrb r3, [r3, #-2740] @ zero_extendqisi2
2464	2661	cmp r3, #0
2465		- beq .L415
	2662	+ beq .L431
2466	2663	bl flash_enter_slc_mode
2467		- b .L416
2468		-.L415:
2469		- bl flash_exit_slc_mode
2470		-.L416:
2471		- ldr r3, [sp, #20]
	2664	+.L432:
	2665	+ ldr r3, [sp, #12]
2472	2666	mov r0, r6
2473		- ldr r1, [sp, #16]
	2667	+ ldr r1, [sp, #8]
2474	2668	add r5, r5, r7
2475		- add r3, r4, r3, asl #2
2476		- ldr r2, [r3, #3164]
	2669	+ add r3, r4, r3, lsl #2
	2670	+ ldr r2, [r3, #3168]
2477	2671	adds r2, r2, #0
2478	2672	movne r2, #1
2479	2673	bl FlashWaitReadyEN
2480		- mov r0, r6
2481	2674	mov r2, r7
2482		- ldr r1, [sp, #16]
	2675	+ ldr r1, [sp, #8]
	2676	+ mov r0, r6
2483	2677	bl FlashEraseCmd
2484	2678	mov r0, r6
2485	2679	bl NandcFlashDeCs
2486		-.L411:
	2680	+.L427:
2487	2681	add r5, r5, #1
2488		- b .L408
2489		-.L440:
2490		- ldr r6, .L442+4
	2682	+.L424:
	2683	+ cmp r5, r8
	2684	+ bcc .L433
	2685	+ ldr r6, .L455+4
2491	2686	mov r5, #0
2492		- ldr r7, .L442+8
2493		-.L418:
2494		- ldrb r3, [r4, #3152] @ zero_extendqisi2
	2687	+ ldr r7, .L455+8
	2688	+.L434:
	2689	+ ldrb r3, [r4, #3156] @ zero_extendqisi2
2495	2690	cmp r5, r3
2496		- bcs .L441
	2691	+ bcc .L436
	2692	+ ldr r3, .L455+4
	2693	+ ldr r3, [r3, #-1868]
	2694	+ cmp r3, #0
	2695	+ bne .L437
	2696	+.L438:
	2697	+ mov r0, #0
	2698	+ b .L422
	2699	+.L431:
	2700	+ bl flash_exit_slc_mode
	2701	+ b .L432
	2702	+.L436:
2497	2703	uxtb r0, r5
2498	2704	bl FlashWaitCmdDone
2499	2705	cmp r10, #1
2500		- bne .L419
2501		- ldrb r3, [r6, #-2744] @ zero_extendqisi2
	2706	+ bne .L435
	2707	+ ldrb r3, [r6, #-2740] @ zero_extendqisi2
2502	2708	cmp r3, #0
2503		- beq .L419
2504		- ldrb r0, [r7, r5, asl #4] @ zero_extendqisi2
	2709	+ beq .L435
	2710	+ ldrb r0, [r7, r5, lsl #4] @ zero_extendqisi2
2505	2711	bl flash_exit_slc_mode
2506		-.L419:
	2712	+.L435:
2507	2713	add r5, r5, #1
2508		- b .L418
2509		-.L441:
2510		- ldr r3, .L442+4
2511		- ldr r3, [r3, #-1872]
2512		- cmp r3, #0
2513		- bne .L421
2514		-.L423:
2515		- mov r0, #0
2516		- b .L409
2517		-.L421:
2518		- ldr r3, .L442+12
	2714	+ b .L434
	2715	+.L437:
	2716	+ ldr r3, .L455+12
2519	2717	ldrb r3, [r3] @ zero_extendqisi2
2520	2718	cmp r3, #69
2521		- bne .L423
2522		- mov r3, #0
2523		- mov r2, #36
2524		- mov r1, r3
2525		-.L422:
	2719	+ moveq r3, #0
	2720	+ moveq r2, #36
	2721	+ moveq r1, r3
	2722	+ bne .L438
	2723	+.L439:
2526	2724	cmp r3, r8
2527		- beq .L423
	2725	+ beq .L438
2528	2726	mul r0, r2, r3
2529	2727	add r3, r3, #1
2530	2728	str r1, [r9, r0]
2531		- b .L422
2532		-.L409:
2533		- add sp, sp, #28
2534		- @ sp needed
2535		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
2536		-.L443:
	2729	+ b .L439
	2730	+.L456:
2537	2731	.align 2
2538		-.L442:
	2732	+.L455:
2539	2733	.word .LANCHOR0
2540	2734	.word .LANCHOR2
2541		- .word .LANCHOR0+3196
	2735	+ .word .LANCHOR0+3200
2542	2736	.word IDByte
2543	2737	.fnend
2544	2738	.size FlashEraseBlocks, .-FlashEraseBlocks
2545	2739	.align 2
2546	2740	.global HynixGetReadRetryDefault
	2741	+ .syntax unified
	2742	+ .arm
	2743	+ .fpu softvfp
2547	2744	.type HynixGetReadRetryDefault, %function
2548	2745	HynixGetReadRetryDefault:
2549	2746	.fnstart
2550		- @ args = 0, pretend = 0, frame = 40
	2747	+ @ args = 0, pretend = 0, frame = 48
2551	2748	@ frame_needed = 0, uses_anonymous_args = 0
2552		- ldr r3, .L553
	2749	+ ldr r3, .L574
2553	2750	mvn r2, #83
2554		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	2751	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
2555	2752	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
2556	2753	mov r4, r0
2557	2754	cmp r4, #2
2558		- strb r0, [r3, #-2732]
2559		- strb r2, [r3, #-2728]
2560		- mvn r0, #82
2561	2755	mvn r1, #81
	2756	+ .pad #52
	2757	+ sub sp, sp, #52
	2758	+ strb r0, [r3, #-2728]
	2759	+ mvn r0, #82
	2760	+ strb r2, [r3, #-2724]
2562	2761	mvn r2, #80
2563		- .pad #44
2564		- sub sp, sp, #44
2565		- strb r0, [r3, #-2727]
2566		- strb r1, [r3, #-2726]
2567		- strb r2, [r3, #-2725]
2568		- bne .L445
2569		- mvn r2, #88
2570		- strb r2, [r3, #-2728]
2571		- ldr r3, .L553+4
2572		- mvn r2, #8
2573		- mov r5, #7
2574		- strb r2, [r3, #3401]
2575		- b .L506
2576		-.L445:
2577		- cmp r4, #3
2578		- bne .L447
2579		- mvn r2, #79
2580		- strb r2, [r3, #-2728]
2581		- mvn r2, #78
2582		- strb r2, [r3, #-2727]
2583		- mvn r2, #77
2584		- strb r2, [r3, #-2726]
2585		- mvn r2, #76
2586		- strb r2, [r3, #-2725]
2587		- mvn r2, #75
2588		- strb r2, [r3, #-2724]
2589		- mvn r2, #74
2590		- strb r2, [r3, #-2723]
2591		- mvn r2, #73
2592		- strb r2, [r3, #-2722]
2593		- mvn r2, #72
2594		- b .L547
2595		-.L447:
2596		- cmp r4, #4
2597		- bne .L448
2598		- mvn ip, #51
2599	2762	strb r0, [r3, #-2723]
2600		- strb ip, [r3, #-2728]
2601		- mvn ip, #64
2602	2763	strb r1, [r3, #-2722]
2603		- strb ip, [r3, #-2727]
2604		- mvn ip, #85
2605		- strb ip, [r3, #-2726]
2606		- mvn ip, #84
2607		- strb ip, [r3, #-2725]
2608		- mvn ip, #50
2609		- strb ip, [r3, #-2724]
2610		-.L547:
2611		- mov r5, #8
2612	2764	strb r2, [r3, #-2721]
2613		- mov r6, r5
2614		- b .L446
2615		-.L448:
2616		- cmp r4, #5
2617		- bne .L449
2618		- mov r2, #56
2619		- mov r5, #8
2620		- strb r2, [r3, #-2728]
2621		- mov r2, #57
2622		- strb r2, [r3, #-2727]
2623		- mov r2, #58
2624		- strb r2, [r3, #-2726]
2625		- mov r2, #59
2626		- strb r2, [r3, #-2725]
2627		- b .L506
2628		-.L449:
2629		- cmp r4, #6
2630		- bne .L450
2631		- mov r2, #14
2632		- mov r5, #12
2633		- strb r2, [r3, #-2728]
2634		- mov r2, #15
2635		- strb r2, [r3, #-2727]
2636		- mov r2, #16
2637		- strb r2, [r3, #-2726]
2638		- mov r2, #17
2639		- strb r2, [r3, #-2725]
2640		- b .L506
2641		-.L450:
2642		- cmp r4, #7
2643		- bne .L451
2644		- mvn r2, #79
2645		- mov r5, #12
2646		- strb r2, [r3, #-2728]
2647		- mov r6, #10
2648		- mvn r2, #78
2649		- strb r2, [r3, #-2727]
2650		- mvn r2, #77
2651		- strb r2, [r3, #-2726]
2652		- mvn r2, #76
2653		- strb r2, [r3, #-2725]
2654		- mvn r2, #75
2655		- strb r2, [r3, #-2724]
2656		- mvn r2, #74
2657		- strb r2, [r3, #-2723]
2658		- mvn r2, #73
2659		- strb r2, [r3, #-2722]
2660		- mvn r2, #72
2661		- strb r2, [r3, #-2721]
2662		- mvn r2, #43
2663		- strb r2, [r3, #-2720]
2664		- mvn r2, #42
2665		- strb r2, [r3, #-2719]
2666		- b .L446
2667		-.L451:
2668		- cmp r4, #8
	2765	+ bne .L458
	2766	+ mvn r2, #88
2669	2767	mov r5, #7
2670		- bne .L506
2671		- mov r2, #6
2672		- strb r5, [r3, #-2727]
2673		- strb r2, [r3, #-2728]
2674		- mov r5, #50
2675		- mov r2, #9
2676		- strb r4, [r3, #-2726]
2677		- strb r2, [r3, #-2725]
2678		- mov r6, #5
2679		- mov r2, #10
2680	2768	strb r2, [r3, #-2724]
2681		- b .L446
2682		-.L506:
	2769	+ mvn r2, #8
	2770	+ ldr r3, .L574+4
	2771	+ strb r2, [r3, #3397]
	2772	+.L523:
2683	2773	mov r6, #4
2684		-.L446:
	2774	+ b .L459
	2775	+.L458:
	2776	+ cmp r4, #3
	2777	+ bne .L460
	2778	+ mvn r2, #79
	2779	+ strb r2, [r3, #-2724]
	2780	+ mvn r2, #78
	2781	+ strb r2, [r3, #-2723]
	2782	+ mvn r2, #77
	2783	+ strb r2, [r3, #-2722]
	2784	+ mvn r2, #76
	2785	+ strb r2, [r3, #-2721]
	2786	+ mvn r2, #75
	2787	+ strb r2, [r3, #-2720]
	2788	+ mvn r2, #74
	2789	+ strb r2, [r3, #-2719]
	2790	+ mvn r2, #73
	2791	+ strb r2, [r3, #-2718]
	2792	+ mvn r2, #72
	2793	+.L568:
	2794	+ mov r5, #8
	2795	+ strb r2, [r3, #-2717]
	2796	+ mov r6, r5
	2797	+.L459:
2685	2798	sub r3, r4, #1
2686	2799	cmp r3, #1
2687		- bhi .L543
2688		- ldr r10, .L553+8
2689		- mov r9, #0
2690		-.L452:
2691		- ldr r3, .L553+12
2692		- uxtb r2, r9
2693		- ldrb r1, [r3, #3152] @ zero_extendqisi2
2694		- cmp r1, r2
2695		- bls .L459
2696		- add r2, r3, r2
2697		- ldr r8, .L553+16
2698		- ldrb r2, [r2, #3156] @ zero_extendqisi2
2699		- add r3, r3, r2, asl #3
2700		- add r4, r8, r2, asl #6
2701		- add r4, r4, #20
2702		- add r8, r8, #3
2703		- ldrb r7, [r3, #16] @ zero_extendqisi2
2704		- ldr r1, [r3, #12]
2705		- mov fp, r4
2706		- mov r2, r4
2707		- add r7, r1, r7, asl #8
2708		- mov r1, #55
2709		-.L454:
2710		- str r1, [r7, #2056]
2711		- mov r0, #80
2712		- ldrb r3, [r8, #1]! @ zero_extendqisi2
	2800	+ movls r9, #0
	2801	+ ldrls r10, .L574+8
	2802	+ bls .L466
	2803	+ sub r3, r4, #3
	2804	+ cmp r3, #5
	2805	+ bhi .L473
	2806	+ smulbb r3, r6, r5
	2807	+ asr r2, r3, #1
	2808	+ lsl r3, r3, #4
	2809	+ str r3, [sp, #44]
	2810	+ lsl r3, r2, #2
2713	2811	str r2, [sp, #4]
2714		- str r1, [sp]
2715		- str r3, [r7, #2052]
2716		- bl NandcDelayns
2717		- ldr r3, [r7, #2048]
2718		- ldr r2, [sp, #4]
2719		- ldr r1, [sp]
2720		- strb r3, [r2], #1
2721		- rsb r3, r4, r2
2722		- uxtb r3, r3
2723		- cmp r3, r6
2724		- bcc .L454
	2812	+ str r3, [sp, #36]
	2813	+ lsl r3, r2, #1
	2814	+ str r3, [sp, #24]
	2815	+ mov r3, #0
	2816	+.L573:
	2817	+ str r3, [sp, #20]
	2818	+ ldrb r3, [sp, #20] @ zero_extendqisi2
	2819	+ str r3, [sp, #8]
	2820	+ ldr r3, .L574+12
	2821	+ ldr r2, [sp, #8]
	2822	+ ldrb r3, [r3, #3156] @ zero_extendqisi2
	2823	+ cmp r3, r2
	2824	+ bls .L473
	2825	+ ldr r2, [sp, #8]
	2826	+ ldr r3, .L574+12
	2827	+ add r3, r3, r2
	2828	+ ldrb r9, [r3, #3160] @ zero_extendqisi2
	2829	+ ldr r3, .L574+12
	2830	+ mov r0, r9
	2831	+ ldr fp, [r3, r9, lsl #3]
	2832	+ add r3, r3, r9, lsl #3
	2833	+ ldrb r10, [r3, #4] @ zero_extendqisi2
	2834	+ mov r3, #255
	2835	+ add r7, fp, r10, lsl #8
	2836	+ str r3, [r7, #2056]
	2837	+ bl NandcWaitFlashReady
	2838	+ cmp r4, #7
	2839	+ bne .L475
	2840	+ ldr r3, .L574+16
	2841	+ mov r0, #160
	2842	+ mla r0, r0, r9, r3
	2843	+ add r3, r0, #20
	2844	+.L569:
	2845	+ str r3, [sp, #16]
	2846	+ cmp r4, #4
	2847	+ add r3, fp, r10, lsl #8
	2848	+ mov r2, #54
	2849	+ str r2, [r3, #2056]
	2850	+ bne .L478
	2851	+ mov r2, #255
	2852	+ str r2, [r3, #2052]
	2853	+ mov r2, #64
	2854	+ str r2, [r3, #2048]
	2855	+ mov r2, #204
	2856	+.L570:
	2857	+ str r2, [r3, #2052]
	2858	+ mov r2, #77
	2859	+ b .L571
	2860	+.L460:
	2861	+ cmp r4, #4
	2862	+ bne .L461
	2863	+ mvn ip, #51
	2864	+ strb r0, [r3, #-2719]
	2865	+ strb ip, [r3, #-2724]
	2866	+ mvn ip, #64
	2867	+ strb ip, [r3, #-2723]
	2868	+ mvn ip, #85
	2869	+ strb ip, [r3, #-2722]
	2870	+ mvn ip, #84
	2871	+ strb ip, [r3, #-2721]
	2872	+ mvn ip, #50
	2873	+ strb ip, [r3, #-2720]
	2874	+ strb r1, [r3, #-2718]
	2875	+ b .L568
	2876	+.L461:
	2877	+ cmp r4, #5
	2878	+ bne .L462
	2879	+ mov r2, #56
	2880	+ mov r5, #8
	2881	+ strb r2, [r3, #-2724]
	2882	+ mov r2, #57
	2883	+ strb r2, [r3, #-2723]
	2884	+ mov r2, #58
	2885	+ strb r2, [r3, #-2722]
	2886	+ mov r2, #59
	2887	+ strb r2, [r3, #-2721]
	2888	+ b .L523
	2889	+.L462:
	2890	+ cmp r4, #6
	2891	+ bne .L463
	2892	+ mov r2, #14
	2893	+ mov r5, #12
	2894	+ strb r2, [r3, #-2724]
	2895	+ mov r2, #15
	2896	+ strb r2, [r3, #-2723]
	2897	+ mov r2, #16
	2898	+ strb r2, [r3, #-2722]
	2899	+ mov r2, #17
	2900	+ strb r2, [r3, #-2721]
	2901	+ b .L523
	2902	+.L463:
	2903	+ cmp r4, #7
	2904	+ bne .L464
	2905	+ mvn r2, #79
	2906	+ mov r5, #12
	2907	+ strb r2, [r3, #-2724]
	2908	+ mvn r2, #78
	2909	+ strb r2, [r3, #-2723]
	2910	+ mvn r2, #77
	2911	+ strb r2, [r3, #-2722]
	2912	+ mvn r2, #76
	2913	+ strb r2, [r3, #-2721]
	2914	+ mvn r2, #75
	2915	+ strb r2, [r3, #-2720]
	2916	+ mvn r2, #74
	2917	+ strb r2, [r3, #-2719]
	2918	+ mvn r2, #73
	2919	+ strb r2, [r3, #-2718]
	2920	+ mvn r2, #72
	2921	+ strb r2, [r3, #-2717]
	2922	+ mvn r2, #43
	2923	+ strb r2, [r3, #-2716]
	2924	+ mvn r2, #42
	2925	+ strb r2, [r3, #-2715]
	2926	+ mov r6, #10
	2927	+ b .L459
	2928	+.L464:
	2929	+ cmp r4, #8
	2930	+ mov r5, #7
	2931	+ bne .L523
	2932	+ mov r2, #6
	2933	+ strb r5, [r3, #-2723]
	2934	+ strb r2, [r3, #-2724]
	2935	+ mov r2, #9
	2936	+ strb r2, [r3, #-2721]
	2937	+ mov r2, #10
	2938	+ strb r4, [r3, #-2722]
	2939	+ mov r5, #50
	2940	+ strb r2, [r3, #-2720]
	2941	+ mov r6, #5
	2942	+ b .L459
	2943	+.L472:
	2944	+ add r2, r3, r2
	2945	+ ldr r4, .L574+8
	2946	+ ldrb r2, [r2, #3160] @ zero_extendqisi2
	2947	+ mov r7, #0
	2948	+ mov fp, #55
	2949	+ ldr r8, [r3, r2, lsl #3]
	2950	+ add r3, r3, r2, lsl #3
	2951	+ add r4, r4, r2, lsl #6
	2952	+ ldrb r3, [r3, #4] @ zero_extendqisi2
	2953	+ add r4, r4, #20
	2954	+ add r8, r8, r3, lsl #8
	2955	+.L467:
	2956	+ add r3, r10, r7
	2957	+ str fp, [r8, #2056]
	2958	+ ldrb r3, [r3, #4] @ zero_extendqisi2
	2959	+ mov r0, #80
	2960	+ str r3, [r8, #2052]
	2961	+ bl ndelay
	2962	+ ldr r3, [r8, #2048]
	2963	+ strb r3, [r4, r7]
	2964	+ add r7, r7, #1
	2965	+ uxtb r3, r7
	2966	+ cmp r6, r3
	2967	+ bhi .L467
	2968	+ ldr lr, .L574+20
	2969	+ mov r1, r4
2725	2970	mov r2, #0
2726		-.L455:
2727		- add r0, r10, r2
	2971	+.L470:
2728	2972	mov r3, #1
2729		-.L456:
2730		- ldrb r1, [r0, r3, asl #2] @ zero_extendqisi2
2731		- ldrb ip, [fp] @ zero_extendqisi2
2732		- add r1, r1, ip
2733		- strb r1, [fp, r3, asl #3]
	2973	+ add ip, lr, r2
	2974	+.L469:
	2975	+ ldrb r0, [ip, r3, lsl #2] @ zero_extendqisi2
	2976	+ ldrb r7, [r1] @ zero_extendqisi2
	2977	+ add r0, r0, r7
	2978	+ strb r0, [r1, r3, lsl #3]
2734	2979	add r3, r3, #1
2735	2980	cmp r3, #7
2736		- bne .L456
	2981	+ bne .L469
2737	2982	add r2, r2, #1
2738		- add fp, fp, #1
	2983	+ add r1, r1, #1
2739	2984	cmp r2, #4
2740		- bne .L455
2741		- mov r3, #0
	2985	+ bne .L470
2742	2986	add r9, r9, #1
	2987	+ mov r3, #0
2743	2988	strb r3, [r4, #16]
2744	2989	strb r3, [r4, #24]
2745	2990	strb r3, [r4, #32]
..	..	@@ -2747,378 +2992,329 @@
2747	2992	strb r3, [r4, #48]
2748	2993	strb r3, [r4, #41]
2749	2994	strb r3, [r4, #49]
2750		- b .L452
2751		-.L543:
2752		- sub r3, r4, #3
2753		- cmp r3, #5
2754		- bhi .L459
2755		- smulbb r8, r6, r5
2756		- ldr fp, .L553
2757		- mov r3, r8, asl #4
2758		- mov r8, r8, asr #1
2759		- str r3, [sp, #36]
2760		- mov r3, r8, asl #1
2761		- str r3, [sp, #4]
2762		- mov r3, #0
2763		- str r3, [sp, #16]
2764		-.L460:
2765		- ldrb r3, [sp, #16] @ zero_extendqisi2
2766		- str r3, [sp, #12]
2767		- ldr r3, .L553+12
2768		- ldr r2, [sp, #12]
2769		- ldrb r3, [r3, #3152] @ zero_extendqisi2
2770		- cmp r3, r2
2771		- bhi .L504
2772		-.L459:
2773		- ldr r3, .L553
2774		- strb r6, [r3, #-2731]
2775		- strb r5, [r3, #-2730]
2776		- add sp, sp, #44
	2995	+.L466:
	2996	+ ldr r3, .L574+12
	2997	+ uxtb r2, r9
	2998	+ ldrb r1, [r3, #3156] @ zero_extendqisi2
	2999	+ cmp r1, r2
	3000	+ bhi .L472
	3001	+.L473:
	3002	+ ldr r3, .L574
	3003	+ strb r6, [r3, #-2727]
	3004	+ strb r5, [r3, #-2726]
	3005	+ add sp, sp, #52
2777	3006	@ sp needed
2778		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
2779		-.L504:
2780		- ldr r2, [sp, #12]
2781		- ldr r3, .L553+12
2782		- add r3, r3, r2
2783		- ldrb r10, [r3, #3156] @ zero_extendqisi2
2784		- ldr r3, .L553+12
2785		- add r3, r3, r10, asl #3
2786		- mov r0, r10
2787		- ldr r8, [r3, #12]
2788		- ldrb r3, [r3, #16] @ zero_extendqisi2
2789		- mov r9, r3, asl #8
2790		- str r3, [sp, #8]
2791		- add r7, r8, r9
2792		- mov r3, #255
2793		- str r3, [r7, #2056]
2794		- bl NandcWaitFlashReady
2795		- cmp r4, #7
2796		- ldreq r7, .L553+16
2797		- moveq r3, #160
2798		- mlaeq r7, r3, r10, r7
2799		- addeq r3, r7, #28
2800		- beq .L548
2801		-.L461:
	3007	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	3008	+.L475:
2802	3009	cmp r4, #8
2803		- beq .L463
2804		- ldr r7, .L553+16
2805		- add r7, r7, r10, asl #6
2806		- add r3, r7, #20
2807		-.L548:
2808		- str r3, [sp, #20]
2809		- cmp r4, #4
2810		- add r3, r8, r9
2811		- mov r2, #54
2812		- str r2, [r3, #2056]
2813		- bne .L464
2814		- mov r2, #255
2815		- str r2, [r3, #2052]
2816		- mov r2, #64
2817		- str r2, [r3, #2048]
2818		- mov r2, #204
2819		- b .L549
2820		-.L464:
	3010	+ beq .L477
	3011	+ ldr r3, .L574+16
	3012	+ add r0, r3, r9, lsl #6
	3013	+ add r3, r0, #12
	3014	+ b .L569
	3015	+.L478:
2821	3016	sub r2, r4, #5
2822	3017	cmp r2, #1
2823		- ldrlsb r2, [fp, #-2728] @ zero_extendqisi2
2824		- strls r2, [r3, #2052]
2825		- movls r2, #82
2826		- bls .L550
	3018	+ bhi .L480
	3019	+ ldr r2, .L574
	3020	+ ldrb r2, [r2, #-2724] @ zero_extendqisi2
	3021	+ str r2, [r3, #2052]
	3022	+ mov r2, #82
	3023	+.L571:
	3024	+ str r2, [r3, #2048]
	3025	+.L479:
	3026	+ add r3, fp, r10, lsl #8
	3027	+ mov r2, #22
	3028	+ cmp r4, #6
	3029	+ str r2, [r3, #2056]
	3030	+ mov r2, #23
	3031	+ str r2, [r3, #2056]
	3032	+ mov r2, #4
	3033	+ str r2, [r3, #2056]
	3034	+ mov r2, #25
	3035	+ str r2, [r3, #2056]
	3036	+ mov r2, #0
	3037	+ str r2, [r3, #2056]
	3038	+ str r2, [r3, #2052]
	3039	+ str r2, [r3, #2052]
	3040	+ moveq r2, #31
	3041	+ str r2, [r3, #2052]
	3042	+ mov r2, #2
	3043	+ str r2, [r3, #2052]
	3044	+ mov r2, #0
	3045	+ str r2, [r3, #2052]
	3046	+.L522:
	3047	+ add r3, fp, r10, lsl #8
	3048	+ mov r2, #48
	3049	+ mov r0, r9
	3050	+ str r2, [r3, #2056]
	3051	+ bl NandcWaitFlashReady
	3052	+ sub r3, r4, #5
	3053	+ cmp r4, #8
	3054	+ cmpne r3, #1
	3055	+ str r3, [sp, #40]
	3056	+ movls r2, #16
	3057	+ bls .L483
2827	3058	cmp r4, #7
2828		- bne .L465
	3059	+ moveq r2, #32
	3060	+ movne r2, #2
	3061	+.L483:
	3062	+ ldr r3, .L574
	3063	+ sub r2, r2, #1
	3064	+ add ip, fp, r10, lsl #8
	3065	+ ldr r3, [r3, #-1864]
	3066	+ str ip, [sp]
	3067	+ sub r1, r3, #1
	3068	+ uxtab r2, r3, r2
	3069	+ mov r0, r1
	3070	+.L484:
	3071	+ ldr ip, [sp]
	3072	+ ldr ip, [ip, #2048]
	3073	+ strb ip, [r0, #1]!
	3074	+ cmp r2, r0
	3075	+ bne .L484
	3076	+ cmp r4, #8
	3077	+ bne .L485
	3078	+ mov r2, #0
	3079	+.L487:
	3080	+ ldrb r0, [r3, r2, lsl #2] @ zero_extendqisi2
	3081	+ uxtb r1, r2
	3082	+ cmp r0, #50
	3083	+ beq .L486
	3084	+ add r0, r3, r2, lsl #2
	3085	+ ldrb r0, [r0, #1] @ zero_extendqisi2
	3086	+ cmp r0, #5
	3087	+ beq .L486
	3088	+ add r2, r2, #1
	3089	+ cmp r2, #8
	3090	+ bne .L487
	3091	+.L488:
	3092	+ mov r1, #0
	3093	+ ldr r0, .L574+24
	3094	+ bl printk
	3095	+.L490:
	3096	+ b .L490
	3097	+.L480:
	3098	+ cmp r4, #7
	3099	+ bne .L479
2829	3100	mov r2, #174
2830	3101	str r2, [r3, #2052]
2831	3102	mov r2, #0
2832	3103	str r2, [r3, #2048]
2833	3104	mov r2, #176
2834		-.L549:
2835		- str r2, [r3, #2052]
2836		- mov r2, #77
2837		-.L550:
2838		- str r2, [r3, #2048]
2839		-.L465:
2840		- add r9, r8, r9
2841		- cmp r4, #6
2842		- mov r3, #22
2843		- str r3, [r9, #2056]
2844		- mov r3, #23
2845		- str r3, [r9, #2056]
2846		- mov r3, #4
2847		- str r3, [r9, #2056]
2848		- mov r3, #25
2849		- str r3, [r9, #2056]
2850		- mov r3, #0
2851		- str r3, [r9, #2056]
2852		- str r3, [r9, #2052]
2853		- str r3, [r9, #2052]
2854		- moveq r3, #31
2855		- str r3, [r9, #2052]
2856		- mov r3, #2
2857		- str r3, [r9, #2052]
2858		- mov r3, #0
2859		- str r3, [r9, #2052]
2860		-.L505:
2861		- ldr r3, [sp, #8]
2862		- mov r2, #48
2863		- mov r0, r10
2864		- add r3, r8, r3, asl #8
2865		- str r2, [r3, #2056]
2866		- bl NandcWaitFlashReady
2867		- sub r3, r4, #5
2868		- cmp r3, #1
2869		- movhi r3, #0
2870		- movls r3, #1
2871		- str r3, [sp, #24]
2872		- sub r3, r4, #8
2873		- clz r3, r3
2874		- mov r3, r3, lsr #5
2875		- str r3, [sp]
2876		- ldr r2, [sp]
2877		- ldr r3, [sp, #24]
2878		- orrs r3, r3, r2
2879		- movne ip, #16
2880		- bne .L469
2881		- cmp r4, #7
2882		- movne ip, #2
2883		- moveq ip, #32
2884		-.L469:
2885		- ldr r2, [sp, #8]
2886		- ldr r3, [fp, #-1868]
2887		- add r1, r8, r2, asl #8
2888		- mov r0, r3
2889		-.L470:
2890		- ldr r2, [r1, #2048]
2891		- strb r2, [r0], #1
2892		- rsb r2, r3, r0
2893		- uxtb r2, r2
2894		- cmp r2, ip
2895		- bcc .L470
2896		- ldr r2, [sp]
2897		- cmp r2, #0
2898		- beq .L471
2899		- mov r2, #0
2900		-.L473:
2901		- ldrb ip, [r3, r2, asl #2] @ zero_extendqisi2
2902		- uxtb r0, r2
2903		- cmp ip, #50
2904		- beq .L472
2905		- add ip, r3, r2, asl #2
2906		- ldrb ip, [ip, #1] @ zero_extendqisi2
2907		- cmp ip, #5
2908		- beq .L472
2909		- add r2, r2, #1
2910		- cmp r2, #8
2911		- bne .L473
2912		- b .L474
2913		-.L472:
2914		- cmp r0, #6
2915		- bls .L475
2916		-.L474:
2917		- ldr r0, .L553+20
2918		- mov r1, #0
2919		- bl printk
2920		-.L476:
2921		- b .L476
2922		-.L471:
2923		- cmp r4, #7
2924		- bne .L477
2925		- ldr r2, [sp]
2926		-.L479:
2927		- ldrb ip, [r3, r2, asl #2] @ zero_extendqisi2
2928		- uxtb r0, r2
2929		- cmp ip, #12
2930		- beq .L478
2931		- add ip, r3, r2, asl #2
2932		- ldrb ip, [ip, #1] @ zero_extendqisi2
2933		- cmp ip, #10
2934		- beq .L478
2935		- add r2, r2, #1
2936		- cmp r2, #8
2937		- bne .L479
2938		- b .L480
2939		-.L478:
2940		- cmp r0, #7
2941		- bne .L475
2942		-.L480:
2943		- ldr r0, .L553+20
2944		- mov r1, #0
2945		- bl printk
2946		-.L481:
2947		- b .L481
2948		-.L477:
2949		- cmp r4, #6
2950		- bne .L475
2951		- sub r2, r3, #1
2952		- add r3, r3, #7
2953		-.L482:
2954		- ldrb r0, [r2, #1]! @ zero_extendqisi2
2955		- cmp r0, #12
2956		- beq .L475
2957		- ldrb r0, [r2, #8] @ zero_extendqisi2
2958		- cmp r0, #4
2959		- beq .L475
2960		- cmp r2, r3
2961		- bne .L482
2962		- ldr r0, .L553+20
2963		- mov r1, #0
2964		- bl printk
2965		-.L484:
2966		- b .L484
2967		-.L475:
2968		- ldr r2, [fp, #-1868]
2969		- ldr r0, [sp, #36]
2970		- add r0, r2, r0
2971		- mov r3, r2
2972		-.L485:
2973		- cmp r3, r0
2974		- ldrne ip, [r1, #2048]
2975		- strneb ip, [r3], #1
2976		- bne .L485
2977		-.L552:
2978		- ldr r3, .L553
2979		- mov r0, #8
2980		- ldr r1, [sp, #4]
2981		- ldr r3, [r3, #-1868]
2982		- add r1, r3, r1
2983		- str r1, [sp, #28]
2984		-.L488:
2985		- ldr ip, [sp, #4]
2986		- add lr, r1, ip
2987		-.L487:
2988		- ldrh ip, [r1]
2989		- mvn ip, ip
2990		- strh ip, [r1], #2 @ movhi
2991		- cmp r1, lr
2992		- bne .L487
2993		- ldr ip, [sp, #4]
2994		- subs r0, r0, #1
2995		- add r1, r1, ip
2996		- bne .L488
	3105	+ b .L570
	3106	+.L486:
	3107	+ cmp r1, #6
	3108	+ bhi .L488
2997	3109	.L489:
	3110	+ ldr r1, .L574
	3111	+ ldr r2, [r1, #-1864]
	3112	+ mov r3, r2
	3113	+.L499:
	3114	+ ldr ip, [sp, #44]
	3115	+ sub r0, r3, r2
	3116	+ cmp r0, ip
	3117	+ blt .L500
	3118	+ ldr r3, [sp, #24]
	3119	+ ldr r1, [r1, #-1864]
	3120	+ add r0, r1, r3
	3121	+ mov r3, #8
	3122	+.L502:
	3123	+ mov lr, r0
	3124	+ mov ip, #0
	3125	+.L501:
	3126	+ ldrh r7, [lr]
	3127	+ add ip, ip, #1
	3128	+ mvn r7, r7
	3129	+ strh r7, [lr], #2 @ movhi
	3130	+ ldr r7, [sp, #4]
	3131	+ cmp r7, ip
	3132	+ bgt .L501
	3133	+ ldr ip, [sp, #36]
	3134	+ subs r3, r3, #1
	3135	+ add r0, r0, ip
	3136	+ bne .L502
	3137	+ str r3, [sp, #12]
	3138	+.L508:
2998	3139	mov ip, #0
2999	3140	mov r0, ip
3000		-.L492:
3001		- mov r1, #1
3002		- mov lr, #0
3003		- mov r1, r1, asl r0
3004		- mov r7, #16
3005		- str r7, [sp, #32]
3006		- mov r7, lr
3007		-.L490:
3008		- ldrh r9, [r3, lr]
3009		- and r9, r9, r1
3010		- cmp r9, r1
	3141	+.L507:
	3142	+ mov lr, #1
	3143	+ mov r7, #0
	3144	+ lsl lr, lr, r0
	3145	+ mov r3, #16
	3146	+ str r3, [sp, #32]
	3147	+ str lr, [sp, #28]
	3148	+ mov lr, r1
	3149	+.L505:
	3150	+ ldrh r8, [lr]
	3151	+ mov r3, r8
	3152	+ ldr r8, [sp, #28]
	3153	+ bics r3, r8, r3
	3154	+ ldr r3, [sp, #24]
3011	3155	addeq r7, r7, #1
3012		- ldr r9, [sp, #4]
3013		- add lr, lr, r9
3014		- ldr r9, [sp, #32]
3015		- subs r9, r9, #1
3016		- str r9, [sp, #32]
3017		- bne .L490
	3156	+ add lr, lr, r3
	3157	+ ldr r3, [sp, #32]
	3158	+ subs r3, r3, #1
	3159	+ str r3, [sp, #32]
	3160	+ bne .L505
3018	3161	cmp r7, #8
3019	3162	add r0, r0, #1
3020		- orrhi ip, ip, r1
	3163	+ ldrhi r3, [sp, #28]
	3164	+ orrhi ip, ip, r3
3021	3165	uxthhi ip, ip
3022	3166	cmp r0, #16
3023		- bne .L492
3024		- ldr r1, [sp, #28]
3025		- strh ip, [r3], #2 @ movhi
3026		- cmp r3, r1
3027		- bne .L489
3028		- ldr r1, [fp, #-1868]
	3167	+ bne .L507
	3168	+ ldr r3, [sp, #12]
	3169	+ strh ip, [r1], #2 @ movhi
	3170	+ add r3, r3, #1
	3171	+ str r3, [sp, #12]
	3172	+ ldr r0, [sp, #12]
	3173	+ ldr r3, [sp, #4]
	3174	+ cmp r3, r0
	3175	+ bgt .L508
	3176	+ ldr r3, .L574
	3177	+ ldr r1, [r3, #-1864]
3029	3178	mov r3, #0
3030	3179	sub r0, r1, #4
3031	3180	add ip, r1, #28
3032		-.L494:
	3181	+.L511:
3033	3182	ldr lr, [r0, #4]!
3034	3183	cmp lr, #0
3035	3184	addeq r3, r3, #1
3036		- cmp r0, ip
3037		- bne .L494
	3185	+ cmp ip, r0
	3186	+ bne .L511
3038	3187	cmp r3, #7
3039		- ble .L495
3040		- ldr r0, .L553+24
3041		- mov r2, #1
	3188	+ ble .L512
	3189	+ ldr r0, .L574+28
3042	3190	mov r3, #1024
	3191	+ mov r2, #1
3043	3192	bl rknand_print_hex
3044		- ldr r0, .L553+20
3045	3193	mov r1, #0
	3194	+ ldr r0, .L574+24
3046	3195	bl printk
3047		-.L496:
3048		- b .L496
3049		-.L495:
3050		- cmp r4, #6
3051		- moveq r0, #4
3052		- beq .L497
	3196	+.L513:
	3197	+ b .L513
	3198	+.L485:
3053	3199	cmp r4, #7
3054		- moveq r0, #10
3055		- beq .L497
3056		- ldr r3, [sp]
3057		- cmp r3, #0
3058		- moveq r0, #8
3059		- movne r0, #5
3060		-.L497:
3061		- sub r9, r6, #1
3062		- ldr r1, [sp, #20]
3063		- mov ip, #0
3064		- uxtb r9, r9
3065		- add r9, r9, #1
	3200	+ bne .L491
	3201	+ mov r2, #0
	3202	+.L493:
	3203	+ ldrb r0, [r3, r2, lsl #2] @ zero_extendqisi2
	3204	+ uxtb r1, r2
	3205	+ cmp r0, #12
	3206	+ beq .L492
	3207	+ add r0, r3, r2, lsl #2
	3208	+ ldrb r0, [r0, #1] @ zero_extendqisi2
	3209	+ cmp r0, #10
	3210	+ beq .L492
	3211	+ add r2, r2, #1
	3212	+ cmp r2, #8
	3213	+ bne .L493
	3214	+.L494:
	3215	+ mov r1, #0
	3216	+ ldr r0, .L574+24
	3217	+ bl printk
	3218	+.L495:
	3219	+ b .L495
	3220	+.L492:
	3221	+ cmp r1, #6
	3222	+ bls .L489
	3223	+ b .L494
	3224	+.L491:
	3225	+ cmp r4, #6
	3226	+ bne .L489
	3227	+ add r3, r3, #7
	3228	+.L496:
	3229	+ ldrb r2, [r1, #1]! @ zero_extendqisi2
	3230	+ cmp r2, #12
	3231	+ beq .L489
	3232	+ ldrb r2, [r1, #8] @ zero_extendqisi2
	3233	+ cmp r2, #4
	3234	+ beq .L489
	3235	+ cmp r3, r1
	3236	+ bne .L496
	3237	+ mov r1, #0
	3238	+ ldr r0, .L574+24
	3239	+ bl printk
3066	3240	.L498:
3067		- mov r7, r1
3068		- mov r3, r2
3069		-.L499:
3070		- ldrb lr, [r3], #1 @ zero_extendqisi2
3071		- strb lr, [r7], #1
3072		- rsb lr, r2, r3
3073		- uxtb lr, lr
3074		- cmp lr, r6
3075		- bcc .L499
3076		- add ip, ip, #1
3077		- add r2, r2, r9
3078		- cmp ip, r5
3079		- add r1, r1, r0
3080		- blt .L498
3081		- ldr r3, [sp, #8]
3082		- mov r0, r10
3083		- add r7, r8, r3, asl #8
3084		- mov r3, #255
3085		- str r3, [r7, #2056]
3086		- bl NandcWaitFlashReady
3087		- ldr r3, [sp, #24]
3088		- cmp r3, #0
3089		- beq .L501
3090		- mov r3, #54
3091		- str r3, [r7, #2056]
3092		- ldrb r3, [fp, #-2728] @ zero_extendqisi2
3093		- mvn r1, #0
3094		- ldr r0, [sp, #12]
3095		- str r3, [r7, #2052]
3096		- mov r3, #0
3097		- str r3, [r7, #2048]
3098		- mov r3, #22
3099		- str r3, [r7, #2056]
3100		- bl FlashReadCmd
3101		- b .L502
3102		-.L501:
3103		- ldr r3, [sp]
3104		- cmp r3, #0
3105		- movne r3, #190
3106		- moveq r3, #56
3107		- str r3, [r7, #2056]
3108		-.L502:
3109		- mov r0, r10
3110		- bl NandcWaitFlashReady
3111		- ldr r3, [sp, #16]
	3241	+ b .L498
	3242	+.L500:
	3243	+ ldr r0, [sp]
	3244	+ ldr r0, [r0, #2048]
	3245	+ strb r0, [r3], #1
	3246	+ b .L499
	3247	+.L512:
	3248	+ cmp r4, #6
	3249	+ moveq ip, #4
	3250	+ beq .L514
	3251	+ cmp r4, #7
	3252	+ moveq ip, #10
	3253	+ beq .L514
	3254	+ cmp r4, #8
	3255	+ moveq ip, #5
	3256	+ movne ip, #8
	3257	+.L514:
	3258	+ sub r3, r6, #1
	3259	+ ldr r0, [sp, #16]
	3260	+ uxtb r3, r3
	3261	+ mov lr, #0
3112	3262	add r3, r3, #1
3113		- str r3, [sp, #16]
3114		- b .L460
3115		-.L463:
	3263	+.L515:
	3264	+ mov r8, r0
	3265	+ mov r1, r2
	3266	+.L516:
	3267	+ ldrb r7, [r1], #1 @ zero_extendqisi2
	3268	+ strb r7, [r8], #1
	3269	+ sub r7, r1, r2
	3270	+ uxtb r7, r7
	3271	+ cmp r6, r7
	3272	+ bhi .L516
	3273	+ add lr, lr, #1
	3274	+ add r2, r2, r3
	3275	+ cmp r5, lr
	3276	+ add r0, r0, ip
	3277	+ bgt .L515
	3278	+ add r10, fp, r10, lsl #8
	3279	+ mov r3, #255
	3280	+ mov r0, r9
	3281	+ str r3, [r10, #2056]
	3282	+ bl NandcWaitFlashReady
	3283	+ ldr r3, [sp, #40]
	3284	+ cmp r3, #1
	3285	+ bhi .L518
	3286	+ mov r3, #54
	3287	+ ldr r2, [sp]
	3288	+ str r3, [r10, #2056]
	3289	+ mvn r1, #0
	3290	+ ldr r3, .L574
	3291	+ ldr r0, [sp, #8]
	3292	+ ldrb r3, [r3, #-2724] @ zero_extendqisi2
	3293	+ str r3, [r2, #2052]
	3294	+ mov r3, #0
	3295	+ str r3, [r2, #2048]
	3296	+ mov r3, #22
	3297	+ str r3, [r10, #2056]
	3298	+ bl FlashReadCmd
	3299	+.L519:
	3300	+ mov r0, r9
	3301	+ bl NandcWaitFlashReady
	3302	+ ldr r3, [sp, #20]
	3303	+ add r3, r3, #1
	3304	+ b .L573
	3305	+.L518:
	3306	+ cmp r4, #8
	3307	+ moveq r3, #190
	3308	+ movne r3, #56
	3309	+ str r3, [r10, #2056]
	3310	+ b .L519
	3311	+.L477:
3116	3312	mov r3, #120
3117	3313	mov r2, #23
3118	3314	str r3, [r7, #2056]
3119		- mov r1, #25
3120	3315	mov r3, #0
3121	3316	str r3, [r7, #2052]
	3317	+ mov r1, #25
3122	3318	str r3, [r7, #2052]
3123	3319	str r3, [r7, #2052]
3124	3320	str r2, [r7, #2056]
..	..	@@ -3134,24 +3330,28 @@
3134	3330	str r1, [r7, #2052]
3135	3331	str r2, [r7, #2052]
3136	3332	str r3, [r7, #2052]
3137		- ldr r3, .L553+28
3138		- str r3, [sp, #20]
3139		- b .L505
3140		-.L554:
	3333	+ ldr r3, .L574+32
	3334	+ str r3, [sp, #16]
	3335	+ b .L522
	3336	+.L575:
3141	3337	.align 2
3142		-.L553:
	3338	+.L574:
3143	3339	.word .LANCHOR2
3144	3340	.word .LANCHOR1
3145		- .word .LANCHOR1+3384
	3341	+ .word .LANCHOR2-2728
3146	3342	.word .LANCHOR0
3147		- .word .LANCHOR2-2732
	3343	+ .word .LANCHOR2-2720
	3344	+ .word .LANCHOR1+3380
3148	3345	.word .LC2
3149	3346	.word .LC3
3150		- .word .LANCHOR2-2704
	3347	+ .word .LANCHOR2-2700
3151	3348	.fnend
3152	3349	.size HynixGetReadRetryDefault, .-HynixGetReadRetryDefault
3153	3350	.align 2
3154	3351	.global FlashGetReadRetryDefault
	3352	+ .syntax unified
	3353	+ .arm
	3354	+ .fpu softvfp
3155	3355	.type FlashGetReadRetryDefault, %function
3156	3356	FlashGetReadRetryDefault:
3157	3357	.fnstart
..	..	@@ -3162,131 +3362,136 @@
3162	3362	bxeq lr
3163	3363	sub r2, r3, #1
3164	3364	cmp r2, #7
3165		- bhi .L557
	3365	+ bhi .L578
3166	3366	b HynixGetReadRetryDefault
3167		-.L557:
	3367	+.L578:
3168	3368	cmp r3, #49
3169		- bne .L558
3170		- ldr r2, .L569
3171		- ldr r0, .L569+4
3172		- ldr r1, .L569+8
3173		- strb r3, [r2, #-2732]
3174		- mov r3, #4
3175		- strb r3, [r2, #-2731]
3176		- mov r3, #15
3177		- strb r3, [r2, #-2730]
	3369	+ bne .L579
	3370	+ ldr r0, .L590
3178	3371	mov r2, #64
3179		- b .L567
3180		-.L558:
	3372	+ ldr r1, .L590+4
	3373	+ strb r3, [r0, #-2728]
	3374	+ mov r3, #4
	3375	+ strb r3, [r0, #-2727]
	3376	+ mov r3, #15
	3377	+ strb r3, [r0, #-2726]
	3378	+.L588:
	3379	+ sub r0, r0, #2720
	3380	+ sub r0, r0, #4
	3381	+ b ftl_memcpy
	3382	+.L579:
3181	3383	sub r2, r3, #65
3182	3384	cmp r3, #33
3183	3385	cmpne r2, #1
3184		- ldrls r2, .L569
3185		- strlsb r3, [r2, #-2732]
3186		- movls r3, #4
3187		- bls .L568
3188		-.L559:
3189		- cmp r3, #34
3190		- cmpne r3, #67
3191		- bne .L560
3192		- ldr r2, .L569
3193		- strb r3, [r2, #-2732]
3194		- mov r3, #5
3195		-.L568:
3196		- strb r3, [r2, #-2731]
	3386	+ bhi .L580
	3387	+ ldr r0, .L590
	3388	+ strb r3, [r0, #-2728]
	3389	+ mov r3, #4
	3390	+.L589:
	3391	+ strb r3, [r0, #-2727]
3197	3392	mov r3, #7
3198		- ldr r0, .L569+4
3199		- strb r3, [r2, #-2730]
	3393	+ strb r3, [r0, #-2726]
3200	3394	mov r2, #45
3201		- ldr r1, .L569+12
3202		- b .L567
3203		-.L560:
3204		- cmp r3, #35
3205		- cmpne r3, #68
	3395	+ ldr r1, .L590+8
	3396	+ b .L588
	3397	+.L580:
	3398	+ cmp r3, #67
	3399	+ cmpne r3, #34
	3400	+ ldreq r0, .L590
	3401	+ strbeq r3, [r0, #-2728]
	3402	+ moveq r3, #5
	3403	+ beq .L589
	3404	+.L581:
	3405	+ cmp r3, #68
	3406	+ cmpne r3, #35
3206	3407	bxne lr
3207		- ldr r2, .L569
3208		- ldr r0, .L569+4
3209		- ldr r1, .L569+16
3210		- strb r3, [r2, #-2732]
3211		- mov r3, #5
3212		- strb r3, [r2, #-2731]
3213		- mov r3, #17
3214		- strb r3, [r2, #-2730]
	3408	+ ldr r0, .L590
3215	3409	mov r2, #95
3216		-.L567:
3217		- b ftl_memcpy
3218		-.L570:
	3410	+ ldr r1, .L590+12
	3411	+ strb r3, [r0, #-2728]
	3412	+ mov r3, #5
	3413	+ strb r3, [r0, #-2727]
	3414	+ mov r3, #17
	3415	+ strb r3, [r0, #-2726]
	3416	+ b .L588
	3417	+.L591:
3219	3418	.align 2
3220		-.L569:
	3419	+.L590:
3221	3420	.word .LANCHOR2
3222		- .word .LANCHOR2-2728
3223		- .word .LANCHOR1+3320
3224		- .word .LANCHOR1+3168
3225		- .word .LANCHOR1+3216
	3421	+ .word .LANCHOR1+404
	3422	+ .word .LANCHOR1+256
	3423	+ .word .LANCHOR1+301
3226	3424	.fnend
3227	3425	.size FlashGetReadRetryDefault, .-FlashGetReadRetryDefault
3228	3426	.align 2
3229	3427	.global FlashReadDpCmd
	3428	+ .syntax unified
	3429	+ .arm
	3430	+ .fpu softvfp
3230	3431	.type FlashReadDpCmd, %function
3231	3432	FlashReadDpCmd:
3232	3433	.fnstart
3233	3434	@ args = 0, pretend = 0, frame = 0
3234	3435	@ frame_needed = 0, uses_anonymous_args = 0
3235		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
	3436	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
3236	3437	.save {r4, r5, r6, r7, r8, r9, r10, lr}
3237		- mov r8, r0
3238		- ldr r0, .L577
3239		- mov r7, r1
	3438	+ mov r7, r0
	3439	+ ldr r0, .L598
	3440	+ mov r8, r1
3240	3441	uxtb r10, r2
3241		- mov r9, r2, lsr #8
3242		- add r3, r0, r8, asl #3
3243		- mov r5, r2, lsr #16
3244		- ldrb r1, [r0, #64] @ zero_extendqisi2
3245		- uxtb lr, r7
3246		- ldr r4, [r3, #12]
3247		- mov ip, r7, lsr #8
3248		- ldrb r3, [r3, #16] @ zero_extendqisi2
3249		- cmp r1, #1
3250		- ldr r2, [r0, #44]
3251		- mov r1, r7, lsr #16
3252		- mov r3, r3, asl #8
	3442	+ lsr r9, r2, #8
	3443	+ lsr r6, r2, #16
	3444	+ uxtb lr, r8
	3445	+ ldr r2, [r0, #48]
	3446	+ lsr ip, r8, #8
	3447	+ add r1, r0, r7, lsl #3
	3448	+ ldr r3, [r0, r7, lsl #3]
	3449	+ ldrb r4, [r1, #4] @ zero_extendqisi2
	3450	+ ldrb r1, [r0, #68] @ zero_extendqisi2
3253	3451	ldrb r2, [r2, #7] @ zero_extendqisi2
3254		- bne .L572
	3452	+ cmp r1, #1
	3453	+ lsl r4, r4, #8
	3454	+ lsr r1, r8, #16
	3455	+ bne .L593
3255	3456	cmp r2, #1
3256		- addeq r2, r4, r3
3257		- add r4, r4, r3
3258		- moveq r6, #38
3259		- streq r6, [r2, #2056]
3260		- mov r6, #0
3261		- ldrb r3, [r0, #57] @ zero_extendqisi2
3262		- ldrb r2, [r0, #56] @ zero_extendqisi2
3263		- mov r0, r8
	3457	+ addeq r2, r3, r4
	3458	+ moveq r5, #38
	3459	+ add r4, r3, r4
	3460	+ streq r5, [r2, #2056]
	3461	+ ldrb r3, [r0, #61] @ zero_extendqisi2
	3462	+ mov r5, #0
	3463	+ ldrb r2, [r0, #60] @ zero_extendqisi2
	3464	+ mov r0, r7
3264	3465	str r2, [r4, #2056]
3265		- str r6, [r4, #2052]
3266		- str r6, [r4, #2052]
	3466	+ str r5, [r4, #2052]
	3467	+ str r5, [r4, #2052]
3267	3468	str lr, [r4, #2052]
3268	3469	str ip, [r4, #2052]
3269	3470	str r1, [r4, #2052]
3270	3471	str r3, [r4, #2056]
3271	3472	bl NandcWaitFlashReady
3272		- str r6, [r4, #2056]
3273	3473	mov r3, #48
3274		- str r6, [r4, #2052]
3275		- str r6, [r4, #2052]
	3474	+ str r5, [r4, #2056]
	3475	+ str r5, [r4, #2052]
	3476	+ str r5, [r4, #2052]
3276	3477	str r10, [r4, #2052]
3277	3478	str r9, [r4, #2052]
3278		- str r5, [r4, #2052]
	3479	+ str r6, [r4, #2052]
3279	3480	str r3, [r4, #2056]
3280		- b .L574
3281		-.L572:
	3481	+.L595:
	3482	+ mov r1, r8
	3483	+ mov r0, r7
	3484	+ pop {r4, r5, r6, r7, r8, r9, r10, lr}
	3485	+ b FlashSetRandomizer
	3486	+.L593:
3282	3487	cmp r2, #1
3283		- addeq r2, r4, r3
3284		- add r3, r4, r3
3285		- moveq r6, #38
3286		- streq r6, [r2, #2056]
3287		- ldrb r2, [r0, #56] @ zero_extendqisi2
	3488	+ addeq r2, r3, r4
	3489	+ moveq r5, #38
	3490	+ streq r5, [r2, #2056]
	3491	+ add r3, r3, r4
	3492	+ ldrb r2, [r0, #60] @ zero_extendqisi2
3288	3493	str r2, [r3, #2056]
3289		- ldrb r2, [r0, #57] @ zero_extendqisi2
	3494	+ ldrb r2, [r0, #61] @ zero_extendqisi2
3290	3495	str lr, [r3, #2052]
3291	3496	str ip, [r3, #2052]
3292	3497	str r1, [r3, #2052]
..	..	@@ -3294,135 +3499,142 @@
3294	3499	mov r2, #48
3295	3500	str r10, [r3, #2052]
3296	3501	str r9, [r3, #2052]
3297		- str r5, [r3, #2052]
	3502	+ str r6, [r3, #2052]
3298	3503	str r2, [r3, #2056]
3299		-.L574:
3300		- mov r0, r8
3301		- mov r1, r7
3302		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
3303		- b FlashSetRandomizer
3304		-.L578:
	3504	+ b .L595
	3505	+.L599:
3305	3506	.align 2
3306		-.L577:
	3507	+.L598:
3307	3508	.word .LANCHOR0
3308	3509	.fnend
3309	3510	.size FlashReadDpCmd, .-FlashReadDpCmd
3310	3511	.align 2
3311	3512	.global ftl_flash_de_init
	3513	+ .syntax unified
	3514	+ .arm
	3515	+ .fpu softvfp
3312	3516	.type ftl_flash_de_init, %function
3313	3517	ftl_flash_de_init:
3314	3518	.fnstart
3315	3519	@ args = 0, pretend = 0, frame = 0
3316	3520	@ frame_needed = 0, uses_anonymous_args = 0
3317		- stmfd sp!, {r3, r4, r5, lr}
3318		- .save {r3, r4, r5, lr}
	3521	+ push {r4, lr}
	3522	+ .save {r4, lr}
3319	3523	mov r0, #0
	3524	+ ldr r4, .L611
3320	3525	bl NandcWaitFlashReady
3321	3526	bl FlashSetReadRetryDefault
3322		- ldr r3, .L590
3323		- ldr r0, [r3, #-1864]
3324		- mov r4, r3
	3527	+ ldr r0, [r4, #-1860]
3325	3528	cmp r0, #0
3326		- beq .L580
	3529	+ beq .L601
3327	3530	mov r0, #0
3328	3531	bl flash_enter_slc_mode
3329		- b .L581
3330		-.L580:
3331		- bl flash_exit_slc_mode
3332		-.L581:
3333		- ldrb r3, [r4, #-1860] @ zero_extendqisi2
3334		- ldr r5, .L590
	3532	+.L602:
	3533	+ ldrb r3, [r4, #-1856] @ zero_extendqisi2
3335	3534	cmp r3, #0
3336		- beq .L582
3337		- ldrb r3, [r5, #-1875] @ zero_extendqisi2
	3535	+ beq .L603
	3536	+ ldrb r3, [r4, #-1871] @ zero_extendqisi2
3338	3537	tst r3, #1
3339		- beq .L582
	3538	+ beq .L603
3340	3539	mov r0, #1
3341	3540	bl FlashSetInterfaceMode
3342	3541	mov r0, #1
3343	3542	bl NandcSetMode
3344	3543	mov r3, #0
3345		- strb r3, [r5, #-1860]
3346		-.L582:
3347		- ldr r3, .L590+4
	3544	+ strb r3, [r4, #-1856]
	3545	+.L603:
	3546	+ ldr r3, .L611+4
3348	3547	mov r0, #0
3349		- ldr r3, [r3, #12]
	3548	+ ldr r3, [r3]
3350	3549	str r0, [r3, #336]
3351		- ldmfd sp!, {r3, r4, r5, pc}
3352		-.L591:
	3550	+ pop {r4, pc}
	3551	+.L601:
	3552	+ bl flash_exit_slc_mode
	3553	+ b .L602
	3554	+.L612:
3353	3555	.align 2
3354		-.L590:
	3556	+.L611:
3355	3557	.word .LANCHOR2
3356	3558	.word .LANCHOR0
3357	3559	.fnend
3358	3560	.size ftl_flash_de_init, .-ftl_flash_de_init
3359	3561	.align 2
3360	3562	.global NandcRandmzSel
	3563	+ .syntax unified
	3564	+ .arm
	3565	+ .fpu softvfp
3361	3566	.type NandcRandmzSel, %function
3362	3567	NandcRandmzSel:
3363	3568	.fnstart
3364	3569	@ args = 0, pretend = 0, frame = 0
3365	3570	@ frame_needed = 0, uses_anonymous_args = 0
3366	3571	@ link register save eliminated.
3367		- ldr r3, .L593
3368		- add r0, r3, r0, asl #3
3369		- ldr r3, [r0, #12]
	3572	+ ldr r3, .L614
	3573	+ ldr r3, [r3, r0, lsl #3]
3370	3574	str r1, [r3, #336]
3371	3575	bx lr
3372		-.L594:
	3576	+.L615:
3373	3577	.align 2
3374		-.L593:
	3578	+.L614:
3375	3579	.word .LANCHOR0
3376	3580	.fnend
3377	3581	.size NandcRandmzSel, .-NandcRandmzSel
3378	3582	.global __aeabi_idiv
3379	3583	.align 2
3380	3584	.global NandcTimeCfg
	3585	+ .syntax unified
	3586	+ .arm
	3587	+ .fpu softvfp
3381	3588	.type NandcTimeCfg, %function
3382	3589	NandcTimeCfg:
3383	3590	.fnstart
3384	3591	@ args = 0, pretend = 0, frame = 0
3385	3592	@ frame_needed = 0, uses_anonymous_args = 0
3386		- stmfd sp!, {r4, lr}
	3593	+ push {r4, lr}
3387	3594	.save {r4, lr}
3388	3595	mov r4, r0
3389	3596	mov r0, #0
3390	3597	bl rknand_get_clk_rate
3391		- ldr r1, .L606
	3598	+ ldr r1, .L627
3392	3599	bl __aeabi_idiv
3393		- ldr r3, .L606+4
3394		- ldr r3, [r3, #-2808]
	3600	+ ldr r3, .L627+4
3395	3601	cmp r0, #250
3396	3602	movwgt r2, #8354
3397		- bgt .L604
	3603	+ ldr r3, [r3, #-2804]
	3604	+ bgt .L625
3398	3605	cmp r0, #220
3399		- bgt .L605
	3606	+ ble .L619
	3607	+.L626:
	3608	+ movw r2, #8322
	3609	+ b .L625
	3610	+.L619:
3400	3611	cmp r0, #185
3401	3612	movwgt r2, #4226
3402		- bgt .L604
	3613	+ bgt .L625
3403	3614	cmp r0, #160
3404	3615	movwgt r2, #4194
3405		- bgt .L604
	3616	+ bgt .L625
3406	3617	cmp r4, #35
3407	3618	movwls r2, #4193
3408		- bls .L604
	3619	+ bls .L625
3409	3620	cmp r4, #99
3410	3621	movwls r2, #4225
3411		- bls .L604
3412		-.L605:
3413		- movw r2, #8322
3414		-.L604:
	3622	+ bhi .L626
	3623	+.L625:
3415	3624	str r2, [r3, #4]
3416		- ldmfd sp!, {r4, pc}
3417		-.L607:
	3625	+ pop {r4, pc}
	3626	+.L628:
3418	3627	.align 2
3419		-.L606:
	3628	+.L627:
3420	3629	.word 1000000
3421	3630	.word .LANCHOR2
3422	3631	.fnend
3423	3632	.size NandcTimeCfg, .-NandcTimeCfg
3424	3633	.align 2
3425	3634	.global FlashTimingCfg
	3635	+ .syntax unified
	3636	+ .arm
	3637	+ .fpu softvfp
3426	3638	.type FlashTimingCfg, %function
3427	3639	FlashTimingCfg:
3428	3640	.fnstart
..	..	@@ -3433,245 +3645,259 @@
3433	3645	sub r3, r3, #33
3434	3646	bic r3, r3, #32
3435	3647	cmp r3, #1
3436		- bls .L609
	3648	+ bls .L630
3437	3649	movw r3, #8322
3438	3650	cmp r0, r3
3439		- bne .L610
3440		-.L609:
3441		- ldr r3, .L611
3442		- ldr r3, [r3, #-2808]
	3651	+ bne .L631
	3652	+.L630:
	3653	+ ldr r3, .L632
	3654	+ ldr r3, [r3, #-2804]
3443	3655	str r0, [r3, #4]
3444		-.L610:
3445		- ldr r3, .L611+4
3446		- ldrb r0, [r3, #277] @ zero_extendqisi2
	3656	+.L631:
	3657	+ ldr r3, .L632+4
	3658	+ ldrb r0, [r3, #489] @ zero_extendqisi2
3447	3659	b NandcTimeCfg
3448		-.L612:
	3660	+.L633:
3449	3661	.align 2
3450		-.L611:
	3662	+.L632:
3451	3663	.word .LANCHOR2
3452	3664	.word .LANCHOR1
3453	3665	.fnend
3454	3666	.size FlashTimingCfg, .-FlashTimingCfg
3455	3667	.align 2
3456	3668	.global NandcInit
	3669	+ .syntax unified
	3670	+ .arm
	3671	+ .fpu softvfp
3457	3672	.type NandcInit, %function
3458	3673	NandcInit:
3459	3674	.fnstart
3460	3675	@ args = 0, pretend = 0, frame = 0
3461	3676	@ frame_needed = 0, uses_anonymous_args = 0
3462		- stmfd sp!, {r3, r4, r5, lr}
3463		- .save {r3, r4, r5, lr}
3464		- mov r2, #0
3465		- ldr r4, .L616
	3677	+ ldr r3, .L637
3466	3678	mov r1, #1
3467		- ldr r3, .L616+4
	3679	+ push {r4, r5, r6, lr}
	3680	+ .save {r4, r5, r6, lr}
	3681	+ mov r2, #0
	3682	+ ldr r4, .L637+4
3468	3683	mov r5, #0
3469		- str r0, [r4, #-2808]
3470		- str r2, [r3, #16]
3471		- str r0, [r3, #12]
3472		- str r1, [r3, #24]
	3684	+ str r1, [r3, #12]
3473	3685	mov r1, #2
3474		- str r0, [r3, #20]
3475		- str r1, [r3, #32]
	3686	+ str r1, [r3, #20]
3476	3687	mov r1, #3
3477		- str r0, [r3, #28]
3478		- str r1, [r3, #40]
3479		- str r0, [r3, #36]
	3688	+ stm r3, {r0, r2}
	3689	+ str r0, [r4, #-2804]
	3690	+ str r0, [r3, #8]
	3691	+ str r0, [r3, #16]
	3692	+ str r1, [r3, #28]
	3693	+ str r0, [r3, #24]
3480	3694	ldr r3, [r0]
3481	3695	and r3, r3, #253952
3482	3696	ubfx r1, r3, #13, #1
3483	3697	bfi r3, r2, #13, #1
3484	3698	ldr r2, [r0, #352]
3485	3699	orr r3, r3, #256
3486		- str r1, [r4, #-1856]
	3700	+ str r1, [r4, #-1852]
3487	3701	movw r1, #2049
3488	3702	ubfx r2, r2, #16, #4
3489		- str r2, [r4, #-1852]
	3703	+ str r2, [r4, #-1848]
3490	3704	ldr r2, [r0, #352]
3491	3705	cmp r2, r1
3492		- str r2, [r4, #-1848]
	3706	+ str r2, [r4, #-1844]
3493	3707	moveq r2, #8
3494		- streq r2, [r4, #-1852]
	3708	+ streq r2, [r4, #-1848]
3495	3709	str r3, [r0]
3496	3710	mov r0, #40
3497		- ldr r3, [r4, #-2808]
	3711	+ ldr r3, [r4, #-2804]
3498	3712	str r5, [r3, #336]
3499	3713	bl NandcTimeCfg
3500		- ldr r3, [r4, #-2808]
	3714	+ ldr r3, [r4, #-2804]
3501	3715	movw r2, #8322
3502	3716	mov r0, #36864
3503	3717	str r2, [r3, #344]
3504		- ldr r2, .L616+8
	3718	+ ldr r2, .L637+8
3505	3719	str r2, [r3, #304]
3506		- bl ftl_malloc
3507		- str r5, [r4, #-1816]
3508		- str r5, [r4, #-1808]
3509		- str r0, [r4, #-1844]
	3720	+ bl ftl_dma32_malloc
3510	3721	str r0, [r4, #-1840]
3511		- add r0, r0, #32768
3512	3722	str r0, [r4, #-1836]
3513		- ldmfd sp!, {r3, r4, r5, pc}
3514		-.L617:
	3723	+ add r0, r0, #32768
	3724	+ str r0, [r4, #-1832]
	3725	+ str r5, [r4, #-1812]
	3726	+ str r5, [r4, #-1804]
	3727	+ pop {r4, r5, r6, pc}
	3728	+.L638:
3515	3729	.align 2
3516		-.L616:
3517		- .word .LANCHOR2
	3730	+.L637:
3518	3731	.word .LANCHOR0
	3732	+ .word .LANCHOR2
3519	3733	.word 1579009
3520	3734	.fnend
3521	3735	.size NandcInit, .-NandcInit
3522	3736	.align 2
3523	3737	.global NandcGetTimeCfg
	3738	+ .syntax unified
	3739	+ .arm
	3740	+ .fpu softvfp
3524	3741	.type NandcGetTimeCfg, %function
3525	3742	NandcGetTimeCfg:
3526	3743	.fnstart
3527	3744	@ args = 0, pretend = 0, frame = 0
3528	3745	@ frame_needed = 0, uses_anonymous_args = 0
3529		- ldr ip, .L620
	3746	+ ldr ip, .L641
3530	3747	str lr, [sp, #-4]!
3531	3748	.save {lr}
3532		- ldr lr, [ip, #-2808]
	3749	+ ldr lr, [ip, #-2804]
3533	3750	ldr lr, [lr, #4]
3534	3751	str lr, [r0]
3535		- ldr r0, [ip, #-2808]
	3752	+ ldr r0, [ip, #-2804]
3536	3753	ldr r0, [r0]
3537	3754	str r0, [r1]
3538		- ldr r1, [ip, #-2808]
	3755	+ ldr r1, [ip, #-2804]
3539	3756	ldr r1, [r1, #304]
3540	3757	str r1, [r2]
3541		- ldr r1, [ip, #-2808]
	3758	+ ldr r1, [ip, #-2804]
3542	3759	ldr r2, [r1, #308]
3543	3760	ldr r1, [r1, #344]
3544	3761	uxtb r2, r2
3545		- orr r2, r2, r1, asl #16
	3762	+ orr r2, r2, r1, lsl #16
3546	3763	str r2, [r3]
3547	3764	ldr pc, [sp], #4
3548		-.L621:
	3765	+.L642:
3549	3766	.align 2
3550		-.L620:
	3767	+.L641:
3551	3768	.word .LANCHOR2
3552	3769	.fnend
3553	3770	.size NandcGetTimeCfg, .-NandcGetTimeCfg
3554	3771	.align 2
3555	3772	.global NandcBchSel
	3773	+ .syntax unified
	3774	+ .arm
	3775	+ .fpu softvfp
3556	3776	.type NandcBchSel, %function
3557	3777	NandcBchSel:
3558	3778	.fnstart
3559	3779	@ args = 0, pretend = 0, frame = 0
3560	3780	@ frame_needed = 0, uses_anonymous_args = 0
3561	3781	@ link register save eliminated.
3562		- ldr r3, .L630
3563		- mov r1, #1
3564		- ldr r2, [r3, #-2808]
3565		- str r0, [r3, #-1804]
3566		- mov r3, #0
3567		- str r1, [r2, #8]
3568		- mov r1, #16
3569		- cmp r0, r1
3570		- bfi r3, r1, #8, #8
3571		- bfc r3, #18, #1
3572		- bne .L623
3573		-.L626:
	3782	+ ldr r3, .L651
	3783	+ mov ip, #1
	3784	+ mov r1, #0
	3785	+ ldr r2, [r3, #-2804]
	3786	+ str r0, [r3, #-1800]
	3787	+ mov r3, r1
	3788	+ str ip, [r2, #8]
	3789	+ mov ip, #16
	3790	+ cmp r0, ip
	3791	+ bfi r3, ip, #8, #8
	3792	+ bfi r3, r1, #18, #1
	3793	+ bne .L644
	3794	+.L647:
3574	3795	bfc r3, #4, #1
3575		- b .L624
3576		-.L623:
3577		- cmp r0, #24
3578		- orreq r3, r3, #16
3579		- beq .L624
3580		- cmp r0, #40
3581		- orr r3, r3, #262144
3582		- orr r3, r3, #16
3583		- beq .L626
3584		-.L624:
	3796	+.L645:
3585	3797	orr r3, r3, #1
3586	3798	str r3, [r2, #12]
3587	3799	bx lr
3588		-.L631:
	3800	+.L644:
	3801	+ cmp r0, #24
	3802	+ orreq r3, r3, #16
	3803	+ beq .L645
	3804	+ cmp r0, #40
	3805	+ orr r3, r3, #262144
	3806	+ orr r3, r3, #16
	3807	+ bne .L645
	3808	+ b .L647
	3809	+.L652:
3589	3810	.align 2
3590		-.L630:
	3811	+.L651:
3591	3812	.word .LANCHOR2
3592	3813	.fnend
3593	3814	.size NandcBchSel, .-NandcBchSel
3594	3815	.align 2
3595	3816	.global FlashBchSel
	3817	+ .syntax unified
	3818	+ .arm
	3819	+ .fpu softvfp
3596	3820	.type FlashBchSel, %function
3597	3821	FlashBchSel:
3598	3822	.fnstart
3599	3823	@ args = 0, pretend = 0, frame = 0
3600	3824	@ frame_needed = 0, uses_anonymous_args = 0
3601	3825	@ link register save eliminated.
3602		- ldr r3, .L633
3603		- strb r0, [r3, #-2743]
	3826	+ ldr r3, .L654
	3827	+ strb r0, [r3, #-2739]
3604	3828	b NandcBchSel
3605		-.L634:
	3829	+.L655:
3606	3830	.align 2
3607		-.L633:
	3831	+.L654:
3608	3832	.word .LANCHOR2
3609	3833	.fnend
3610	3834	.size FlashBchSel, .-FlashBchSel
3611	3835	.align 2
3612	3836	.global ftl_flash_resume
	3837	+ .syntax unified
	3838	+ .arm
	3839	+ .fpu softvfp
3613	3840	.type ftl_flash_resume, %function
3614	3841	ftl_flash_resume:
3615	3842	.fnstart
3616	3843	@ args = 0, pretend = 0, frame = 0
3617	3844	@ frame_needed = 0, uses_anonymous_args = 0
3618		- ldr r3, .L644
3619		- stmfd sp!, {r4, r5, r6, lr}
	3845	+ ldr r3, .L665
	3846	+ push {r4, r5, r6, lr}
3620	3847	.save {r4, r5, r6, lr}
3621	3848	mov r5, #0
3622		- ldr r2, [r3, #-2808]
	3849	+ ldr r6, .L665+4
3623	3850	mov r4, r3
3624		- ldr r1, [r3, #-2804]
3625		- ldr r6, .L644+4
3626		- str r1, [r2]
	3851	+ ldr r2, [r3, #-2804]
3627	3852	ldr r1, [r3, #-2800]
3628		- ldr r2, [r3, #-2808]
3629		- str r1, [r2, #4]
	3853	+ str r1, [r2]
3630	3854	ldr r1, [r3, #-2796]
3631		- str r1, [r2, #8]
	3855	+ ldr r2, [r3, #-2804]
	3856	+ str r1, [r2, #4]
3632	3857	ldr r1, [r3, #-2792]
3633		- str r1, [r2, #12]
	3858	+ str r1, [r2, #8]
3634	3859	ldr r1, [r3, #-2788]
3635		- str r1, [r2, #304]
	3860	+ str r1, [r2, #12]
3636	3861	ldr r1, [r3, #-2784]
3637		- str r1, [r2, #308]
	3862	+ str r1, [r2, #304]
3638	3863	ldr r1, [r3, #-2780]
3639		- str r1, [r2, #336]
	3864	+ str r1, [r2, #308]
3640	3865	ldr r1, [r3, #-2776]
	3866	+ str r1, [r2, #336]
	3867	+ ldr r1, [r3, #-2772]
3641	3868	str r1, [r2, #344]
3642		-.L637:
3643		- ldrb r3, [r6, r5, asl #3] @ zero_extendqisi2
	3869	+.L658:
	3870	+ ldrb r3, [r6, r5, lsl #3] @ zero_extendqisi2
3644	3871	sub r3, r3, #1
3645	3872	uxtb r3, r3
3646	3873	cmp r3, #253
3647		- bhi .L636
	3874	+ bhi .L657
3648	3875	uxtb r0, r5
3649	3876	bl FlashReset
3650		-.L636:
	3877	+.L657:
3651	3878	add r5, r5, #1
3652	3879	cmp r5, #4
3653		- bne .L637
3654		- ldrb r3, [r4, #-1860] @ zero_extendqisi2
3655		- ldr r5, .L644
	3880	+ bne .L658
	3881	+ ldrb r3, [r4, #-1856] @ zero_extendqisi2
3656	3882	cmp r3, #0
3657		- beq .L638
	3883	+ beq .L659
3658	3884	mov r0, #1
3659	3885	bl NandcSetMode
3660		- ldrb r0, [r5, #-1875] @ zero_extendqisi2
	3886	+ ldrb r0, [r4, #-1871] @ zero_extendqisi2
3661	3887	bl FlashSetInterfaceMode
3662		- ldrb r0, [r5, #-1875] @ zero_extendqisi2
	3888	+ ldrb r0, [r4, #-1871] @ zero_extendqisi2
3663	3889	bl NandcSetMode
3664		- ldrb r0, [r5, #-2787] @ zero_extendqisi2
	3890	+ ldrb r0, [r4, #-2783] @ zero_extendqisi2
3665	3891	bl NandcSetDdrPara
3666		-.L638:
3667		- ldr r3, .L644+8
3668		- ldmfd sp!, {r4, r5, r6, lr}
3669		- ldr r3, [r3, #44]
	3892	+.L659:
	3893	+ ldr r3, .L665+8
	3894	+ pop {r4, r5, r6, lr}
	3895	+ ldr r3, [r3, #48]
3670	3896	ldrb r0, [r3, #20] @ zero_extendqisi2
3671	3897	b FlashBchSel
3672		-.L645:
	3898	+.L666:
3673	3899	.align 2
3674		-.L644:
	3900	+.L665:
3675	3901	.word .LANCHOR2
3676	3902	.word IDByte
3677	3903	.word .LANCHOR0
..	..	@@ -3679,6 +3905,9 @@
3679	3905	.size ftl_flash_resume, .-ftl_flash_resume
3680	3906	.align 2
3681	3907	.global ftl_nandc_get_irq_status
	3908	+ .syntax unified
	3909	+ .arm
	3910	+ .fpu softvfp
3682	3911	.type ftl_nandc_get_irq_status, %function
3683	3912	ftl_nandc_get_irq_status:
3684	3913	.fnstart
..	..	@@ -3691,6 +3920,9 @@
3691	3920	.size ftl_nandc_get_irq_status, .-ftl_nandc_get_irq_status
3692	3921	.align 2
3693	3922	.global NandcIqrWaitFlashReady
	3923	+ .syntax unified
	3924	+ .arm
	3925	+ .fpu softvfp
3694	3926	.type NandcIqrWaitFlashReady, %function
3695	3927	NandcIqrWaitFlashReady:
3696	3928	.fnstart
..	..	@@ -3702,6 +3934,9 @@
3702	3934	.size NandcIqrWaitFlashReady, .-NandcIqrWaitFlashReady
3703	3935	.align 2
3704	3936	.global NandcSendDumpDataStart
	3937	+ .syntax unified
	3938	+ .arm
	3939	+ .fpu softvfp
3705	3940	.type NandcSendDumpDataStart, %function
3706	3941	NandcSendDumpDataStart:
3707	3942	.fnstart
..	..	@@ -3711,10 +3946,10 @@
3711	3946	ldr r2, [r0, #16]
3712	3947	.pad #8
3713	3948	sub sp, sp, #8
3714		- ldr r3, .L650
	3949	+ ldr r3, .L671
3715	3950	str r2, [sp, #4]
3716	3951	ldr r2, [sp, #4]
3717		- bic r2, r2, #4
	3952	+ bfc r2, #2, #1
3718	3953	str r2, [sp, #4]
3719	3954	ldr r2, [sp, #4]
3720	3955	str r2, [r0, #16]
..	..	@@ -3724,14 +3959,17 @@
3724	3959	add sp, sp, #8
3725	3960	@ sp needed
3726	3961	bx lr
3727		-.L651:
	3962	+.L672:
3728	3963	.align 2
3729		-.L650:
	3964	+.L671:
3730	3965	.word 538969130
3731	3966	.fnend
3732	3967	.size NandcSendDumpDataStart, .-NandcSendDumpDataStart
3733	3968	.align 2
3734	3969	.global NandcSendDumpDataDone
	3970	+ .syntax unified
	3971	+ .arm
	3972	+ .fpu softvfp
3735	3973	.type NandcSendDumpDataDone, %function
3736	3974	NandcSendDumpDataDone:
3737	3975	.fnstart
..	..	@@ -3740,12 +3978,12 @@
3740	3978	@ link register save eliminated.
3741	3979	.pad #8
3742	3980	sub sp, sp, #8
3743		-.L653:
	3981	+.L674:
3744	3982	ldr r3, [r0, #8]
3745	3983	str r3, [sp, #4]
3746	3984	ldr r3, [sp, #4]
3747	3985	tst r3, #1048576
3748		- beq .L653
	3986	+ beq .L674
3749	3987	add sp, sp, #8
3750	3988	@ sp needed
3751	3989	bx lr
..	..	@@ -3753,315 +3991,312 @@
3753	3991	.size NandcSendDumpDataDone, .-NandcSendDumpDataDone
3754	3992	.align 2
3755	3993	.global NandcXferStart
	3994	+ .syntax unified
	3995	+ .arm
	3996	+ .fpu softvfp
3756	3997	.type NandcXferStart, %function
3757	3998	NandcXferStart:
3758	3999	.fnstart
3759		- @ args = 8, pretend = 0, frame = 24
	4000	+ @ args = 8, pretend = 0, frame = 16
3760	4001	@ frame_needed = 0, uses_anonymous_args = 0
3761		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	4002	+ ldr ip, .L696
	4003	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
3762	4004	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
3763	4005	mov r4, #0
3764		- ldr lr, .L675
3765		- .pad #28
3766		- sub sp, sp, #28
3767		- ldr r5, .L675+4
3768		- add r0, lr, r0, asl #3
3769		- mov lr, #16
3770		- ldr r8, [sp, #64]
3771		- ldr r6, [r0, #12]
3772		- ldrb r0, [r0, #16] @ zero_extendqisi2
3773		- ldr ip, [sp, #68]
	4006	+ ldr r5, .L696+4
	4007	+ .pad #20
	4008	+ sub sp, sp, #20
	4009	+ ldr r6, [ip, r0, lsl #3]
	4010	+ add ip, ip, r0, lsl #3
	4011	+ ldr r8, [sp, #56]
	4012	+ ldrb r0, [ip, #4] @ zero_extendqisi2
	4013	+ mov ip, #16
3774	4014	ldr r7, [r6, #12]
3775		- bfi r7, lr, #8, #8
	4015	+ bfi r7, ip, #8, #8
3776	4016	bfi r7, r4, #3, #1
3777	4017	bfi r4, r1, #1, #1
3778		- orr r4, r4, #8
3779	4018	bfi r7, r0, #5, #3
	4019	+ orr r4, r4, #8
3780	4020	mov r0, #1
3781	4021	bfi r4, r0, #5, #2
	4022	+ lsr r3, r3, r0
3782	4023	orr r4, r4, #536870912
3783		- mov r3, r3, lsr r0
3784	4024	orr r4, r4, #1024
3785	4025	bfi r4, r3, #4, #1
3786		- ldr r3, [r5, #-1852]
	4026	+ ldr r3, [r5, #-1848]
3787	4027	cmp r3, #3
3788		- bls .L658
	4028	+ bls .L679
3789	4029	ldr r3, [r6, #16]
3790		- str r3, [sp, #20]
3791		- ldr r3, [sp, #20]
3792		- bic r3, r3, #4
3793		- str r3, [sp, #20]
3794		- adds r3, ip, #0
3795		- movne r3, #1
3796		- cmp ip, #0
3797		- cmpeq r8, #0
3798		- str r3, [sp, #8]
3799		- beq .L659
	4030	+ str r3, [sp, #12]
	4031	+ ldr r3, [sp, #12]
	4032	+ bfc r3, #2, #1
	4033	+ str r3, [sp, #12]
	4034	+ ldr r3, [sp, #60]
	4035	+ cmp r8, #0
	4036	+ cmpeq r3, #0
	4037	+ beq .L680
3800	4038	cmp r1, #0
3801		- bne .L660
3802		-.L668:
	4039	+ bne .L681
	4040	+.L689:
3803	4041	add r2, r2, #1
3804	4042	cmp r8, #0
3805		- mov r2, r2, asr #1
	4043	+ asr r2, r2, #1
3806	4044	movne r0, r8
3807	4045	bfi r4, r2, #22, #6
3808		- ldreq r0, [r5, #-1840]
3809		- b .L662
3810		-.L660:
3811		- ldr r3, [r5, #-1804]
3812		- mov r9, r5
3813		- cmp r3, #25
3814		- movcc r3, #64
3815		- movcs r3, #128
3816		- str r3, [sp, #4]
3817		- mov r3, r2, lsr #1
3818		- str r3, [sp, #12]
3819		- mov r3, #0
3820		- mov r0, r3
3821		-.L664:
3822		- ldr lr, [sp, #12]
3823		- cmp r0, lr
3824		- bcs .L668
3825		- ldr lr, [sp, #8]
3826		- mov r10, r3, lsr #2
3827		- add r0, r0, #1
3828		- cmp lr, #0
3829		- ldrneh fp, [ip, #2]
3830		- mvneq fp, #0
3831		- ldrneh lr, [ip], #4
3832		- ldreq lr, [r9, #-1836]
3833		- orrne lr, lr, fp, asl #16
3834		- ldrne fp, [r9, #-1836]
3835		- streq fp, [lr, r10, asl #2]
3836		- strne lr, [fp, r10, asl #2]
3837		- ldr lr, [sp, #4]
3838		- add r3, r3, lr
3839		- b .L664
3840		-.L662:
3841		- ldr r3, [r5, #-1836]
	4046	+ ldreq r0, [r5, #-1836]
	4047	+.L683:
	4048	+ ldr r3, [r5, #-1832]
3842	4049	ubfx r10, r4, #22, #5
3843	4050	mov r9, r1
3844		- str r0, [r5, #-1832]
3845		- mov r2, r9
3846		- mov r1, r10, asl #10
3847		- str r3, [r5, #-1828]
	4051	+ mov r2, r1
	4052	+ lsl r1, r10, #10
	4053	+ str r0, [r5, #-1828]
	4054	+ str r3, [r5, #-1824]
3848	4055	bl rknand_dma_map_single
3849	4056	mov r2, r9
3850		- mov r1, r10, asl #7
3851		- clz r9, r9
3852		- mov r9, r9, lsr #5
3853		- str r0, [r5, #-1824]
3854		- ldr r0, [r5, #-1828]
	4057	+ str r0, [r5, #-1820]
	4058	+ lsl r1, r10, #7
	4059	+ ldr r0, [r5, #-1824]
3855	4060	bl rknand_dma_map_single
3856	4061	mov r3, #1
3857		- str r3, [r5, #-1816]
3858		- tst r8, #3
3859		- ldr r3, [r5, #-1824]
3860		- str r0, [r5, #-1820]
3861		- str r3, [r6, #20]
	4062	+ str r0, [r5, #-1816]
	4063	+ str r3, [r5, #-1812]
	4064	+ mov r2, #16
3862	4065	ldr r3, [r5, #-1820]
	4066	+ tst r8, #3
	4067	+ clz r1, r9
	4068	+ lsr r1, r1, #5
	4069	+ str r3, [r6, #20]
	4070	+ ldr r3, [r5, #-1816]
3863	4071	str r3, [r6, #24]
3864	4072	mov r3, #0
3865		- str r3, [sp, #20]
3866		- ldr r3, [sp, #20]
3867		- bic r3, r3, #15872
3868		- orr r3, r3, #8192
3869		- str r3, [sp, #20]
3870		- ldr r3, [sp, #20]
	4073	+ str r3, [sp, #12]
	4074	+ ldr r3, [sp, #12]
	4075	+ bfi r3, r2, #9, #5
	4076	+ moveq r2, #2
	4077	+ str r3, [sp, #12]
	4078	+ ldr r3, [sp, #12]
3871	4079	orr r3, r3, #448
3872		- str r3, [sp, #20]
3873		- ldreq r3, [sp, #20]
3874		- biceq r3, r3, #56
3875		- orreq r3, r3, #16
3876		- streq r3, [sp, #20]
3877		- ldr r3, [sp, #20]
	4080	+ str r3, [sp, #12]
	4081	+ ldreq r3, [sp, #12]
	4082	+ bfieq r3, r2, #3, #3
	4083	+ streq r3, [sp, #12]
	4084	+ ldr r3, [sp, #12]
3878	4085	orr r3, r3, #4
3879		- str r3, [sp, #20]
3880		- ldr r3, [sp, #20]
3881		- bic r3, r3, #2
3882		- orr r9, r3, r9, asl #1
3883		- str r9, [sp, #20]
3884		- ldr r3, [sp, #20]
	4086	+ str r3, [sp, #12]
	4087	+ ldr r3, [sp, #12]
	4088	+ bfi r3, r1, #1, #1
	4089	+ str r3, [sp, #12]
	4090	+ ldr r3, [sp, #12]
3885	4091	orr r3, r3, #1
3886		- str r3, [sp, #20]
3887		-.L659:
3888		- ldr r3, [sp, #20]
	4092	+ str r3, [sp, #12]
	4093	+.L680:
	4094	+ ldr r3, [sp, #12]
3889	4095	str r3, [r6, #16]
3890		-.L658:
	4096	+.L679:
3891	4097	str r7, [r6, #12]
3892	4098	str r4, [r6, #8]
3893	4099	orr r4, r4, #4
3894	4100	str r4, [r6, #8]
3895		- add sp, sp, #28
	4101	+ add sp, sp, #20
3896	4102	@ sp needed
3897		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
3898		-.L676:
	4103	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	4104	+.L681:
	4105	+ ldr r3, [r5, #-1800]
	4106	+ lsr r10, r2, #1
	4107	+ ldr ip, [sp, #60]
	4108	+ cmp r3, #25
	4109	+ movcc r3, #64
	4110	+ movcs r3, #128
	4111	+ str r3, [sp, #4]
	4112	+ mov r3, #0
	4113	+ mov r0, r3
	4114	+.L685:
	4115	+ cmp r0, r10
	4116	+ bcs .L689
	4117	+ ldr lr, [sp, #60]
	4118	+ add r0, r0, #1
	4119	+ cmp lr, #0
	4120	+ bic lr, r3, #3
	4121	+ ldrne fp, [ip], #4 @ unaligned
	4122	+ mvneq r9, #0
	4123	+ ldrne r9, [r5, #-1832]
	4124	+ ldreq fp, [r5, #-1832]
	4125	+ strne fp, [r9, lr]
	4126	+ streq r9, [fp, lr]
	4127	+ ldr lr, [sp, #4]
	4128	+ add r3, r3, lr
	4129	+ b .L685
	4130	+.L697:
3899	4131	.align 2
3900		-.L675:
	4132	+.L696:
3901	4133	.word .LANCHOR0
3902	4134	.word .LANCHOR2
3903	4135	.fnend
3904	4136	.size NandcXferStart, .-NandcXferStart
3905	4137	.align 2
3906	4138	.global NandcXferComp
	4139	+ .syntax unified
	4140	+ .arm
	4141	+ .fpu softvfp
3907	4142	.type NandcXferComp, %function
3908	4143	NandcXferComp:
3909	4144	.fnstart
3910	4145	@ args = 0, pretend = 0, frame = 8
3911	4146	@ frame_needed = 0, uses_anonymous_args = 0
3912		- stmfd sp!, {r0, r1, r4, r5, r6, lr}
3913		- .save {r4, r5, r6, lr}
	4147	+ push {r0, r1, r4, r5, r6, r7, r8, lr}
	4148	+ .save {r4, r5, r6, r7, r8, lr}
3914	4149	.pad #8
3915		- ldr r5, .L717
3916		- ldr r3, .L717+4
3917		- add r0, r3, r0, asl #3
3918		- ldr r3, [r5, #-1852]
	4150	+ ldr r3, .L738
	4151	+ ldr r5, .L738+4
	4152	+ ldr r4, [r3, r0, lsl #3]
	4153	+ ldr r3, [r5, #-1848]
3919	4154	cmp r3, #3
3920		- ldr r4, [r0, #12]
3921		- bls .L708
	4155	+ bls .L729
3922	4156	ldr r3, [r4, #16]
3923	4157	tst r3, #4
3924		- beq .L708
	4158	+ beq .L729
3925	4159	ldr r6, [r4, #16]
3926	4160	ldr r3, [r4, #8]
3927	4161	ubfx r6, r6, #1, #1
3928	4162	cmp r6, #0
3929	4163	str r3, [sp]
3930		- movne r6, #0
3931		- beq .L690
3932		-.L680:
	4164	+ beq .L700
	4165	+ ldr r7, .L738+8
	4166	+ mov r6, #0
	4167	+ ldr r8, .L738+12
	4168	+.L701:
3933	4169	ldr r2, [r4, #28]
3934	4170	ldr r3, [sp]
3935	4171	ubfx r2, r2, #16, #5
3936	4172	ubfx r3, r3, #22, #6
3937	4173	cmp r2, r3
3938		- bge .L688
3939		- ldr r3, [r5, #-1852]
	4174	+ bge .L709
	4175	+ ldr r3, [r5, #-1848]
3940	4176	cmp r3, #5
3941		- bhi .L681
3942		-.L684:
	4177	+ bhi .L702
	4178	+.L705:
3943	4179	add r6, r6, #1
3944		- bic r3, r6, #-16777216
3945		- cmp r3, #0
3946		- bne .L683
	4180	+ bics r3, r6, #-16777216
	4181	+ bne .L704
3947	4182	ldr r2, [r4, #28]
3948	4183	mov r1, r6
3949	4184	ldr r3, [sp]
	4185	+ mov r0, r7
3950	4186	ubfx r2, r2, #16, #5
3951		- ldr r0, .L717+8
3952	4187	ubfx r3, r3, #22, #6
3953	4188	bl printk
3954		- ldr r0, .L717+12
3955		- mov r1, r4
3956		- mov r2, #4
3957	4189	mov r3, #512
	4190	+ mov r2, #4
	4191	+ mov r1, r4
	4192	+ mov r0, r8
3958	4193	bl rknand_print_hex
3959		- b .L683
3960		-.L681:
	4194	+.L704:
	4195	+ mov r1, #5
	4196	+ mov r0, #1
	4197	+ bl usleep_range
	4198	+ b .L701
	4199	+.L702:
3961	4200	ldr r3, [r4]
3962	4201	str r3, [sp, #4]
3963	4202	ldr r3, [sp, #4]
3964	4203	tst r3, #8192
3965		- beq .L684
	4204	+ beq .L705
3966	4205	ldr r3, [sp, #4]
3967	4206	tst r3, #131072
3968		- beq .L684
3969		-.L688:
3970		- ldr r3, [r5, #-1816]
3971		- ldr r4, .L717
	4207	+ beq .L705
	4208	+.L709:
	4209	+ ldr r3, [r5, #-1812]
3972	4210	cmp r3, #0
3973		- beq .L689
	4211	+ beq .L710
3974	4212	ldr r1, [sp]
3975	4213	mov r2, #0
3976		- ldr r0, [r4, #-1824]
	4214	+ ldr r0, [r5, #-1820]
3977	4215	ubfx r1, r1, #22, #5
3978		- mov r1, r1, asl #10
	4216	+ lsl r1, r1, #10
3979	4217	bl rknand_dma_unmap_single
3980		- ldr r0, [r4, #-1820]
3981		- mov r2, #0
3982	4218	ldr r1, [sp]
	4219	+ mov r2, #0
	4220	+ ldr r0, [r5, #-1816]
3983	4221	ubfx r1, r1, #22, #5
3984		- mov r1, r1, asl #7
	4222	+ lsl r1, r1, #7
3985	4223	bl rknand_dma_unmap_single
3986		- b .L689
3987		-.L683:
3988		- mov r0, #1
3989		- mov r1, #5
3990		- bl usleep_range
3991		- b .L680
3992		-.L692:
	4224	+.L710:
	4225	+ mov r3, #0
	4226	+ str r3, [r5, #-1812]
	4227	+.L698:
	4228	+ add sp, sp, #8
	4229	+ @ sp needed
	4230	+ pop {r4, r5, r6, r7, r8, pc}
	4231	+.L700:
	4232	+ ldr r7, .L738+16
	4233	+ ldr r8, .L738+12
	4234	+.L711:
	4235	+ ldr r3, [sp]
	4236	+ tst r3, #1048576
	4237	+ beq .L713
	4238	+ ldr r3, [r5, #-1804]
	4239	+ cmp r3, #0
	4240	+ beq .L714
	4241	+ mov r0, r4
	4242	+ bl NandcSendDumpDataStart
	4243	+.L714:
	4244	+ ldr r3, [r5, #-1812]
	4245	+ cmp r3, #0
	4246	+ beq .L715
	4247	+ ldr r1, [sp]
	4248	+ mov r2, #1
	4249	+ ldr r0, [r5, #-1820]
	4250	+ ubfx r1, r1, #22, #5
	4251	+ lsl r1, r1, #10
	4252	+ bl rknand_dma_unmap_single
	4253	+ ldr r1, [sp]
	4254	+ mov r2, #1
	4255	+ ldr r0, [r5, #-1816]
	4256	+ ubfx r1, r1, #22, #5
	4257	+ lsl r1, r1, #7
	4258	+ bl rknand_dma_unmap_single
	4259	+.L715:
	4260	+ ldr r3, [r5, #-1804]
	4261	+ cmp r3, #0
	4262	+ beq .L710
	4263	+ mov r0, r4
	4264	+ bl NandcSendDumpDataDone
	4265	+ b .L710
	4266	+.L713:
3993	4267	ldr r3, [r4, #8]
3994	4268	add r6, r6, #1
3995	4269	str r3, [sp]
3996		- bic r3, r6, #-16777216
3997		- cmp r3, #0
3998		- bne .L691
	4270	+ bics r3, r6, #-16777216
	4271	+ bne .L712
3999	4272	ldr r2, [sp]
4000	4273	mov r1, r6
4001	4274	ldr r3, [r4, #28]
4002		- ldr r0, .L717+16
	4275	+ mov r0, r7
4003	4276	ubfx r3, r3, #16, #5
4004	4277	bl printk
4005		- ldr r0, .L717+12
4006		- mov r1, r4
4007		- mov r2, #4
4008	4278	mov r3, #512
	4279	+ mov r2, #4
	4280	+ mov r1, r4
	4281	+ mov r0, r8
4009	4282	bl rknand_print_hex
4010		-.L691:
4011		- mov r0, #1
	4283	+.L712:
4012	4284	mov r1, #5
	4285	+ mov r0, #1
4013	4286	bl usleep_range
4014		-.L690:
4015		- ldr r3, [sp]
4016		- tst r3, #1048576
4017		- beq .L692
4018		- ldr r3, [r5, #-1808]
4019		- cmp r3, #0
4020		- beq .L693
4021		- mov r0, r4
4022		- bl NandcSendDumpDataStart
4023		-.L693:
4024		- ldr r3, [r5, #-1816]
4025		- ldr r6, .L717
4026		- cmp r3, #0
4027		- beq .L694
4028		- ldr r1, [sp]
4029		- mov r2, #1
4030		- ldr r0, [r6, #-1824]
4031		- ubfx r1, r1, #22, #5
4032		- mov r1, r1, asl #10
4033		- bl rknand_dma_unmap_single
4034		- ldr r0, [r6, #-1820]
4035		- mov r2, #1
4036		- ldr r1, [sp]
4037		- ubfx r1, r1, #22, #5
4038		- mov r1, r1, asl #7
4039		- bl rknand_dma_unmap_single
4040		-.L694:
4041		- ldr r3, [r5, #-1808]
4042		- cmp r3, #0
4043		- beq .L689
4044		- mov r0, r4
4045		- bl NandcSendDumpDataDone
4046		-.L689:
4047		- mov r3, #0
4048		- str r3, [r5, #-1816]
4049		- b .L677
4050		-.L708:
	4287	+ b .L711
	4288	+.L729:
4051	4289	ldr r3, [r4, #8]
4052	4290	str r3, [sp]
4053	4291	ldr r3, [sp]
4054	4292	tst r3, #1048576
4055		- beq .L708
4056		-.L677:
4057		- add sp, sp, #8
4058		- @ sp needed
4059		- ldmfd sp!, {r4, r5, r6, pc}
4060		-.L718:
	4293	+ beq .L729
	4294	+ b .L698
	4295	+.L739:
4061	4296	.align 2
4062		-.L717:
4063		- .word .LANCHOR2
	4297	+.L738:
4064	4298	.word .LANCHOR0
	4299	+ .word .LANCHOR2
4065	4300	.word .LC4
4066	4301	.word .LC5
4067	4302	.word .LC6
..	..	@@ -4069,367 +4304,362 @@
4069	4304	.size NandcXferComp, .-NandcXferComp
4070	4305	.align 2
4071	4306	.global NandcCopy1KB
	4307	+ .syntax unified
	4308	+ .arm
	4309	+ .fpu softvfp
4072	4310	.type NandcCopy1KB, %function
4073	4311	NandcCopy1KB:
4074	4312	.fnstart
4075	4313	@ args = 4, pretend = 0, frame = 0
4076	4314	@ frame_needed = 0, uses_anonymous_args = 0
4077	4315	cmp r1, #1
4078		- stmfd sp!, {r4, r5, r6, lr}
	4316	+ push {r4, r5, r6, lr}
4079	4317	.save {r4, r5, r6, lr}
4080	4318	mov r4, r2
4081	4319	add r2, r0, #4096
4082		- ldr r5, [sp, #16]
4083	4320	add r6, r0, #512
4084		- add r2, r2, r4, asl #9
4085		- bne .L720
	4321	+ add r0, r2, r4, lsl #9
	4322	+ ldr r5, [sp, #16]
	4323	+ bne .L741
4086	4324	cmp r3, #0
4087		- beq .L721
4088		- mov r0, r2
	4325	+ beq .L742
	4326	+ mov r2, #1024
4089	4327	mov r1, r3
4090		- mov r2, #1024
4091	4328	bl ftl_memcpy
4092		-.L721:
	4329	+.L742:
4093	4330	cmp r5, #0
4094		- ldmeqfd sp!, {r4, r5, r6, pc}
4095		- ldrb r3, [r5, #2] @ zero_extendqisi2
4096		- mov r4, r4, lsr #1
4097		- ldrb r2, [r5, #1] @ zero_extendqisi2
4098		- add r4, r4, r4, asl #1
4099		- mov r3, r3, asl #16
4100		- orr r2, r3, r2, asl #8
4101		- ldrb r3, [r5] @ zero_extendqisi2
4102		- orr r3, r2, r3
4103		- ldrb r2, [r5, #3] @ zero_extendqisi2
4104		- orr r3, r3, r2, asl #24
4105		- str r3, [r6, r4, asl #4]
4106		- ldmfd sp!, {r4, r5, r6, pc}
4107		-.L720:
	4331	+ lsrne r4, r4, #1
	4332	+ ldrne r3, [r5] @ unaligned
	4333	+ addne r4, r4, r4, lsl #1
	4334	+ strne r3, [r6, r4, lsl #4]
	4335	+ pop {r4, r5, r6, pc}
	4336	+.L741:
4108	4337	cmp r3, #0
4109		- beq .L724
4110		- mov r1, r2
4111		- mov r0, r3
	4338	+ beq .L745
	4339	+ mov r1, r0
4112	4340	mov r2, #1024
	4341	+ mov r0, r3
4113	4342	bl ftl_memcpy
4114		-.L724:
	4343	+.L745:
4115	4344	cmp r5, #0
4116		- ldmeqfd sp!, {r4, r5, r6, pc}
4117		- mov r4, r4, lsr #1
4118		- add r4, r4, r4, asl #1
4119		- ldr r3, [r6, r4, asl #4]
4120		- mov r2, r3, lsr #8
	4345	+ popeq {r4, r5, r6, pc}
	4346	+ lsr r4, r4, #1
	4347	+ add r4, r4, r4, lsl #1
	4348	+ ldr r3, [r6, r4, lsl #4]
4121	4349	strb r3, [r5]
	4350	+ lsr r2, r3, #8
4122	4351	strb r2, [r5, #1]
4123		- mov r2, r3, lsr #16
4124		- mov r3, r3, lsr #24
	4352	+ lsr r2, r3, #16
	4353	+ lsr r3, r3, #24
4125	4354	strb r2, [r5, #2]
4126	4355	strb r3, [r5, #3]
4127		- ldmfd sp!, {r4, r5, r6, pc}
	4356	+ pop {r4, r5, r6, pc}
4128	4357	.fnend
4129	4358	.size NandcCopy1KB, .-NandcCopy1KB
4130	4359	.align 2
4131	4360	.global NandcXferData
	4361	+ .syntax unified
	4362	+ .arm
	4363	+ .fpu softvfp
4132	4364	.type NandcXferData, %function
4133	4365	NandcXferData:
4134	4366	.fnstart
4135	4367	@ args = 4, pretend = 0, frame = 80
4136	4368	@ frame_needed = 0, uses_anonymous_args = 0
4137		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	4369	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
4138	4370	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
4139		- mov fp, r3
4140		- ldr r3, .L784
	4371	+ mov r8, r3
	4372	+ ldr r3, .L797
	4373	+ tst r8, #63
4141	4374	.pad #92
4142	4375	sub sp, sp, #92
4143		- tst fp, #63
4144		- mov r10, r0
4145		- add r3, r3, r0, asl #3
4146		- mov r7, r1
4147		- mov r8, r2
4148		- ldr r5, [sp, #128]
4149		- ldr r9, [r3, #12]
4150		- bne .L737
4151		- cmp r5, #0
4152		- bne .L738
4153		- add r0, sp, #24
4154		- mov r1, #255
4155		- mov r2, #64
4156		- bl ftl_memset
4157		- add r5, sp, #24
4158		-.L738:
4159		- mov r0, r10
4160		- mov r1, r7
4161		- mov r2, r8
4162		- mov r3, #0
4163		- str fp, [sp]
4164		- str r5, [sp, #4]
4165		- bl NandcXferStart
4166		- mov r0, r10
4167		- mov r1, r7
4168		- bl NandcXferComp
4169		- cmp r7, #0
4170		- movne r6, #0
4171		- bne .L739
4172		- ldr r4, .L784+4
4173		- mov r1, r8, lsr #1
4174		- mov r2, r7
4175		- ldr r3, [r4, #-1804]
4176		- cmp r3, #25
4177		- mov r3, r7
4178		- movcc ip, #64
4179		- movcs ip, #128
4180		-.L741:
4181		- cmp r2, r1
4182		- add r5, r5, #4
4183		- add r0, r3, ip
4184		- bcs .L782
4185		- ldr lr, [r4, #-1836]
4186		- mov r3, r3, lsr #2
4187		- add r2, r2, #1
4188		- ldr r3, [lr, r3, asl #2]
4189		- mov lr, r3, lsr #8
4190		- strb r3, [r5, #-4]
4191		- strb lr, [r5, #-3]
4192		- mov lr, r3, lsr #16
4193		- mov r3, r3, lsr #24
4194		- strb lr, [r5, #-2]
4195		- strb r3, [r5, #-1]
4196		- mov r3, r0
4197		- b .L741
4198		-.L782:
4199		- ldr r0, [r4, #-1804]
4200		- mov r2, #0
4201		- ldr r1, [r4, #-1852]
4202		- mov r8, r8, lsr #2
4203		- mov r6, r2
4204		-.L743:
4205		- cmp r2, r8
4206		- bcs .L739
4207		- cmp r0, #0
4208		- beq .L739
4209		- add r3, r2, #8
4210		- ldr r3, [r9, r3, asl #2]
4211		- str r3, [sp, #20]
4212		- ldr r3, [sp, #20]
4213		- tst r3, #4
4214		- bne .L767
4215		- ldr r4, [sp, #20]
4216		- ubfx r4, r4, #15, #1
4217		- cmp r4, #0
4218		- bne .L767
4219		- cmp r1, #5
4220		- bls .L745
4221		- ldr ip, [sp, #20]
4222		- ldr r4, [sp, #20]
4223		- ldr r3, [sp, #20]
4224		- ubfx ip, ip, #3, #5
4225		- ldr lr, [sp, #20]
4226		- ubfx r4, r4, #27, #1
4227		- ubfx r3, r3, #16, #5
4228		- ubfx lr, lr, #29, #1
4229		- orr ip, ip, r4, asl #5
4230		- orr r3, r3, lr, asl #5
4231		- cmp ip, r3
4232		- ldr r3, [sp, #20]
4233		- ldrhi r4, [sp, #20]
4234		- ubfxhi r3, r3, #3, #5
4235		- ldrls r4, [sp, #20]
4236		- ubfxls r3, r3, #16, #5
4237		- ubfxhi r4, r4, #27, #1
4238		- ubfxls r4, r4, #29, #1
4239		- b .L781
4240		-.L745:
4241		- cmp r1, #3
4242		- bls .L747
4243		- ldr ip, [sp, #20]
4244		- ldr r4, [sp, #20]
4245		- ldr r3, [sp, #20]
4246		- ubfx ip, ip, #3, #5
4247		- ldr lr, [sp, #20]
4248		- ubfx r4, r4, #28, #1
4249		- ubfx r3, r3, #16, #5
4250		- ubfx lr, lr, #30, #1
4251		- orr ip, ip, r4, asl #5
4252		- orr r3, r3, lr, asl #5
4253		- cmp ip, r3
4254		- bls .L748
4255		- ldr r3, [sp, #20]
4256		- ldr r4, [sp, #20]
4257		- ubfx r3, r3, #3, #5
4258		- ubfx r4, r4, #28, #1
4259		-.L781:
4260		- orr r4, r3, r4, asl #5
4261		- b .L747
4262		-.L748:
4263		- ldr r5, [sp, #20]
4264		- ldr r4, [sp, #20]
4265		- ubfx r5, r5, #16, #5
4266		- ubfx r4, r4, #30, #1
4267		- orr r4, r5, r4, asl #5
4268		-.L747:
4269		- cmp r6, r4
4270		- movcc r6, r4
4271		- b .L744
4272		-.L767:
4273		- mvn r6, #0
4274		-.L744:
4275		- add r2, r2, #1
4276		- b .L743
4277		-.L739:
4278		- mov r3, #0
4279		- str r3, [r9, #16]
4280		- b .L750
4281		-.L737:
4282		- cmp r1, #1
4283		- mov r4, #0
4284		- bne .L779
4285		- mov r6, r4
4286		-.L751:
4287		- cmp r4, r8
4288		- bcs .L783
4289		- cmp fp, #0
4290		- and ip, r4, #3
4291		- addne r3, fp, r4, asl #9
4292		- mov r0, r9
4293		- moveq r3, fp
4294		- cmp r5, #0
4295		- mov r1, #1
4296		- str ip, [sp, #8]
4297		- movne r2, #2
4298		- moveq r2, #0
4299		- mla r2, r4, r2, r5
4300		- add r4, r4, #2
4301		- str r2, [sp]
4302		- mov r2, ip
4303		- bl NandcCopy1KB
4304		- mov r0, r10
4305		- mov r1, #1
4306		- mov r2, #2
4307		- ldr ip, [sp, #8]
4308		- str r6, [sp]
4309		- str r6, [sp, #4]
4310		- mov r3, ip
4311		- bl NandcXferStart
4312		- mov r0, r10
4313		- mov r1, #1
4314		- bl NandcXferComp
4315		- b .L751
4316		-.L783:
4317		- mov r6, #0
4318		- b .L750
4319		-.L779:
4320		- str r4, [sp]
4321		- mov r1, r4
4322		- str r4, [sp, #4]
4323		- mov r2, #2
4324		- mov r3, r4
4325		- mov r6, r4
4326		- bl NandcXferStart
4327		- str fp, [sp, #8]
4328		-.L756:
4329		- cmp r4, r8
4330		- bcs .L750
4331		- mov r0, r10
4332		- mov r1, r7
4333		- bl NandcXferComp
4334		- ldr r3, [r9, #32]
4335		- add ip, r4, #2
4336		- cmp ip, r8
4337		- str r3, [sp, #20]
4338		- bcs .L757
4339		- mov r3, #0
4340		- mov r0, r10
4341		- str r3, [sp]
4342		- mov r1, r3
4343		- str r3, [sp, #4]
4344		- mov r2, #2
4345		- and r3, ip, #3
4346		- str ip, [sp, #12]
4347		- bl NandcXferStart
4348		- ldr ip, [sp, #12]
4349		-.L757:
4350		- ldr r3, [sp, #20]
4351		- tst r3, #4
4352		- mvnne r6, #0
	4376	+ mov r7, r0
	4377	+ mov r5, r1
	4378	+ str r2, [sp, #8]
	4379	+ ldr r4, [sp, #128]
	4380	+ ldr r6, [r3, r0, lsl #3]
4353	4381	bne .L758
4354		- ldr r2, [sp, #20]
4355		- ldr r3, [sp, #20]
4356		- ubfx r2, r2, #3, #5
4357		- ubfx r3, r3, #27, #1
4358		- orr r3, r2, r3, asl #5
4359		- cmp r6, r3
4360		- movcc r6, r3
4361		-.L758:
4362		- cmp fp, #0
4363		- ldr r3, [sp, #8]
4364		- sub r2, ip, #2
4365		- mov r0, r9
4366		- moveq r3, #0
	4382	+ cmp r4, #0
	4383	+ bne .L759
	4384	+ mov r2, #64
	4385	+ mov r1, #255
	4386	+ add r0, sp, #24
	4387	+ bl ftl_memset
	4388	+ add r4, sp, #24
	4389	+.L759:
	4390	+ mov r3, #0
	4391	+ ldr r2, [sp, #8]
	4392	+ mov r1, r5
	4393	+ mov r0, r7
	4394	+ str r4, [sp, #4]
	4395	+ str r8, [sp]
	4396	+ bl NandcXferStart
	4397	+ mov r1, r5
	4398	+ mov r0, r7
	4399	+ bl NandcXferComp
4367	4400	cmp r5, #0
4368		- and r2, r2, #3
4369		- str ip, [sp, #12]
4370		- movne r1, #2
4371		- moveq r1, #0
4372		- mla r4, r4, r1, r5
4373		- mov r1, #0
4374		- str r4, [sp]
4375		- bl NandcCopy1KB
4376		- ldr ip, [sp, #12]
4377		- ldr r3, [sp, #8]
4378		- mov r4, ip
4379		- add r3, r3, #1024
4380		- str r3, [sp, #8]
4381		- b .L756
4382		-.L750:
4383		- ldr r3, .L784+4
4384		- clz r7, r7
4385		- mov r7, r7, lsr #5
4386		- ldr r3, [r3, #-1852]
	4401	+ movne r9, #0
	4402	+ bne .L760
	4403	+ ldr r3, .L797+4
	4404	+ mov r1, r5
	4405	+ ldr r2, [r3, #-1800]
	4406	+ cmp r2, #25
	4407	+ ldr r2, [sp, #8]
	4408	+ movcc lr, #64
	4409	+ movcs lr, #128
	4410	+ lsr r0, r2, #1
	4411	+ mov r2, r5
	4412	+.L762:
	4413	+ cmp r1, r0
	4414	+ add r4, r4, #4
	4415	+ add ip, lr, r2
	4416	+ bcc .L763
	4417	+ ldr r2, [sp, #8]
	4418	+ ldr r0, [r3, #-1800]
	4419	+ ldr r1, [r3, #-1848]
	4420	+ lsr ip, r2, #2
	4421	+ mov r2, #0
	4422	+ mov r9, r2
	4423	+.L764:
	4424	+ cmp r2, ip
	4425	+ bcs .L760
	4426	+ cmp r0, #0
	4427	+ bne .L770
	4428	+.L760:
	4429	+ mov r3, #0
	4430	+ str r3, [r6, #16]
	4431	+.L771:
	4432	+ ldr r3, .L797+4
	4433	+ ldr r3, [r3, #-1848]
4387	4434	cmp r3, #5
4388		- movls r7, #0
4389		- cmp r7, #0
4390		- beq .L762
4391		- ldr r3, [r9]
	4435	+ movls r3, #0
	4436	+ movhi r3, #1
	4437	+ cmp r5, #0
	4438	+ movne r3, #0
	4439	+ cmp r3, #0
	4440	+ beq .L757
	4441	+ ldr r3, [r6]
4392	4442	and r2, r3, #139264
4393	4443	cmp r2, #139264
	4444	+ mvneq r9, #0
4394	4445	orreq r3, r3, #131072
4395		- streq r3, [r9]
4396		- mvneq r6, #0
4397		-.L762:
4398		- mov r0, r6
	4446	+ streq r3, [r6]
	4447	+.L757:
	4448	+ mov r0, r9
4399	4449	add sp, sp, #92
4400	4450	@ sp needed
4401		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
4402		-.L785:
	4451	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	4452	+.L763:
	4453	+ ldr r7, [r3, #-1832]
	4454	+ bic r2, r2, #3
	4455	+ add r1, r1, #1
	4456	+ ldr r2, [r7, r2]
	4457	+ strb r2, [r4, #-4]
	4458	+ lsr r7, r2, #8
	4459	+ strb r7, [r4, #-3]
	4460	+ lsr r7, r2, #16
	4461	+ lsr r2, r2, #24
	4462	+ strb r7, [r4, #-2]
	4463	+ strb r2, [r4, #-1]
	4464	+ mov r2, ip
	4465	+ b .L762
	4466	+.L770:
	4467	+ add r3, r2, #8
	4468	+ ldr r3, [r6, r3, lsl #2]
	4469	+ str r3, [sp, #20]
	4470	+ ldr r3, [sp, #20]
	4471	+ tst r3, #4
	4472	+ bne .L786
	4473	+ ldr r3, [sp, #20]
	4474	+ ubfx r3, r3, #15, #1
	4475	+ cmp r3, #0
	4476	+ bne .L786
	4477	+ cmp r1, #5
	4478	+ bls .L766
	4479	+ ldr lr, [sp, #20]
	4480	+ ldr r7, [sp, #20]
	4481	+ ldr r3, [sp, #20]
	4482	+ ldr r4, [sp, #20]
	4483	+ ubfx lr, lr, #3, #5
	4484	+ ubfx r7, r7, #27, #1
	4485	+ ubfx r3, r3, #16, #5
	4486	+ orr lr, lr, r7, lsl #5
	4487	+ ubfx r4, r4, #29, #1
	4488	+ orr r3, r3, r4, lsl #5
	4489	+ cmp lr, r3
	4490	+ ldr r3, [sp, #20]
	4491	+ ldrhi lr, [sp, #20]
	4492	+ ldrls lr, [sp, #20]
	4493	+ ubfxhi r3, r3, #3, #5
	4494	+ ubfxls r3, r3, #16, #5
	4495	+ ubfxhi lr, lr, #27, #1
	4496	+ ubfxls lr, lr, #29, #1
	4497	+.L796:
	4498	+ orr r3, r3, lr, lsl #5
	4499	+.L768:
	4500	+ cmp r9, r3
	4501	+ movcc r9, r3
	4502	+.L765:
	4503	+ add r2, r2, #1
	4504	+ b .L764
	4505	+.L766:
	4506	+ cmp r1, #3
	4507	+ bls .L768
	4508	+ ldr lr, [sp, #20]
	4509	+ ldr r7, [sp, #20]
	4510	+ ldr r3, [sp, #20]
	4511	+ ldr r4, [sp, #20]
	4512	+ ubfx lr, lr, #3, #5
	4513	+ ubfx r7, r7, #28, #1
	4514	+ ubfx r3, r3, #16, #5
	4515	+ orr lr, lr, r7, lsl #5
	4516	+ ubfx r4, r4, #30, #1
	4517	+ orr r3, r3, r4, lsl #5
	4518	+ cmp lr, r3
	4519	+ ldr r3, [sp, #20]
	4520	+ ldrhi lr, [sp, #20]
	4521	+ ldrls lr, [sp, #20]
	4522	+ ubfxhi r3, r3, #3, #5
	4523	+ ubfxls r3, r3, #16, #5
	4524	+ ubfxhi lr, lr, #28, #1
	4525	+ ubfxls lr, lr, #30, #1
	4526	+ b .L796
	4527	+.L786:
	4528	+ mvn r9, #0
	4529	+ b .L765
	4530	+.L758:
	4531	+ cmp r1, #1
	4532	+ bne .L772
	4533	+ mov r9, #0
	4534	+ cmp r4, #0
	4535	+ mov r10, r9
	4536	+ movne r3, #4
	4537	+ moveq r3, #0
	4538	+ str r3, [sp, #12]
	4539	+.L773:
	4540	+ ldr r3, [sp, #8]
	4541	+ cmp r9, r3
	4542	+ movcs r9, #0
	4543	+ bcs .L771
	4544	+.L775:
	4545	+ cmp r8, #0
	4546	+ and fp, r9, #3
	4547	+ addne r3, r8, r9, lsl #9
	4548	+ moveq r3, r8
	4549	+ str r4, [sp]
	4550	+ mov r2, fp
	4551	+ mov r1, #1
	4552	+ mov r0, r6
	4553	+ bl NandcCopy1KB
	4554	+ mov r3, fp
	4555	+ mov r2, #2
	4556	+ mov r1, #1
	4557	+ mov r0, r7
	4558	+ str r10, [sp, #4]
	4559	+ add r9, r9, #2
	4560	+ str r10, [sp]
	4561	+ bl NandcXferStart
	4562	+ mov r1, #1
	4563	+ mov r0, r7
	4564	+ bl NandcXferComp
	4565	+ ldr r3, [sp, #12]
	4566	+ add r4, r4, r3
	4567	+ b .L773
	4568	+.L772:
	4569	+ mov r10, #0
	4570	+ mov r2, #2
	4571	+ mov r3, r10
	4572	+ str r10, [sp, #4]
	4573	+ str r10, [sp]
	4574	+ mov r1, r10
	4575	+ bl NandcXferStart
	4576	+ mov fp, r8
	4577	+ cmp r4, r10
	4578	+ mov r9, r10
	4579	+ movne r3, #4
	4580	+ moveq r3, r10
	4581	+ str r3, [sp, #12]
	4582	+.L776:
	4583	+ ldr r3, [sp, #8]
	4584	+ cmp r10, r3
	4585	+ bcs .L771
	4586	+ mov r1, r5
	4587	+ mov r0, r7
	4588	+ bl NandcXferComp
	4589	+ ldr r3, [r6, #32]
	4590	+ add r10, r10, #2
	4591	+ str r3, [sp, #20]
	4592	+ ldr r3, [sp, #8]
	4593	+ cmp r3, r10
	4594	+ bls .L777
	4595	+ mov r3, #0
	4596	+ mov r2, #2
	4597	+ str r3, [sp, #4]
	4598	+ mov r1, #0
	4599	+ str r3, [sp]
	4600	+ mov r0, r7
	4601	+ and r3, r10, #3
	4602	+ bl NandcXferStart
	4603	+.L777:
	4604	+ ldr r3, [sp, #20]
	4605	+ tst r3, #4
	4606	+ mvnne r9, #0
	4607	+ bne .L778
	4608	+ ldr r3, [sp, #20]
	4609	+ ldr r2, [sp, #20]
	4610	+ ubfx r3, r3, #3, #5
	4611	+ ubfx r2, r2, #27, #1
	4612	+ orr r3, r3, r2, lsl #5
	4613	+ cmp r9, r3
	4614	+ movcc r9, r3
	4615	+.L778:
	4616	+ cmp r8, #0
	4617	+ sub r2, r10, #2
	4618	+ movne r3, fp
	4619	+ str r4, [sp]
	4620	+ moveq r3, #0
	4621	+ and r2, r2, #3
	4622	+ mov r1, #0
	4623	+ mov r0, r6
	4624	+ bl NandcCopy1KB
	4625	+ ldr r3, [sp, #12]
	4626	+ add fp, fp, #1024
	4627	+ add r4, r4, r3
	4628	+ b .L776
	4629	+.L798:
4403	4630	.align 2
4404		-.L784:
	4631	+.L797:
4405	4632	.word .LANCHOR0
4406	4633	.word .LANCHOR2
4407	4634	.fnend
4408	4635	.size NandcXferData, .-NandcXferData
4409	4636	.align 2
4410	4637	.global FlashReadRawPage
	4638	+ .syntax unified
	4639	+ .arm
	4640	+ .fpu softvfp
4411	4641	.type FlashReadRawPage, %function
4412	4642	FlashReadRawPage:
4413	4643	.fnstart
4414	4644	@ args = 0, pretend = 0, frame = 0
4415	4645	@ frame_needed = 0, uses_anonymous_args = 0
4416		- stmfd sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
	4646	+ push {r0, r1, r4, r5, r6, r7, r8, lr}
4417	4647	.save {r4, r5, r6, r7, r8, lr}
4418	4648	.pad #8
4419	4649	mov r8, r3
4420		- ldr r3, .L789
	4650	+ ldr r3, .L802
4421	4651	subs r4, r0, #0
4422	4652	mov r6, r1
4423	4653	mov r7, r2
4424		- ldrb r5, [r3, #265] @ zero_extendqisi2
4425		- bne .L787
4426		- ldr r2, .L789+4
4427		- ldrb r3, [r2, #1] @ zero_extendqisi2
4428		- ldr r2, [r2, #4]
4429		- mul r2, r2, r3
4430		- cmp r1, r2
4431		- movcc r5, #4
4432		-.L787:
	4654	+ ldrb r5, [r3, #477] @ zero_extendqisi2
	4655	+ bne .L800
	4656	+ ldr r1, .L802+4
	4657	+ ldrb r3, [r1, #37] @ zero_extendqisi2
	4658	+ ldr r0, [r1, #40]
	4659	+ mul r0, r0, r3
	4660	+ cmp r0, r6
	4661	+ movhi r5, #4
	4662	+.L800:
4433	4663	mov r0, r4
4434	4664	bl NandcWaitFlashReady
4435	4665	mov r0, r4
..	..	@@ -4439,184 +4669,179 @@
4439	4669	bl FlashReadCmd
4440	4670	mov r0, r4
4441	4671	bl NandcWaitFlashReady
4442		- mov r2, r5
4443		- mov r1, #0
4444	4672	mov r3, r7
4445		- mov r0, r4
	4673	+ mov r2, r5
4446	4674	str r8, [sp]
	4675	+ mov r1, #0
	4676	+ mov r0, r4
4447	4677	bl NandcXferData
4448		- mov r5, r0
	4678	+ mov r1, r0
4449	4679	mov r0, r4
4450	4680	bl NandcFlashDeCs
4451		- mov r0, r5
	4681	+ mov r0, r1
4452	4682	add sp, sp, #8
4453	4683	@ sp needed
4454		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
4455		-.L790:
	4684	+ pop {r4, r5, r6, r7, r8, pc}
	4685	+.L803:
4456	4686	.align 2
4457		-.L789:
	4687	+.L802:
4458	4688	.word .LANCHOR1
4459	4689	.word .LANCHOR0
4460	4690	.fnend
4461	4691	.size FlashReadRawPage, .-FlashReadRawPage
4462	4692	.align 2
4463	4693	.global FlashDdrTunningRead
	4694	+ .syntax unified
	4695	+ .arm
	4696	+ .fpu softvfp
4464	4697	.type FlashDdrTunningRead, %function
4465	4698	FlashDdrTunningRead:
4466	4699	.fnstart
4467	4700	@ args = 4, pretend = 0, frame = 16
4468	4701	@ frame_needed = 0, uses_anonymous_args = 0
4469		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	4702	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
4470	4703	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
4471	4704	mov r7, r3
4472		- ldr r4, .L818
	4705	+ ldr r4, .L830
4473	4706	.pad #20
4474	4707	sub sp, sp, #20
4475		- mov r10, r0
4476	4708	mov fp, r2
4477		- str r1, [sp]
4478		- ldr r3, [r4, #-2808]
	4709	+ stm sp, {r0, r1}
	4710	+ ldr r3, [r4, #-2804]
4479	4711	ldr r3, [r3, #304]
4480		- str r3, [sp, #8]
4481		- ldr r3, [r4, #-1852]
	4712	+ str r3, [sp, #12]
	4713	+ ldr r3, [r4, #-1848]
4482	4714	cmp r3, #8
4483	4715	ldr r3, [sp, #56]
4484		- movcc r9, #6
4485		- movcs r9, #12
	4716	+ movcc r10, #6
	4717	+ movcs r10, #12
4486	4718	cmp r3, #0
4487		- moveq r6, #1024
4488		- beq .L793
	4719	+ moveq r5, #1024
	4720	+ beq .L806
4489	4721	mov r0, #1
4490	4722	bl FlashSetInterfaceMode
4491	4723	mov r0, #1
4492	4724	bl NandcSetMode
4493		- mov r0, r10
	4725	+ ldr r0, [sp]
4494	4726	bl FlashReset
4495		- mov r2, fp
4496	4727	mov r3, r7
4497		- mov r0, r10
4498		- ldr r1, [sp]
	4728	+ mov r2, fp
	4729	+ ldm sp, {r0, r1}
4499	4730	bl FlashReadRawPage
4500		- mov r6, r0
4501		- ldrb r0, [r4, #-1875] @ zero_extendqisi2
	4731	+ mov r5, r0
	4732	+ ldrb r0, [r4, #-1871] @ zero_extendqisi2
4502	4733	bl FlashSetInterfaceMode
4503		- ldrb r0, [r4, #-1875] @ zero_extendqisi2
	4734	+ ldrb r0, [r4, #-1871] @ zero_extendqisi2
4504	4735	bl NandcSetMode
4505		- cmn r6, #1
4506		- bne .L794
4507		-.L803:
4508		- mvn r6, #0
4509		- b .L795
4510		-.L794:
4511		- ldr r0, .L818+4
4512		- mov r2, r6
4513		- ldr r1, [sp]
	4736	+ cmn r5, #1
	4737	+ bne .L807
	4738	+.L816:
	4739	+ mvn r5, #0
	4740	+.L804:
	4741	+ mov r0, r5
	4742	+ add sp, sp, #20
	4743	+ @ sp needed
	4744	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	4745	+.L807:
	4746	+ mov r2, r5
	4747	+ ldr r1, [sp, #4]
	4748	+ ldr r0, .L830+4
4514	4749	bl printk
4515		- cmp r6, #9
4516		- bhi .L796
4517		- ldr r3, .L818+8
4518		- add r3, r3, r10, asl #3
4519		- ldr r3, [r3, #12]
	4750	+ cmp r5, #9
	4751	+ bhi .L809
	4752	+ ldr r2, [sp]
	4753	+ ldr r3, .L830+8
	4754	+ ldr r3, [r3, r2, lsl #3]
4520	4755	ldr r2, [r3, #3840]
4521	4756	ldr r2, [r3]
4522	4757	orr r2, r2, #131072
4523	4758	str r2, [r3]
4524		-.L796:
4525		- ldr r3, [r4, #-1800]
	4759	+.L809:
	4760	+ ldr r3, [r4, #-1796]
4526	4761	add r3, r3, #1
4527		- str r3, [r4, #-1800]
4528	4762	cmp r3, #2048
4529		- bcc .L795
4530		- ldr r3, .L818
4531		- mov r7, #0
4532		- mov fp, r7
4533		- str r7, [r3, #-1800]
4534		-.L793:
4535		- mov r4, #0
	4763	+ str r3, [r4, #-1796]
	4764	+ movcs r7, #0
	4765	+ strcs r7, [r4, #-1796]
	4766	+ movcs fp, r7
	4767	+ bcc .L804
	4768	+.L806:
	4769	+ mov r9, #0
4536	4770	mvn r8, #0
4537		- mov ip, r4
4538		- mov r5, r4
4539		- str r4, [sp, #4]
4540		-.L801:
4541		- uxtb r0, r9
4542		- str ip, [sp, #12]
	4771	+ mov r6, r9
	4772	+ mov r4, r9
	4773	+ str r9, [sp, #8]
	4774	+.L814:
	4775	+ uxtb r0, r10
4543	4776	bl NandcSetDdrPara
4544	4777	mov r3, r7
4545		- mov r0, r10
4546	4778	mov r2, fp
4547		- ldr r1, [sp]
	4779	+ ldm sp, {r0, r1}
4548	4780	bl FlashReadRawPage
4549		- add r3, r6, #1
	4781	+ add r3, r5, #1
4550	4782	cmp r0, r3
4551		- ldr ip, [sp, #12]
4552		- bhi .L797
	4783	+ bhi .L810
4553	4784	cmp r0, #2
4554		- bhi .L807
4555		- add r5, r5, #1
4556		- cmp r5, #9
4557		- bls .L807
4558		- rsb r4, r5, r9
4559		- mov r6, r0
	4785	+ bhi .L820
	4786	+ add r4, r4, #1
	4787	+ cmp r4, #9
	4788	+ bls .L820
	4789	+ mov r3, r6
	4790	+ mov r5, r0
	4791	+ sub r6, r10, r4
4560	4792	mov r8, #0
4561		- b .L799
4562		-.L797:
4563		- ldr r3, [sp, #4]
4564		- cmp r3, r5
4565		- bcs .L808
4566		- cmp r5, #7
4567		- rsb ip, r5, r4
4568		- bhi .L809
4569		- str r5, [sp, #4]
4570		- b .L808
4571		-.L807:
4572		- mov r8, #0
4573		- mov r4, r9
4574		- mov r6, r0
4575		- mov r7, r8
4576		- mov fp, r8
4577		- b .L798
4578		-.L808:
4579		- mov r5, #0
4580		-.L798:
4581		- add r9, r9, #2
4582		- cmp r9, #69
4583		- bls .L801
4584		-.L799:
4585		- ldr r3, [sp, #4]
4586		- cmp r3, r5
4587		- movcs r4, ip
4588		- b .L800
4589		-.L809:
4590		- mov r4, ip
4591		-.L800:
4592		- cmp r4, #0
4593		- beq .L802
4594		- ldr r0, .L818+12
4595		- mov r1, r4
	4793	+.L812:
	4794	+ ldr r2, [sp, #8]
	4795	+ cmp r4, r2
	4796	+ movls r6, r3
	4797	+.L813:
	4798	+ cmp r6, #0
	4799	+ beq .L815
	4800	+ mov r1, r6
	4801	+ ldr r0, .L830+12
4596	4802	bl printk
4597		- uxtb r0, r4
	4803	+ uxtb r0, r6
4598	4804	bl NandcSetDdrPara
4599		-.L802:
	4805	+.L815:
4600	4806	cmn r8, #1
4601		- bne .L795
4602		- ldr r0, .L818+16
4603		- mov r1, r10
4604		- ldr r2, [sp]
	4807	+ bne .L804
	4808	+ ldm sp, {r1, r2}
	4809	+ ldr r0, .L830+16
4605	4810	bl printk
4606	4811	ldr r3, [sp, #56]
4607	4812	cmp r3, #0
4608		- beq .L803
4609		- ldr r3, [sp, #8]
	4813	+ beq .L816
	4814	+ ldr r3, [sp, #12]
4610	4815	ubfx r0, r3, #8, #8
4611	4816	bl NandcSetDdrPara
4612		-.L795:
4613		- mov r0, r6
4614		- add sp, sp, #20
4615		- @ sp needed
4616		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
4617		-.L819:
	4817	+ b .L804
	4818	+.L810:
	4819	+ ldr r3, [sp, #8]
	4820	+ cmp r4, r3
	4821	+ bls .L821
	4822	+ cmp r4, #7
	4823	+ sub r6, r9, r4
	4824	+ bhi .L813
	4825	+ str r4, [sp, #8]
	4826	+.L821:
	4827	+ mov r4, #0
	4828	+ b .L811
	4829	+.L820:
	4830	+ mov r8, #0
	4831	+ mov r9, r10
	4832	+ mov r5, r0
	4833	+ mov r7, r8
	4834	+ mov fp, r8
	4835	+.L811:
	4836	+ add r10, r10, #2
	4837	+ cmp r10, #69
	4838	+ bls .L814
	4839	+ mov r3, r6
	4840	+ mov r6, r9
	4841	+ b .L812
	4842	+.L831:
4618	4843	.align 2
4619		-.L818:
	4844	+.L830:
4620	4845	.word .LANCHOR2
4621	4846	.word .LC7
4622	4847	.word .LANCHOR0
..	..	@@ -4626,109 +4851,108 @@
4626	4851	.size FlashDdrTunningRead, .-FlashDdrTunningRead
4627	4852	.align 2
4628	4853	.global FlashReadPage
	4854	+ .syntax unified
	4855	+ .arm
	4856	+ .fpu softvfp
4629	4857	.type FlashReadPage, %function
4630	4858	FlashReadPage:
4631	4859	.fnstart
4632	4860	@ args = 0, pretend = 0, frame = 0
4633	4861	@ frame_needed = 0, uses_anonymous_args = 0
4634		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	4862	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
4635	4863	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
4636	4864	.pad #12
4637	4865	mov r5, r0
4638		- mov r6, r1
	4866	+ mov r7, r1
4639	4867	mov r8, r2
4640		- mov r7, r3
	4868	+ mov r9, r3
4641	4869	bl FlashReadRawPage
4642		- ldr r10, .L841
4643	4870	cmn r0, #1
4644	4871	mov r4, r0
4645		- bne .L821
4646		- ldr r9, .L841+4
4647		- ldrb fp, [r9, #8] @ zero_extendqisi2
	4872	+ ldr r6, .L852
	4873	+ bne .L833
	4874	+ ldr r10, .L852+4
	4875	+ ldrb fp, [r10, #44] @ zero_extendqisi2
4648	4876	cmp fp, #0
4649		- bne .L822
4650		-.L824:
4651		- ldrb r3, [r10, #-1860] @ zero_extendqisi2
4652		- ldr r9, .L841
	4877	+ bne .L834
	4878	+.L836:
	4879	+ ldrb r3, [r6, #-1856] @ zero_extendqisi2
4653	4880	cmp r3, #0
4654		- beq .L821
4655		- b .L840
4656		-.L822:
4657		- mov r3, #0
4658		- mov r0, r5
4659		- strb r3, [r9, #8]
4660		- mov r1, r6
	4881	+ beq .L833
	4882	+ ldr r3, [r6, #-2804]
4661	4883	mov r2, r8
4662		- mov r3, r7
4663		- bl FlashReadRawPage
4664		- strb fp, [r9, #8]
4665		- cmn r0, #1
4666		- movne r4, r0
4667		- beq .L824
4668		- b .L821
4669		-.L840:
4670		- ldr r3, [r9, #-2808]
	4884	+ mov r1, r7
4671	4885	mov r0, r5
4672		- mov r1, r6
4673		- mov r2, r8
4674		- ldr fp, [r3, #304]
	4886	+ ldr r10, [r3, #304]
4675	4887	mov r3, #1
4676	4888	str r3, [sp]
4677		- mov r3, r7
	4889	+ mov r3, r9
4678	4890	bl FlashDdrTunningRead
4679	4891	cmn r0, #1
4680	4892	mov r4, r0
4681		- beq .L825
4682		- ldrb r3, [r9, #-2743] @ zero_extendqisi2
	4893	+ beq .L837
	4894	+ ldrb r3, [r6, #-2739] @ zero_extendqisi2
4683	4895	cmp r0, r3, lsr #1
4684		- bls .L821
4685		-.L825:
4686		- ubfx r0, fp, #8, #8
	4896	+ bls .L833
	4897	+.L837:
	4898	+ ubfx r0, r10, #8, #8
4687	4899	bl NandcSetDdrPara
4688		-.L821:
4689		- ldr ip, [r10, #-1796]
4690		- ldr r9, .L841
4691		- adds r3, ip, #0
	4900	+ b .L833
	4901	+.L834:
	4902	+ mov r3, #0
	4903	+ mov r2, r8
	4904	+ strb r3, [r10, #44]
	4905	+ mov r1, r7
	4906	+ mov r3, r9
	4907	+ mov r0, r5
	4908	+ bl FlashReadRawPage
	4909	+ cmn r0, #1
	4910	+ strb fp, [r10, #44]
	4911	+ movne r4, r0
	4912	+ beq .L836
	4913	+.L833:
	4914	+ ldr r10, [r6, #-1792]
	4915	+ adds r3, r10, #0
4692	4916	movne r3, #1
4693	4917	cmn r4, #1
4694	4918	movne r3, #0
4695	4919	cmp r3, #0
4696		- beq .L826
4697		- mov r1, r6
	4920	+ beq .L832
	4921	+ mov r3, r9
4698	4922	mov r2, r8
4699		- mov r3, r7
	4923	+ mov r1, r7
4700	4924	mov r0, r5
4701		- blx ip
4702		- mov r2, r5
4703		- mov r3, r6
	4925	+ blx r10
	4926	+ mov r3, r7
4704	4927	mov r4, r0
4705		- ldr r0, .L841+8
4706		- mov r1, r4
	4928	+ mov r1, r0
	4929	+ mov r2, r5
	4930	+ ldr r0, .L852+8
4707	4931	bl printk
4708	4932	cmn r4, #1
4709		- bne .L826
4710		- ldrb r3, [r9, #-2744] @ zero_extendqisi2
	4933	+ bne .L832
	4934	+ ldrb r3, [r6, #-2740] @ zero_extendqisi2
4711	4935	cmp r3, #0
4712		- beq .L826
	4936	+ beq .L832
4713	4937	mov r0, r5
4714	4938	bl flash_enter_slc_mode
4715		- ldr ip, [r9, #-1796]
4716		- mov r0, r5
4717		- mov r1, r6
	4939	+ ldr r4, [r6, #-1792]
	4940	+ mov r3, r9
4718	4941	mov r2, r8
4719		- mov r3, r7
4720		- blx ip
	4942	+ mov r1, r7
	4943	+ mov r0, r5
	4944	+ blx r4
4721	4945	mov r4, r0
4722	4946	mov r0, r5
4723	4947	bl flash_exit_slc_mode
4724		-.L826:
	4948	+.L832:
4725	4949	mov r0, r4
4726	4950	add sp, sp, #12
4727	4951	@ sp needed
4728		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
4729		-.L842:
	4952	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	4953	+.L853:
4730	4954	.align 2
4731		-.L841:
	4955	+.L852:
4732	4956	.word .LANCHOR2
4733	4957	.word .LANCHOR0
4734	4958	.word .LC10
..	..	@@ -4736,356 +4960,368 @@
4736	4960	.size FlashReadPage, .-FlashReadPage
4737	4961	.align 2
4738	4962	.global FlashDdrParaScan
	4963	+ .syntax unified
	4964	+ .arm
	4965	+ .fpu softvfp
4739	4966	.type FlashDdrParaScan, %function
4740	4967	FlashDdrParaScan:
4741	4968	.fnstart
4742	4969	@ args = 0, pretend = 0, frame = 0
4743	4970	@ frame_needed = 0, uses_anonymous_args = 0
4744		- stmfd sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
	4971	+ push {r0, r1, r4, r5, r6, r7, r8, lr}
4745	4972	.save {r4, r5, r6, r7, r8, lr}
4746	4973	.pad #8
4747		- mov r7, r0
4748		- ldr r5, .L853
4749		- mov r6, r1
	4974	+ mov r6, r0
	4975	+ ldr r5, .L864
4750	4976	mov r4, #0
4751		- ldrb r0, [r5, #-1875] @ zero_extendqisi2
	4977	+ mov r7, r1
	4978	+ ldrb r0, [r5, #-1871] @ zero_extendqisi2
4752	4979	bl FlashSetInterfaceMode
4753		- ldrb r0, [r5, #-1875] @ zero_extendqisi2
	4980	+ ldrb r0, [r5, #-1871] @ zero_extendqisi2
4754	4981	bl NandcSetMode
4755		- mov r1, r6
4756		- mov r2, r4
4757	4982	mov r3, r4
4758		- mov r0, r7
	4983	+ mov r2, r4
	4984	+ mov r1, r7
4759	4985	str r4, [sp]
	4986	+ mov r0, r6
4760	4987	bl FlashDdrTunningRead
4761	4988	mov r3, r4
4762		- mov r1, r6
4763		- mov r2, r4
4764	4989	mov r8, r0
4765		- mov r0, r7
	4990	+ mov r2, r4
	4991	+ mov r1, r7
	4992	+ mov r0, r6
4766	4993	bl FlashReadRawPage
	4994	+ cmn r8, #1
	4995	+ cmnne r0, #1
4767	4996	mov r3, r5
4768		- cmn r0, #1
4769		- cmnne r8, #1
4770		- bne .L844
4771		- ldrb r2, [r5, #-1875] @ zero_extendqisi2
	4997	+ bne .L855
	4998	+ ldrb r2, [r5, #-1871] @ zero_extendqisi2
4772	4999	tst r2, #1
4773		- beq .L844
	5000	+ beq .L855
4774	5001	mov r0, #1
4775	5002	bl FlashSetInterfaceMode
4776	5003	mov r0, #1
4777	5004	bl NandcSetMode
4778		- strb r4, [r5, #-1860]
4779		- b .L845
4780		-.L844:
4781		- mov r2, #1
4782		- strb r2, [r3, #-1860]
4783		-.L845:
	5005	+ strb r4, [r5, #-1856]
	5006	+.L856:
4784	5007	mov r0, #0
4785	5008	add sp, sp, #8
4786	5009	@ sp needed
4787		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
4788		-.L854:
	5010	+ pop {r4, r5, r6, r7, r8, pc}
	5011	+.L855:
	5012	+ mov r2, #1
	5013	+ strb r2, [r3, #-1856]
	5014	+ b .L856
	5015	+.L865:
4789	5016	.align 2
4790		-.L853:
	5017	+.L864:
4791	5018	.word .LANCHOR2
4792	5019	.fnend
4793	5020	.size FlashDdrParaScan, .-FlashDdrParaScan
4794	5021	.align 2
4795	5022	.global FlashLoadPhyInfo
	5023	+ .syntax unified
	5024	+ .arm
	5025	+ .fpu softvfp
4796	5026	.type FlashLoadPhyInfo, %function
4797	5027	FlashLoadPhyInfo:
4798	5028	.fnstart
4799	5029	@ args = 0, pretend = 0, frame = 16
4800	5030	@ frame_needed = 0, uses_anonymous_args = 0
4801		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	5031	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
4802	5032	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	5033	+ mov r3, #60
4803	5034	.pad #20
4804	5035	sub sp, sp, #20
4805		- ldr r3, .L871
4806		- mov r4, #0
4807		- ldr r8, .L871+4
4808		- mov r9, #4
4809		- ldr r5, .L871+8
4810		- mvn r7, #0
4811		- ldr r0, [r3] @ unaligned
4812		- ldr r3, [r8, #4]
4813		- str r4, [r5, #-1788]
4814		- mov r6, r5
4815		- str r0, [sp, #12] @ unaligned
4816		- mov r0, r4
	5036	+ ldr r10, .L881
	5037	+ mov r5, #0
	5038	+ mov r7, #4
	5039	+ strb r3, [sp, #12]
	5040	+ mov r3, #40
	5041	+ strb r3, [sp, #13]
	5042	+ mov r3, #24
	5043	+ strb r3, [sp, #14]
	5044	+ mov r3, #16
	5045	+ ldr r4, .L881+4
	5046	+ mvn r6, #0
	5047	+ strb r3, [sp, #15]
	5048	+ mov r0, r5
	5049	+ ldr r3, [r10, #40]
	5050	+ sub r9, r4, #2720
	5051	+ str r5, [r4, #-1784]
	5052	+ sub r9, r9, #8
4817	5053	str r3, [sp, #4]
4818		- ldr r3, [r5, #-1868]
4819		- str r3, [r5, #-1792]
	5054	+ ldr r3, [r4, #-1864]
	5055	+ str r3, [r4, #-1788]
4820	5056	bl flash_enter_slc_mode
4821		-.L856:
4822		- add fp, r4, #1
4823		- mov r10, #0
4824		-.L858:
	5057	+.L867:
	5058	+ add fp, r5, #1
	5059	+ mov r8, #0
	5060	+.L869:
4825	5061	add r3, sp, #12
4826		- ldrb r0, [r3, r10] @ zero_extendqisi2
	5062	+ ldrb r0, [r3, r8] @ zero_extendqisi2
4827	5063	bl FlashBchSel
4828		- mov r0, #0
4829		- mov r1, r4
4830		- ldr r2, [r5, #-1868]
4831		- mov r3, r0
	5064	+ mov r3, #0
	5065	+ ldr r2, [r4, #-1864]
	5066	+ mov r1, r5
	5067	+ mov r0, r3
4832	5068	bl FlashReadRawPage
4833	5069	cmn r0, #1
4834		- bne .L857
4835		- mov r0, #0
	5070	+ bne .L868
	5071	+ mov r3, #0
	5072	+ ldr r2, [r4, #-1864]
4836	5073	mov r1, fp
4837		- ldr r2, [r6, #-1868]
4838		- mov r3, r0
	5074	+ mov r0, r3
4839	5075	bl FlashReadRawPage
4840	5076	cmn r0, #1
4841		- bne .L857
4842		- add r10, r10, #1
4843		- cmp r10, #4
4844		- beq .L859
4845		- b .L858
4846		-.L860:
4847		- add r0, fp, #12
4848		- movw r1, #2036
4849		- bl js_hash
4850		- ldr r3, [fp, #8]
4851		- cmp r3, r0
4852		- mvnne r7, #0
4853		- bne .L859
4854		- ldr r7, .L871+12
4855		- add r1, fp, #160
4856		- mov r2, #32
	5077	+ bne .L868
	5078	+ add r8, r8, #1
	5079	+ cmp r8, #4
	5080	+ bne .L869
	5081	+.L870:
	5082	+ ldr r3, [sp, #4]
	5083	+ subs r7, r7, #1
	5084	+ add r5, r5, r3
	5085	+ bne .L867
4857	5086	mov r0, r7
4858		- bl ftl_memcpy
4859		- ldr r1, [r6, #-1792]
	5087	+ b .L880
	5088	+.L871:
	5089	+ movw r1, #2036
	5090	+ add r0, r8, #12
	5091	+ bl js_hash
	5092	+ ldr r3, [r8, #8]
	5093	+ cmp r3, r0
	5094	+ mvnne r6, #0
	5095	+ bne .L870
	5096	+ ldr r6, .L881+8
4860	5097	mov r2, #32
4861		- ldr r0, .L871+16
	5098	+ add r1, r8, #160
	5099	+ mov r0, r6
	5100	+ bl ftl_memcpy
	5101	+ ldr r1, [r4, #-1788]
	5102	+ mov r2, #32
	5103	+ ldr r0, .L881+12
4862	5104	add r1, r1, #192
4863	5105	bl ftl_memcpy
4864		- ldr r1, [r6, #-1792]
	5106	+ ldr r1, [r4, #-1788]
4865	5107	mov r2, #852
4866		- ldr r0, .L871+20
	5108	+ mov r0, r9
4867	5109	add r1, r1, #224
4868	5110	bl ftl_memcpy
4869		- ldrh r0, [r7, #10]
	5111	+ ldrh r0, [r6, #10]
4870	5112	bl FlashBlockAlignInit
4871		- ldr r7, [r6, #-1792]
4872		- str r4, [r6, #-1788]
4873		- mov r0, r4
4874		- ldr r1, [r8, #4]
4875		- ldr r3, [r7, #1076]
4876		- strb r3, [r6, #-1860]
	5113	+ ldr r6, [r4, #-1788]
	5114	+ mov r0, r5
	5115	+ str r5, [r4, #-1784]
	5116	+ ldr r1, [r10, #40]
	5117	+ ldr r3, [r6, #1076]
	5118	+ strb r3, [r4, #-1856]
4877	5119	bl __aeabi_uidiv
4878	5120	add r0, r0, #1
4879	5121	cmp r0, #1
4880		- strhi r0, [r6, #-1784]
4881	5122	movls r3, #2
4882		- strls r3, [r6, #-1784]
4883		- ldrh r3, [r7, #14]
4884		- mov r7, #0
4885		- strb r3, [r5, #-1780]
4886		-.L859:
4887		- ldr r3, [sp, #4]
4888		- subs r9, r9, #1
4889		- add r4, r4, r3
4890		- bne .L856
4891		- mov r0, r9
4892		-.L870:
	5123	+ strhi r0, [r4, #-1780]
	5124	+ strls r3, [r4, #-1780]
	5125	+ ldrh r3, [r6, #14]
	5126	+ mov r6, #0
	5127	+ strb r3, [r4, #-1776]
	5128	+ b .L870
	5129	+.L868:
	5130	+ ldr r8, [r4, #-1788]
	5131	+ ldr r2, .L881+16
	5132	+ ldr r3, [r8]
	5133	+ cmp r3, r2
	5134	+ bne .L870
	5135	+ cmp r6, #0
	5136	+ bne .L871
	5137	+ ldr r1, [r10, #40]
	5138	+ mov r0, r5
	5139	+ bl __aeabi_uidiv
	5140	+ add r0, r0, #1
	5141	+ str r0, [r4, #-1780]
	5142	+ mov r0, r6
	5143	+.L880:
4893	5144	bl flash_exit_slc_mode
4894		- mov r0, r7
	5145	+ mov r0, r6
4895	5146	add sp, sp, #20
4896	5147	@ sp needed
4897		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
4898		-.L857:
4899		- ldr fp, [r5, #-1792]
4900		- ldr r2, .L871+24
4901		- ldr r3, [fp]
4902		- cmp r3, r2
4903		- bne .L859
4904		- cmp r7, #0
4905		- bne .L860
4906		- mov r0, r4
4907		- ldr r1, [r8, #4]
4908		- bl __aeabi_uidiv
4909		- ldr r3, .L871+8
4910		- add r0, r0, #1
4911		- str r0, [r3, #-1784]
4912		- mov r0, r7
4913		- b .L870
4914		-.L872:
	5148	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	5149	+.L882:
4915	5150	.align 2
4916		-.L871:
4917		- .word .LANCHOR3
	5151	+.L881:
4918	5152	.word .LANCHOR0
4919	5153	.word .LANCHOR2
4920		- .word .LANCHOR1+256
4921		- .word .LANCHOR0+48
4922		- .word .LANCHOR2-2732
	5154	+ .word .LANCHOR1+468
	5155	+ .word .LANCHOR0+52
4923	5156	.word 1312902724
4924	5157	.fnend
4925	5158	.size FlashLoadPhyInfo, .-FlashLoadPhyInfo
4926	5159	.align 2
4927	5160	.global ToshibaReadRetrial
	5161	+ .syntax unified
	5162	+ .arm
	5163	+ .fpu softvfp
4928	5164	.type ToshibaReadRetrial, %function
4929	5165	ToshibaReadRetrial:
4930	5166	.fnstart
4931	5167	@ args = 0, pretend = 0, frame = 24
4932	5168	@ frame_needed = 0, uses_anonymous_args = 0
4933		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	5169	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
4934	5170	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
4935	5171	.pad #28
4936	5172	sub sp, sp, #28
4937		- mov r8, r0
	5173	+ mov r7, r0
	5174	+ str r2, [sp, #8]
4938	5175	mov r10, r3
4939	5176	str r1, [sp, #20]
4940		- str r2, [sp, #8]
4941	5177	bl NandcWaitFlashReady
4942		- ldr r3, .L902
4943		- add r3, r3, r8, asl #3
4944		- ldr r5, [r3, #12]
4945		- ldrb r3, [r3, #16] @ zero_extendqisi2
4946		- add r6, r3, #8
4947		- add r6, r5, r6, asl #8
	5178	+ ldr r3, .L911
	5179	+ ldr r2, .L911+4
	5180	+ ldr r5, [r3, r7, lsl #3]
	5181	+ add r3, r3, r7, lsl #3
	5182	+ str r2, [sp, #12]
	5183	+ ldrb r3, [r3, #4] @ zero_extendqisi2
4948	5184	str r3, [sp, #4]
4949		- ldr r3, .L902+4
4950		- ldrb r7, [r3] @ zero_extendqisi2
4951		- str r3, [sp, #12]
4952		- sub r4, r7, #67
	5185	+ add r6, r3, #8
	5186	+ ldrb r3, [r2] @ zero_extendqisi2
	5187	+ add r6, r5, r6, lsl #8
	5188	+ sub r3, r3, #67
	5189	+ cmp r3, #1
4953	5190	ldr r3, [sp, #4]
4954		- cmp r4, #1
4955		- mov r3, r3, asl #8
4956	5191	movls r4, #0
	5192	+ lsl r3, r3, #8
4957	5193	str r3, [sp, #16]
4958		- bls .L874
4959		- ldr r3, .L902+8
4960		- ldrb r4, [r3, #-1860] @ zero_extendqisi2
	5194	+ bls .L884
	5195	+ ldr r3, .L911+8
	5196	+ ldrb r4, [r3, #-1856] @ zero_extendqisi2
4961	5197	cmp r4, #0
4962		- beq .L875
4963		- mov r0, #0
	5198	+ beq .L885
4964	5199	mov r4, #1
	5200	+ mov r0, #0
4965	5201	bl NandcSetDdrMode
4966		-.L875:
	5202	+.L885:
4967	5203	ldr r3, [sp, #16]
4968	5204	mov r2, #92
4969	5205	add r3, r5, r3
4970	5206	str r2, [r3, #2056]
4971	5207	mov r2, #197
4972	5208	str r2, [r3, #2056]
4973		-.L874:
4974		- mov r7, #1
	5209	+.L884:
	5210	+ mov r8, #1
4975	5211	mvn r9, #0
4976		-.L876:
4977		- ldr r3, .L902+12
	5212	+.L886:
	5213	+ ldr r3, .L911+12
4978	5214	ldrb r3, [r3] @ zero_extendqisi2
4979	5215	add r3, r3, #1
4980		- cmp r7, r3
4981		- bcs .L901
4982		- ldr r3, [sp, #12]
4983		- mov r0, r6
4984		- uxtb r1, r7
4985		- ldrb r3, [r3] @ zero_extendqisi2
4986		- sub r3, r3, #67
4987		- cmp r3, #1
4988		- bhi .L877
4989		- bl SandiskSetRRPara
4990		- b .L878
4991		-.L877:
4992		- bl ToshibaSetRRPara
4993		-.L878:
4994		- ldr r3, [sp, #12]
4995		- ldrb r3, [r3] @ zero_extendqisi2
4996		- cmp r3, #34
4997		- bne .L879
4998		- ldr r3, .L902+12
4999		- ldrb r3, [r3] @ zero_extendqisi2
5000		- sub r3, r3, #3
5001		- cmp r7, r3
5002		- ldreq r3, [sp, #4]
5003		- moveq r2, #179
5004		- addeq r3, r5, r3, asl #8
5005		- streq r2, [r3, #2056]
5006		-.L879:
5007		- ldr r3, [sp, #16]
5008		- cmp r4, #0
5009		- mov r2, #38
5010		- add r3, r5, r3
5011		- str r2, [r3, #2056]
5012		- mov r2, #93
5013		- str r2, [r3, #2056]
5014		- beq .L880
5015		- mov r0, #4
5016		- bl NandcSetDdrMode
5017		- mov r0, r8
5018		- mov r3, r10
5019		- ldr r1, [sp, #20]
5020		- ldr r2, [sp, #8]
5021		- bl FlashReadRawPage
5022		- mov fp, r0
5023		- mov r0, #0
5024		- bl NandcSetDdrMode
5025		- b .L881
5026		-.L880:
5027		- mov r0, r8
5028		- ldr r1, [sp, #20]
5029		- ldr r2, [sp, #8]
5030		- mov r3, r10
5031		- bl FlashReadRawPage
5032		- mov fp, r0
5033		-.L881:
5034		- cmn fp, #1
5035		- beq .L882
5036		- ldr r3, .L902+8
5037		- cmn r9, #1
5038		- moveq r9, fp
5039		- ldrb r2, [r3, #-2743] @ zero_extendqisi2
5040		- add r2, r2, r2, asl #1
5041		- cmp fp, r2, asr #2
5042		- bcc .L884
5043		- mov r10, #0
5044		- str r10, [sp, #8]
5045		-.L882:
5046		- add r7, r7, #1
5047		- b .L876
5048		-.L901:
	5216	+ cmp r8, r3
	5217	+ bcc .L895
5049	5218	mov fp, r9
5050		-.L884:
	5219	+.L894:
5051	5220	ldr r3, [sp, #12]
5052		- mov r0, r6
5053	5221	mov r1, #0
	5222	+ mov r0, r6
5054	5223	ldrb r2, [r3] @ zero_extendqisi2
5055	5224	sub r2, r2, #67
5056	5225	cmp r2, #1
5057		- bhi .L886
	5226	+ bhi .L896
5058	5227	bl SandiskSetRRPara
5059		- b .L887
5060		-.L886:
5061		- bl ToshibaSetRRPara
5062		-.L887:
	5228	+.L897:
5063	5229	ldr r3, [sp, #16]
5064	5230	mov r2, #255
5065	5231	add r5, r5, r3
5066	5232	str r2, [r5, #2056]
5067		- ldr r2, .L902+8
5068		- ldrb r2, [r2, #-2743] @ zero_extendqisi2
5069		- add r2, r2, r2, asl #1
	5233	+ ldr r2, .L911+8
	5234	+ ldrb r2, [r2, #-2739] @ zero_extendqisi2
	5235	+ add r2, r2, r2, lsl #1
5070	5236	cmp fp, r2, asr #2
5071		- bcc .L888
	5237	+ bcc .L898
5072	5238	cmn fp, #1
5073	5239	movne fp, #256
5074		-.L888:
5075		- mov r0, r8
	5240	+.L898:
	5241	+ mov r0, r7
5076	5242	bl NandcWaitFlashReady
5077	5243	cmp r4, #0
5078		- beq .L889
	5244	+ beq .L883
5079	5245	mov r0, #4
5080	5246	bl NandcSetDdrMode
5081		-.L889:
	5247	+.L883:
5082	5248	mov r0, fp
5083	5249	add sp, sp, #28
5084	5250	@ sp needed
5085		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
5086		-.L903:
	5251	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	5252	+.L895:
	5253	+ ldr r3, [sp, #12]
	5254	+ mov r0, r6
	5255	+ uxtb r1, r8
	5256	+ ldrb r3, [r3] @ zero_extendqisi2
	5257	+ sub r3, r3, #67
	5258	+ cmp r3, #1
	5259	+ bhi .L887
	5260	+ bl SandiskSetRRPara
	5261	+.L888:
	5262	+ ldr r3, [sp, #12]
	5263	+ ldrb r3, [r3] @ zero_extendqisi2
	5264	+ cmp r3, #34
	5265	+ bne .L889
	5266	+ ldr r3, .L911+12
	5267	+ ldrb r3, [r3] @ zero_extendqisi2
	5268	+ sub r3, r3, #3
	5269	+ cmp r8, r3
	5270	+ ldreq r3, [sp, #4]
	5271	+ moveq r2, #179
	5272	+ addeq r3, r5, r3, lsl #8
	5273	+ streq r2, [r3, #2056]
	5274	+.L889:
	5275	+ ldr r3, [sp, #16]
	5276	+ mov r2, #38
	5277	+ cmp r4, #0
	5278	+ add r3, r5, r3
	5279	+ str r2, [r3, #2056]
	5280	+ mov r2, #93
	5281	+ str r2, [r3, #2056]
	5282	+ beq .L890
	5283	+ mov r0, #4
	5284	+ bl NandcSetDdrMode
	5285	+ mov r3, r10
	5286	+ ldr r2, [sp, #8]
	5287	+ ldr r1, [sp, #20]
	5288	+ mov r0, r7
	5289	+ bl FlashReadRawPage
	5290	+ mov fp, r0
	5291	+ mov r0, #0
	5292	+ bl NandcSetDdrMode
	5293	+.L891:
	5294	+ cmn fp, #1
	5295	+ beq .L892
	5296	+ ldr r3, .L911+8
	5297	+ cmn r9, #1
	5298	+ moveq r9, fp
	5299	+ ldrb r2, [r3, #-2739] @ zero_extendqisi2
	5300	+ add r2, r2, r2, lsl #1
	5301	+ cmp fp, r2, asr #2
	5302	+ bcc .L894
	5303	+ mov r10, #0
	5304	+ str r10, [sp, #8]
	5305	+.L892:
	5306	+ add r8, r8, #1
	5307	+ b .L886
	5308	+.L887:
	5309	+ bl ToshibaSetRRPara
	5310	+ b .L888
	5311	+.L890:
	5312	+ mov r3, r10
	5313	+ ldr r2, [sp, #8]
	5314	+ ldr r1, [sp, #20]
	5315	+ mov r0, r7
	5316	+ bl FlashReadRawPage
	5317	+ mov fp, r0
	5318	+ b .L891
	5319	+.L896:
	5320	+ bl ToshibaSetRRPara
	5321	+ b .L897
	5322	+.L912:
5087	5323	.align 2
5088		-.L902:
	5324	+.L911:
5089	5325	.word .LANCHOR0
5090	5326	.word g_retryMode
5091	5327	.word .LANCHOR2
..	..	@@ -5094,186 +5330,155 @@
5094	5330	.size ToshibaReadRetrial, .-ToshibaReadRetrial
5095	5331	.align 2
5096	5332	.global SamsungReadRetrial
	5333	+ .syntax unified
	5334	+ .arm
	5335	+ .fpu softvfp
5097	5336	.type SamsungReadRetrial, %function
5098	5337	SamsungReadRetrial:
5099	5338	.fnstart
5100		- @ args = 0, pretend = 0, frame = 8
	5339	+ @ args = 0, pretend = 0, frame = 0
5101	5340	@ frame_needed = 0, uses_anonymous_args = 0
5102		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
5103		- .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
5104		- .pad #12
5105		- mov r8, r0
5106		- ldr r4, .L918
5107		- mov r7, r3
5108		- mov fp, r1
	5341	+ push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	5342	+ .save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	5343	+ mov r7, r0
5109	5344	mov r9, r2
5110		- add r4, r4, r8, asl #3
5111		- bl NandcWaitFlashReady
5112		- ldr r10, .L918+4
	5345	+ mov r8, r3
	5346	+ mov r10, r1
5113	5347	mov r6, #1
5114		- ldrb r3, [r4, #16] @ zero_extendqisi2
5115		- ldr r5, [r4, #12]
	5348	+ bl NandcWaitFlashReady
	5349	+ ldr r2, .L927
5116	5350	mvn r4, #0
5117		- add r3, r3, #8
5118		- ldr ip, .L918+8
5119		- add r5, r5, r3, asl #8
5120		-.L905:
5121		- ldrb r3, [r10] @ zero_extendqisi2
	5351	+ ldr fp, .L927+4
	5352	+ add r3, r2, r7, lsl #3
	5353	+ ldrb r5, [r3, #4] @ zero_extendqisi2
	5354	+ add r3, r5, #8
	5355	+ ldr r5, [r2, r7, lsl #3]
	5356	+ add r5, r5, r3, lsl #8
	5357	+.L914:
	5358	+ ldr r3, .L927+8
	5359	+ ldrb r3, [r3] @ zero_extendqisi2
5122	5360	add r3, r3, #1
5123	5361	cmp r6, r3
5124		- bcs .L908
5125		- mov r0, r5
5126		- uxtb r1, r6
5127		- str ip, [sp, #4]
5128		- bl SamsungSetRRPara
5129		- mov r0, r8
5130		- mov r1, fp
5131		- mov r2, r9
5132		- mov r3, r7
5133		- bl FlashReadRawPage
5134		- cmn r0, #1
5135		- ldr ip, [sp, #4]
5136		- beq .L906
5137		- ldrb r3, [ip, #-2743] @ zero_extendqisi2
5138		- cmn r4, #1
5139		- moveq r4, r0
5140		- add r3, r3, r3, asl #1
5141		- cmp r0, r3, asr #2
5142		- bcc .L911
5143		- mov r7, #0
5144		- mov r9, r7
5145		-.L906:
5146		- add r6, r6, #1
5147		- b .L905
5148		-.L911:
5149		- mov r4, r0
5150		-.L908:
5151		- mov r0, r5
	5362	+ bcc .L918
	5363	+.L917:
5152	5364	mov r1, #0
	5365	+ mov r0, r5
5153	5366	bl SamsungSetRRPara
5154		- ldr r3, .L918+8
5155		- ldrb r3, [r3, #-2743] @ zero_extendqisi2
5156		- add r3, r3, r3, asl #1
	5367	+ ldr r3, .L927+4
	5368	+ ldrb r3, [r3, #-2739] @ zero_extendqisi2
	5369	+ add r3, r3, r3, lsl #1
5157	5370	cmp r4, r3, asr #2
5158		- bcc .L910
	5371	+ bcc .L913
5159	5372	cmn r4, #1
5160	5373	movne r4, #256
5161		-.L910:
	5374	+.L913:
5162	5375	mov r0, r4
5163		- add sp, sp, #12
5164		- @ sp needed
5165		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
5166		-.L919:
5167		- .align 2
	5376	+ pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
5168	5377	.L918:
	5378	+ uxtb r1, r6
	5379	+ mov r0, r5
	5380	+ bl SamsungSetRRPara
	5381	+ mov r3, r8
	5382	+ mov r2, r9
	5383	+ mov r1, r10
	5384	+ mov r0, r7
	5385	+ bl FlashReadRawPage
	5386	+ cmn r0, #1
	5387	+ beq .L915
	5388	+ ldrb r3, [fp, #-2739] @ zero_extendqisi2
	5389	+ cmn r4, #1
	5390	+ moveq r4, r0
	5391	+ add r3, r3, r3, lsl #1
	5392	+ cmp r0, r3, asr #2
	5393	+ bcc .L921
	5394	+ mov r8, #0
	5395	+ mov r9, r8
	5396	+.L915:
	5397	+ add r6, r6, #1
	5398	+ b .L914
	5399	+.L921:
	5400	+ mov r4, r0
	5401	+ b .L917
	5402	+.L928:
	5403	+ .align 2
	5404	+.L927:
5169	5405	.word .LANCHOR0
5170		- .word g_maxRetryCount
5171	5406	.word .LANCHOR2
	5407	+ .word g_maxRetryCount
5172	5408	.fnend
5173	5409	.size SamsungReadRetrial, .-SamsungReadRetrial
5174	5410	.align 2
5175	5411	.global MicronReadRetrial
	5412	+ .syntax unified
	5413	+ .arm
	5414	+ .fpu softvfp
5176	5415	.type MicronReadRetrial, %function
5177	5416	MicronReadRetrial:
5178	5417	.fnstart
5179	5418	@ args = 0, pretend = 0, frame = 24
5180	5419	@ frame_needed = 0, uses_anonymous_args = 0
5181		-.L922:
5182		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	5420	+.L931:
	5421	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
5183	5422	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
5184	5423	mov r8, r3
5185		- ldr r3, .L946
	5424	+ ldr r3, .L954
5186	5425	mov fp, r2
5187	5426	.pad #36
5188	5427	sub sp, sp, #36
5189	5428	mov r6, r0
5190		- mov r10, #0
5191		- ldrb r5, [r3, #-2743] @ zero_extendqisi2
5192		- ldrb r3, [r3, #-2744] @ zero_extendqisi2
5193	5429	str r1, [sp, #20]
	5430	+ ldrb r2, [r3, #-2739] @ zero_extendqisi2
	5431	+ ldrb r3, [r3, #-2740] @ zero_extendqisi2
5194	5432	cmp r3, #0
5195		- addeq r5, r5, r5, asl #1
5196		- ldrne r2, .L946+4
5197		- ubfxeq r5, r5, #2, #8
5198		- smullne r2, r3, r5, r2
5199		- uxtbne r5, r3
5200		- ldr r3, .L946+8
5201		- add r3, r3, r0, asl #3
5202		- str r3, [sp, #24]
5203		-.L932:
	5433	+ ldrne r5, .L954+4
	5434	+ addeq r2, r2, r2, lsl #1
	5435	+ asreq r5, r2, #2
	5436	+ smullne r2, r3, r2, r5
	5437	+ movne r5, r3
	5438	+ mov r3, #0
	5439	+ str r3, [sp, #8]
	5440	+ ldr r3, .L954+8
	5441	+ add r3, r3, r0, lsl #3
	5442	+ str r3, [sp, #28]
	5443	+.L941:
5204	5444	mov r0, r6
5205		- mov r9, #0
	5445	+ mov r10, #0
5206	5446	bl NandcWaitFlashReady
	5447	+ ldr r3, .L954+8
5207	5448	mvn r4, #0
5208		- ldr r3, [sp, #24]
5209		- ldr r3, [r3, #12]
	5449	+ ldr r3, [r3, r6, lsl #3]
5210	5450	str r3, [sp, #12]
5211		- ldr r3, [sp, #24]
5212		- ldrb r3, [r3, #16] @ zero_extendqisi2
	5451	+ ldr r3, [sp, #28]
	5452	+ ldrb r3, [r3, #4] @ zero_extendqisi2
5213	5453	str r3, [sp, #16]
5214	5454	ldr r2, [sp, #16]
5215	5455	ldr r3, [sp, #12]
5216		- add r7, r3, r2, asl #8
5217		-.L923:
5218		- ldr r3, .L946+12
	5456	+ add r7, r3, r2, lsl #8
	5457	+.L932:
	5458	+ ldr r3, .L954+12
5219	5459	ldrb r3, [r3] @ zero_extendqisi2
5220		- cmp r9, r3
5221		- bcs .L926
5222		- mov r3, #239
5223		- mov r0, #200
5224		- str r3, [r7, #2056]
5225		- mov r3, #137
5226		- str r3, [r7, #2052]
5227		- bl NandcDelayns
5228		- mov ip, #0
5229		- add r3, r9, #1
5230		- mov r0, r6
5231		- str r3, [r7, #2048]
5232		- mov r2, fp
5233		- str ip, [r7, #2048]
5234		- str ip, [r7, #2048]
5235		- str ip, [r7, #2048]
5236		- str r3, [sp, #8]
5237		- mov r3, r8
5238		- ldr r1, [sp, #20]
5239		- str ip, [sp, #28]
5240		- bl FlashReadRawPage
5241		- cmn r0, #1
5242		- beq .L924
5243		- cmn r4, #1
5244		- ldr ip, [sp, #28]
5245		- moveq r4, r0
5246		- cmp r0, r5
5247		- bcc .L934
5248		- mov r8, ip
5249		- mov fp, ip
5250		-.L924:
5251		- ldr r9, [sp, #8]
5252		- b .L923
5253		-.L934:
5254		- mov r4, r0
5255		- mov r8, ip
5256		- mov fp, ip
5257		-.L926:
5258		- ldr r2, [sp, #16]
5259		- mov r0, #200
	5460	+ cmp r10, r3
	5461	+ bcc .L936
	5462	+.L935:
5260	5463	ldr r3, [sp, #12]
5261		- add r7, r3, r2, asl #8
	5464	+ mov r0, #200
	5465	+ ldr r2, [sp, #16]
	5466	+ add r7, r3, r2, lsl #8
5262	5467	mov r3, #239
5263	5468	str r3, [r7, #2056]
5264	5469	mov r3, #137
5265	5470	str r3, [r7, #2052]
5266		- bl NandcDelayns
	5471	+ bl ndelay
5267	5472	cmp r4, r5
5268	5473	mov r3, #0
5269	5474	str r3, [r7, #2048]
5270	5475	str r3, [r7, #2048]
5271	5476	str r3, [r7, #2048]
5272	5477	str r3, [r7, #2048]
5273		- bcc .L928
	5478	+ bcc .L937
5274	5479	cmn r4, #1
5275	5480	movne r4, #256
5276		-.L928:
	5481	+.L937:
5277	5482	cmn r4, #1
5278	5483	movne r7, #0
5279	5484	moveq r7, #1
..	..	@@ -5281,48 +5486,86 @@
5281	5486	movne r1, r7
5282	5487	orreq r1, r7, #1
5283	5488	cmp r1, #0
5284		- beq .L929
	5489	+ beq .L938
	5490	+ mov r3, r10
5285	5491	str r4, [sp]
5286		- mov r1, r9
5287		- ldr r0, .L946+16
5288		- mov r3, r9
5289	5492	ldr r2, [sp, #20]
	5493	+ mov r1, r10
	5494	+ ldr r0, .L954+16
5290	5495	bl printk
5291		- cmp r10, #0
5292		- bne .L930
5293		- ldr r3, .L946
5294		- ldrb r3, [r3, #-2744] @ zero_extendqisi2
	5496	+ ldr r3, [sp, #8]
	5497	+ cmp r3, #0
	5498	+ bne .L939
	5499	+ ldr r3, .L954
	5500	+ ldrb r3, [r3, #-2740] @ zero_extendqisi2
5295	5501	cmp r3, #0
5296	5502	moveq r7, #0
5297	5503	andne r7, r7, #1
5298	5504	cmp r7, #0
5299		- beq .L939
5300		- mov r0, r6
	5505	+ beq .L929
5301	5506	mov r1, #3
5302		- bl micron_auto_read_calibration_config
5303		- mov r10, #1
5304		- b .L932
5305		-.L930:
5306	5507	mov r0, r6
	5508	+ bl micron_auto_read_calibration_config
	5509	+ mov r3, #1
	5510	+ str r3, [sp, #8]
	5511	+ b .L941
	5512	+.L936:
	5513	+ mov r3, #239
	5514	+ mov r0, #200
	5515	+ str r3, [r7, #2056]
	5516	+ mov r3, #137
	5517	+ str r3, [r7, #2052]
	5518	+ mov r9, #0
	5519	+ bl ndelay
	5520	+ add r3, r10, #1
	5521	+ mov r2, fp
	5522	+ str r3, [r7, #2048]
	5523	+ mov r0, r6
	5524	+ str r9, [r7, #2048]
	5525	+ str r3, [sp, #24]
	5526	+ mov r3, r8
	5527	+ str r9, [r7, #2048]
	5528	+ ldr r1, [sp, #20]
	5529	+ str r9, [r7, #2048]
	5530	+ bl FlashReadRawPage
	5531	+ cmn r0, #1
	5532	+ beq .L933
	5533	+ cmn r4, #1
	5534	+ moveq r4, r0
	5535	+ cmp r0, r5
	5536	+ bcc .L943
	5537	+ mov r8, r9
	5538	+ mov fp, r9
	5539	+.L933:
	5540	+ ldr r10, [sp, #24]
	5541	+ b .L932
	5542	+.L943:
	5543	+ mov r4, r0
	5544	+ mov r8, r9
	5545	+ mov fp, r9
	5546	+ b .L935
	5547	+.L939:
5307	5548	mov r1, #0
	5549	+ mov r0, r6
5308	5550	bl micron_auto_read_calibration_config
5309	5551	cmn r4, #1
5310	5552	movne r4, #256
5311		- b .L939
5312	5553	.L929:
5313		- cmp r10, #0
5314		- beq .L939
5315		- mov r0, r6
5316		- mov r4, #256
5317		- bl micron_auto_read_calibration_config
5318		-.L939:
5319	5554	mov r0, r4
5320	5555	add sp, sp, #36
5321	5556	@ sp needed
5322		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
5323		-.L947:
	5557	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	5558	+.L938:
	5559	+ ldr r3, [sp, #8]
	5560	+ cmp r3, #0
	5561	+ beq .L929
	5562	+ mov r0, r6
	5563	+ mov r4, #256
	5564	+ bl micron_auto_read_calibration_config
	5565	+ b .L929
	5566	+.L955:
5324	5567	.align 2
5325		-.L946:
	5568	+.L954:
5326	5569	.word .LANCHOR2
5327	5570	.word 1431655766
5328	5571	.word .LANCHOR0
..	..	@@ -5332,303 +5575,305 @@
5332	5575	.size MicronReadRetrial, .-MicronReadRetrial
5333	5576	.align 2
5334	5577	.global HynixReadRetrial
	5578	+ .syntax unified
	5579	+ .arm
	5580	+ .fpu softvfp
5335	5581	.type HynixReadRetrial, %function
5336	5582	HynixReadRetrial:
5337	5583	.fnstart
5338	5584	@ args = 0, pretend = 0, frame = 8
5339	5585	@ frame_needed = 0, uses_anonymous_args = 0
5340		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	5586	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
5341	5587	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
5342	5588	.pad #12
5343		- mov r10, r2
5344		- ldr r2, .L966
5345		- mov fp, r1
5346		- ldr ip, .L966+4
5347		- mov r8, r3
5348		- mov r5, r0
5349		- ldr r1, [r2, #44]
5350		- add r3, ip, r0
5351		- ldrb r9, [ip, #-2730] @ zero_extendqisi2
5352		- mov r7, ip
5353		- ldrb r4, [r3, #-2720] @ zero_extendqisi2
5354		- ldrb r6, [r1, #19] @ zero_extendqisi2
5355		- str r2, [sp]
5356		- sub r6, r6, #7
5357		- cmp r6, #1
5358		- mvn r6, #0
5359		- ldrlsb r4, [r3, #-2712] @ zero_extendqisi2
5360		- bl NandcWaitFlashReady
5361		- mov ip, #0
5362		-.L950:
5363		- cmp ip, r9
5364		- bcs .L954
5365		- add r4, r4, #1
5366		- mov r0, r5
5367		- ldrb r1, [r7, #-2731] @ zero_extendqisi2
5368		- uxtb r4, r4
5369		- ldr r2, .L966+8
5370		- cmp r4, r9
5371		- str ip, [sp, #4]
5372		- movcs r4, #0
5373		- mov r3, r4
5374		- bl HynixSetRRPara
5375		- mov r0, r5
5376		- mov r1, fp
5377		- mov r2, r10
5378		- mov r3, r8
5379		- bl FlashReadRawPage
5380		- cmn r0, #1
5381		- ldr ip, [sp, #4]
5382		- beq .L952
5383		- ldrb r3, [r7, #-2743] @ zero_extendqisi2
5384		- cmn r6, #1
5385		- moveq r6, r0
5386		- add r3, r3, r3, asl #1
5387		- cmp r0, r3, asr #2
5388		- bcc .L959
	5589	+ mov r9, r3
	5590	+ str r1, [sp]
5389	5591	mov r8, #0
5390		- mov r10, r8
5391		-.L952:
5392		- add ip, ip, #1
5393		- b .L950
5394		-.L959:
5395		- mov r6, r0
5396		-.L954:
5397		- ldr r3, [sp]
	5592	+ mvn r6, #0
	5593	+ mov fp, r2
	5594	+ ldr r1, .L974
	5595	+ mov r5, r0
	5596	+ ldr r7, .L974+4
	5597	+ ldr r3, [r1, #48]
	5598	+ add r2, r7, r0
	5599	+ ldrb r10, [r7, #-2726] @ zero_extendqisi2
	5600	+ ldrb r4, [r2, #-2716] @ zero_extendqisi2
	5601	+ ldrb r3, [r3, #19] @ zero_extendqisi2
	5602	+ str r1, [sp, #4]
	5603	+ sub r3, r3, #7
	5604	+ cmp r3, #1
	5605	+ ldrbls r4, [r2, #-2708] @ zero_extendqisi2
	5606	+ bl NandcWaitFlashReady
	5607	+.L958:
	5608	+ cmp r8, r10
	5609	+ bcc .L963
	5610	+.L962:
	5611	+ ldr r3, [sp, #4]
5398	5612	add r5, r7, r5
5399		- ldr r3, [r3, #44]
	5613	+ ldr r3, [r3, #48]
5400	5614	ldrb r3, [r3, #19] @ zero_extendqisi2
5401	5615	sub r3, r3, #7
5402	5616	cmp r3, #1
5403		- ldrb r3, [r7, #-2743] @ zero_extendqisi2
5404		- strlsb r4, [r5, #-2712]
5405		- strhib r4, [r5, #-2720]
5406		- add r3, r3, r3, asl #1
	5617	+ ldrb r3, [r7, #-2739] @ zero_extendqisi2
	5618	+ strbls r4, [r5, #-2708]
	5619	+ strbhi r4, [r5, #-2716]
	5620	+ add r3, r3, r3, lsl #1
5407	5621	cmp r6, r3, asr #2
5408		- bcc .L958
	5622	+ bcc .L956
5409	5623	cmn r6, #1
5410	5624	movne r6, #256
5411		-.L958:
	5625	+.L956:
5412	5626	mov r0, r6
5413	5627	add sp, sp, #12
5414	5628	@ sp needed
5415		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	5629	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	5630	+.L963:
	5631	+ add r4, r4, #1
	5632	+ ldr r2, .L974+8
	5633	+ uxtb r4, r4
	5634	+ ldrb r1, [r7, #-2727] @ zero_extendqisi2
	5635	+ mov r0, r5
	5636	+ cmp r10, r4
	5637	+ movls r4, #0
	5638	+ mov r3, r4
	5639	+ bl HynixSetRRPara
	5640	+ mov r3, r9
	5641	+ mov r2, fp
	5642	+ ldr r1, [sp]
	5643	+ mov r0, r5
	5644	+ bl FlashReadRawPage
	5645	+ cmn r0, #1
	5646	+ beq .L960
	5647	+ ldrb r3, [r7, #-2739] @ zero_extendqisi2
	5648	+ cmn r6, #1
	5649	+ moveq r6, r0
	5650	+ add r3, r3, r3, lsl #1
	5651	+ cmp r0, r3, asr #2
	5652	+ bcc .L967
	5653	+ mov r9, #0
	5654	+ mov fp, r9
	5655	+.L960:
	5656	+ add r8, r8, #1
	5657	+ b .L958
5416	5658	.L967:
	5659	+ mov r6, r0
	5660	+ b .L962
	5661	+.L975:
5417	5662	.align 2
5418		-.L966:
	5663	+.L974:
5419	5664	.word .LANCHOR0
5420	5665	.word .LANCHOR2
5421		- .word .LANCHOR2-2728
	5666	+ .word .LANCHOR2-2724
5422	5667	.fnend
5423	5668	.size HynixReadRetrial, .-HynixReadRetrial
5424	5669	.align 2
	5670	+ .syntax unified
	5671	+ .arm
	5672	+ .fpu softvfp
5425	5673	.type samsung_read_retrial, %function
5426	5674	samsung_read_retrial:
5427	5675	.fnstart
5428	5676	@ args = 0, pretend = 0, frame = 16
5429	5677	@ frame_needed = 0, uses_anonymous_args = 0
5430		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	5678	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
5431	5679	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
5432	5680	.pad #28
5433	5681	sub sp, sp, #28
5434	5682	mov r10, r0
5435	5683	mov fp, r2
5436		- mov r8, r3
5437		- str r1, [sp, #12]
	5684	+ mov r9, r3
	5685	+ str r1, [sp, #16]
5438	5686	bl NandcWaitFlashReady
5439		- ldr r3, .L998
5440		- add r3, r3, r10, asl #3
5441		- ldr r4, [r3, #12]
5442		- ldrb r3, [r3, #16] @ zero_extendqisi2
5443		- str r3, [sp, #8]
5444		- ldr r3, .L998+4
5445		- ldrb r2, [r3, #-1876] @ zero_extendqisi2
5446		- str r3, [sp, #16]
	5687	+ ldr r3, .L1006
	5688	+ ldr r2, [r3, r10, lsl #3]
	5689	+ add r3, r3, r10, lsl #3
	5690	+ ldrb r6, [r3, #4] @ zero_extendqisi2
	5691	+ ldr r3, .L1006+4
	5692	+ str r2, [sp, #12]
	5693	+ ldrb r2, [r3, #-1872] @ zero_extendqisi2
	5694	+ str r3, [sp, #20]
5447	5695	cmp r2, #0
5448		- bne .L969
5449		- ldr r3, [sp, #8]
5450		- mvn r5, #0
5451		- mov r6, #1
5452		- mov r9, r3, asl #8
5453		- add r7, r4, r9
5454		-.L973:
5455		- mov r3, #239
5456		- str r3, [r7, #2056]
5457		- mov r3, #141
5458		- str r3, [r7, #2052]
5459		- ldr r3, .L998+8
5460		- mov ip, #0
5461		- mov r0, r10
5462		- ldr r1, [sp, #12]
5463		- mov r2, fp
5464		- str ip, [sp, #20]
5465		- ldrsb r3, [r6, r3]
5466		- str r3, [r7, #2048]
5467		- mov r3, r8
5468		- str ip, [r7, #2048]
5469		- str ip, [r7, #2048]
5470		- str ip, [r7, #2048]
5471		- bl FlashReadRawPage
5472		- cmn r0, #1
5473		- beq .L970
5474		- ldr r3, [sp, #16]
5475		- cmn r5, #1
5476		- moveq r5, r0
5477		- ldrb r3, [r3, #-2743] @ zero_extendqisi2
5478		- add r3, r3, r3, asl #1
5479		- cmp r0, r3, asr #2
5480		- bcc .L981
5481		- ldr ip, [sp, #20]
5482		- mov r8, ip
5483		- mov fp, ip
5484		-.L970:
5485		- add r6, r6, #1
5486		- cmp r6, #26
5487		- bne .L973
5488		- b .L972
	5696	+ bne .L977
	5697	+ ldr r3, [sp, #12]
	5698	+ lsl r8, r6, #8
	5699	+ mvn r4, #0
	5700	+ mov r7, #1
	5701	+ add r5, r3, r8
5489	5702	.L981:
5490		- mov r5, r0
5491		-.L972:
5492		- add r9, r4, r9
5493	5703	mov r3, #239
5494		- str r3, [r9, #2056]
5495		- ldr r3, [sp, #8]
5496		- add r4, r4, r3, asl #8
	5704	+ mov r6, #0
	5705	+ str r3, [r5, #2056]
5497	5706	mov r3, #141
5498		- b .L997
5499		-.L969:
5500		- ldr r3, [sp, #8]
5501		- mvn r5, #0
5502		- ldr r7, .L998+12
5503		- mov r6, #1
5504		- mov ip, r3, asl #8
5505		- add r9, r4, ip
5506		-.L978:
5507		- mov r3, #239
5508		- str r3, [r9, #2056]
5509		- mov r3, #137
5510		- str r3, [r9, #2052]
5511		- ldrb r3, [r7, #4] @ zero_extendqisi2
5512		- mov r0, r10
5513		- ldr r1, [sp, #12]
	5707	+ str r3, [r5, #2052]
5514	5708	mov r2, fp
5515		- str ip, [sp, #20]
5516		- str r3, [r9, #2048]
5517		- ldrb r3, [r7, #5] @ zero_extendqisi2
5518		- str r3, [r9, #2048]
5519		- ldrb r3, [r7, #6] @ zero_extendqisi2
5520		- str r3, [r9, #2048]
5521		- ldrb r3, [r7, #7] @ zero_extendqisi2
5522		- str r3, [r9, #2048]
5523		- mov r3, r8
	5709	+ ldr r3, .L1006+8
	5710	+ mov r0, r10
	5711	+ ldr r1, [sp, #16]
	5712	+ ldrsb r3, [r7, r3]
	5713	+ str r3, [r5, #2048]
	5714	+ mov r3, r9
	5715	+ str r6, [r5, #2048]
	5716	+ str r6, [r5, #2048]
	5717	+ str r6, [r5, #2048]
5524	5718	bl FlashReadRawPage
5525	5719	cmn r0, #1
5526		- ldr ip, [sp, #20]
5527		- beq .L975
5528		- ldr r3, [sp, #16]
5529		- cmn r5, #1
5530		- moveq r5, r0
5531		- ldrb r3, [r3, #-2743] @ zero_extendqisi2
5532		- add r3, r3, r3, asl #1
	5720	+ beq .L978
	5721	+ ldr r3, [sp, #20]
	5722	+ cmn r4, #1
	5723	+ moveq r4, r0
	5724	+ ldrb r3, [r3, #-2739] @ zero_extendqisi2
	5725	+ add r3, r3, r3, lsl #1
5533	5726	cmp r0, r3, asr #2
5534		- bcc .L982
5535		- mov r8, #0
5536		- mov fp, r8
5537		-.L975:
5538		- add r6, r6, #1
5539		- add r7, r7, #4
5540		- cmp r6, #26
5541		- bne .L978
5542		- b .L977
5543		-.L982:
5544		- mov r5, r0
5545		-.L977:
5546		- add ip, r4, ip
5547		- mov r3, #239
5548		- str r3, [ip, #2056]
5549		- ldr r3, [sp, #8]
5550		- add r4, r4, r3, asl #8
5551		- mov r3, #137
5552		-.L997:
5553		- str r3, [r4, #2052]
5554		- mov r3, #0
5555		- str r3, [r4, #2048]
5556		- str r3, [r4, #2048]
5557		- str r3, [r4, #2048]
5558		- str r3, [r4, #2048]
5559		- ldr r3, [sp, #16]
5560		- ldrb r3, [r3, #-2743] @ zero_extendqisi2
5561		- add r3, r3, r3, asl #1
5562		- cmp r5, r3, asr #2
5563		- bcc .L979
5564		- cmn r5, #1
5565		- movne r5, #256
5566		-.L979:
5567		- cmn r5, #1
5568		- cmpne r5, #256
5569		- bne .L980
5570		- str r5, [sp]
5571		- mov r1, r6
5572		- ldr r0, .L998+16
5573		- mov r3, r6
5574		- ldr r2, [sp, #12]
5575		- bl printk
	5727	+ bcc .L989
	5728	+ mov r9, r6
	5729	+ mov fp, r6
	5730	+.L978:
	5731	+ add r7, r7, #1
	5732	+ cmp r7, #26
	5733	+ bne .L981
5576	5734	.L980:
	5735	+ ldr r3, [sp, #12]
	5736	+ add r8, r3, r8
	5737	+ mov r3, #239
	5738	+ str r3, [r8, #2056]
	5739	+ mov r3, #141
	5740	+.L1005:
	5741	+ str r3, [r5, #2052]
	5742	+ mov r3, #0
	5743	+ str r3, [r5, #2048]
	5744	+ str r3, [r5, #2048]
	5745	+ str r3, [r5, #2048]
	5746	+ str r3, [r5, #2048]
	5747	+ ldr r3, .L1006+4
	5748	+ ldrb r3, [r3, #-2739] @ zero_extendqisi2
	5749	+ add r3, r3, r3, lsl #1
	5750	+ cmp r4, r3, asr #2
	5751	+ bcc .L987
	5752	+ cmn r4, #1
	5753	+ movne r4, #256
	5754	+.L987:
	5755	+ cmn r4, #1
	5756	+ cmpne r4, #256
	5757	+ bne .L988
	5758	+ str r4, [sp]
	5759	+ mov r3, r7
	5760	+ ldr r2, [sp, #16]
	5761	+ mov r1, r7
	5762	+ ldr r0, .L1006+12
	5763	+ bl printk
	5764	+.L988:
5577	5765	mov r0, r10
5578	5766	bl NandcWaitFlashReady
5579		- mov r0, r5
	5767	+ mov r0, r4
5580	5768	add sp, sp, #28
5581	5769	@ sp needed
5582		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
5583		-.L999:
	5770	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	5771	+.L989:
	5772	+ mov r4, r0
	5773	+ b .L980
	5774	+.L977:
	5775	+ ldr r3, [sp, #12]
	5776	+ lsl r6, r6, #8
	5777	+ ldr r8, .L1006+16
	5778	+ mvn r4, #0
	5779	+ mov r7, #1
	5780	+ add r5, r3, r6
	5781	+.L986:
	5782	+ mov r3, #239
	5783	+ mov r2, fp
	5784	+ str r3, [r5, #2056]
	5785	+ mov r3, #137
	5786	+ str r3, [r5, #2052]
	5787	+ mov r0, r10
	5788	+ ldrb r3, [r8, #4] @ zero_extendqisi2
	5789	+ ldr r1, [sp, #16]
	5790	+ str r3, [r5, #2048]
	5791	+ ldrb r3, [r8, #5] @ zero_extendqisi2
	5792	+ str r3, [r5, #2048]
	5793	+ ldrb r3, [r8, #6] @ zero_extendqisi2
	5794	+ str r3, [r5, #2048]
	5795	+ ldrb r3, [r8, #7] @ zero_extendqisi2
	5796	+ str r3, [r5, #2048]
	5797	+ mov r3, r9
	5798	+ bl FlashReadRawPage
	5799	+ cmn r0, #1
	5800	+ beq .L983
	5801	+ ldr r3, .L1006+4
	5802	+ cmn r4, #1
	5803	+ moveq r4, r0
	5804	+ ldrb r3, [r3, #-2739] @ zero_extendqisi2
	5805	+ add r3, r3, r3, lsl #1
	5806	+ cmp r0, r3, asr #2
	5807	+ bcc .L990
	5808	+ mov r9, #0
	5809	+ mov fp, r9
	5810	+.L983:
	5811	+ add r7, r7, #1
	5812	+ add r8, r8, #4
	5813	+ cmp r7, #26
	5814	+ bne .L986
	5815	+.L985:
	5816	+ ldr r3, [sp, #12]
	5817	+ add r6, r3, r6
	5818	+ mov r3, #239
	5819	+ str r3, [r6, #2056]
	5820	+ mov r3, #137
	5821	+ b .L1005
	5822	+.L990:
	5823	+ mov r4, r0
	5824	+ b .L985
	5825	+.L1007:
5584	5826	.align 2
5585		-.L998:
	5827	+.L1006:
5586	5828	.word .LANCHOR0
5587	5829	.word .LANCHOR2
5588		- .word .LANCHOR3+4
5589		- .word .LANCHOR3+32
	5830	+ .word .LANCHOR3
5590	5831	.word .LC12
	5832	+ .word .LANCHOR3+26
5591	5833	.fnend
5592	5834	.size samsung_read_retrial, .-samsung_read_retrial
5593	5835	.align 2
5594	5836	.global FlashProgPage
	5837	+ .syntax unified
	5838	+ .arm
	5839	+ .fpu softvfp
5595	5840	.type FlashProgPage, %function
5596	5841	FlashProgPage:
5597	5842	.fnstart
5598	5843	@ args = 0, pretend = 0, frame = 0
5599	5844	@ frame_needed = 0, uses_anonymous_args = 0
5600		- stmfd sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
	5845	+ push {r0, r1, r4, r5, r6, r7, r8, lr}
5601	5846	.save {r4, r5, r6, r7, r8, lr}
5602	5847	.pad #8
5603	5848	mov r8, r3
5604		- ldr r3, .L1004
	5849	+ ldr r3, .L1012
5605	5850	subs r4, r0, #0
5606	5851	mov r5, r1
5607	5852	mov r7, r2
5608		- ldrb r6, [r3, #265] @ zero_extendqisi2
5609		- bne .L1001
5610		- ldr r2, .L1004+4
5611		- ldrb r3, [r2, #1] @ zero_extendqisi2
5612		- ldr r1, [r2, #4]
5613		- mul r1, r1, r3
5614		- cmp r5, r1
5615		- bcs .L1001
5616		- ldrb r3, [r2] @ zero_extendqisi2
	5853	+ ldrb r6, [r3, #477] @ zero_extendqisi2
	5854	+ bne .L1009
	5855	+ ldr r1, .L1012+4
	5856	+ ldrb r3, [r1, #37] @ zero_extendqisi2
	5857	+ ldr r0, [r1, #40]
	5858	+ mul r0, r0, r3
	5859	+ cmp r0, r5
	5860	+ bls .L1009
	5861	+ ldrb r3, [r1, #36] @ zero_extendqisi2
5617	5862	cmp r3, #0
5618	5863	movne r6, #4
5619		-.L1001:
	5864	+.L1009:
5620	5865	mov r0, r4
5621	5866	bl NandcWaitFlashReady
5622	5867	mov r0, r4
5623	5868	bl NandcFlashCs
5624		- mov r0, r4
5625	5869	mov r1, r5
5626		- bl FlashProgFirstCmd
5627		- mov r2, r6
5628		- mov r3, r7
5629	5870	mov r0, r4
5630		- mov r1, #1
	5871	+ bl FlashProgFirstCmd
	5872	+ mov r3, r7
	5873	+ mov r2, r6
5631	5874	str r8, [sp]
	5875	+ mov r1, #1
	5876	+ mov r0, r4
5632	5877	bl NandcXferData
5633	5878	mov r1, r5
5634	5879	mov r0, r4
..	..	@@ -5638,288 +5883,289 @@
5638	5883	mov r1, r5
5639	5884	mov r0, r4
5640	5885	bl FlashReadStatus
5641		- mov r5, r0
	5886	+ mov r1, r0
5642	5887	mov r0, r4
5643	5888	bl NandcFlashDeCs
5644		- and r0, r5, #1
	5889	+ and r0, r1, #1
5645	5890	add sp, sp, #8
5646	5891	@ sp needed
5647		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
5648		-.L1005:
	5892	+ pop {r4, r5, r6, r7, r8, pc}
	5893	+.L1013:
5649	5894	.align 2
5650		-.L1004:
	5895	+.L1012:
5651	5896	.word .LANCHOR1
5652	5897	.word .LANCHOR0
5653	5898	.fnend
5654	5899	.size FlashProgPage, .-FlashProgPage
5655	5900	.align 2
5656	5901	.global FlashSavePhyInfo
	5902	+ .syntax unified
	5903	+ .arm
	5904	+ .fpu softvfp
5657	5905	.type FlashSavePhyInfo, %function
5658	5906	FlashSavePhyInfo:
5659	5907	.fnstart
5660		- @ args = 0, pretend = 0, frame = 8
	5908	+ @ args = 0, pretend = 0, frame = 0
5661	5909	@ frame_needed = 0, uses_anonymous_args = 0
5662		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
5663		- .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
5664		- .pad #12
5665		- ldr r4, .L1020
5666		- ldr r7, .L1020+4
5667		- ldr r9, .L1020+8
5668		- ldr r3, [r4, #-1868]
5669		- mov r8, r4
5670		- ldrb r0, [r4, #-1779] @ zero_extendqisi2
5671		- mov fp, r7
5672		- str r3, [r4, #-1792]
	5910	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
	5911	+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
	5912	+ ldr r4, .L1028
	5913	+ ldr r5, .L1028+4
	5914	+ ldr r3, [r4, #-1864]
	5915	+ ldrb r0, [r4, #-1775] @ zero_extendqisi2
	5916	+ ldr r8, .L1028+8
	5917	+ str r3, [r4, #-1788]
5673	5918	bl FlashBchSel
5674		- mov r1, #0
5675	5919	mov r2, #2048
5676		- ldr r0, [r4, #-1868]
	5920	+ mov r1, #0
	5921	+ ldr r0, [r4, #-1864]
5677	5922	bl ftl_memset
5678		- ldr r3, [r4, #-1792]
5679		- ldr r1, .L1020+12
	5923	+ ldr r3, [r4, #-1788]
5680	5924	mov r2, #32
5681		- str r9, [r3]
5682		- ldr r0, [r4, #-1792]
5683		- ldrb r3, [r7, #3152] @ zero_extendqisi2
	5925	+ ldr r1, .L1028+12
	5926	+ str r8, [r3]
	5927	+ ldr r0, [r4, #-1788]
	5928	+ ldrb r3, [r5, #3156] @ zero_extendqisi2
5684	5929	add r0, r0, #16
5685	5930	strh r3, [r0, #-4] @ movhi
5686		- ldrb r3, [r7, #1] @ zero_extendqisi2
	5931	+ ldrb r3, [r5, #37] @ zero_extendqisi2
5687	5932	strh r3, [r0, #-2] @ movhi
5688		- ldrb r3, [r4, #-1860] @ zero_extendqisi2
	5933	+ ldrb r3, [r4, #-1856] @ zero_extendqisi2
5689	5934	str r3, [r0, #1060]
5690	5935	bl ftl_memcpy
5691		- ldr r0, [r4, #-1792]
5692		- ldr r1, .L1020+16
	5936	+ ldr r0, [r4, #-1788]
5693	5937	mov r2, #8
	5938	+ ldr r1, .L1028+16
5694	5939	add r0, r0, #80
5695	5940	bl ftl_memcpy
5696		- ldr r0, [r4, #-1792]
5697		- ldr r1, .L1020+20
	5941	+ ldr r0, [r4, #-1788]
5698	5942	mov r2, #32
	5943	+ add r1, r5, #3168
5699	5944	add r0, r0, #96
5700	5945	bl ftl_memcpy
5701		- ldr r0, [r4, #-1792]
5702		- ldr r1, .L1020+24
	5946	+ ldr r0, [r4, #-1788]
5703	5947	mov r2, #32
	5948	+ ldr r1, .L1028+20
5704	5949	add r0, r0, #160
5705	5950	bl ftl_memcpy
5706		- ldr r0, [r4, #-1792]
5707		- add r1, r7, #48
	5951	+ ldr r0, [r4, #-1788]
5708	5952	mov r2, #32
	5953	+ add r1, r5, #52
5709	5954	add r0, r0, #192
5710	5955	bl ftl_memcpy
5711		- ldr r0, [r4, #-1792]
	5956	+ ldr r0, [r4, #-1788]
	5957	+ sub r1, r4, #2720
5712	5958	mov r2, #852
5713		- ldr r1, .L1020+28
	5959	+ sub r1, r1, #8
5714	5960	add r0, r0, #224
5715	5961	bl ftl_memcpy
5716		- ldr r5, [r4, #-1792]
	5962	+ ldr r6, [r4, #-1788]
5717	5963	movw r1, #2036
5718		- add r0, r5, #12
	5964	+ add r0, r6, #12
5719	5965	bl js_hash
5720	5966	movw r3, #1592
5721		- str r3, [r5, #4]
5722		- ldr r3, [r4, #-1776]
5723		- str r3, [r4, #-1792]
5724		- str r0, [r5, #8]
	5967	+ str r0, [r6, #8]
	5968	+ str r3, [r6, #4]
	5969	+ mov r6, #0
	5970	+ ldr r3, [r4, #-1772]
	5971	+ mov r7, r6
5725	5972	mov r0, #0
	5973	+ str r3, [r4, #-1788]
5726	5974	bl flash_enter_slc_mode
5727		- mov r5, #0
5728		- mov r6, r5
5729		-.L1012:
5730		- ldr r1, [r7, #4]
5731		- mov r0, #0
5732		- mov r2, r0
5733		- mul r1, r1, r6
	5975	+.L1020:
	5976	+ ldr r1, [r5, #40]
	5977	+ mov r2, #0
	5978	+ mov r0, r2
	5979	+ mul r1, r1, r7
5734	5980	bl FlashEraseBlock
5735		- ldrb r10, [r4, #-2744] @ zero_extendqisi2
5736		- cmp r10, #0
5737		- beq .L1007
5738		- mov r10, #0
5739		-.L1008:
5740		- ldr r1, [r7, #4]
5741		- mov r0, #0
5742		- ldr r2, [r4, #-1868]
5743		- mov r3, r0
5744		- mla r1, r1, r6, r10
5745		- add r10, r10, #1
	5981	+ ldrb r9, [r4, #-2740] @ zero_extendqisi2
	5982	+ cmp r9, #0
	5983	+ beq .L1015
	5984	+ mov r9, #0
	5985	+.L1016:
	5986	+ ldr r1, [r5, #40]
	5987	+ mov r3, #0
	5988	+ ldr r2, [r4, #-1864]
	5989	+ mov r0, r3
	5990	+ mla r1, r1, r7, r9
	5991	+ add r9, r9, #1
5746	5992	bl FlashProgPage
5747		- cmp r10, #10
5748		- bne .L1008
5749		- b .L1009
5750		-.L1007:
5751		- ldr r1, [fp, #4]
5752		- mov r3, r10
5753		- ldr r2, [r8, #-1868]
5754		- mov r0, r10
5755		- mul r1, r1, r6
5756		- bl FlashProgPage
5757		- ldr r1, [fp, #4]
5758		- mov r0, r10
5759		- ldr r2, [r8, #-1868]
5760		- mov r3, r10
5761		- mul r1, r1, r6
5762		- add r1, r1, #1
5763		- bl FlashProgPage
5764		-.L1009:
5765		- ldr r1, [r7, #4]
5766		- mov r0, #0
5767		- ldr r2, [r4, #-1776]
5768		- mov r3, r0
5769		- mul r1, r1, r6
	5993	+ cmp r9, #10
	5994	+ bne .L1016
	5995	+.L1017:
	5996	+ ldr r1, [r5, #40]
	5997	+ mov r3, #0
	5998	+ ldr r2, [r4, #-1772]
	5999	+ mov r0, r3
	6000	+ add r10, r7, #1
	6001	+ mul r1, r1, r7
5770	6002	bl FlashReadRawPage
5771		- add r2, r6, #1
5772	6003	cmn r0, #1
5773		- beq .L1010
5774		- ldr r10, [r8, #-1792]
5775		- ldr r3, [r10]
5776		- cmp r3, r9
5777		- bne .L1010
5778		- add r0, r10, #12
	6004	+ beq .L1018
	6005	+ ldr r9, [r4, #-1788]
	6006	+ ldr r3, [r9]
	6007	+ cmp r3, r8
	6008	+ bne .L1018
5779	6009	movw r1, #2036
5780		- str r2, [sp, #4]
	6010	+ add r0, r9, #12
5781	6011	bl js_hash
5782		- ldr r3, [r10, #8]
	6012	+ ldr r3, [r9, #8]
5783	6013	cmp r3, r0
5784		- ldr r2, [sp, #4]
5785		- bne .L1010
5786		- ldr r3, [fp, #4]
5787		- cmp r5, #1
5788		- str r2, [r8, #-1784]
5789		- mul r6, r3, r6
5790		- str r6, [r8, #-1788]
5791		- beq .L1013
5792		- mov r5, #1
5793		-.L1010:
5794		- cmp r2, #4
5795		- mov r6, r2
5796		- bne .L1012
5797		- b .L1011
5798		-.L1013:
5799		- mov r5, #2
5800		-.L1011:
	6014	+ bne .L1018
	6015	+ ldr r3, [r5, #40]
	6016	+ cmp r6, #1
	6017	+ str r10, [r4, #-1780]
	6018	+ mul r7, r7, r3
	6019	+ str r7, [r4, #-1784]
	6020	+ beq .L1021
	6021	+ mov r6, #1
	6022	+.L1018:
	6023	+ cmp r10, #4
	6024	+ mov r7, r10
	6025	+ bne .L1020
	6026	+.L1019:
5801	6027	mov r0, #0
5802	6028	bl flash_exit_slc_mode
5803		- clz r0, r5
5804		- mov r0, r0, lsr #5
	6029	+ clz r0, r6
	6030	+ lsr r0, r0, #5
5805	6031	rsb r0, r0, #0
5806		- add sp, sp, #12
5807		- @ sp needed
5808		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	6032	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	6033	+.L1015:
	6034	+ ldr r1, [r5, #40]
	6035	+ mov r3, r9
	6036	+ ldr r2, [r4, #-1864]
	6037	+ mov r0, r9
	6038	+ mul r1, r1, r7
	6039	+ bl FlashProgPage
	6040	+ ldr r1, [r5, #40]
	6041	+ mov r3, r9
	6042	+ ldr r2, [r4, #-1864]
	6043	+ mov r0, r9
	6044	+ mul r1, r1, r7
	6045	+ add r1, r1, #1
	6046	+ bl FlashProgPage
	6047	+ b .L1017
5809	6048	.L1021:
	6049	+ mov r6, #2
	6050	+ b .L1019
	6051	+.L1029:
5810	6052	.align 2
5811		-.L1020:
	6053	+.L1028:
5812	6054	.word .LANCHOR2
5813	6055	.word .LANCHOR0
5814	6056	.word 1312902724
5815	6057	.word IDByte
5816		- .word .LANCHOR0+3156
5817		- .word .LANCHOR0+3164
5818		- .word .LANCHOR1+256
5819		- .word .LANCHOR2-2732
	6058	+ .word .LANCHOR0+3160
	6059	+ .word .LANCHOR1+468
5820	6060	.fnend
5821	6061	.size FlashSavePhyInfo, .-FlashSavePhyInfo
5822	6062	.align 2
5823	6063	.global FlashReadIdbDataRaw
	6064	+ .syntax unified
	6065	+ .arm
	6066	+ .fpu softvfp
5824	6067	.type FlashReadIdbDataRaw, %function
5825	6068	FlashReadIdbDataRaw:
5826	6069	.fnstart
5827	6070	@ args = 0, pretend = 0, frame = 16
5828	6071	@ frame_needed = 0, uses_anonymous_args = 0
5829		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	6072	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
5830	6073	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
5831		- mov r9, r0
5832		- ldr r3, .L1042
	6074	+ mov r3, #60
5833	6075	.pad #20
5834	6076	sub sp, sp, #20
5835		- ldr r5, .L1042+4
5836		- ldr r0, [r3] @ unaligned
5837		- ldrb r3, [r5, #-2743] @ zero_extendqisi2
5838		- str r0, [sp, #12] @ unaligned
5839		- str r3, [sp]
5840		- ldr r3, [r5, #-1864]
	6077	+ ldr r4, .L1049
	6078	+ mov r9, r0
	6079	+ strb r3, [sp, #12]
	6080	+ mov r3, #40
	6081	+ strb r3, [sp, #13]
	6082	+ mov r3, #24
	6083	+ strb r3, [sp, #14]
	6084	+ mov r3, #16
	6085	+ strb r3, [sp, #15]
	6086	+ ldrb r3, [r4, #-2739] @ zero_extendqisi2
	6087	+ str r3, [sp, #4]
	6088	+ ldr r3, [r4, #-1860]
5841	6089	cmp r3, #0
5842		- beq .L1023
	6090	+ beq .L1031
5843	6091	mov r0, #0
5844	6092	bl flash_enter_slc_mode
5845		-.L1023:
5846		- mov r0, r9
5847		- mov r1, #0
5848		- mov r2, #2048
5849		- ldr r10, .L1042+8
5850		- bl ftl_memset
5851		- mvn r8, #0
5852		- mov r4, #2
5853		- mov fp, r10
5854		-.L1024:
5855		- ldrb r3, [r10, #1] @ zero_extendqisi2
5856		- cmp r4, r3
5857		- bcs .L1028
5858		- mov r7, #0
5859		-.L1026:
5860		- add r3, sp, #12
5861		- ldr r6, .L1042+4
5862		- ldrb ip, [r7, r3] @ zero_extendqisi2
5863		- mov r0, ip
5864		- str ip, [sp, #4]
5865		- bl FlashBchSel
5866		- ldr r1, [fp, #4]
5867		- mov r0, #0
5868		- ldr r2, [r5, #-1868]
5869		- mov r3, r0
5870		- mul r1, r1, r4
5871		- bl FlashReadRawPage
5872		- cmn r0, #1
5873		- ldr ip, [sp, #4]
5874		- bne .L1025
5875		- add r7, r7, #1
5876		- cmp r7, #4
5877		- bne .L1026
5878		- b .L1027
5879		-.L1025:
5880		- ldr r3, [r6, #-1868]
5881		- ldr r2, .L1042+12
5882		- ldr r3, [r3]
5883		- cmp r3, r2
5884		- bne .L1027
5885		- mov r1, ip
5886		- ldr r0, .L1042+16
5887		- bl printk
5888		- mov r0, r9
5889		- ldr r1, [r6, #-1868]
5890		- mov r2, #2048
5891		- bl ftl_memcpy
5892		- ldr r3, [r6, #-1868]
5893		- ldr r3, [r3, #512]
5894		- strb r3, [fp, #1]
5895		- ldr r3, [r6, #-1784]
5896		- cmp r3, r4
5897		- bls .L1031
5898		- str r4, [r6, #-1784]
5899		- bl FlashSavePhyInfo
5900		- mov r8, #0
5901		-.L1027:
5902		- add r4, r4, #1
5903		- b .L1024
5904	6093	.L1031:
5905		- mov r8, #0
5906		-.L1028:
5907		- ldr r0, [sp]
	6094	+ ldr fp, .L1049+4
	6095	+ mvn r7, #0
	6096	+ mov r5, #2
	6097	+ mov r2, #2048
	6098	+ mov r1, #0
	6099	+ mov r0, r9
	6100	+ mov r10, fp
	6101	+ bl ftl_memset
	6102	+.L1032:
	6103	+ ldrb r3, [fp, #37] @ zero_extendqisi2
	6104	+ cmp r5, r3
	6105	+ bcc .L1037
	6106	+.L1036:
	6107	+ ldr r0, [sp, #4]
5908	6108	bl FlashBchSel
5909		- ldr r3, [r5, #-1864]
	6109	+ ldr r3, [r4, #-1860]
5910	6110	cmp r3, #0
5911		- beq .L1035
	6111	+ beq .L1030
5912	6112	mov r0, #0
5913	6113	bl flash_exit_slc_mode
5914		-.L1035:
5915		- mov r0, r8
	6114	+.L1030:
	6115	+ mov r0, r7
5916	6116	add sp, sp, #20
5917	6117	@ sp needed
5918		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
5919		-.L1043:
	6118	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	6119	+.L1037:
	6120	+ mov r6, #0
	6121	+.L1034:
	6122	+ add r3, sp, #12
	6123	+ ldrb r8, [r3, r6] @ zero_extendqisi2
	6124	+ mov r0, r8
	6125	+ bl FlashBchSel
	6126	+ ldr r1, [r10, #40]
	6127	+ mov r3, #0
	6128	+ ldr r2, [r4, #-1864]
	6129	+ mov r0, r3
	6130	+ mul r1, r1, r5
	6131	+ bl FlashReadRawPage
	6132	+ cmn r0, #1
	6133	+ bne .L1033
	6134	+ add r6, r6, #1
	6135	+ cmp r6, #4
	6136	+ bne .L1034
	6137	+.L1035:
	6138	+ add r5, r5, #1
	6139	+ b .L1032
	6140	+.L1040:
	6141	+ mov r7, #0
	6142	+ b .L1036
	6143	+.L1033:
	6144	+ ldr r3, [r4, #-1864]
	6145	+ ldr r2, .L1049+8
	6146	+ ldr r3, [r3]
	6147	+ cmp r3, r2
	6148	+ bne .L1035
	6149	+ mov r1, r8
	6150	+ ldr r0, .L1049+12
	6151	+ bl printk
	6152	+ mov r2, #2048
	6153	+ ldr r1, [r4, #-1864]
	6154	+ mov r0, r9
	6155	+ bl ftl_memcpy
	6156	+ ldr r3, [r4, #-1864]
	6157	+ ldr r3, [r3, #512]
	6158	+ strb r3, [r10, #37]
	6159	+ ldr r3, [r4, #-1780]
	6160	+ cmp r5, r3
	6161	+ bcs .L1040
	6162	+ str r5, [r4, #-1780]
	6163	+ mov r7, #0
	6164	+ bl FlashSavePhyInfo
	6165	+ b .L1035
	6166	+.L1050:
5920	6167	.align 2
5921		-.L1042:
5922		- .word .LANCHOR3
	6168	+.L1049:
5923	6169	.word .LANCHOR2
5924	6170	.word .LANCHOR0
5925	6171	.word -52655045
..	..	@@ -5928,530 +6174,437 @@
5928	6174	.size FlashReadIdbDataRaw, .-FlashReadIdbDataRaw
5929	6175	.align 2
5930	6176	.global FlashInit
	6177	+ .syntax unified
	6178	+ .arm
	6179	+ .fpu softvfp
5931	6180	.type FlashInit, %function
5932	6181	FlashInit:
5933	6182	.fnstart
5934		- @ args = 0, pretend = 0, frame = 0
	6183	+ @ args = 0, pretend = 0, frame = 8
5935	6184	@ frame_needed = 0, uses_anonymous_args = 0
5936		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	6185	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
5937	6186	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
5938	6187	mov r6, r0
5939		- .pad #20
5940		- sub sp, sp, #20
	6188	+ ldr r4, .L1149
	6189	+ .pad #28
	6190	+ sub sp, sp, #28
5941	6191	mov r0, #32768
5942		- bl ftl_malloc
5943		- ldr r4, .L1143
5944		- ldr r5, .L1143+4
5945	6192	mov r7, #0
5946		- str r0, [r4, #-1868]
	6193	+ bl ftl_dma32_malloc
	6194	+ str r0, [r4, #-1864]
5947	6195	mov r0, #32768
5948		- bl ftl_malloc
5949		- str r0, [r4, #-1776]
5950		- mov r0, #4096
5951		- bl ftl_malloc
	6196	+ bl ftl_dma32_malloc
5952	6197	str r0, [r4, #-1772]
5953		- mov r0, #32768
5954		- bl ftl_malloc
5955		- str r0, [r4, #-1768]
5956	6198	mov r0, #4096
5957		- bl ftl_malloc
5958		- mov r3, #50
5959		- str r7, [r4, #-1784]
5960		- strb r3, [r5, #1]
5961		- strb r3, [r4, #-1780]
5962		- mov r3, #128
5963		- strb r7, [r4, #-1860]
5964		- str r3, [r5, #4]
5965		- mov r3, #60
5966		- str r7, [r4, #-1800]
5967		- strb r7, [r5]
5968		- strb r7, [r4, #-1760]
5969		- strb r3, [r4, #-1779]
	6199	+ bl ftl_dma32_malloc
	6200	+ str r0, [r4, #-1768]
	6201	+ mov r0, #32768
	6202	+ bl ftl_dma32_malloc
5970	6203	str r0, [r4, #-1764]
	6204	+ mov r0, #4096
	6205	+ bl ftl_dma32_malloc
	6206	+ ldr r5, .L1149+4
	6207	+ mov r3, #50
	6208	+ str r0, [r4, #-1760]
5971	6209	mov r0, r6
5972		- bl NandcInit
5973		- ldr r6, .L1143+8
	6210	+ ldr r6, .L1149+8
	6211	+ mov r9, r7
	6212	+ strb r3, [r5, #37]
	6213	+ strb r3, [r4, #-1776]
	6214	+ mov r3, #128
5974	6215	mov r8, r6
5975		-.L1050:
5976		- ldr r3, .L1143+12
5977		- uxtb r9, r7
5978		- add r2, r3, r7, asl #3
5979		- mov r0, r9
5980		- ldr r10, [r3, r7, asl #3]
5981		- ldrb fp, [r2, #4] @ zero_extendqisi2
	6216	+ str r3, [r5, #40]
	6217	+ mov r3, #60
	6218	+ str r7, [r4, #-1780]
	6219	+ strb r7, [r4, #-1856]
	6220	+ str r7, [r4, #-1796]
	6221	+ strb r7, [r5, #36]
	6222	+ strb r7, [r4, #-1756]
	6223	+ strb r3, [r4, #-1775]
	6224	+ bl NandcInit
	6225	+.L1057:
	6226	+ add r2, r5, r7, lsl #3
	6227	+ uxtb r10, r7
	6228	+ ldr fp, [r5, r7, lsl #3]
	6229	+ ldrb r2, [r2, #4] @ zero_extendqisi2
	6230	+ mov r0, r10
	6231	+ str r2, [sp, #20]
5982	6232	bl FlashReset
5983		- mov r0, r9
	6233	+ mov r0, r10
5984	6234	bl NandcFlashCs
5985		- mov r2, #144
5986		- add fp, r10, fp, asl #8
	6235	+ ldr r2, [sp, #20]
	6236	+ mov r3, #144
5987	6237	mov r0, #200
5988		- mov r10, #0
5989		- str r2, [fp, #2056]
5990		- str r10, [fp, #2052]
5991		- bl NandcDelayns
	6238	+ add fp, fp, r2, lsl #8
	6239	+ str r3, [fp, #2056]
	6240	+ str r9, [fp, #2052]
	6241	+ bl ndelay
	6242	+ ldr r2, [fp, #2048]
	6243	+ uxtb r2, r2
	6244	+ strb r2, [r6]
	6245	+ cmp r2, #44
5992	6246	ldr r1, [fp, #2048]
5993		- uxtb r1, r1
5994		- strb r1, [r6]
5995		- ldr r0, [fp, #2048]
5996		- cmp r1, #44
5997		- strb r0, [r6, #1]
5998		- ldr r0, [fp, #2048]
5999		- strb r0, [r6, #2]
6000		- ldr r0, [fp, #2048]
6001		- strb r0, [r6, #3]
6002		- ldr r0, [fp, #2048]
6003		- strb r0, [r6, #4]
6004		- ldr r0, [fp, #2048]
6005		- strb r0, [r6, #5]
6006		- bne .L1045
6007		- mov r1, #239
	6247	+ strb r1, [r6, #1]
	6248	+ ldr r1, [fp, #2048]
	6249	+ strb r1, [r6, #2]
	6250	+ ldr r1, [fp, #2048]
	6251	+ strb r1, [r6, #3]
	6252	+ ldr r1, [fp, #2048]
	6253	+ strb r1, [r6, #4]
	6254	+ ldr r1, [fp, #2048]
	6255	+ strb r1, [r6, #5]
	6256	+ bne .L1052
	6257	+ mov r2, #239
6008	6258	mov r0, #200
6009		- str r1, [fp, #2056]
6010		- mov r1, #1
6011		- str r1, [fp, #2052]
6012		- bl NandcDelayns
6013		- mov r1, #4
6014		- str r1, [fp, #2048]
6015		- str r10, [fp, #2048]
6016		- str r10, [fp, #2048]
6017		- str r10, [fp, #2048]
6018		-.L1045:
6019		- mov r0, r9
	6259	+ str r2, [fp, #2056]
	6260	+ mov r2, #1
	6261	+ str r2, [fp, #2052]
	6262	+ bl ndelay
	6263	+ mov r2, #4
	6264	+ str r2, [fp, #2048]
	6265	+ str r9, [fp, #2048]
	6266	+ str r9, [fp, #2048]
	6267	+ str r9, [fp, #2048]
	6268	+.L1052:
	6269	+ mov r0, r10
6020	6270	bl NandcFlashDeCs
6021	6271	ldrb r2, [r6] @ zero_extendqisi2
6022	6272	sub r3, r2, #1
6023	6273	uxtb r3, r3
6024	6274	cmp r3, #253
6025		- bhi .L1046
6026		- ldrb r1, [r6, #2] @ zero_extendqisi2
	6275	+ bhi .L1053
	6276	+ ldrb r1, [r6, #5] @ zero_extendqisi2
6027	6277	ldrb r3, [r6, #1] @ zero_extendqisi2
6028		- ldr r0, .L1143+16
6029		- str r1, [sp]
6030		- ldrb r1, [r6, #3] @ zero_extendqisi2
6031		- str r1, [sp, #4]
	6278	+ ldr r0, .L1149+12
	6279	+ str r1, [sp, #12]
6032	6280	ldrb r1, [r6, #4] @ zero_extendqisi2
6033	6281	str r1, [sp, #8]
6034		- ldrb r1, [r6, #5] @ zero_extendqisi2
6035		- str r1, [sp, #12]
	6282	+ ldrb r1, [r6, #3] @ zero_extendqisi2
	6283	+ str r1, [sp, #4]
	6284	+ ldrb r1, [r6, #2] @ zero_extendqisi2
	6285	+ str r1, [sp]
6036	6286	add r1, r7, #1
6037	6287	bl printk
6038		-.L1046:
	6288	+.L1053:
6039	6289	cmp r7, #0
6040		- bne .L1047
	6290	+ bne .L1054
6041	6291	ldrb r3, [r8] @ zero_extendqisi2
6042	6292	sub r3, r3, #1
6043	6293	uxtb r3, r3
6044	6294	cmp r3, #253
6045		- bhi .L1097
6046		- ldr r3, .L1143+8
6047		- ldrb r3, [r3, #1] @ zero_extendqisi2
	6295	+ bhi .L1104
	6296	+ ldrb r3, [r8, #1] @ zero_extendqisi2
6048	6297	cmp r3, #255
6049		- beq .L1097
	6298	+ beq .L1104
6050	6299	bl FlashCs123Init
6051		-.L1047:
	6300	+.L1054:
6052	6301	ldrb r3, [r6] @ zero_extendqisi2
6053	6302	add r7, r7, #1
6054	6303	add r6, r6, #8
6055	6304	cmp r3, #181
6056	6305	moveq r3, #44
6057		- streqb r3, [r6, #-8]
	6306	+ strbeq r3, [r6, #-8]
6058	6307	cmp r7, #4
6059		- bne .L1050
	6308	+ bne .L1057
6060	6309	ldrb r3, [r8] @ zero_extendqisi2
6061	6310	cmp r3, #173
6062		- beq .L1051
6063		- ldr r0, [r4, #-1856]
	6311	+ beq .L1058
	6312	+ ldr r0, [r4, #-1852]
6064	6313	bl NandcSetDdrMode
6065		-.L1051:
	6314	+.L1058:
6066	6315	mov r2, #852
6067		- ldr r0, .L1143+20
6068	6316	mov r1, #0
6069		- ldr r7, .L1143+24
	6317	+ ldr r0, .L1149+16
6070	6318	bl ftl_memset
6071		- ldr r2, [r4, #-1848]
6072		- ldr r0, .L1143+28
6073		- cmp r2, r7
6074		- add r3, r0, #256
6075		- str r3, [r5, #44]
	6319	+ ldr r7, .L1149+20
	6320	+ ldr r2, .L1149+24
	6321	+ ldr r0, [r4, #-1844]
	6322	+ ldr r6, .L1149+28
	6323	+ add r3, r2, #468
	6324	+ cmp r0, r7
	6325	+ str r3, [r5, #48]
6076	6326	mov r3, #0
6077		- strb r3, [r5, #8]
6078		- bne .L1052
6079		- ldrb r3, [r0, #275] @ zero_extendqisi2
	6327	+ strb r3, [r5, #44]
	6328	+ bne .L1059
	6329	+ ldrb r3, [r2, #487] @ zero_extendqisi2
6080	6330	cmp r3, #50
6081		- ldrne r3, .L1143
6082		- movne r1, #1
6083		- strne r1, [r3, #-1864]
6084		-.L1052:
6085		- ldrb r6, [r8, #1] @ zero_extendqisi2
6086		- sub ip, r6, #218
6087		- cmp r6, #161
6088		- cmpne r6, #241
6089		- clz ip, ip
6090		- and r1, r6, #253
6091		- moveq r3, #1
6092		- movne r3, #0
6093		- mov ip, ip, lsr #5
6094		- orr r3, ip, r3
6095		- cmp r1, #209
6096		- orreq r3, r3, #1
6097		- cmp r3, #0
6098		- bne .L1053
6099		- cmp r6, #220
6100		- bne .L1054
6101		- ldr r3, .L1143+8
6102		- ldrb r3, [r3, #3] @ zero_extendqisi2
6103		- cmp r3, #149
6104		- bne .L1054
6105		-.L1053:
6106		- mov lr, #16
6107		- strb lr, [r5, #1]
6108		- strb lr, [r4, #-1779]
6109		- mov r1, #1
6110		- ldrb lr, [r8] @ zero_extendqisi2
6111		- strb r1, [r5]
6112		- cmp lr, #152
6113		- ldr r3, .L1143
6114		- strb lr, [r0, #3413]
6115		- strb r6, [r0, #3414]
6116		- bne .L1056
6117		- ldr lr, .L1143+8
6118		- ldrsb lr, [lr, #4]
6119		- cmp lr, #0
6120		- strltb r1, [r3, #-1760]
6121		- movge r1, #24
6122		- strgeb r1, [r3, #-1779]
6123		-.L1056:
6124		- movw r3, #2049
6125		- cmp r2, r7
6126		- cmpne r2, r3
6127		- moveq r3, #16
6128		- streqb r3, [r4, #-1779]
6129		- cmp ip, #0
6130		- ldrne r3, .L1143+32
6131		- movne r2, #2048
6132		- strneh r2, [r3, #14] @ movhi
6133		- mvnne r3, #37
6134		- bne .L1137
	6331	+ movne r3, #1
	6332	+ strne r3, [r4, #-1860]
	6333	+.L1059:
	6334	+ ldrb r3, [r8, #1] @ zero_extendqisi2
	6335	+ cmp r3, #241
	6336	+ cmpne r3, #161
	6337	+ and ip, r3, #253
	6338	+ moveq r1, #1
	6339	+ movne r1, #0
	6340	+ cmp r3, #218
	6341	+ orreq r1, r1, #1
	6342	+ cmp ip, #209
	6343	+ orreq r1, r1, #1
	6344	+ cmp r1, #0
	6345	+ bne .L1060
	6346	+ cmp r3, #220
	6347	+ bne .L1061
	6348	+ ldrb r1, [r8, #3] @ zero_extendqisi2
	6349	+ cmp r1, #149
	6350	+ bne .L1061
6135	6351	.L1060:
6136		- cmp r6, #220
6137		- bne .L1062
6138		- ldr r3, .L1143+32
6139		- mov r2, #4096
6140		- strh r2, [r3, #14] @ movhi
6141		- mvn r3, #35
6142		-.L1137:
6143		- strb r3, [r0, #3414]
6144		- b .L1061
6145		-.L1062:
6146		- cmp r6, #211
6147		- ldreq r3, .L1143+32
6148		- moveq r2, #4096
6149		- streqh r2, [r3, #14] @ movhi
6150		- moveq r3, #2
6151		- streqb r3, [r0, #3425]
6152		-.L1061:
6153		- ldr r1, .L1143+36
6154		- mov r2, #32
6155		- ldr r0, .L1143+40
6156		- bl ftl_memcpy
6157		- ldr r0, .L1143+44
6158		- ldr r1, .L1143+32
6159		- mov r2, #32
6160		- bl ftl_memcpy
6161		-.L1054:
6162		- ldrb r3, [r5] @ zero_extendqisi2
6163		- cmp r3, #0
	6352	+ mov ip, #16
	6353	+ mov r1, #1
	6354	+ strb ip, [r5, #37]
	6355	+ strb ip, [r4, #-1775]
	6356	+ ldrb ip, [r8] @ zero_extendqisi2
	6357	+ strb r1, [r5, #36]
	6358	+ strb r3, [r2, #3410]
	6359	+ cmp ip, #152
	6360	+ strb ip, [r2, #3409]
6164	6361	bne .L1063
	6362	+ ldrsb ip, [r8, #4]
	6363	+ cmp ip, #0
	6364	+ movge r1, #24
	6365	+ strblt r1, [r4, #-1756]
	6366	+ strbge r1, [r4, #-1775]
	6367	+.L1063:
	6368	+ movw r1, #2049
	6369	+ cmp r0, r1
	6370	+ cmpne r0, r7
	6371	+ moveq r1, #16
	6372	+ strbeq r1, [r4, #-1775]
	6373	+ cmp r3, #218
	6374	+ bne .L1067
	6375	+ ldr r3, .L1149+32
	6376	+ mov r1, #2048
	6377	+ strh r1, [r3, #14] @ movhi
	6378	+ mvn r3, #37
	6379	+.L1143:
	6380	+ strb r3, [r2, #3410]
	6381	+.L1068:
	6382	+ mov r2, #32
	6383	+ ldr r1, .L1149+36
	6384	+ ldr r0, .L1149+40
	6385	+ bl ftl_memcpy
	6386	+ mov r2, #32
	6387	+ ldr r1, .L1149+32
	6388	+ ldr r0, .L1149+44
	6389	+ bl ftl_memcpy
	6390	+.L1061:
	6391	+ ldrb r3, [r5, #36] @ zero_extendqisi2
	6392	+ cmp r3, #0
	6393	+ bne .L1071
6165	6394	bl FlashLoadPhyInfoInRam
6166	6395	cmp r0, #0
6167		- bne .L1065
6168		- ldr r3, .L1143+4
6169		- ldr r6, .L1143
6170		- ldr r3, [r3, #44]
	6396	+ bne .L1073
	6397	+ ldr r3, [r5, #48]
6171	6398	ldrh r3, [r3, #16]
6172		- mov r3, r3, lsr #8
	6399	+ lsr r3, r3, #8
6173	6400	tst r3, #1
6174	6401	and r0, r3, #7
6175		- strb r0, [r4, #-1875]
6176		- bne .L1065
	6402	+ strb r0, [r4, #-1871]
	6403	+ bne .L1073
6177	6404	mov r3, #1
6178		- strb r3, [r6, #-1860]
	6405	+ strb r3, [r4, #-1856]
6179	6406	bl FlashSetInterfaceMode
6180		- ldrb r0, [r6, #-1875] @ zero_extendqisi2
	6407	+ ldrb r0, [r4, #-1871] @ zero_extendqisi2
6181	6408	bl NandcSetMode
6182		-.L1065:
6183		- ldr r3, [r5, #44]
6184		- ldr r6, .L1143
	6409	+.L1073:
	6410	+ ldr r3, [r5, #48]
6185	6411	ldrb r3, [r3, #26] @ zero_extendqisi2
6186		- strb r3, [r4, #-2744]
	6412	+ strb r3, [r4, #-2740]
6187	6413	bl FlashLoadPhyInfo
6188	6414	cmp r0, #0
6189		- beq .L1063
6190		- ldr r3, [r6, #-1856]
	6415	+ beq .L1071
	6416	+ ldr r3, [r4, #-1852]
6191	6417	cmp r3, #0
6192		- beq .L1068
	6418	+ beq .L1076
6193	6419	mov r0, #1
6194	6420	bl FlashSetInterfaceMode
6195	6421	mov r0, #1
6196		- b .L1138
6197		-.L1068:
6198		- ldrb r0, [r6, #-1875] @ zero_extendqisi2
6199		- bl FlashSetInterfaceMode
6200		- ldrb r0, [r6, #-1875] @ zero_extendqisi2
6201		-.L1138:
	6422	+.L1144:
6202	6423	bl NandcSetMode
6203	6424	bl FlashLoadPhyInfo
6204	6425	cmp r0, #0
6205		- beq .L1063
	6426	+ beq .L1071
6206	6427	mov r0, #1
6207		- ldr r6, .L1143+4
6208	6428	bl FlashSetInterfaceMode
6209	6429	mov r0, #1
6210	6430	bl NandcSetMode
6211		- ldr r3, [r5, #44]
6212		- ldr r0, .L1143+48
	6431	+ ldr r3, [r5, #48]
	6432	+ ldr r0, .L1149+48
6213	6433	ldrh r1, [r3, #14]
6214	6434	bl printk
6215	6435	bl FlashLoadPhyInfoInRam
6216	6436	cmn r0, #1
6217		- beq .L1111
	6437	+ beq .L1051
6218	6438	bl FlashDieInfoInit
6219		- ldr r3, [r6, #44]
	6439	+ ldr r3, [r5, #48]
6220	6440	ldrb r0, [r3, #19] @ zero_extendqisi2
6221	6441	bl FlashGetReadRetryDefault
6222		- movw r3, #3324
6223		- ldr r2, [r6, #44]
6224		- ldrh r3, [r6, r3]
6225		- add r3, r3, #4080
	6442	+ ldr r3, .L1149+52
	6443	+ ldr r2, [r5, #48]
	6444	+ ldrh r3, [r3]
6226	6445	ldrb r1, [r2, #9] @ zero_extendqisi2
	6446	+ add r3, r3, #4080
6227	6447	add r3, r3, #15
6228	6448	cmp r1, r3, asr #12
6229	6449	ldrh r3, [r2, #14]
6230		- blt .L1070
	6450	+ blt .L1078
6231	6451	add r0, r3, #255
6232	6452	cmp r1, r0, asr #8
6233		- bge .L1071
6234		-.L1070:
	6453	+ bge .L1079
	6454	+.L1078:
6235	6455	bic r3, r3, #255
6236	6456	strh r3, [r2, #14] @ movhi
6237		-.L1071:
6238		- ldrb r3, [r4, #-1875] @ zero_extendqisi2
	6457	+.L1079:
	6458	+ ldrb r3, [r4, #-1871] @ zero_extendqisi2
6239	6459	tst r3, #6
6240		- beq .L1072
	6460	+ beq .L1080
6241	6461	bl FlashSavePhyInfo
6242	6462	mov r0, #0
6243	6463	bl flash_enter_slc_mode
6244		- ldr r3, .L1143
	6464	+ ldr r1, [r4, #-1784]
6245	6465	mov r0, #0
6246		- ldr r1, [r3, #-1788]
6247	6466	bl FlashDdrParaScan
6248	6467	mov r0, #0
6249	6468	bl flash_exit_slc_mode
6250		-.L1072:
	6469	+.L1080:
6251	6470	bl FlashSavePhyInfo
6252		-.L1063:
6253		- ldr r2, [r5, #44]
6254		- ldr r6, .L1143
6255		- ldrb r3, [r2, #26] @ zero_extendqisi2
6256		- ldrh r0, [r2, #10]
6257		- ldrb r9, [r2, #18] @ zero_extendqisi2
6258		- strb r3, [r4, #-2744]
6259		- ldrh r3, [r2, #16]
6260		- ubfx r1, r3, #7, #1
6261		- strb r1, [r5, #8]
6262		- ubfx r1, r3, #3, #1
6263		- strb r1, [r4, #-1759]
6264		- ubfx r1, r3, #4, #1
	6471	+.L1071:
	6472	+ ldr r9, [r5, #48]
	6473	+ ldrb r3, [r9, #26] @ zero_extendqisi2
	6474	+ ldrb r1, [r9, #12] @ zero_extendqisi2
	6475	+ ldrh r0, [r9, #10]
	6476	+ strb r3, [r4, #-2740]
	6477	+ ldrh r3, [r9, #16]
	6478	+ ubfx r2, r3, #7, #1
	6479	+ strb r2, [r5, #44]
	6480	+ ubfx r2, r3, #3, #1
	6481	+ strb r2, [r4, #-1755]
	6482	+ ubfx r2, r3, #4, #1
6265	6483	ubfx r3, r3, #8, #3
6266		- strb r1, [r4, #-1874]
6267		- strb r3, [r4, #-1875]
	6484	+ strb r2, [r4, #-1870]
	6485	+ strb r3, [r4, #-1871]
6268	6486	mov r3, #0
6269		- ldrb r1, [r2, #12] @ zero_extendqisi2
6270		- str r3, [r4, #-1796]
	6487	+ str r3, [r4, #-1792]
6271	6488	bl __aeabi_idiv
6272	6489	mov r1, r0
6273		- mov r0, r9
	6490	+ ldrb r0, [r9, #18] @ zero_extendqisi2
6274	6491	bl BuildFlashLsbPageTable
6275	6492	bl FlashDieInfoInit
6276		- ldr r3, [r5, #44]
	6493	+ ldr r3, [r5, #48]
6277	6494	ldrh r2, [r3, #16]
6278	6495	tst r2, #64
6279		- beq .L1074
	6496	+ beq .L1082
6280	6497	ldrb r0, [r3, #19] @ zero_extendqisi2
6281		- ldr r3, .L1143+52
6282		- ldr r2, .L1143+56
6283		- ldrb r1, [r6, #-2730] @ zero_extendqisi2
	6498	+ ldr r3, .L1149+56
	6499	+ ldr r2, .L1149+60
	6500	+ ldrb r1, [r4, #-2726] @ zero_extendqisi2
6284	6501	strb r0, [r3]
6285		- ldrb r3, [r6, #-2731] @ zero_extendqisi2
	6502	+ ldrb r3, [r4, #-2727] @ zero_extendqisi2
6286	6503	mov ip, r2
6287	6504	strb r3, [r2]
6288		- ldr r3, .L1143+60
	6505	+ ldr r3, .L1149+64
6289	6506	strb r1, [r3]
6290	6507	sub r1, r0, #1
6291	6508	cmp r1, #7
6292		- bhi .L1075
6293		- ldr r3, .L1143+64
6294		- sub r2, r0, #5
	6509	+ bhi .L1083
	6510	+ ldr r3, .L1149+68
	6511	+ str r3, [r4, #-1792]
	6512	+ sub r3, r0, #5
6295	6513	cmp r0, #8
6296		- cmpne r2, #1
6297		- sub r1, r0, #8
6298		- clz r1, r1
6299		- str r3, [r6, #-1796]
	6514	+ cmpne r3, #1
6300	6515	movls r3, #1
6301		- strls r3, [r6, #-1808]
	6516	+ strls r3, [r4, #-1804]
6302	6517	cmp r0, #7
6303		- mov r1, r1, lsr #5
6304		- ldreq r3, .L1143+68
6305		- beq .L1078
6306		- ldr r2, .L1143+68
	6518	+ beq .L1105
	6519	+ cmp r0, #8
	6520	+ addne r6, r6, #12
	6521	+ bne .L1085
	6522	+.L1105:
	6523	+ add r6, r6, #20
	6524	+.L1085:
	6525	+ sub r2, r6, #1
	6526	+ mov r3, #0
	6527	+ add r6, r6, #31
	6528	+.L1087:
	6529	+ ldrsb r1, [r2, #1]!
6307	6530	cmp r1, #0
6308		- sub r3, r2, #8
6309		- movne r3, r2
6310		-.L1078:
6311		- sub r1, r3, #1
6312		- add r3, r3, #31
6313		- mov r2, #0
6314		-.L1079:
6315		- ldrsb ip, [r1, #1]!
6316		- cmp ip, #0
6317		- addeq r2, r2, #1
6318		- cmp r1, r3
6319		- bne .L1079
6320		- cmp r2, #27
6321		- bls .L1074
	6531	+ addeq r3, r3, #1
	6532	+ cmp r6, r2
	6533	+ bne .L1087
	6534	+ cmp r3, #27
	6535	+ bls .L1082
6322	6536	bl FlashGetReadRetryDefault
6323	6537	bl FlashSavePhyInfo
6324		- b .L1074
6325		-.L1075:
6326		- sub r1, r0, #17
6327		- cmp r1, #2
6328		- bhi .L1081
6329		- ldr r2, .L1143+72
6330		- cmp r0, #19
6331		- str r2, [r6, #-1796]
6332		- moveq r2, #15
6333		- bne .L1142
6334		- b .L1140
6335		-.L1081:
6336		- sub r1, r0, #65
6337		- cmp r0, #33
6338		- cmpne r1, #1
6339		- bhi .L1083
6340		- ldr r1, .L1143+76
6341		- str r1, [r6, #-1796]
6342		- mov r1, #4
6343		- strb r1, [r2]
6344		-.L1142:
6345		- mov r2, #7
6346		-.L1140:
6347		- strb r2, [r3]
6348		- b .L1074
6349		-.L1083:
6350		- sub r1, r0, #67
6351		- sub r2, r0, #34
6352		- cmp r1, #1
6353		- movhi r1, #0
6354		- movls r1, #1
6355		- cmp r2, #1
6356		- movhi r2, r1
6357		- orrls r2, r1, #1
6358		- cmp r2, #0
6359		- beq .L1084
6360		- ldr r2, .L1143+76
6361		- cmp r0, #68
6362		- cmpne r0, #35
6363		- str r2, [r6, #-1796]
6364		- movne r2, #7
6365		- moveq r2, #17
6366		- cmp r1, #0
6367		- strb r2, [r3]
6368		- movne r3, #4
6369		- moveq r3, #5
6370		- strb r3, [ip]
6371		- b .L1074
6372		-.L1084:
6373		- cmp r0, #49
6374		- ldreq r3, .L1143+80
6375		- streq r3, [r6, #-1796]
6376		- beq .L1074
6377		- cmp r0, #50
6378		- streq r2, [r6, #-1864]
6379		- ldreq r3, .L1143+84
6380		- streq r3, [r6, #-1796]
6381		-.L1074:
6382		- ldr r3, [r4, #-1848]
	6538	+.L1082:
	6539	+ ldr r3, [r4, #-1844]
6383	6540	cmp r3, r7
6384		- bne .L1089
6385		- ldr r2, .L1143
6386		- ldrb r2, [r2, #-2744] @ zero_extendqisi2
	6541	+ bne .L1097
	6542	+ ldrb r2, [r4, #-2740] @ zero_extendqisi2
6387	6543	cmp r2, #0
6388		- ldrne r2, [r5, #44]
	6544	+ ldrne r2, [r5, #48]
6389	6545	movne r1, #0
6390		- strneb r1, [r2, #18]
6391		-.L1089:
	6546	+ strbne r1, [r2, #18]
	6547	+.L1097:
6392	6548	ldrb r2, [r8] @ zero_extendqisi2
6393	6549	cmp r2, #44
6394		- bne .L1090
6395		- ldrb r2, [r4, #-1860] @ zero_extendqisi2
	6550	+ bne .L1098
	6551	+ ldrb r2, [r4, #-1856] @ zero_extendqisi2
6396	6552	cmp r2, #0
6397		- beq .L1090
	6553	+ beq .L1098
6398	6554	cmp r3, r7
6399		- bne .L1091
6400		- ldr r3, .L1143
6401		- ldrb r3, [r3, #-2744] @ zero_extendqisi2
	6555	+ bne .L1099
	6556	+ ldrb r3, [r4, #-2740] @ zero_extendqisi2
6402	6557	cmp r3, #0
6403		- bne .L1090
6404		-.L1091:
6405		- mov r0, #1
	6558	+ bne .L1098
	6559	+.L1099:
6406	6560	mov r3, #0
6407		- strb r3, [r4, #-1860]
	6561	+ mov r0, #1
	6562	+ strb r3, [r4, #-1856]
6408	6563	bl FlashSetInterfaceMode
6409	6564	mov r0, #1
6410	6565	bl NandcSetMode
6411		-.L1090:
6412		- ldrb r3, [r4, #-1875] @ zero_extendqisi2
	6566	+.L1098:
	6567	+ ldrb r3, [r4, #-1871] @ zero_extendqisi2
6413	6568	tst r3, #6
6414		- beq .L1092
6415		- ldr r2, .L1143
6416		- ldrb r2, [r2, #-1860] @ zero_extendqisi2
	6569	+ beq .L1100
	6570	+ ldrb r2, [r4, #-1856] @ zero_extendqisi2
6417	6571	cmp r2, #0
6418		- bne .L1093
	6572	+ bne .L1101
6419	6573	tst r3, #1
6420		- bne .L1092
6421		-.L1093:
	6574	+ bne .L1100
	6575	+.L1101:
6422	6576	mov r0, #0
6423	6577	bl flash_enter_slc_mode
	6578	+ ldr r1, [r4, #-1784]
6424	6579	mov r0, #0
6425		- ldr r1, [r4, #-1788]
6426	6580	bl FlashDdrParaScan
6427	6581	mov r0, #0
6428	6582	bl flash_exit_slc_mode
6429		-.L1092:
6430		- ldr r3, [r5, #44]
6431		- mov r10, #16
6432		- ldr r9, .L1143+4
6433		- ldr r6, .L1143+88
	6583	+.L1100:
	6584	+ ldr r3, [r5, #48]
	6585	+ mov r9, #16
	6586	+ ldr r6, .L1149+72
6434	6587	ldrb r0, [r3, #20] @ zero_extendqisi2
6435	6588	bl FlashBchSel
6436		- add r0, r9, #3328
	6589	+ ldr r0, .L1149+76
6437	6590	bl FlashReadIdbDataRaw
6438		- ldr r0, .L1143+92
6439		- strb r10, [r5, #1]
	6591	+ ldr r0, .L1149+80
	6592	+ strb r9, [r5, #37]
6440	6593	bl FlashTimingCfg
6441		- ldr r7, [r5, #44]
	6594	+ ldr r7, [r5, #48]
6442	6595	ldrb r2, [r8, #1] @ zero_extendqisi2
6443	6596	ldrb r3, [r7, #12] @ zero_extendqisi2
6444	6597	strh r3, [r6, #8] @ movhi
6445	6598	ldrb r3, [r7, #7] @ zero_extendqisi2
6446		- str r3, [r4, #-2768]
6447		- mov r3, r2, asl r10
6448		- orr r2, r3, r2, asl #8
6449		- ldrb r3, [r8] @ zero_extendqisi2
6450		- orr r3, r2, r3
	6599	+ str r3, [r4, #-2764]
	6600	+ lsl r3, r2, r9
	6601	+ orr r3, r3, r2, lsl #8
	6602	+ ldrb r2, [r8] @ zero_extendqisi2
	6603	+ orr r3, r3, r2
6451	6604	ldrb r2, [r8, #3] @ zero_extendqisi2
6452		- orr r3, r3, r2, asl #24
6453		- str r3, [r4, #-2772]
6454		- ldrb r3, [r5, #3152] @ zero_extendqisi2
	6605	+ orr r3, r3, r2, lsl #24
	6606	+ str r3, [r4, #-2768]
	6607	+ ldrb r3, [r5, #3156] @ zero_extendqisi2
6455	6608	ldrh r4, [r7, #14]
6456	6609	strh r3, [r6, #10] @ movhi
6457	6610	ldrb r3, [r7, #13] @ zero_extendqisi2
..	..	@@ -6465,319 +6618,395 @@
6465	6618	strh r0, [r6, #18] @ movhi
6466	6619	ldrb r2, [r7, #9] @ zero_extendqisi2
6467	6620	strh r2, [r6, #20] @ movhi
6468		- ldrb r1, [r7, #9] @ zero_extendqisi2
6469		- ldrh r3, [r7, #10]
6470		- smulbb r3, r1, r3
	6621	+ ldrh r1, [r7, #10]
	6622	+ ldrb r3, [r7, #9] @ zero_extendqisi2
	6623	+ smulbb r3, r3, r1
6471	6624	mov r1, #512
6472	6625	strh r1, [r6, #24] @ movhi
6473		- ldrb r1, [r5, #1] @ zero_extendqisi2
6474		- strh r1, [r6, #26] @ movhi
	6626	+ ldrb r1, [r5, #37] @ zero_extendqisi2
6475	6627	uxth r3, r3
6476		- ldrb r1, [r5] @ zero_extendqisi2
	6628	+ strh r1, [r6, #26] @ movhi
	6629	+ ldrb r1, [r5, #36] @ zero_extendqisi2
6477	6630	strh r3, [r6, #22] @ movhi
6478	6631	cmp r1, #1
6479		- bne .L1095
6480		- mov r3, r3, asl #1
6481		- mov r4, r4, lsr #1
6482		- mov r2, r2, asl #1
	6632	+ bne .L1102
	6633	+ lsl r3, r3, #1
	6634	+ lsr r4, r4, #1
	6635	+ lsl r2, r2, #1
	6636	+ strb r9, [r5, #37]
6483	6637	strh r3, [r6, #22] @ movhi
6484		- strb r10, [r9, #1]
6485	6638	mov r3, #8
6486	6639	strh r4, [r6, #14] @ movhi
6487	6640	strh r2, [r6, #20] @ movhi
6488	6641	strh r3, [r6, #26] @ movhi
6489		-.L1095:
	6642	+.L1102:
6490	6643	ldrb r0, [r7, #20] @ zero_extendqisi2
6491	6644	bl FlashBchSel
6492	6645	bl ftl_flash_suspend
6493	6646	mov r0, #0
6494		- b .L1111
6495		-.L1097:
6496		- mvn r0, #1
6497		-.L1111:
6498		- add sp, sp, #20
	6647	+.L1051:
	6648	+ add sp, sp, #28
6499	6649	@ sp needed
6500		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
6501		-.L1144:
	6650	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	6651	+.L1067:
	6652	+ cmp r3, #220
	6653	+ ldreq r3, .L1149+32
	6654	+ moveq r1, #4096
	6655	+ strheq r1, [r3, #14] @ movhi
	6656	+ mvneq r3, #35
	6657	+ beq .L1143
	6658	+.L1069:
	6659	+ cmp r3, #211
	6660	+ ldreq r3, .L1149+32
	6661	+ moveq r1, #4096
	6662	+ strheq r1, [r3, #14] @ movhi
	6663	+ moveq r3, #2
	6664	+ strbeq r3, [r2, #3421]
	6665	+ b .L1068
	6666	+.L1076:
	6667	+ ldrb r0, [r4, #-1871] @ zero_extendqisi2
	6668	+ bl FlashSetInterfaceMode
	6669	+ ldrb r0, [r4, #-1871] @ zero_extendqisi2
	6670	+ b .L1144
	6671	+.L1083:
	6672	+ sub r1, r0, #17
	6673	+ cmp r1, #2
	6674	+ bhi .L1089
	6675	+ ldr r2, .L1149+84
	6676	+ cmp r0, #19
	6677	+ str r2, [r4, #-1792]
	6678	+ moveq r2, #15
	6679	+ beq .L1146
	6680	+.L1148:
	6681	+ mov r2, #7
	6682	+.L1146:
	6683	+ strb r2, [r3]
	6684	+ b .L1082
	6685	+.L1089:
	6686	+ sub r1, r0, #65
	6687	+ cmp r0, #33
	6688	+ cmpne r1, #1
	6689	+ ldrls r1, .L1149+88
	6690	+ strls r1, [r4, #-1792]
	6691	+ movls r1, #4
	6692	+ strbls r1, [r2]
	6693	+ bls .L1148
	6694	+.L1091:
	6695	+ sub r2, r0, #67
	6696	+ sub r1, r0, #34
	6697	+ uxtb r2, r2
	6698	+ cmp r2, #1
	6699	+ cmphi r1, #1
	6700	+ movls r1, #1
	6701	+ movhi r1, #0
	6702	+ bhi .L1092
	6703	+ ldr r1, .L1149+88
	6704	+ cmp r0, #68
	6705	+ cmpne r0, #35
	6706	+ str r1, [r4, #-1792]
	6707	+ movne r1, #7
	6708	+ moveq r1, #17
	6709	+ cmp r2, #1
	6710	+ strb r1, [r3]
	6711	+ movls r3, #4
	6712	+ movhi r3, #5
	6713	+ strb r3, [ip]
	6714	+ b .L1082
	6715	+.L1092:
	6716	+ cmp r0, #49
	6717	+ ldreq r3, .L1149+92
	6718	+ streq r3, [r4, #-1792]
	6719	+ beq .L1082
	6720	+ cmp r0, #50
	6721	+ ldreq r3, .L1149+96
	6722	+ streq r1, [r4, #-1860]
	6723	+ streq r3, [r4, #-1792]
	6724	+ b .L1082
	6725	+.L1104:
	6726	+ mvn r0, #1
	6727	+ b .L1051
	6728	+.L1150:
6502	6729	.align 2
6503		-.L1143:
	6730	+.L1149:
6504	6731	.word .LANCHOR2
6505	6732	.word .LANCHOR0
6506	6733	.word IDByte
6507		- .word .LANCHOR0+12
6508	6734	.word .LC14
6509		- .word .LANCHOR2-2732
	6735	+ .word .LANCHOR2-2728
6510	6736	.word 1446522928
6511	6737	.word .LANCHOR1
6512		- .word .LANCHOR1+3412
6513		- .word .LANCHOR1+3072
6514		- .word .LANCHOR0+48
6515		- .word .LANCHOR1+256
	6738	+ .word .LANCHOR2-2720
	6739	+ .word .LANCHOR1+3408
	6740	+ .word .LANCHOR1+3284
	6741	+ .word .LANCHOR0+52
	6742	+ .word .LANCHOR1+468
6516	6743	.word .LC15
	6744	+ .word .LANCHOR0+3328
6517	6745	.word g_retryMode
6518	6746	.word g_maxRegNum
6519	6747	.word g_maxRetryCount
6520	6748	.word HynixReadRetrial
6521		- .word .LANCHOR2-2704
	6749	+ .word .LANCHOR2-2768
	6750	+ .word .LANCHOR0+3332
	6751	+ .word 150000
6522	6752	.word MicronReadRetrial
6523	6753	.word ToshibaReadRetrial
6524	6754	.word SamsungReadRetrial
6525	6755	.word samsung_read_retrial
6526		- .word .LANCHOR2-2772
6527		- .word 150000
6528	6756	.fnend
6529	6757	.size FlashInit, .-FlashInit
6530	6758	.align 2
6531	6759	.global FlashPageProgMsbFFData
	6760	+ .syntax unified
	6761	+ .arm
	6762	+ .fpu softvfp
6532	6763	.type FlashPageProgMsbFFData, %function
6533	6764	FlashPageProgMsbFFData:
6534	6765	.fnstart
6535	6766	@ args = 0, pretend = 0, frame = 0
6536	6767	@ frame_needed = 0, uses_anonymous_args = 0
6537		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
	6768	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
6538	6769	.save {r4, r5, r6, r7, r8, r9, r10, lr}
6539		- mov r7, r1
6540		- ldr r5, .L1162
6541		- mov r4, r2
6542		- ldr r1, .L1162+4
6543	6770	mov r6, r0
6544		- ldrb r2, [r5, #-2744] @ zero_extendqisi2
6545		- ldr r3, [r1, #44]
6546		- mov r8, r1
6547		- cmp r2, #0
6548		- ldrb r3, [r3, #19] @ zero_extendqisi2
6549		- beq .L1146
6550		- ldr r2, [r5, #-1864]
6551		- cmp r2, #0
6552		- ldmnefd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
6553		-.L1146:
6554		- sub r2, r3, #5
6555		- cmp r3, #50
6556		- cmpne r2, #2
6557		- bls .L1147
6558		- sub r2, r3, #19
6559		- tst r2, #239
6560		- moveq r2, #1
6561		- movne r2, #0
6562		- cmp r3, #68
6563		- movne r3, r2
6564		- orreq r3, r2, #1
	6771	+ ldr r5, .L1167
	6772	+ mov r7, r1
	6773	+ mov r4, r2
	6774	+ ldrb r3, [r5, #-2740] @ zero_extendqisi2
6565	6775	cmp r3, #0
6566		- ldmeqfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
6567		-.L1147:
6568		- ldr r9, .L1162+8
	6776	+ beq .L1152
	6777	+ ldr r3, [r5, #-1860]
	6778	+ cmp r3, #0
	6779	+ popne {r4, r5, r6, r7, r8, r9, r10, pc}
	6780	+.L1152:
	6781	+ ldr r2, .L1167+4
	6782	+ ldr r3, [r2, #48]
	6783	+ mov r8, r2
	6784	+ ldrb r3, [r3, #19] @ zero_extendqisi2
	6785	+ sub r1, r3, #5
	6786	+ cmp r3, #50
	6787	+ cmpne r1, #2
	6788	+ bls .L1153
	6789	+ sub r2, r3, #19
	6790	+ and r2, r2, #239
	6791	+ cmp r2, #0
	6792	+ cmpne r3, #68
	6793	+ popne {r4, r5, r6, r7, r8, r9, r10, pc}
	6794	+.L1153:
	6795	+ ldr r9, .L1167+8
6569	6796	movw r10, #65535
6570		-.L1149:
6571		- ldr r3, [r8, #44]
	6797	+.L1155:
	6798	+ ldr r3, [r8, #48]
6572	6799	ldrh r3, [r3, #10]
6573	6800	cmp r3, r4
6574		- bls .L1161
6575		- mov r3, r4, asl #1
	6801	+ bhi .L1156
	6802	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	6803	+.L1156:
	6804	+ lsl r3, r4, #1
6576	6805	ldrh r3, [r9, r3]
6577	6806	cmp r3, r10
6578		- ldmnefd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
6579		- mov r1, #255
	6807	+ popne {r4, r5, r6, r7, r8, r9, r10, pc}
6580	6808	mov r2, #32768
6581		- ldr r0, [r5, #-1776]
	6809	+ mov r1, #255
	6810	+ ldr r0, [r5, #-1772]
6582	6811	bl ftl_memset
6583		- ldr r2, [r5, #-1776]
	6812	+ ldr r3, [r5, #-1772]
6584	6813	add r1, r4, r7
6585		- add r4, r4, #1
6586	6814	mov r0, r6
6587		- mov r3, r2
	6815	+ add r4, r4, #1
6588	6816	uxth r4, r4
	6817	+ mov r2, r3
6589	6818	bl FlashProgPage
6590		- b .L1149
6591		-.L1161:
6592		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
6593		-.L1163:
	6819	+ b .L1155
	6820	+.L1168:
6594	6821	.align 2
6595		-.L1162:
	6822	+.L1167:
6596	6823	.word .LANCHOR2
6597	6824	.word .LANCHOR0
6598		- .word .LANCHOR0+1104
	6825	+ .word .LANCHOR0+1108
6599	6826	.fnend
6600	6827	.size FlashPageProgMsbFFData, .-FlashPageProgMsbFFData
6601	6828	.align 2
6602	6829	.global FlashReadSlc2KPages
	6830	+ .syntax unified
	6831	+ .arm
	6832	+ .fpu softvfp
6603	6833	.type FlashReadSlc2KPages, %function
6604	6834	FlashReadSlc2KPages:
6605	6835	.fnstart
6606	6836	@ args = 0, pretend = 0, frame = 24
6607	6837	@ frame_needed = 0, uses_anonymous_args = 0
6608		- ldr r3, .L1215
6609		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	6838	+ ldr r3, .L1218
	6839	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
6610	6840	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	6841	+ mov r4, r0
	6842	+ ldr r10, .L1218+4
	6843	+ mov r8, #0
6611	6844	.pad #36
6612	6845	sub sp, sp, #36
6613		- ldrb r3, [r3, #265] @ zero_extendqisi2
6614		- mov r4, r0
6615		- ldr r10, .L1215+4
6616		- mov r9, #0
	6846	+ ldr r9, .L1218+8
	6847	+ ldrb r3, [r3, #477] @ zero_extendqisi2
6617	6848	str r1, [sp, #16]
6618	6849	str r2, [sp, #20]
6619	6850	str r3, [sp, #12]
6620		-.L1165:
	6851	+.L1170:
6621	6852	ldr r3, [sp, #16]
6622		- cmp r9, r3
6623		- beq .L1214
	6853	+ cmp r8, r3
	6854	+ bne .L1190
	6855	+ mov r0, #0
	6856	+ add sp, sp, #36
	6857	+ @ sp needed
	6858	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	6859	+.L1190:
6624	6860	ldr r3, [sp, #16]
6625		- mov r0, r4
6626		- ldr r1, [sp, #20]
6627	6861	add r2, sp, #28
6628		- rsb r3, r9, r3
6629		- ldr r8, .L1215+8
	6862	+ ldr r1, [sp, #20]
	6863	+ mov r0, r4
	6864	+ sub r3, r3, r8
6630	6865	uxtb r3, r3
6631	6866	str r3, [sp]
6632	6867	add r3, sp, #24
6633	6868	bl LogAddr2PhyAddr
6634		- ldrb r3, [r8, #3152] @ zero_extendqisi2
6635		- ldr r5, [sp, #24]
6636		- cmp r5, r3
6637		- mvncs r3, #0
6638		- strcs r3, [r4]
6639		- bcs .L1167
6640		- add r5, r8, r5
	6869	+ ldrb r2, [r10, #3156] @ zero_extendqisi2
	6870	+ ldr r3, [sp, #24]
	6871	+ cmp r2, r3
	6872	+ mvnls r3, #0
	6873	+ strls r3, [r4]
	6874	+ bls .L1172
	6875	+ add r3, r10, r3
6641	6876	mov r7, #0
6642		- ldrb r5, [r5, #3156] @ zero_extendqisi2
6643		- mov r0, r5
	6877	+ ldrb r6, [r3, #3160] @ zero_extendqisi2
	6878	+ mov r0, r6
6644	6879	bl NandcWaitFlashReady
6645		- mov r0, r5
	6880	+ mov r0, r6
6646	6881	bl NandcFlashCs
6647		-.L1168:
	6882	+.L1173:
6648	6883	ldr r1, [sp, #28]
6649		- mov r0, r5
	6884	+ mov r0, r6
6650	6885	bl FlashReadCmd
6651		- mov r0, r5
	6886	+ mov r0, r6
6652	6887	bl NandcWaitFlashReady
6653	6888	ldr r3, [r4, #12]
6654		- mov r0, r5
6655	6889	mov r1, #0
6656		- str r3, [sp]
6657	6890	ldr r2, [sp, #12]
	6891	+ mov r0, r6
	6892	+ str r3, [sp]
6658	6893	ldr r3, [r4, #8]
6659	6894	bl NandcXferData
6660		- ldr r3, .L1215+4
6661		- ldrb r3, [r3, #-1760] @ zero_extendqisi2
	6895	+ ldrb r3, [r9, #-1756] @ zero_extendqisi2
	6896	+ mov r5, r0
6662	6897	cmp r3, #0
6663		- mov r6, r0
6664		- beq .L1169
6665		- mov r0, r5
	6898	+ beq .L1174
	6899	+ mov r0, r6
6666	6900	bl flash_read_ecc
6667	6901	cmp r0, #5
6668		- movhi r6, #256
6669		-.L1169:
	6902	+ movhi r5, #256
	6903	+.L1174:
6670	6904	cmp r7, #9
6671		- cmnls r6, #1
	6905	+ cmnls r5, #1
6672	6906	moveq r3, #1
6673	6907	movne r3, #0
6674	6908	addeq r7, r7, #1
6675		- beq .L1168
6676		-.L1170:
	6909	+ beq .L1173
	6910	+.L1175:
6677	6911	cmp r7, #0
6678	6912	mov r7, r3
6679		- movne r6, #256
6680		-.L1172:
6681		- ldr r3, [sp, #28]
6682		- mov r0, r5
6683		- ldr r1, [r8, #4]
	6913	+ movne r5, #256
	6914	+.L1177:
	6915	+ ldr r3, [r10, #40]
	6916	+ mov r0, r6
	6917	+ ldr r1, [sp, #28]
6684	6918	add r1, r1, r3
6685	6919	bl FlashReadCmd
6686		- mov r0, r5
	6920	+ mov r0, r6
6687	6921	bl NandcWaitFlashReady
6688	6922	ldr r3, [r4, #8]
6689		- ldr r2, [r4, #12]
6690		- mov r0, r5
6691		- cmp r3, #0
6692	6923	mov r1, #0
	6924	+ ldr r2, [r4, #12]
	6925	+ mov r0, r6
	6926	+ cmp r3, #0
6693	6927	addne r3, r3, #2048
6694	6928	cmp r2, #0
6695	6929	addne r2, r2, #8
6696	6930	str r2, [sp]
6697	6931	ldr r2, [sp, #12]
6698	6932	bl NandcXferData
6699		- ldrb r2, [r10, #-1760] @ zero_extendqisi2
6700		- cmp r2, #0
	6933	+ ldrb r2, [r9, #-1756] @ zero_extendqisi2
6701	6934	mov fp, r0
6702		- beq .L1175
6703		- mov r0, r5
	6935	+ cmp r2, #0
	6936	+ beq .L1180
	6937	+ mov r0, r6
6704	6938	bl flash_read_ecc
6705	6939	cmp r0, #5
6706	6940	movhi fp, #256
6707		-.L1175:
	6941	+.L1180:
6708	6942	cmp r7, #9
6709	6943	cmnls fp, #1
6710	6944	addeq r7, r7, #1
6711		- beq .L1172
6712		-.L1176:
	6945	+ beq .L1177
	6946	+.L1181:
6713	6947	cmp r7, #0
6714		- mov r0, r5
	6948	+ mov r0, r6
6715	6949	movne fp, #256
6716	6950	bl NandcFlashDeCs
6717		- ldrb r2, [r10, #-2743] @ zero_extendqisi2
6718		- cmp fp, r6
6719		- movcs r3, fp
6720		- movcc r3, r6
6721		- add r2, r2, r2, asl #1
6722		- cmp r3, r2, asr #2
6723		- bls .L1178
6724		- cmn r3, #1
6725		- movne r3, #256
6726		-.L1178:
6727		- cmp r3, #256
6728		- cmnne r3, #1
	6951	+ ldrb r3, [r9, #-2739] @ zero_extendqisi2
	6952	+ cmp r5, fp
	6953	+ movcc r5, fp
	6954	+ add r3, r3, r3, lsl #1
	6955	+ cmp r5, r3, asr #2
	6956	+ bls .L1183
	6957	+ cmn r5, #1
	6958	+ movne r5, #256
	6959	+.L1183:
	6960	+ cmp r5, #256
	6961	+ cmnne r5, #1
6729	6962	movne r3, #0
6730		- str r3, [r4]
	6963	+ streq r5, [r4]
	6964	+ strne r3, [r4]
6731	6965	ldr r3, [r4, #12]
6732	6966	cmp r3, #0
6733		- beq .L1181
	6967	+ beq .L1186
6734	6968	ldr r2, [r3, #12]
6735	6969	cmn r2, #1
6736		- bne .L1181
	6970	+ bne .L1186
6737	6971	ldr r2, [r3, #8]
6738	6972	cmn r2, #1
6739		- bne .L1181
	6973	+ bne .L1186
6740	6974	ldr r3, [r3]
6741	6975	cmn r3, #1
6742	6976	strne r2, [r4]
6743		-.L1181:
	6977	+.L1186:
6744	6978	ldr r3, [r4]
6745	6979	cmn r3, #1
6746		- bne .L1167
	6980	+ bne .L1172
6747	6981	ldr r1, [r4, #4]
6748		- ldr r0, .L1215+12
6749		- ldrb r2, [r10, #-2743] @ zero_extendqisi2
	6982	+ ldrb r2, [r9, #-2739] @ zero_extendqisi2
	6983	+ ldr r0, .L1218+12
6750	6984	bl printk
6751	6985	ldr r1, [r4, #8]
6752	6986	cmp r1, #0
6753		- beq .L1183
6754		- ldr r0, .L1215+16
6755		- mov r2, #4
	6987	+ beq .L1188
6756	6988	mov r3, #8
	6989	+ mov r2, #4
	6990	+ ldr r0, .L1218+16
6757	6991	bl rknand_print_hex
6758		-.L1183:
	6992	+.L1188:
6759	6993	ldr r1, [r4, #12]
6760	6994	cmp r1, #0
6761		- beq .L1167
6762		- mov r2, #4
6763		- ldr r0, .L1215+20
6764		- mov r3, r2
	6995	+ beq .L1172
	6996	+ mov r3, #4
	6997	+ ldr r0, .L1218+20
	6998	+ mov r2, r3
6765	6999	bl rknand_print_hex
6766		-.L1167:
6767		- add r9, r9, #1
	7000	+.L1172:
	7001	+ add r8, r8, #1
6768	7002	add r4, r4, #36
6769		- b .L1165
6770		-.L1214:
6771		- mov r0, #0
6772		- add sp, sp, #36
6773		- @ sp needed
6774		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
6775		-.L1216:
	7003	+ b .L1170
	7004	+.L1219:
6776	7005	.align 2
6777		-.L1215:
	7006	+.L1218:
6778	7007	.word .LANCHOR1
6779		- .word .LANCHOR2
6780	7008	.word .LANCHOR0
	7009	+ .word .LANCHOR2
6781	7010	.word .LC16
6782	7011	.word .LC17
6783	7012	.word .LC18
..	..	@@ -6785,1281 +7014,1394 @@
6785	7014	.size FlashReadSlc2KPages, .-FlashReadSlc2KPages
6786	7015	.align 2
6787	7016	.global FlashReadPages
	7017	+ .syntax unified
	7018	+ .arm
	7019	+ .fpu softvfp
6788	7020	.type FlashReadPages, %function
6789	7021	FlashReadPages:
6790	7022	.fnstart
6791	7023	@ args = 0, pretend = 0, frame = 40
6792	7024	@ frame_needed = 0, uses_anonymous_args = 0
6793		- ldr r3, .L1292
6794		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	7025	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
6795	7026	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
6796	7027	.pad #52
6797	7028	sub sp, sp, #52
6798		- ldr r9, .L1292+4
6799		- ldrb r3, [r3, #265] @ zero_extendqisi2
6800		- str r1, [sp, #20]
6801		- ldrb r8, [r9] @ zero_extendqisi2
6802		- str r3, [sp, #16]
6803		- ldrb r3, [r9, #8] @ zero_extendqisi2
6804		- cmp r8, #0
6805		- str r2, [sp, #24]
6806		- str r3, [sp, #28]
6807		- beq .L1254
	7029	+ ldr r9, .L1291
	7030	+ str r1, [sp, #24]
	7031	+ ldrb r10, [r9, #36] @ zero_extendqisi2
	7032	+ str r2, [sp, #28]
	7033	+ cmp r10, #0
	7034	+ bne .L1221
	7035	+ ldr r3, .L1291+4
	7036	+ mov fp, r0
	7037	+ ldr r6, .L1291+8
	7038	+ str r10, [sp, #8]
	7039	+ ldrb r3, [r3, #477] @ zero_extendqisi2
	7040	+ str r3, [sp, #20]
	7041	+ ldrb r3, [r9, #44] @ zero_extendqisi2
	7042	+ str r3, [sp, #36]
	7043	+.L1222:
	7044	+ ldr r3, [sp, #8]
	7045	+ ldr r2, [sp, #24]
	7046	+ cmp r3, r2
	7047	+ bcc .L1255
	7048	+ mov r0, #0
	7049	+ b .L1220
	7050	+.L1221:
6808	7051	bl FlashReadSlc2KPages
6809		- b .L1287
6810		-.L1254:
6811		- ldr r7, .L1292+8
6812		- mov r10, r0
6813		- mov fp, r8
6814		-.L1218:
6815		- ldr r3, [sp, #20]
6816		- cmp fp, r3
6817		- bcs .L1290
	7052	+.L1220:
	7053	+ add sp, sp, #52
	7054	+ @ sp needed
	7055	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	7056	+.L1255:
	7057	+ ldr r2, [sp, #8]
6818	7058	mov r3, #36
6819		- add r2, sp, #44
6820		- mul r3, r3, fp
6821		- ldr r1, [sp, #24]
6822		- add r6, r10, r3
6823		- str r3, [sp, #8]
6824		- mov r0, r6
6825		- ldr r3, [r6, #4]
	7059	+ ldr r1, [sp, #28]
	7060	+ mul r3, r3, r2
	7061	+ add r8, fp, r3
6826	7062	str r3, [sp, #12]
6827		- ldr r3, [sp, #20]
6828		- rsb r3, fp, r3
	7063	+ ldr r3, [sp, #24]
	7064	+ mov r0, r8
	7065	+ ldr r7, [r8, #4]
	7066	+ sub r3, r3, r2
	7067	+ add r2, sp, #44
6829	7068	uxtb r3, r3
6830	7069	str r3, [sp]
6831	7070	add r3, sp, #40
6832	7071	bl LogAddr2PhyAddr
6833		- ldrb r2, [r9, #3152] @ zero_extendqisi2
6834		- ldr r3, [sp, #40]
	7072	+ ldrb r2, [r9, #3156] @ zero_extendqisi2
6835	7073	mov r5, r0
6836		- cmp r3, r2
6837		- ldrcs r2, [sp, #8]
6838		- mvncs r3, #0
6839		- strcs r3, [r10, r2]
6840		- bcs .L1221
	7074	+ ldr r3, [sp, #40]
	7075	+ cmp r2, r3
	7076	+ ldrls r2, [sp, #12]
	7077	+ mvnls r3, #0
	7078	+ strls r3, [fp, r2]
	7079	+ bls .L1225
6841	7080	add r3, r9, r3
6842		- ldrb r4, [r3, #3156] @ zero_extendqisi2
6843		- ldrb r3, [r7, #-1759] @ zero_extendqisi2
6844		- cmp r3, #0
	7081	+ ldrb r4, [r3, #3160] @ zero_extendqisi2
	7082	+ ldrb r3, [r6, #-1755] @ zero_extendqisi2
6845	7083	mov r0, r4
	7084	+ cmp r3, #0
6846	7085	moveq r5, #0
6847	7086	bl NandcWaitFlashReady
6848		- ldr r3, .L1292+4
6849		- ldr r3, [r3, #44]
	7087	+ ldr r3, [r9, #48]
6850	7088	ldrb r2, [r3, #19] @ zero_extendqisi2
6851	7089	sub r3, r2, #1
6852	7090	cmp r3, #7
6853		- bhi .L1223
	7091	+ bhi .L1227
6854	7092	sub r2, r2, #7
6855		- add r1, r7, r4
	7093	+ add r1, r6, r4
6856	7094	cmp r2, #1
6857		- ldr r2, .L1292+8
6858		- ldrb r3, [r1, #-2720] @ zero_extendqisi2
6859		- add r2, r2, r4
6860		- ldrlsb r3, [r1, #-2712] @ zero_extendqisi2
6861		- ldrb r2, [r2, #-1880] @ zero_extendqisi2
	7095	+ add r2, r6, r4
	7096	+ ldrb r3, [r1, #-2716] @ zero_extendqisi2
	7097	+ ldrb r2, [r2, #-1876] @ zero_extendqisi2
	7098	+ ldrbls r3, [r1, #-2708] @ zero_extendqisi2
6862	7099	cmp r2, r3
6863		- beq .L1223
	7100	+ beq .L1227
	7101	+ ldr r2, .L1291+12
6864	7102	mov r0, r4
6865		- ldrb r1, [r7, #-2731] @ zero_extendqisi2
6866		- ldr r2, .L1292+12
	7103	+ ldrb r1, [r6, #-2727] @ zero_extendqisi2
6867	7104	bl HynixSetRRPara
6868		-.L1223:
	7105	+.L1227:
6869	7106	mov r0, r4
	7107	+ lsr r7, r7, #31
6870	7108	bl NandcFlashCs
	7109	+ ldr r3, [sp, #28]
6871	7110	mov r0, r4
6872		- ldr r3, [sp, #12]
6873		- ldr r2, [sp, #24]
6874		- mov r3, r3, lsr #31
6875		- cmp r2, #1
6876		- orreq r3, r3, #1
6877		- str r3, [sp, #12]
	7111	+ cmp r3, #1
	7112	+ orreq r7, r7, #1
	7113	+ cmp r7, #0
	7114	+ str r7, [sp, #16]
	7115	+ beq .L1229
	7116	+ ldrb r3, [r6, #-2740] @ zero_extendqisi2
6878	7117	cmp r3, #0
6879		- beq .L1225
6880		- ldrb r3, [r7, #-2744] @ zero_extendqisi2
6881		- cmp r3, #0
6882		- beq .L1225
	7118	+ beq .L1229
6883	7119	bl flash_enter_slc_mode
6884		- b .L1226
6885		-.L1225:
6886		- bl flash_exit_slc_mode
6887		-.L1226:
	7120	+.L1235:
6888	7121	ldr r1, [sp, #44]
6889	7122	cmn r1, #1
6890	7123	cmpeq r4, #255
6891	7124	moveq r3, #0
6892	7125	movne r3, #1
6893	7126	moveq r5, r3
6894		- beq .L1228
	7127	+ beq .L1231
6895	7128	cmp r5, #0
6896		- beq .L1229
6897		- ldr r2, [r9, #4]
	7129	+ beq .L1232
	7130	+ ldr r2, [r9, #40]
6898	7131	mov r0, r4
6899	7132	add r2, r1, r2
6900	7133	bl FlashReadDpCmd
6901		- b .L1230
6902		-.L1229:
6903		- mov r0, r4
6904		- bl FlashReadCmd
6905		-.L1230:
	7134	+.L1233:
6906	7135	mov r0, r4
6907	7136	bl NandcWaitFlashReady
6908	7137	cmp r5, #0
6909		- beq .L1228
6910		- mov r0, r4
	7138	+ beq .L1231
6911	7139	ldr r1, [sp, #44]
6912		- bl FlashReadDpDataOutCmd
6913		-.L1228:
6914		- ldr r3, [r6, #12]
6915	7140	mov r0, r4
6916		- ldr r2, [sp, #16]
	7141	+ bl FlashReadDpDataOutCmd
	7142	+.L1231:
	7143	+ ldr r3, [r8, #12]
6917	7144	mov r1, #0
	7145	+ ldr r2, [sp, #20]
	7146	+ mov r0, r4
6918	7147	str r3, [sp]
6919		- ldr r3, [r6, #8]
	7148	+ ldr r3, [r8, #8]
6920	7149	bl NandcXferData
6921		- ldrb r2, [r9, #8] @ zero_extendqisi2
6922		- adds r2, r2, #0
	7150	+ ldrb r3, [r9, #44] @ zero_extendqisi2
	7151	+ mov r7, r0
	7152	+ adds r2, r3, #0
6923	7153	movne r2, #1
6924	7154	cmn r0, #1
6925		- mov ip, r0
6926	7155	movne r2, #0
6927	7156	cmp r2, #0
6928		- movne r3, #0
6929		- strneb r3, [r9, #8]
6930		- movne r5, r3
6931		- bne .L1226
6932		-.L1231:
6933		- cmp r5, #0
6934		- beq .L1232
6935		- ldr r3, .L1292+4
6936		- str r0, [sp, #32]
6937		- mov r0, r4
6938		- str r2, [sp, #36]
6939		- ldr r1, [r3, #4]
6940		- ldr r3, [sp, #44]
6941		- add r1, r1, r3
6942		- bl FlashReadDpDataOutCmd
6943		- mov r0, r4
6944		- ldr r3, [sp, #8]
6945		- ldr r2, [sp, #36]
6946		- add r3, r3, #36
6947		- add r3, r10, r3
6948		- ldr r1, [r3, #12]
6949		- str r1, [sp]
6950		- mov r1, r2
6951		- ldr r3, [r3, #8]
6952		- ldr r2, [sp, #16]
6953		- bl NandcXferData
6954		- cmn r0, #1
6955		- ldr ip, [sp, #32]
6956		- mov r8, r0
6957		- moveq r5, #0
	7157	+ str r2, [sp, #32]
	7158	+ beq .L1234
	7159	+ mov r3, #0
	7160	+ mov r5, #0
	7161	+ strb r3, [r9, #44]
	7162	+ b .L1235
	7163	+.L1229:
	7164	+ bl flash_exit_slc_mode
	7165	+ b .L1235
6958	7166	.L1232:
6959	7167	mov r0, r4
6960		- str ip, [sp, #32]
6961		- bl NandcFlashDeCs
6962		- ldr ip, [sp, #32]
6963		- ldrb r3, [sp, #28] @ zero_extendqisi2
6964		- cmn ip, #1
6965		- strb r3, [r9, #8]
6966		- bne .L1239
6967		- ldrb r3, [r7, #-1860] @ zero_extendqisi2
6968		- cmp r3, #0
6969		- bne .L1234
6970		-.L1238:
6971		- ldr r5, [r7, #-1796]
6972		- cmp r5, #0
6973		- bne .L1235
6974		- b .L1291
	7168	+ bl FlashReadCmd
	7169	+ b .L1233
6975	7170	.L1234:
6976		- ldr r3, [r7, #-2808]
	7171	+ cmp r5, #0
	7172	+ beq .L1236
	7173	+ ldr r3, [r9, #40]
	7174	+ mov r0, r4
	7175	+ ldr r1, [sp, #44]
	7176	+ add r1, r1, r3
	7177	+ bl FlashReadDpDataOutCmd
	7178	+ ldr r3, [sp, #12]
	7179	+ mov r0, r4
	7180	+ ldr r1, [sp, #32]
	7181	+ add r3, r3, #36
	7182	+ add r3, fp, r3
	7183	+ ldr r2, [r3, #12]
	7184	+ str r2, [sp]
	7185	+ ldr r2, [sp, #20]
	7186	+ ldr r3, [r3, #8]
	7187	+ bl NandcXferData
	7188	+ cmn r0, #1
	7189	+ mov r10, r0
	7190	+ moveq r5, #0
	7191	+.L1236:
	7192	+ mov r0, r4
	7193	+ bl NandcFlashDeCs
	7194	+ ldrb r3, [sp, #36] @ zero_extendqisi2
	7195	+ cmn r7, #1
	7196	+ strb r3, [r9, #44]
	7197	+ bne .L1237
	7198	+ ldrb r3, [r6, #-1856] @ zero_extendqisi2
	7199	+ cmp r3, #0
	7200	+ bne .L1238
	7201	+.L1242:
	7202	+ ldr r5, [r6, #-1792]
	7203	+ cmp r5, #0
	7204	+ bne .L1239
	7205	+ ldr r3, [r8, #12]
	7206	+ mov r0, r4
	7207	+ ldr r2, [r8, #8]
	7208	+ ldr r1, [sp, #44]
	7209	+ bl FlashReadRawPage
	7210	+ mov r7, r0
	7211	+.L1243:
	7212	+ cmp r7, #256
	7213	+ cmnne r7, #1
	7214	+ ldreq r3, [sp, #12]
	7215	+ movne r3, #0
	7216	+ ldrne r2, [sp, #12]
	7217	+ streq r7, [fp, r3]
	7218	+ strne r3, [fp, r2]
	7219	+ ldr r3, [sp, #12]
	7220	+ ldr r3, [fp, r3]
	7221	+ cmn r3, #1
	7222	+ bne .L1250
	7223	+ ldr r1, [r8, #4]
	7224	+ ldrb r2, [r6, #-2739] @ zero_extendqisi2
	7225	+ ldr r0, .L1291+16
	7226	+ bl printk
	7227	+ ldr r1, [r8, #12]
	7228	+ cmp r1, #0
	7229	+ beq .L1250
	7230	+ mov r3, #4
	7231	+ ldr r0, .L1291+20
	7232	+ mov r2, r3
	7233	+ bl rknand_print_hex
	7234	+.L1250:
	7235	+ cmp r5, #0
	7236	+ beq .L1252
	7237	+ ldrb r3, [r6, #-2739] @ zero_extendqisi2
	7238	+ add r3, r3, r3, lsl #1
	7239	+ cmp r10, r3, asr #2
	7240	+ bls .L1253
	7241	+ ldr r3, [r6, #-1792]
	7242	+ cmp r3, #0
	7243	+ moveq r10, #256
	7244	+.L1253:
	7245	+ ldr r3, [sp, #12]
	7246	+ cmp r10, #256
	7247	+ cmnne r10, #1
	7248	+ movne r2, #0
	7249	+ add r3, r3, #36
	7250	+ streq r10, [fp, r3]
	7251	+ strne r2, [fp, r3]
	7252	+.L1252:
	7253	+ ldr r3, [sp, #8]
	7254	+ add r3, r3, r5
	7255	+ str r3, [sp, #8]
	7256	+ ldr r3, [sp, #16]
	7257	+ cmp r3, #0
	7258	+ beq .L1225
	7259	+ ldrb r3, [r6, #-2740] @ zero_extendqisi2
	7260	+ cmp r3, #0
	7261	+ beq .L1225
	7262	+ mov r0, r4
	7263	+ bl flash_exit_slc_mode
	7264	+.L1225:
	7265	+ ldr r3, [sp, #8]
	7266	+ add r3, r3, #1
	7267	+ str r3, [sp, #8]
	7268	+ b .L1222
	7269	+.L1238:
	7270	+ ldr r3, [r6, #-2804]
6977	7271	mov r0, r4
6978	7272	ldr r1, [sp, #44]
6979	7273	ldr r5, [r3, #304]
6980	7274	mov r3, #1
6981	7275	str r3, [sp]
6982		- ldr r2, [r6, #8]
6983		- ldr r3, [r6, #12]
	7276	+ ldr r3, [r8, #12]
	7277	+ ldr r2, [r8, #8]
6984	7278	bl FlashDdrTunningRead
6985	7279	cmn r0, #1
6986		- mov ip, r0
6987		- beq .L1237
6988		- ldrb r3, [r7, #-2743] @ zero_extendqisi2
	7280	+ mov r7, r0
	7281	+ beq .L1241
	7282	+ ldrb r3, [r6, #-2739] @ zero_extendqisi2
6989	7283	cmp r0, r3, lsr #1
6990		- bls .L1257
6991		-.L1237:
	7284	+ bls .L1258
	7285	+.L1241:
6992	7286	ubfx r0, r5, #8, #8
6993		- str ip, [sp, #32]
6994	7287	bl NandcSetDdrPara
6995		- ldr ip, [sp, #32]
6996		- cmn ip, #1
6997		- beq .L1238
6998		- b .L1257
6999		-.L1235:
	7288	+ cmn r7, #1
	7289	+ beq .L1242
	7290	+.L1258:
	7291	+ mov r5, #0
	7292	+.L1237:
	7293	+ ldrb r3, [r6, #-2739] @ zero_extendqisi2
	7294	+ add r3, r3, r3, lsl #1
	7295	+ cmp r7, r3, asr #2
	7296	+ bls .L1243
	7297	+ ldr r3, [r6, #-1792]
	7298	+ cmp r3, #0
	7299	+ moveq r7, #256
	7300	+ b .L1243
	7301	+.L1239:
	7302	+ ldr r3, [r8, #12]
7000	7303	mov r0, r4
	7304	+ ldr r2, [r8, #8]
7001	7305	ldr r1, [sp, #44]
7002		- ldr r2, [r6, #8]
7003		- ldr r3, [r6, #12]
7004	7306	blx r5
7005	7307	cmn r0, #1
7006		- mov ip, r0
7007		- bne .L1259
7008		- ldr r3, [r9, #44]
	7308	+ mov r7, r0
	7309	+ bne .L1260
	7310	+ ldr r3, [r9, #48]
7009	7311	ldrb r3, [r3, #19] @ zero_extendqisi2
7010	7312	sub r3, r3, #1
7011	7313	cmp r3, #7
7012		- bhi .L1241
7013		- mov r0, r4
7014		- ldrb r1, [r7, #-2731] @ zero_extendqisi2
7015		- ldr r2, .L1292+12
	7314	+ bhi .L1244
7016	7315	mov r3, #0
	7316	+ ldr r2, .L1291+12
	7317	+ ldrb r1, [r6, #-2727] @ zero_extendqisi2
	7318	+ mov r0, r4
7017	7319	bl HynixSetRRPara
7018		-.L1241:
7019		- ldr r1, [sp, #44]
	7320	+.L1244:
	7321	+ ldr r3, [r8, #12]
7020	7322	mov r0, r4
7021		- ldr r2, [r6, #8]
7022		- ldr r3, [r6, #12]
	7323	+ ldr r2, [r8, #8]
	7324	+ ldr r1, [sp, #44]
7023	7325	bl FlashReadRawPage
7024		- ldr r1, [r6, #4]
7025		- ldrb r2, [r7, #-2743] @ zero_extendqisi2
7026		- mov ip, r0
7027		- ldr r0, .L1292+16
7028		- mov r3, ip
7029		- str ip, [sp, #32]
	7326	+ ldrb r2, [r6, #-2739] @ zero_extendqisi2
	7327	+ mov r7, r0
	7328	+ mov r3, r0
	7329	+ ldr r1, [r8, #4]
	7330	+ ldr r0, .L1291+24
7030	7331	bl printk
7031		- ldr ip, [sp, #32]
7032		- cmn ip, #1
7033		- bne .L1259
7034		- ldrb r5, [r7, #-2744] @ zero_extendqisi2
	7332	+ cmn r7, #1
	7333	+ bne .L1260
	7334	+ ldrb r5, [r6, #-2740] @ zero_extendqisi2
7035	7335	cmp r5, #0
7036		- beq .L1240
7037		- ldr r3, [sp, #12]
	7336	+ beq .L1243
	7337	+ ldr r3, [sp, #16]
7038	7338	mov r0, r4
7039	7339	cmp r3, #0
7040		- beq .L1242
	7340	+ beq .L1245
7041	7341	bl flash_enter_slc_mode
	7342	+.L1246:
	7343	+ ldr r5, [r6, #-1792]
	7344	+ mov r0, r4
	7345	+ ldr r3, [r8, #12]
	7346	+ ldr r2, [r8, #8]
	7347	+ ldr r1, [sp, #44]
	7348	+ blx r5
	7349	+ mov r7, r0
	7350	+.L1260:
	7351	+ mov r5, #0
7042	7352	b .L1243
7043		-.L1242:
	7353	+.L1245:
7044	7354	bl flash_exit_slc_mode
7045		-.L1243:
7046		- ldr r3, .L1292+8
7047		- mov r0, r4
7048		- ldr r1, [sp, #44]
7049		- ldr r2, [r6, #8]
7050		- ldr ip, [r3, #-1796]
7051		- ldr r3, [r6, #12]
7052		- blx ip
7053		- mov ip, r0
7054		- b .L1259
7055		-.L1291:
7056		- mov r0, r4
7057		- ldr r1, [sp, #44]
7058		- ldr r2, [r6, #8]
7059		- ldr r3, [r6, #12]
7060		- bl FlashReadRawPage
7061		- mov ip, r0
7062		- b .L1240
7063		-.L1257:
7064		- mov r5, #0
7065		-.L1239:
7066		- ldrb r3, [r7, #-2743] @ zero_extendqisi2
7067		- add r3, r3, r3, asl #1
7068		- cmp ip, r3, asr #2
7069		- bls .L1240
7070		- ldr r3, [r7, #-1796]
7071		- cmp r3, #0
7072		- moveq ip, #256
7073		- b .L1240
7074		-.L1259:
7075		- mov r5, #0
7076		-.L1240:
7077		- cmp ip, #256
7078		- cmnne ip, #1
7079		- ldreq r3, [sp, #8]
7080		- movne r3, #0
7081		- ldrne r2, [sp, #8]
7082		- streq ip, [r10, r3]
7083		- strne r3, [r10, r2]
7084		- ldr r3, [sp, #8]
7085		- ldr r3, [r10, r3]
7086		- cmn r3, #1
7087		- bne .L1247
7088		- ldr r1, [r6, #4]
7089		- ldr r0, .L1292+20
7090		- ldrb r2, [r7, #-2743] @ zero_extendqisi2
7091		- bl printk
7092		- ldr r1, [r6, #12]
7093		- cmp r1, #0
7094		- beq .L1247
7095		- mov r2, #4
7096		- ldr r0, .L1292+24
7097		- mov r3, r2
7098		- bl rknand_print_hex
7099		-.L1247:
7100		- cmp r5, #0
7101		- beq .L1249
7102		- ldrb r3, [r7, #-2743] @ zero_extendqisi2
7103		- add r3, r3, r3, asl #1
7104		- cmp r8, r3, asr #2
7105		- bls .L1250
7106		- ldr r3, [r7, #-1796]
7107		- cmp r3, #0
7108		- moveq r8, #256
7109		-.L1250:
7110		- ldr r3, [sp, #8]
7111		- cmp r8, #256
7112		- cmnne r8, #1
7113		- add r3, r3, #36
7114		- movne r2, #0
7115		- streq r8, [r10, r3]
7116		- strne r2, [r10, r3]
7117		-.L1249:
7118		- ldr r3, [sp, #12]
7119		- add fp, fp, r5
7120		- cmp r3, #0
7121		- beq .L1221
7122		- ldrb r3, [r7, #-2744] @ zero_extendqisi2
7123		- cmp r3, #0
7124		- beq .L1221
7125		- mov r0, r4
7126		- bl flash_exit_slc_mode
7127		-.L1221:
7128		- add fp, fp, #1
7129		- b .L1218
7130		-.L1290:
7131		- mov r0, #0
7132		-.L1287:
7133		- add sp, sp, #52
7134		- @ sp needed
7135		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
7136		-.L1293:
7137		- .align 2
	7355	+ b .L1246
7138	7356	.L1292:
7139		- .word .LANCHOR1
	7357	+ .align 2
	7358	+.L1291:
7140	7359	.word .LANCHOR0
	7360	+ .word .LANCHOR1
7141	7361	.word .LANCHOR2
7142		- .word .LANCHOR2-2728
7143		- .word .LC19
	7362	+ .word .LANCHOR2-2724
7144	7363	.word .LC16
7145	7364	.word .LC18
	7365	+ .word .LC19
7146	7366	.fnend
7147	7367	.size FlashReadPages, .-FlashReadPages
7148	7368	.align 2
7149	7369	.global FlashLoadFactorBbt
	7370	+ .syntax unified
	7371	+ .arm
	7372	+ .fpu softvfp
7150	7373	.type FlashLoadFactorBbt, %function
7151	7374	FlashLoadFactorBbt:
7152	7375	.fnstart
7153		- @ args = 0, pretend = 0, frame = 48
	7376	+ @ args = 0, pretend = 0, frame = 56
7154	7377	@ frame_needed = 0, uses_anonymous_args = 0
7155		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	7378	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
7156	7379	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
7157		- mov r1, #0
7158		- ldr r5, .L1307
7159		- .pad #52
7160		- sub sp, sp, #52
7161	7380	mov r2, #16
7162		- ldr r9, .L1307+4
7163		- add r0, r5, #1016
7164		- ldr fp, .L1307+8
7165		- ldrh r7, [r5, #12]
7166		- mvn r10, #0
7167		- ldrh r4, [r5, #14]
7168		- bl ftl_memset
7169		- ldr r3, [r9, #-1772]
	7381	+ ldr r8, .L1305
	7382	+ .pad #60
	7383	+ sub sp, sp, #60
	7384	+ mov r1, #0
7170	7385	mov r5, #0
7171		- mov r8, r5
7172		- smulbb r7, r7, r4
7173		- uxth r6, r7
7174		- str r5, [sp, #20]
7175		- str r3, [sp, #24]
7176		-.L1295:
7177		- ldrb r3, [fp, #3152] @ zero_extendqisi2
	7386	+ ldr fp, .L1305+4
	7387	+ mov r9, r5
	7388	+ sub r3, r8, #2768
	7389	+ sub r4, r8, #1744
	7390	+ ldrh r6, [r3, #14]
	7391	+ sub r0, r4, #10
	7392	+ ldrh r3, [r3, #12]
	7393	+ mvn r10, #0
	7394	+ smulbb r6, r6, r3
	7395	+ bl ftl_memset
	7396	+ uxth r6, r6
	7397	+ ldr r3, [r8, #-1768]
	7398	+ str r5, [sp, #28]
	7399	+ str r4, [sp, #8]
	7400	+ str r3, [sp, #32]
	7401	+.L1294:
	7402	+ ldrb r3, [fp, #3156] @ zero_extendqisi2
7178	7403	uxtb r7, r5
7179	7404	cmp r3, r7
7180		- bls .L1306
7181		- mul ip, r6, r7
	7405	+ bhi .L1300
	7406	+ mov r0, r10
	7407	+ add sp, sp, #60
	7408	+ @ sp needed
	7409	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	7410	+.L1300:
7182	7411	sub r4, r6, #1
7183		- sub r3, r6, #12
	7412	+ mul r3, r7, r6
7184	7413	uxth r4, r4
7185		-.L1296:
7186		- cmp r4, r3
7187		- ble .L1298
7188		- add r2, ip, r4
7189		- mov r1, #1
7190		- add r0, sp, #12
7191		- str r3, [sp, #4]
7192		- mov r2, r2, asl #10
7193		- str r2, [sp, #16]
7194		- mov r2, r1
7195		- str ip, [sp]
	7414	+ sub r2, r6, #12
	7415	+ str r2, [sp, #4]
	7416	+.L1295:
	7417	+ ldr r2, [sp, #4]
	7418	+ cmp r4, r2
	7419	+ ble .L1297
	7420	+ add r2, r4, r3
	7421	+ add r0, sp, #20
	7422	+ lsl r2, r2, #10
	7423	+ str r3, [sp, #12]
	7424	+ str r2, [sp, #24]
	7425	+ mov r2, #1
	7426	+ mov r1, r2
7196	7427	bl FlashReadPages
7197		- ldr r2, [sp, #12]
7198		- ldr ip, [sp]
	7428	+ ldr r2, [sp, #20]
	7429	+ ldr r3, [sp, #12]
7199	7430	cmn r2, #1
7200		- ldr r3, [sp, #4]
7201		- beq .L1297
7202		- ldr r2, [r9, #-1772]
	7431	+ beq .L1296
	7432	+ ldr r2, [r8, #-1768]
7203	7433	ldrh r1, [r2]
7204	7434	movw r2, #61664
7205	7435	cmp r1, r2
7206		- bne .L1297
	7436	+ bne .L1296
7207	7437	mov r1, r7
7208		- ldr r0, .L1307+12
7209	7438	mov r2, r4
7210		- mov r7, r7, asl #1
	7439	+ ldr r0, .L1305+8
	7440	+ add r9, r9, #1
7211	7441	bl printk
7212		- ldr r3, .L1307+16
7213		- add r8, r8, #1
7214		- strh r4, [r3, r7] @ movhi
7215		- uxth r8, r8
7216		- b .L1298
	7442	+ ldr r3, [sp, #8]
	7443	+ uxth r9, r9
	7444	+ add r7, r3, r7, lsl #1
	7445	+ strh r4, [r7, #-10] @ movhi
7217	7446	.L1297:
	7447	+ ldr r3, .L1305+4
	7448	+ add r5, r5, #1
	7449	+ ldrb r3, [r3, #3156] @ zero_extendqisi2
	7450	+ cmp r3, r9
	7451	+ moveq r10, #0
	7452	+ b .L1294
	7453	+.L1296:
7218	7454	sub r4, r4, #1
7219	7455	uxth r4, r4
7220		- b .L1296
7221		-.L1298:
7222		- ldr r3, .L1307+8
7223		- add r5, r5, #1
7224		- ldrb r3, [r3, #3152] @ zero_extendqisi2
7225		- cmp r3, r8
7226		- moveq r10, #0
7227	7456	b .L1295
7228	7457	.L1306:
7229		- mov r0, r10
7230		- add sp, sp, #52
7231		- @ sp needed
7232		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
7233		-.L1308:
7234	7458	.align 2
7235		-.L1307:
7236		- .word .LANCHOR2-2772
	7459	+.L1305:
7237	7460	.word .LANCHOR2
7238	7461	.word .LANCHOR0
7239	7462	.word .LC20
7240		- .word .LANCHOR2-1756
7241	7463	.fnend
7242	7464	.size FlashLoadFactorBbt, .-FlashLoadFactorBbt
7243	7465	.align 2
7244	7466	.global FlashReadFacBbtData
	7467	+ .syntax unified
	7468	+ .arm
	7469	+ .fpu softvfp
7245	7470	.type FlashReadFacBbtData, %function
7246	7471	FlashReadFacBbtData:
7247	7472	.fnstart
7248	7473	@ args = 0, pretend = 0, frame = 40
7249	7474	@ frame_needed = 0, uses_anonymous_args = 0
7250		- ldr r3, .L1324
7251		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
	7475	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
7252	7476	.save {r4, r5, r6, r7, r8, r9, r10, lr}
7253	7477	mov r8, r2
7254		- ldrh r4, [r3, #14]
	7478	+ ldr r5, .L1320
7255	7479	.pad #40
7256	7480	sub sp, sp, #40
7257		- ldrh r2, [r3, #12]
7258		- mov r5, r0
7259		- ldr r9, .L1324+4
7260		- mov r7, r1
7261		- smulbb r4, r2, r4
7262		- ldr r2, [r9, #-1868]
	7481	+ mov r6, r0
	7482	+ mov r9, r1
	7483	+ sub r2, r5, #2768
	7484	+ ldrh r3, [r2, #14]
	7485	+ ldrh r2, [r2, #12]
	7486	+ smulbb r3, r3, r2
	7487	+ ldr r2, [r5, #-1864]
	7488	+ uxth r3, r3
7263	7489	str r2, [sp, #12]
7264		- ldr r2, [r9, #-1772]
7265		- uxth r3, r4
7266		- sub r6, r3, #1
	7490	+ ldr r2, [r5, #-1768]
	7491	+ sub r7, r3, #1
	7492	+ mul r10, r1, r3
	7493	+ uxth r7, r7
7267	7494	sub r4, r3, #16
7268		- mul r10, r3, r1
7269		- uxth r6, r6
7270	7495	str r2, [sp, #16]
7271		-.L1310:
7272		- cmp r6, r4
7273		- ble .L1323
7274		- mov r1, #1
7275		- add r3, r6, r10
	7496	+.L1308:
	7497	+ cmp r7, r4
	7498	+ mvnle r0, #0
	7499	+ ble .L1307
	7500	+.L1314:
	7501	+ add r3, r7, r10
	7502	+ mov r2, #1
	7503	+ lsl r3, r3, #10
	7504	+ mov r1, r2
7276	7505	add r0, sp, #4
7277		- mov r2, r1
7278		- mov r3, r3, asl #10
7279	7506	str r3, [sp, #8]
7280	7507	bl FlashReadPages
7281	7508	ldr r3, [sp, #4]
7282	7509	cmn r3, #1
7283		- beq .L1311
7284		- ldr r3, [r9, #-1772]
	7510	+ beq .L1309
	7511	+ ldr r3, [r5, #-1768]
7285	7512	ldrh r2, [r3]
7286	7513	movw r3, #61664
7287	7514	cmp r2, r3
7288		- bne .L1311
7289		- cmp r5, #0
7290		- moveq r0, r5
7291		- beq .L1312
7292		- cmp r7, #0
7293		- ldreq ip, .L1324+4
	7515	+ bne .L1309
	7516	+ cmp r6, #0
	7517	+ moveq r0, r6
	7518	+ beq .L1307
	7519	+ cmp r9, #0
	7520	+ moveq r1, r9
7294	7521	moveq lr, #1
7295		- beq .L1313
7296		-.L1315:
7297		- ldr r1, [r9, #-1868]
	7522	+ beq .L1312
	7523	+.L1311:
7298	7524	mov r2, r8
7299		- mov r0, r5
	7525	+ ldr r1, [r5, #-1864]
	7526	+ mov r0, r6
7300	7527	bl ftl_memcpy
7301		- mov r2, #4
7302		- ldr r0, .L1324+8
7303		- mov r1, r5
7304		- mov r3, r2
	7528	+ mov r3, #4
	7529	+ ldr r0, .L1320+4
	7530	+ mov r2, r3
	7531	+ mov r1, r6
7305	7532	bl rknand_print_hex
7306	7533	mov r0, #0
7307		- b .L1312
7308		-.L1313:
7309		- ldr r3, [r9, #-1784]
7310		- uxth r4, r7
7311		- add r7, r7, #1
7312		- cmp r4, r3
7313		- bcs .L1315
7314		- ldr r1, [ip, #-1868]
7315		- mov r0, r4, lsr #5
7316		- and r3, r4, #31
7317		- ldr r2, [r1, r0, asl #2]
7318		- orr r3, r2, lr, asl r3
7319		- str r3, [r1, r0, asl #2]
7320		- b .L1313
7321		-.L1311:
7322		- sub r6, r6, #1
7323		- uxth r6, r6
7324		- b .L1310
7325		-.L1323:
7326		- mvn r0, #0
7327		-.L1312:
	7534	+.L1307:
7328	7535	add sp, sp, #40
7329	7536	@ sp needed
7330		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
7331		-.L1325:
	7537	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	7538	+.L1313:
	7539	+ ldr r0, [r5, #-1864]
	7540	+ lsr ip, r3, #5
	7541	+ and r3, r3, #31
	7542	+ ldr r2, [r0, ip, lsl #2]
	7543	+ orr r3, r2, lr, lsl r3
	7544	+ str r3, [r0, ip, lsl #2]
	7545	+.L1312:
	7546	+ ldr r0, [r5, #-1780]
	7547	+ uxth r3, r1
	7548	+ add r1, r1, #1
	7549	+ cmp r3, r0
	7550	+ bcc .L1313
	7551	+ b .L1311
	7552	+.L1309:
	7553	+ sub r7, r7, #1
	7554	+ uxth r7, r7
	7555	+ b .L1308
	7556	+.L1321:
7332	7557	.align 2
7333		-.L1324:
7334		- .word .LANCHOR2-2772
	7558	+.L1320:
7335	7559	.word .LANCHOR2
7336	7560	.word .LC21
7337	7561	.fnend
7338	7562	.size FlashReadFacBbtData, .-FlashReadFacBbtData
7339	7563	.align 2
7340	7564	.global FlashGetBadBlockList
	7565	+ .syntax unified
	7566	+ .arm
	7567	+ .fpu softvfp
7341	7568	.type FlashGetBadBlockList, %function
7342	7569	FlashGetBadBlockList:
7343	7570	.fnstart
7344	7571	@ args = 0, pretend = 0, frame = 0
7345	7572	@ frame_needed = 0, uses_anonymous_args = 0
7346		- ldr r3, .L1337
7347		- stmfd sp!, {r4, r5, r6, r7, r8, lr}
	7573	+ ldr r3, .L1333
	7574	+ push {r4, r5, r6, r7, r8, lr}
7348	7575	.save {r4, r5, r6, r7, r8, lr}
7349	7576	mov r5, r0
7350		- ldr r3, [r3, #44]
7351		- ldr r6, .L1337+4
	7577	+ ldr r6, .L1333+4
	7578	+ ldr r3, [r3, #48]
	7579	+ ldr r0, [r6, #-1772]
7352	7580	ldrb r4, [r3, #13] @ zero_extendqisi2
7353	7581	ldrh r3, [r3, #14]
7354		- ldr r0, [r6, #-1776]
7355	7582	smulbb r4, r4, r3
7356	7583	uxth r4, r4
7357	7584	add r2, r4, #7
7358		- mov r2, r2, asr #3
	7585	+ asr r2, r2, #3
7359	7586	bl FlashReadFacBbtData
7360	7587	cmn r0, #1
7361		- bne .L1327
7362		-.L1331:
7363		- mov r3, #0
7364		- b .L1328
	7588	+ bne .L1323
7365	7589	.L1327:
7366		- mov lr, r4, lsr #4
7367		- mov ip, #0
7368		- sub r4, r4, #1
7369		- mov r3, ip
7370		- mov r7, #1
7371		-.L1329:
7372		- uxth r0, ip
7373		- cmp r0, r4
7374		- bge .L1328
7375		- ldr r8, [r6, #-1776]
7376		- mov r1, r0, lsr #5
7377		- and r2, r0, #31
7378		- add ip, ip, #1
7379		- ldr r1, [r8, r1, asl #2]
7380		- ands r2, r1, r7, asl r2
7381		- addne r2, r3, #1
7382		- movne r3, r3, asl #1
7383		- strneh r0, [r5, r3] @ movhi
7384		- uxthne r3, r2
7385		- cmp r3, lr
7386		- bcc .L1329
7387		- b .L1331
7388		-.L1328:
7389		- mov r3, r3, asl #1
	7590	+ mov r3, #0
	7591	+.L1324:
	7592	+ lsl r3, r3, #1
7390	7593	mvn r2, #0
7391	7594	mov r0, #0
7392	7595	strh r2, [r5, r3] @ movhi
7393		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
7394		-.L1338:
	7596	+ pop {r4, r5, r6, r7, r8, pc}
	7597	+.L1323:
	7598	+ mov r2, #0
	7599	+ lsr lr, r4, #4
	7600	+ mov r3, r2
	7601	+ sub r4, r4, #1
	7602	+ mov r7, #1
	7603	+.L1325:
	7604	+ uxth r1, r2
	7605	+ cmp r1, r4
	7606	+ bge .L1324
	7607	+ ldr r8, [r6, #-1772]
	7608	+ lsr ip, r1, #5
	7609	+ and r0, r1, #31
	7610	+ add r2, r2, #1
	7611	+ ldr ip, [r8, ip, lsl #2]
	7612	+ ands r0, ip, r7, lsl r0
	7613	+ addne r0, r3, #1
	7614	+ lslne r3, r3, #1
	7615	+ strhne r1, [r5, r3] @ movhi
	7616	+ uxthne r3, r0
	7617	+ cmp r3, lr
	7618	+ bcc .L1325
	7619	+ b .L1327
	7620	+.L1334:
7395	7621	.align 2
7396		-.L1337:
	7622	+.L1333:
7397	7623	.word .LANCHOR0
7398	7624	.word .LANCHOR2
7399	7625	.fnend
7400	7626	.size FlashGetBadBlockList, .-FlashGetBadBlockList
7401	7627	.align 2
7402	7628	.global FlashProgSlc2KPages
	7629	+ .syntax unified
	7630	+ .arm
	7631	+ .fpu softvfp
7403	7632	.type FlashProgSlc2KPages, %function
7404	7633	FlashProgSlc2KPages:
7405	7634	.fnstart
7406		- @ args = 0, pretend = 0, frame = 56
	7635	+ @ args = 0, pretend = 0, frame = 48
7407	7636	@ frame_needed = 0, uses_anonymous_args = 0
7408		- ldr r3, .L1369
7409		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	7637	+ ldr r3, .L1363
	7638	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
7410	7639	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
7411		- .pad #68
7412		- sub sp, sp, #68
7413		- ldr r8, .L1369+4
7414		- mov r6, r1
7415		- ldrb r3, [r3, #265] @ zero_extendqisi2
7416		- mov r9, r2
	7640	+ mov r10, r1
	7641	+ ldr r9, .L1363+4
	7642	+ .pad #60
	7643	+ sub sp, sp, #60
	7644	+ mov r8, r2
7417	7645	mov r4, r0
7418		- mov r10, r0
	7646	+ ldrb fp, [r3, #477] @ zero_extendqisi2
	7647	+ mov r6, r0
7419	7648	mov r7, #0
7420		- mov fp, r8
7421		- str r3, [sp, #12]
7422		-.L1340:
	7649	+.L1336:
	7650	+ cmp r7, r10
	7651	+ bne .L1342
	7652	+ ldr r5, .L1363+8
	7653	+ mov r6, #0
	7654	+ ldr r9, .L1363+12
	7655	+.L1343:
7423	7656	cmp r7, r6
7424		- beq .L1367
7425		- rsb r3, r7, r6
7426		- add r2, sp, #20
7427		- mov r0, r10
7428		- mov r1, r9
	7657	+ bne .L1350
	7658	+ mov r0, #0
	7659	+ add sp, sp, #60
	7660	+ @ sp needed
	7661	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	7662	+.L1342:
	7663	+ sub r3, r10, r7
	7664	+ add r2, sp, #12
7429	7665	uxtb r3, r3
	7666	+ mov r1, r8
	7667	+ mov r0, r6
7430	7668	str r3, [sp]
7431		- add r3, sp, #24
	7669	+ add r3, sp, #16
7432	7670	bl LogAddr2PhyAddr
7433		- ldrb r2, [r8, #3152] @ zero_extendqisi2
7434		- ldr r3, [sp, #24]
7435		- cmp r3, r2
7436		- mvncs r3, #0
7437		- strcs r3, [r10]
7438		- bcs .L1342
7439		- add r3, r8, r3
7440		- ldrb r5, [r3, #3156] @ zero_extendqisi2
	7671	+ ldrb r2, [r9, #3156] @ zero_extendqisi2
	7672	+ ldr r3, [sp, #16]
	7673	+ cmp r2, r3
	7674	+ mvnls r3, #0
	7675	+ strls r3, [r6]
	7676	+ bls .L1338
	7677	+ add r3, r9, r3
	7678	+ ldrb r5, [r3, #3160] @ zero_extendqisi2
7441	7679	mov r0, r5
7442	7680	bl NandcWaitFlashReady
7443	7681	mov r0, r5
7444	7682	bl NandcFlashCs
7445	7683	mov r0, r5
7446		- ldr r1, [sp, #20]
	7684	+ ldr r1, [sp, #12]
7447	7685	bl FlashProgFirstCmd
7448		- ldr r3, [r10, #12]
	7686	+ ldr r3, [r6, #12]
	7687	+ mov r2, fp
7449	7688	mov r1, #1
7450	7689	mov r0, r5
7451		- ldr r2, [sp, #12]
7452	7690	str r3, [sp]
7453		- ldr r3, [r10, #8]
	7691	+ ldr r3, [r6, #8]
7454	7692	bl NandcXferData
7455	7693	mov r0, r5
7456		- ldr r1, [sp, #20]
	7694	+ ldr r1, [sp, #12]
7457	7695	bl FlashProgSecondCmd
7458	7696	mov r0, r5
7459	7697	bl NandcWaitFlashReady
7460	7698	mov r0, r5
7461		- ldr r1, [sp, #20]
	7699	+ ldr r1, [sp, #12]
7462	7700	bl FlashReadStatus
7463		- ldr r3, [sp, #20]
7464	7701	sbfx r0, r0, #0, #1
7465		- str r0, [r10]
	7702	+ ldr r1, [sp, #12]
	7703	+ str r0, [r6]
7466	7704	mov r0, r5
7467		- ldr r1, [r8, #4]
	7705	+ ldr r3, [r9, #40]
7468	7706	add r1, r1, r3
7469	7707	bl FlashProgFirstCmd
7470		- ldr r3, [r10, #8]
7471		- ldr r2, [r10, #12]
	7708	+ ldr r3, [r6, #8]
7472	7709	mov r1, #1
7473		- cmp r3, #0
	7710	+ ldr r2, [r6, #12]
7474	7711	mov r0, r5
	7712	+ cmp r3, #0
7475	7713	addne r3, r3, #2048
7476	7714	cmp r2, #0
7477	7715	addne r2, r2, #8
7478	7716	str r2, [sp]
7479		- ldr r2, [sp, #12]
	7717	+ mov r2, fp
7480	7718	bl NandcXferData
7481		- ldr r1, [fp, #4]
	7719	+ ldr r3, [r9, #40]
7482	7720	mov r0, r5
7483		- ldr r3, [sp, #20]
	7721	+ ldr r1, [sp, #12]
7484	7722	add r1, r1, r3
7485	7723	bl FlashProgSecondCmd
7486	7724	mov r0, r5
7487	7725	bl NandcWaitFlashReady
7488	7726	mov r0, r5
7489		- ldr r1, [sp, #20]
	7727	+ ldr r1, [sp, #12]
7490	7728	bl FlashReadStatus
7491	7729	tst r0, #1
7492	7730	mov r0, r5
7493	7731	mvnne r3, #0
7494		- strne r3, [r10]
	7732	+ strne r3, [r6]
7495	7733	bl NandcFlashDeCs
7496		-.L1342:
	7734	+.L1338:
7497	7735	add r7, r7, #1
7498		- add r10, r10, #36
7499		- b .L1340
7500		-.L1367:
7501		- ldr r5, .L1369+8
7502		- mov r7, #0
7503		- mov r8, r5
7504		-.L1347:
7505		- cmp r7, r6
7506		- beq .L1368
	7736	+ add r6, r6, #36
	7737	+ b .L1336
	7738	+.L1350:
7507	7739	ldr r3, [r4]
7508	7740	cmn r3, #1
7509		- bne .L1348
	7741	+ bne .L1344
7510	7742	ldr r1, [r4, #4]
7511		- ldr r0, .L1369+12
	7743	+ ldr r0, .L1363+16
7512	7744	bl printk
7513		- b .L1349
7514		-.L1348:
7515		- rsb r3, r7, r6
7516		- mov r1, r9
7517		- add r2, sp, #20
7518		- mov r0, r4
	7745	+.L1345:
	7746	+ add r6, r6, #1
	7747	+ add r4, r4, #36
	7748	+ b .L1343
	7749	+.L1344:
	7750	+ sub r3, r7, r6
	7751	+ add r2, sp, #12
7519	7752	uxtb r3, r3
	7753	+ mov r1, r8
	7754	+ mov r0, r4
7520	7755	str r3, [sp]
7521		- add r3, sp, #24
	7756	+ add r3, sp, #16
7522	7757	bl LogAddr2PhyAddr
7523		- ldr r2, [r5, #-1768]
	7758	+ ldr r2, [r5, #-1764]
7524	7759	mov r3, #0
7525	7760	mov lr, r4
	7761	+ add ip, sp, #20
7526	7762	str r3, [r2]
7527		- ldr r2, [r5, #-1764]
	7763	+ ldr r2, [r5, #-1760]
7528	7764	str r3, [r2]
7529	7765	ldmia lr!, {r0, r1, r2, r3}
7530		- add ip, sp, #28
7531	7766	stmia ip!, {r0, r1, r2, r3}
7532	7767	ldmia lr!, {r0, r1, r2, r3}
7533	7768	stmia ip!, {r0, r1, r2, r3}
7534		- add r0, sp, #28
	7769	+ mov r2, r8
7535	7770	ldr r3, [lr]
7536	7771	mov r1, #1
7537		- mov r2, r9
	7772	+ add r0, sp, #20
7538	7773	str r3, [ip]
7539		- ldr r3, [r5, #-1768]
7540		- str r3, [sp, #36]
7541	7774	ldr r3, [r5, #-1764]
7542		- str r3, [sp, #40]
	7775	+ str r3, [sp, #28]
	7776	+ ldr r3, [r5, #-1760]
	7777	+ str r3, [sp, #32]
7543	7778	bl FlashReadPages
7544		- ldr r10, [sp, #28]
	7779	+ ldr r10, [sp, #20]
7545	7780	cmn r10, #1
7546		- bne .L1350
7547		- ldr r0, .L1369+16
	7781	+ bne .L1346
7548	7782	ldr r1, [r4, #4]
	7783	+ ldr r0, .L1363+20
7549	7784	bl printk
7550	7785	str r10, [r4]
7551		-.L1350:
7552		- ldr r10, [sp, #28]
	7786	+.L1346:
	7787	+ ldr r10, [sp, #20]
7553	7788	cmp r10, #256
7554		- bne .L1351
7555		- ldr r0, .L1369+20
	7789	+ bne .L1347
7556	7790	ldr r1, [r4, #4]
	7791	+ ldr r0, .L1363+24
7557	7792	bl printk
7558	7793	str r10, [r4]
7559		-.L1351:
	7794	+.L1347:
7560	7795	ldr r3, [r4, #12]
7561	7796	cmp r3, #0
7562		- beq .L1352
	7797	+ beq .L1348
7563	7798	ldr r2, [r3]
7564		- ldr r3, [r8, #-1764]
	7799	+ ldr r3, [r5, #-1760]
7565	7800	ldr r3, [r3]
7566	7801	cmp r2, r3
7567		- beq .L1352
7568		- ldr r0, .L1369+24
	7802	+ beq .L1348
7569	7803	ldr r1, [r4, #4]
	7804	+ ldr r0, .L1363+28
7570	7805	bl printk
7571	7806	mvn r3, #0
7572	7807	str r3, [r4]
7573		-.L1352:
	7808	+.L1348:
7574	7809	ldr r3, [r4, #8]
7575	7810	cmp r3, #0
7576		- beq .L1349
	7811	+ beq .L1345
7577	7812	ldr r2, [r3]
7578		- ldr r3, [r8, #-1768]
	7813	+ ldr r3, [r5, #-1764]
7579	7814	ldr r3, [r3]
7580	7815	cmp r2, r3
7581		- beq .L1349
7582		- ldr r0, .L1369+28
	7816	+ beq .L1345
7583	7817	ldr r1, [r4, #4]
	7818	+ mov r0, r9
7584	7819	bl printk
7585	7820	mvn r3, #0
7586	7821	str r3, [r4]
7587		-.L1349:
7588		- add r7, r7, #1
7589		- add r4, r4, #36
7590		- b .L1347
7591		-.L1368:
7592		- mov r0, #0
7593		- add sp, sp, #68
7594		- @ sp needed
7595		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
7596		-.L1370:
	7822	+ b .L1345
	7823	+.L1364:
7597	7824	.align 2
7598		-.L1369:
	7825	+.L1363:
7599	7826	.word .LANCHOR1
7600	7827	.word .LANCHOR0
7601	7828	.word .LANCHOR2
	7829	+ .word .LC26
7602	7830	.word .LC22
7603	7831	.word .LC23
7604	7832	.word .LC24
7605	7833	.word .LC25
7606		- .word .LC26
7607	7834	.fnend
7608	7835	.size FlashProgSlc2KPages, .-FlashProgSlc2KPages
7609	7836	.align 2
7610	7837	.global FlashProgPages
	7838	+ .syntax unified
	7839	+ .arm
	7840	+ .fpu softvfp
7611	7841	.type FlashProgPages, %function
7612	7842	FlashProgPages:
7613	7843	.fnstart
7614	7844	@ args = 0, pretend = 0, frame = 64
7615	7845	@ frame_needed = 0, uses_anonymous_args = 0
7616		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	7846	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
7617	7847	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
7618	7848	.pad #76
7619	7849	sub sp, sp, #76
7620		- ldr r6, .L1427
7621		- mov r4, r0
	7850	+ ldr r6, .L1418
7622	7851	str r1, [sp, #8]
7623		- mov r9, r2
	7852	+ ldr ip, [r6, #48]
	7853	+ ldrb r8, [r6, #36] @ zero_extendqisi2
7624	7854	str r3, [sp, #20]
7625		- ldr ip, [r6, #44]
7626		- ldrb r8, [r6] @ zero_extendqisi2
7627	7855	ldrb ip, [ip, #19] @ zero_extendqisi2
7628	7856	cmp r8, #0
7629	7857	str ip, [sp, #16]
7630		- ldr ip, .L1427+4
7631		- ldrb ip, [ip, #265] @ zero_extendqisi2
7632		- str ip, [sp, #12]
7633		- beq .L1372
7634		- bl FlashProgSlc2KPages
7635		- b .L1373
7636		-.L1385:
7637		- mov r7, #36
	7858	+ bne .L1366
	7859	+ ldr r3, .L1418+4
	7860	+ mov r4, r0
	7861	+ mov r9, r2
	7862	+ ldrb r3, [r3, #477] @ zero_extendqisi2
	7863	+ str r3, [sp, #12]
	7864	+.L1367:
7638	7865	ldr r3, [sp, #8]
	7866	+ cmp r8, r3
	7867	+ bcc .L1380
	7868	+ ldr r7, .L1418+8
	7869	+ mov r5, #0
	7870	+ ldr r8, .L1418+12
	7871	+.L1381:
	7872	+ ldrb r3, [r6, #3156] @ zero_extendqisi2
	7873	+ cmp r5, r3
	7874	+ bcc .L1383
	7875	+ ldr r3, [sp, #20]
	7876	+ cmp r3, #0
	7877	+ bne .L1384
	7878	+.L1392:
	7879	+ mov r0, #0
	7880	+ b .L1365
	7881	+.L1366:
	7882	+ bl FlashProgSlc2KPages
	7883	+.L1365:
	7884	+ add sp, sp, #76
	7885	+ @ sp needed
	7886	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	7887	+.L1380:
	7888	+ ldr r3, [sp, #8]
	7889	+ mov r7, #36
7639	7890	mul r7, r7, r8
7640		- rsb r3, r8, r3
7641		- mov r1, r9
7642	7891	add r2, sp, #28
	7892	+ mov r1, r9
	7893	+ sub r3, r3, r8
7643	7894	uxtb r3, r3
7644		- str r3, [sp]
7645	7895	add fp, r4, r7
7646		- add r3, sp, #32
	7896	+ str r3, [sp]
7647	7897	mov r0, fp
	7898	+ add r3, sp, #32
7648	7899	bl LogAddr2PhyAddr
7649		- ldrb r3, [r6, #3152] @ zero_extendqisi2
	7900	+ ldrb r3, [r6, #3156] @ zero_extendqisi2
7650	7901	mov r10, r0
7651	7902	ldr r0, [sp, #32]
7652		- cmp r0, r3
7653		- mvncs r3, #0
7654		- strcs r3, [r4, r7]
7655		- bcc .L1424
7656		-.L1375:
7657		- add r8, r8, #1
7658		-.L1372:
7659		- ldr r3, [sp, #8]
7660		- ldr r5, .L1427
7661		- cmp r8, r3
7662		- bcc .L1385
7663		- b .L1425
7664		-.L1424:
7665		- ldr r3, .L1427+8
7666		- ldrb r3, [r3, #-1874] @ zero_extendqisi2
	7903	+ cmp r3, r0
	7904	+ mvnls r3, #0
	7905	+ strls r3, [r4, r7]
	7906	+ bls .L1370
	7907	+ ldr r3, .L1418+8
	7908	+ ldrb r3, [r3, #-1870] @ zero_extendqisi2
7667	7909	cmp r3, #0
7668		- add r3, r6, r0, asl #4
7669		- ldr r3, [r3, #3204]
	7910	+ add r3, r6, r0, lsl #4
7670	7911	moveq r10, #0
	7912	+ ldr r3, [r3, #3208]
7671	7913	cmp r3, #0
7672		- beq .L1377
	7914	+ beq .L1372
7673	7915	uxtb r0, r0
7674	7916	bl FlashWaitCmdDone
7675		-.L1377:
	7917	+.L1372:
7676	7918	ldr r3, [sp, #32]
7677	7919	mov r1, #0
7678	7920	cmp r10, #0
7679		- add r2, r6, r3, asl #4
7680		- str r1, [r2, #3208]
	7921	+ add r2, r6, r3, lsl #4
	7922	+ str r1, [r2, #3212]
7681	7923	ldr r1, [sp, #28]
7682		- str fp, [r2, #3204]
7683		- str r1, [r2, #3200]
	7924	+ str fp, [r2, #3208]
	7925	+ str r1, [r2, #3204]
7684	7926	addne r1, r7, #36
7685	7927	addne r1, r4, r1
7686		- strne r1, [r2, #3208]
	7928	+ strne r1, [r2, #3212]
7687	7929	add r2, r6, r3
7688		- add r3, r6, r3, asl #4
7689		- ldrb r5, [r2, #3156] @ zero_extendqisi2
7690		- strb r5, [r3, #3196]
	7930	+ ldrb r5, [r2, #3160] @ zero_extendqisi2
	7931	+ add r3, r6, r3, lsl #4
	7932	+ strb r5, [r3, #3200]
7691	7933	mov r0, r5
7692		- ldrb r3, [r6, #3152] @ zero_extendqisi2
	7934	+ ldrb r3, [r6, #3156] @ zero_extendqisi2
7693	7935	cmp r3, #1
7694		- bne .L1379
	7936	+ bne .L1374
7695	7937	bl NandcWaitFlashReady
7696		- b .L1380
7697		-.L1379:
7698		- bl NandcFlashCs
7699		- mov r0, r5
7700		- ldr r3, [sp, #32]
7701		- ldr r1, [sp, #28]
7702		- add r3, r6, r3, asl #2
7703		- ldr r2, [r3, #3164]
7704		- adds r2, r2, #0
7705		- movne r2, #1
7706		- bl FlashWaitReadyEN
7707		- mov r0, r5
7708		- bl NandcFlashDeCs
7709		-.L1380:
	7938	+.L1375:
7710	7939	ldr r3, [sp, #16]
7711	7940	sub r3, r3, #1
7712	7941	cmp r3, #7
7713		- bhi .L1381
7714		- ldr r3, .L1427+8
7715		- add r3, r3, r5
7716		- ldrb r3, [r3, #-1880] @ zero_extendqisi2
	7942	+ bhi .L1376
	7943	+ ldr r1, .L1418+8
	7944	+ add r3, r1, r5
	7945	+ ldrb r3, [r3, #-1876] @ zero_extendqisi2
7717	7946	cmp r3, #0
7718		- beq .L1381
7719		- ldr r3, .L1427+8
7720		- mov r0, r5
7721		- ldr r2, .L1427+12
7722		- ldrb r1, [r3, #-2731] @ zero_extendqisi2
	7947	+ beq .L1376
7723	7948	mov r3, #0
	7949	+ ldr r2, .L1418+16
	7950	+ ldrb r1, [r1, #-2727] @ zero_extendqisi2
	7951	+ mov r0, r5
7724	7952	bl HynixSetRRPara
7725		-.L1381:
	7953	+.L1376:
7726	7954	mov r0, r5
7727	7955	bl NandcFlashCs
7728	7956	cmp r9, #1
7729	7957	mov r0, r5
7730		- bne .L1382
7731		- ldr r3, .L1427+8
7732		- ldrb r3, [r3, #-2744] @ zero_extendqisi2
	7958	+ bne .L1377
	7959	+ ldr r3, .L1418+8
	7960	+ ldrb r3, [r3, #-2740] @ zero_extendqisi2
7733	7961	cmp r3, #0
7734		- beq .L1382
	7962	+ beq .L1377
7735	7963	bl flash_enter_slc_mode
7736		- b .L1383
7737		-.L1382:
7738		- bl flash_exit_slc_mode
7739		-.L1383:
7740		- mov r0, r5
	7964	+.L1378:
7741	7965	ldr r1, [sp, #28]
	7966	+ mov r0, r5
7742	7967	bl FlashProgFirstCmd
7743	7968	ldr r3, [fp, #12]
7744		- mov r0, r5
7745	7969	mov r1, #1
7746		- str r3, [sp]
7747	7970	ldr r2, [sp, #12]
	7971	+ mov r0, r5
	7972	+ str r3, [sp]
7748	7973	ldr r3, [fp, #8]
7749	7974	bl NandcXferData
7750	7975	cmp r10, #0
7751		- beq .L1384
	7976	+ beq .L1379
	7977	+ ldr r1, [sp, #28]
	7978	+ mov r0, r5
	7979	+ bl FlashProgDpFirstCmd
	7980	+ ldr r3, [sp, #32]
7752	7981	mov r0, r5
7753	7982	ldr r1, [sp, #28]
7754		- bl FlashProgDpFirstCmd
7755		- mov r0, r5
7756	7983	add r7, r7, #36
7757	7984	add r7, r4, r7
7758		- ldr r3, [sp, #32]
7759		- ldr r1, [sp, #28]
7760		- add r3, r6, r3, asl #2
7761		- ldr r2, [r3, #3164]
	7985	+ add r3, r6, r3, lsl #2
	7986	+ ldr r2, [r3, #3168]
7762	7987	adds r2, r2, #0
7763	7988	movne r2, #1
7764	7989	bl FlashWaitReadyEN
7765		- ldr r1, [r6, #4]
	7990	+ ldr r3, [r6, #40]
7766	7991	mov r0, r5
7767		- ldr r3, [sp, #28]
	7992	+ ldr r1, [sp, #28]
7768	7993	add r1, r1, r3
7769	7994	bl FlashProgDpSecondCmd
7770	7995	ldr r3, [r7, #12]
7771		- mov r0, r5
7772	7996	mov r1, #1
7773		- str r3, [sp]
7774	7997	ldr r2, [sp, #12]
	7998	+ mov r0, r5
	7999	+ str r3, [sp]
7775	8000	ldr r3, [r7, #8]
7776	8001	bl NandcXferData
7777		-.L1384:
7778		- mov r0, r5
	8002	+.L1379:
7779	8003	ldr r1, [sp, #28]
	8004	+ mov r0, r5
	8005	+ add r8, r8, r10
7780	8006	bl FlashProgSecondCmd
7781	8007	mov r0, r5
7782	8008	bl NandcFlashDeCs
7783		- add r8, r8, r10
	8009	+.L1370:
	8010	+ add r8, r8, #1
	8011	+ b .L1367
	8012	+.L1374:
	8013	+ bl NandcFlashCs
	8014	+ ldr r3, [sp, #32]
	8015	+ mov r0, r5
	8016	+ ldr r1, [sp, #28]
	8017	+ add r3, r6, r3, lsl #2
	8018	+ ldr r2, [r3, #3168]
	8019	+ adds r2, r2, #0
	8020	+ movne r2, #1
	8021	+ bl FlashWaitReadyEN
	8022	+ mov r0, r5
	8023	+ bl NandcFlashDeCs
7784	8024	b .L1375
7785		-.L1425:
7786		- ldr r7, .L1427+8
7787		- mov r6, #0
7788		- ldr r8, .L1427+16
7789		-.L1386:
7790		- ldrb r3, [r5, #3152] @ zero_extendqisi2
7791		- cmp r6, r3
7792		- bcs .L1426
7793		- uxtb r0, r6
	8025	+.L1377:
	8026	+ bl flash_exit_slc_mode
	8027	+ b .L1378
	8028	+.L1383:
	8029	+ uxtb r0, r5
7794	8030	bl FlashWaitCmdDone
7795	8031	cmp r9, #1
7796		- bne .L1387
7797		- ldrb r3, [r7, #-2744] @ zero_extendqisi2
	8032	+ bne .L1382
	8033	+ ldrb r3, [r7, #-2740] @ zero_extendqisi2
7798	8034	cmp r3, #0
7799		- beq .L1387
7800		- ldrb r0, [r8, r6, asl #4] @ zero_extendqisi2
	8035	+ beq .L1382
	8036	+ ldrb r0, [r8, r5, lsl #4] @ zero_extendqisi2
7801	8037	bl flash_exit_slc_mode
7802		-.L1387:
7803		- add r6, r6, #1
7804		- b .L1386
7805		-.L1426:
7806		- ldr r3, [sp, #20]
7807		- cmp r3, #0
7808		- bne .L1389
7809		-.L1397:
7810		- mov r0, #0
7811		- b .L1373
7812		-.L1389:
7813		- ldr r5, .L1427+8
	8038	+.L1382:
	8039	+ add r5, r5, #1
	8040	+ b .L1381
	8041	+.L1384:
	8042	+ ldr r5, .L1418+8
7814	8043	mov r6, #0
7815		- mov r7, r5
7816		-.L1390:
	8044	+ ldr r7, .L1418+20
	8045	+.L1385:
7817	8046	ldr r3, [sp, #8]
7818	8047	cmp r6, r3
7819		- beq .L1397
	8048	+ beq .L1392
7820	8049	ldr r3, [r4]
7821	8050	cmn r3, #1
7822		- bne .L1391
	8051	+ bne .L1386
7823	8052	ldr r1, [r4, #4]
7824		- ldr r0, .L1427+20
	8053	+ ldr r0, .L1418+24
7825	8054	bl printk
7826		- b .L1392
7827		-.L1391:
	8055	+.L1387:
	8056	+ add r6, r6, #1
	8057	+ add r4, r4, #36
	8058	+ b .L1385
	8059	+.L1386:
7828	8060	ldr r3, [sp, #8]
7829		- mov r1, r9
7830	8061	add r2, sp, #28
	8062	+ mov r1, r9
7831	8063	mov r0, r4
7832		- rsb r3, r6, r3
	8064	+ sub r3, r3, r6
7833	8065	uxtb r3, r3
7834	8066	str r3, [sp]
7835	8067	add r3, sp, #32
7836	8068	bl LogAddr2PhyAddr
7837		- ldr r2, [r5, #-1768]
	8069	+ ldr r2, [r5, #-1764]
7838	8070	mov r3, #0
7839	8071	mov lr, r4
7840		- str r3, [r2]
7841		- ldr r2, [r5, #-1764]
7842		- str r3, [r2]
7843		- ldmia lr!, {r0, r1, r2, r3}
7844	8072	add ip, sp, #36
	8073	+ str r3, [r2]
	8074	+ ldr r2, [r5, #-1760]
	8075	+ str r3, [r2]
	8076	+ ldmia lr!, {r0, r1, r2, r3}
7845	8077	stmia ip!, {r0, r1, r2, r3}
7846	8078	ldmia lr!, {r0, r1, r2, r3}
7847	8079	stmia ip!, {r0, r1, r2, r3}
7848		- add r0, sp, #36
	8080	+ mov r2, r9
7849	8081	ldr r3, [lr]
7850	8082	mov r1, #1
7851		- mov r2, r9
	8083	+ add r0, sp, #36
7852	8084	str r3, [ip]
7853		- ldr r3, [r5, #-1768]
7854		- str r3, [sp, #44]
7855	8085	ldr r3, [r5, #-1764]
	8086	+ str r3, [sp, #44]
	8087	+ ldr r3, [r5, #-1760]
7856	8088	str r3, [sp, #48]
7857	8089	bl FlashReadPages
7858	8090	ldr r8, [sp, #36]
7859	8091	cmn r8, #1
7860		- bne .L1393
7861		- ldr r0, .L1427+24
	8092	+ bne .L1388
7862	8093	ldr r1, [r4, #4]
	8094	+ ldr r0, .L1418+28
7863	8095	bl printk
7864	8096	str r8, [r4]
7865		-.L1393:
	8097	+.L1388:
7866	8098	ldr r3, [r4, #12]
7867	8099	cmp r3, #0
7868		- beq .L1394
	8100	+ beq .L1389
7869	8101	ldr r2, [r3]
7870		- ldr r3, [r7, #-1764]
	8102	+ ldr r3, [r5, #-1760]
7871	8103	ldr r3, [r3]
7872	8104	cmp r2, r3
7873		- beq .L1394
7874		- ldr r0, .L1427+28
	8105	+ beq .L1389
7875	8106	ldr r1, [r4, #4]
	8107	+ ldr r0, .L1418+32
7876	8108	bl printk
7877	8109	mvn r3, #0
7878	8110	str r3, [r4]
7879		-.L1394:
	8111	+.L1389:
7880	8112	ldr r3, [r4, #8]
7881	8113	cmp r3, #0
7882		- beq .L1392
	8114	+ beq .L1387
7883	8115	ldr r2, [r3]
7884		- ldr r3, [r7, #-1768]
	8116	+ ldr r3, [r5, #-1764]
7885	8117	ldr r3, [r3]
7886	8118	cmp r2, r3
7887		- beq .L1392
7888		- ldr r0, .L1427+32
	8119	+ beq .L1387
7889	8120	ldr r1, [r4, #4]
	8121	+ mov r0, r7
7890	8122	bl printk
7891	8123	mvn r3, #0
7892	8124	str r3, [r4]
7893		-.L1392:
7894		- add r6, r6, #1
7895		- add r4, r4, #36
7896		- b .L1390
7897		-.L1373:
7898		- add sp, sp, #76
7899		- @ sp needed
7900		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
7901		-.L1428:
	8125	+ b .L1387
	8126	+.L1419:
7902	8127	.align 2
7903		-.L1427:
	8128	+.L1418:
7904	8129	.word .LANCHOR0
7905	8130	.word .LANCHOR1
7906	8131	.word .LANCHOR2
7907		- .word .LANCHOR2-2728
7908		- .word .LANCHOR0+3196
	8132	+ .word .LANCHOR0+3200
	8133	+ .word .LANCHOR2-2724
	8134	+ .word .LC26
7909	8135	.word .LC22
7910	8136	.word .LC23
7911	8137	.word .LC25
7912		- .word .LC26
7913	8138	.fnend
7914	8139	.size FlashProgPages, .-FlashProgPages
7915	8140	.align 2
7916	8141	.global FlashTestBlk
	8142	+ .syntax unified
	8143	+ .arm
	8144	+ .fpu softvfp
7917	8145	.type FlashTestBlk, %function
7918	8146	FlashTestBlk:
7919	8147	.fnstart
7920	8148	@ args = 0, pretend = 0, frame = 104
7921	8149	@ frame_needed = 0, uses_anonymous_args = 0
7922		- stmfd sp!, {r4, r5, lr}
	8150	+ push {r4, r5, lr}
7923	8151	.save {r4, r5, lr}
7924	8152	.pad #108
7925	8153	sub sp, sp, #108
7926		- ldr r5, .L1433
7927		- ldr r3, [r5, #-1784]
	8154	+ ldr r5, .L1424
	8155	+ ldr r3, [r5, #-1780]
7928	8156	cmp r0, r3
7929	8157	movcc r4, #0
7930		- bcc .L1430
7931		- ldr r3, [r5, #-1776]
	8158	+ bcc .L1420
	8159	+ ldr r3, [r5, #-1772]
7932	8160	mov r4, r0
7933		- mov r1, #165
7934		- add r0, sp, #40
7935	8161	mov r2, #32
	8162	+ add r0, sp, #40
	8163	+ mov r1, #165
7936	8164	str r0, [sp, #16]
7937	8165	str r3, [sp, #12]
7938	8166	bl ftl_memset
7939		- mov r1, #90
7940	8167	mov r2, #8
7941		- ldr r0, [r5, #-1776]
7942		- mov r4, r4, asl #10
	8168	+ mov r1, #90
	8169	+ ldr r0, [r5, #-1772]
7943	8170	bl ftl_memset
7944		- mov r1, #1
7945		- mov r2, r1
7946		- add r0, sp, #4
7947		- str r4, [sp, #8]
7948		- bl FlashEraseBlocks
7949		- mov r1, #1
7950		- mov r2, r1
7951		- mov r3, r1
7952		- add r0, sp, #4
7953		- bl FlashProgPages
7954		- mov r1, #0
	8171	+ lsl r0, r4, #10
7955	8172	mov r2, #1
	8173	+ mov r1, r2
	8174	+ str r0, [sp, #8]
	8175	+ add r0, sp, #4
	8176	+ bl FlashEraseBlocks
	8177	+ mov r3, #1
	8178	+ add r0, sp, #4
	8179	+ mov r2, r3
	8180	+ mov r1, r3
	8181	+ bl FlashProgPages
7956	8182	ldr r4, [sp, #4]
	8183	+ mov r2, #1
	8184	+ mov r1, #0
7957	8185	add r0, sp, #4
7958	8186	adds r4, r4, #0
7959	8187	movne r4, #1
7960	8188	rsb r4, r4, #0
7961	8189	bl FlashEraseBlocks
7962		-.L1430:
	8190	+.L1420:
7963	8191	mov r0, r4
7964	8192	add sp, sp, #108
7965	8193	@ sp needed
7966		- ldmfd sp!, {r4, r5, pc}
7967		-.L1434:
	8194	+ pop {r4, r5, pc}
	8195	+.L1425:
7968	8196	.align 2
7969		-.L1433:
	8197	+.L1424:
7970	8198	.word .LANCHOR2
7971	8199	.fnend
7972	8200	.size FlashTestBlk, .-FlashTestBlk
7973	8201	.align 2
7974	8202	.global FlashMakeFactorBbt
	8203	+ .syntax unified
	8204	+ .arm
	8205	+ .fpu softvfp
7975	8206	.type FlashMakeFactorBbt, %function
7976	8207	FlashMakeFactorBbt:
7977	8208	.fnstart
7978	8209	@ args = 0, pretend = 0, frame = 80
7979	8210	@ frame_needed = 0, uses_anonymous_args = 0
7980		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	8211	+ ldr r3, .L1477
	8212	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
7981	8213	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
7982	8214	.pad #84
7983	8215	sub sp, sp, #84
7984		- ldr r4, .L1491
	8216	+ ldr r0, .L1477+4
	8217	+ sub r1, r3, #2768
	8218	+ mov r4, r3
	8219	+ ldr r2, [r3, #-1768]
	8220	+ str r2, [sp, #20]
	8221	+ ldrh r2, [r1, #14]
	8222	+ ldrh r1, [r1, #12]
	8223	+ smulbb r2, r2, r1
	8224	+ uxth r2, r2
	8225	+ str r2, [sp]
	8226	+ ldr r2, .L1477+8
	8227	+ ldr r1, [r2, #48]
	8228	+ ldrb r1, [r1, #24] @ zero_extendqisi2
	8229	+ str r1, [sp, #24]
	8230	+ ldrh r1, [r2, #40]
	8231	+ ldrb r2, [r2, #36] @ zero_extendqisi2
	8232	+ str r1, [sp, #16]
	8233	+ cmp r2, #1
	8234	+ moveq r3, r1
7985	8235	mov r1, #1
7986		- ldr r5, .L1491+4
7987		- ldr r0, .L1491+8
7988		- ldr r3, [r4, #-1772]
7989		- ldrh r8, [r5, #12]
7990		- ldr r7, .L1491+12
7991		- str r3, [sp, #20]
7992		- ldrh r3, [r5, #14]
7993		- smulbb r8, r8, r3
7994		- ldr r3, .L1491+12
7995		- ldr r2, [r3, #44]
7996		- uxth r8, r8
7997		- ldrb r2, [r2, #24] @ zero_extendqisi2
7998		- str r2, [sp, #24]
7999		- ldrh r2, [r3, #4]
8000		- ldrb r3, [r3] @ zero_extendqisi2
8001		- cmp r3, #1
8002		- str r2, [sp, #16]
8003		- moveq r3, r2
8004		- moveq r3, r3, asl #1
	8236	+ lsleq r3, r3, #1
8005	8237	uxtheq r3, r3
8006	8238	streq r3, [sp, #16]
8007	8239	bl printk
8008		- ldr r0, [r4, #-1772]
8009		- mov r1, #0
	8240	+ ldr r0, [r4, #-1768]
8010	8241	mov r2, #4096
	8242	+ mov r1, #0
	8243	+ ldr r4, .L1477
8011	8244	bl ftl_memset
8012		- ldr r4, .L1491
8013		- mov r3, r8, lsr #4
	8245	+ ldr r3, [sp]
	8246	+ lsr r3, r3, #4
8014	8247	str r3, [sp, #28]
8015	8248	mov r3, #0
8016	8249	str r3, [sp, #8]
8017		-.L1437:
8018		- ldrb r6, [sp, #8] @ zero_extendqisi2
8019		- ldrb r3, [r7, #3152] @ zero_extendqisi2
8020		- cmp r3, r6
8021		- bls .L1487
8022		- ldr r3, .L1491+16
8023		- mov r2, r6, asl #1
8024		- ldrh r5, [r3, r2]
8025		- cmp r5, #0
8026		- bne .L1467
8027		- sub r3, r3, #1016
8028		- ldr r0, [r4, #-1868]
8029		- mov r1, r5
8030		- mov r9, r5
8031		- ldrh r2, [r3, #20]
8032		- mov r2, r2, asl #9
8033		- bl ftl_memset
8034		- add r3, r7, r6
8035		- ldrb r10, [r3, #3156] @ zero_extendqisi2
8036		- mov r3, r6, asl #2
8037		- add fp, r7, r3
8038		- str r5, [sp, #4]
	8250	+ sub r3, r4, #1744
	8251	+ sub r3, r3, #10
8039	8252	str r3, [sp, #32]
8040		-.L1439:
	8253	+.L1428:
	8254	+ ldr r5, .L1477+8
	8255	+ ldrb r7, [sp, #8] @ zero_extendqisi2
	8256	+ ldrb r3, [r5, #3156] @ zero_extendqisi2
	8257	+ cmp r3, r7
	8258	+ bhi .L1455
	8259	+ add sp, sp, #84
	8260	+ @ sp needed
	8261	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	8262	+.L1455:
	8263	+ ldr r2, [sp, #32]
	8264	+ lsl r3, r7, #1
	8265	+ ldrh r6, [r2, r3]
	8266	+ cmp r6, #0
	8267	+ bne .L1429
	8268	+ ldr r3, .L1477+12
	8269	+ mov r1, r6
	8270	+ ldr r0, [r4, #-1864]
	8271	+ add fp, r5, r7, lsl #2
	8272	+ mov r8, r6
	8273	+ ldrh r2, [r3, #20]
	8274	+ mov r9, r6
	8275	+ lsl r2, r2, #9
	8276	+ bl ftl_memset
	8277	+ add r3, r5, r7
	8278	+ str r6, [sp, #4]
	8279	+ ldrb r10, [r3, #3160] @ zero_extendqisi2
	8280	+.L1430:
8041	8281	ldrh r3, [sp, #4]
8042		- cmp r3, r8
	8282	+ ldr r2, [sp]
8043	8283	str r3, [sp, #12]
8044		- bcs .L1449
	8284	+ cmp r3, r2
	8285	+ bcc .L1441
	8286	+.L1440:
	8287	+ ldr r5, .L1477+8
	8288	+ mov r2, r8
	8289	+ mov r1, r7
	8290	+ ldr r0, .L1477+16
	8291	+ bl printk
	8292	+ ldrb r3, [r5, #3156] @ zero_extendqisi2
	8293	+ ldr r2, [sp, #28]
	8294	+ mul r3, r2, r3
	8295	+ cmp r8, r3
	8296	+ mov r8, r5
	8297	+ blt .L1442
	8298	+ ldr r3, .L1477+12
	8299	+ mov r1, #0
	8300	+ ldr r0, [r4, #-1864]
	8301	+ ldrh r2, [r3, #20]
	8302	+ lsl r2, r2, #9
	8303	+ bl ftl_memset
	8304	+.L1442:
	8305	+ cmp r7, #0
	8306	+ bne .L1444
	8307	+ sub r3, r4, #1776
	8308	+ ldr r9, .L1477+20
	8309	+ sub r3, r3, #4
	8310	+ ldrh fp, [r3]
	8311	+ mov r10, #1
	8312	+.L1445:
	8313	+ ldrb r3, [r8, #37] @ zero_extendqisi2
	8314	+ cmp r3, fp
	8315	+ bhi .L1447
	8316	+ ldr r3, [sp]
	8317	+ mov r10, #1
	8318	+ ldr r9, .L1477+20
	8319	+ sub fp, r3, #1
	8320	+ sub r8, r3, #50
	8321	+ uxth fp, fp
	8322	+.L1448:
	8323	+ cmp fp, r8
	8324	+ bgt .L1450
	8325	+ ldrb r3, [r5, #37] @ zero_extendqisi2
	8326	+ ldr r2, [r4, #-1780]
	8327	+ sub r3, r3, r2
	8328	+ cmp r6, r3
	8329	+ bcc .L1444
	8330	+ ldr r3, .L1477+12
	8331	+ mov r1, #0
	8332	+ ldr r0, [r4, #-1864]
	8333	+ ldrh r2, [r3, #20]
	8334	+ lsl r2, r2, #9
	8335	+ bl ftl_memset
	8336	+.L1444:
	8337	+ ldr r3, [sp]
	8338	+ ldrb r6, [sp, #8] @ zero_extendqisi2
	8339	+ ldr r8, .L1477+24
	8340	+ sub r5, r3, #1
	8341	+ ldr r10, .L1477+28
	8342	+ ldr r9, .L1477+32
	8343	+ uxth r5, r5
	8344	+ mul r6, r3, r6
	8345	+ add r8, r8, r7, lsl #1
	8346	+.L1452:
	8347	+ mov r1, r7
	8348	+ mov r2, r5
	8349	+ mov r0, r10
	8350	+ bl printk
	8351	+ ldr r1, [r4, #-1864]
	8352	+.L1453:
	8353	+ lsr r2, r5, #5
	8354	+ and r3, r5, #31
	8355	+ ldr r2, [r1, r2, lsl #2]
	8356	+ lsr r3, r2, r3
	8357	+ ands r3, r3, #1
	8358	+ bne .L1454
	8359	+ ldr r2, [sp, #20]
	8360	+ add r0, sp, #44
	8361	+ strh r5, [r8] @ movhi
	8362	+ strh r9, [r2] @ movhi
	8363	+ strh r5, [r2, #2] @ movhi
	8364	+ strh r3, [r2, #8] @ movhi
	8365	+ mov r2, #1
	8366	+ ldr r3, [r4, #-1864]
	8367	+ mov r1, r2
	8368	+ str r3, [sp, #52]
	8369	+ ldr r3, [r4, #-1768]
	8370	+ str r3, [sp, #56]
	8371	+ add r3, r5, r6
	8372	+ lsl r3, r3, #10
	8373	+ str r3, [sp, #48]
	8374	+ bl FlashEraseBlocks
	8375	+ mov r3, #1
	8376	+ add r0, sp, #44
	8377	+ mov r2, r3
	8378	+ mov r1, r3
	8379	+ bl FlashProgPages
	8380	+ ldr r3, [sp, #44]
	8381	+ cmp r3, #0
	8382	+ beq .L1429
	8383	+ sub r5, r5, #1
	8384	+ uxth r5, r5
	8385	+ b .L1452
	8386	+.L1441:
8045	8387	mvn r3, #0
8046	8388	strb r3, [sp, #42]
8047	8389	strb r3, [sp, #43]
8048	8390	ldr r3, [sp, #24]
8049	8391	tst r3, #1
8050		- beq .L1441
8051		- ldr r3, [fp, #3164]
	8392	+ beq .L1432
	8393	+ ldr r3, [fp, #3168]
8052	8394	add r2, sp, #42
8053	8395	mov r0, r10
8054		- add r3, r5, r3
8055		- str r3, [sp, #36]
	8396	+ add r3, r9, r3
8056	8397	mov r1, r3
	8398	+ str r3, [sp, #36]
8057	8399	bl FlashReadSpare
8058		- ldrb r2, [r7] @ zero_extendqisi2
8059		- cmp r2, #1
	8400	+ ldrb r2, [r5, #36] @ zero_extendqisi2
8060	8401	ldr r3, [sp, #36]
8061		- bne .L1441
8062		- ldr r1, [r7, #4]
	8402	+ cmp r2, #1
	8403	+ bne .L1432
	8404	+ ldr r1, [r5, #40]
8063	8405	add r2, sp, #43
8064	8406	mov r0, r10
8065	8407	add r1, r3, r1
..	..	@@ -8068,246 +8410,148 @@
8068	8410	ldrb r2, [sp, #43] @ zero_extendqisi2
8069	8411	and r3, r3, r2
8070	8412	strb r3, [sp, #42]
8071		-.L1441:
	8413	+.L1432:
8072	8414	ldr r3, [sp, #24]
8073	8415	tst r3, #2
8074		- beq .L1443
8075		- ldr r3, [r7, #44]
8076		- mov r0, r10
	8416	+ beq .L1434
	8417	+ ldr r3, [r5, #48]
8077	8418	add r2, sp, #43
	8419	+ mov r0, r10
8078	8420	ldrh r1, [r3, #10]
8079		- ldr r3, [fp, #3164]
	8421	+ ldr r3, [fp, #3168]
8080	8422	sub r1, r1, #1
8081	8423	add r1, r1, r3
8082		- add r1, r1, r5
	8424	+ add r1, r1, r9
8083	8425	bl FlashReadSpare
8084		-.L1443:
8085		- ldr r2, [r7, #44]
	8426	+.L1434:
	8427	+ ldr r2, [r5, #48]
8086	8428	ldrb r3, [r2, #7] @ zero_extendqisi2
8087		- cmp r3, #1
8088		- cmpne r3, #8
	8429	+ cmp r3, #8
	8430	+ cmpne r3, #1
8089	8431	ldrb r3, [sp, #42] @ zero_extendqisi2
8090		- beq .L1444
	8432	+ beq .L1435
8091	8433	ldrb r2, [r2, #18] @ zero_extendqisi2
8092	8434	cmp r2, #12
8093		- bne .L1445
8094		-.L1444:
	8435	+ bne .L1436
	8436	+.L1435:
8095	8437	cmp r3, #0
8096		- ldrneb r0, [sp, #43] @ zero_extendqisi2
	8438	+ ldrbne r0, [sp, #43] @ zero_extendqisi2
8097	8439	clzne r0, r0
8098		- movne r0, r0, lsr #5
8099		- bne .L1446
8100		- b .L1466
8101		-.L1445:
	8440	+ lsrne r0, r0, #5
	8441	+ bne .L1437
	8442	+.L1457:
	8443	+ mov r0, #1
	8444	+ b .L1437
	8445	+.L1436:
8102	8446	cmp r3, #255
8103		- bne .L1466
	8447	+ bne .L1457
8104	8448	ldrb r0, [sp, #43] @ zero_extendqisi2
8105	8449	subs r0, r0, #255
8106	8450	movne r0, #1
8107		- b .L1446
8108		-.L1466:
8109		- mov r0, #1
8110		-.L1446:
	8451	+.L1437:
8111	8452	ldr r3, [sp, #24]
8112	8453	tst r3, #4
8113		- beq .L1447
8114		- ldr r3, .L1491+12
	8454	+ beq .L1438
	8455	+ ldr r1, [fp, #3168]
8115	8456	mov r0, r10
8116		- ldr r2, [sp, #32]
8117		- add r3, r3, r2
8118		- ldr r1, [r3, #3164]
8119		- add r1, r5, r1
	8457	+ add r1, r9, r1
8120	8458	bl SandiskProgTestBadBlock
8121		-.L1447:
	8459	+.L1438:
8122	8460	cmp r0, #0
8123		- beq .L1448
8124		- mov r1, r6
	8461	+ beq .L1439
8125	8462	ldr r2, [sp, #4]
8126		- ldr r0, .L1491+20
8127		- add r9, r9, #1
	8463	+ mov r1, r7
	8464	+ ldr r0, .L1477+36
	8465	+ add r8, r8, #1
8128	8466	bl printk
8129		- ldr r1, [r4, #-1868]
8130		- mov ip, #1
8131		- uxth r9, r9
8132	8467	ldr r3, [sp, #12]
8133		- mov r0, r3, lsr #5
8134		- and r3, r3, #31
8135		- ldr r2, [r1, r0, asl #2]
8136		- orr r3, r2, ip, asl r3
	8468	+ mov ip, #1
	8469	+ ldr r2, [r4, #-1864]
	8470	+ uxth r8, r8
	8471	+ and r0, r3, #31
	8472	+ lsr r1, r3, #5
	8473	+ ldr r3, [r2, r1, lsl #2]
	8474	+ orr r3, r3, ip, lsl r0
	8475	+ str r3, [r2, r1, lsl #2]
8137	8476	ldr r2, [sp, #28]
8138		- str r3, [r1, r0, asl #2]
8139		- ldrb r3, [r7, #3152] @ zero_extendqisi2
8140		- mul r3, r3, r2
8141		- cmp r9, r3
8142		- bgt .L1449
8143		-.L1448:
	8477	+ ldrb r3, [r5, #3156] @ zero_extendqisi2
	8478	+ mul r3, r2, r3
	8479	+ cmp r8, r3
	8480	+ bgt .L1440
	8481	+.L1439:
8144	8482	ldr r3, [sp, #4]
8145	8483	add r3, r3, #1
8146	8484	str r3, [sp, #4]
8147	8485	ldr r3, [sp, #16]
8148		- add r5, r5, r3
8149		- b .L1439
8150		-.L1449:
8151		- mov r2, r9
8152		- ldr r0, .L1491+24
8153		- mov r1, r6
8154		- bl printk
8155		- ldrb r3, [r7, #3152] @ zero_extendqisi2
8156		- ldr r2, [sp, #28]
8157		- mul r3, r3, r2
8158		- cmp r9, r3
8159		- blt .L1451
8160		- ldr r3, .L1491+4
8161		- mov r1, #0
8162		- ldr r0, [r4, #-1868]
8163		- ldrh r2, [r3, #20]
8164		- mov r2, r2, asl #9
8165		- bl ftl_memset
8166		-.L1451:
8167		- cmp r6, #0
8168		- bne .L1453
8169		- ldr r3, [r4, #-1784]
8170		- mov r5, r6
8171		- mov r9, #1
8172		- uxth r10, r3
8173		-.L1454:
8174		- ldr r3, .L1491+12
8175		- ldrb r3, [r3, #1] @ zero_extendqisi2
8176		- cmp r3, r10
8177		- bls .L1488
8178		- mov r0, r10
8179		- bl FlashTestBlk
8180		- cmp r0, #0
8181		- beq .L1455
8182		- mov r1, r10
8183		- ldr r0, .L1491+28
8184		- bl printk
8185		- ldr r1, [r4, #-1868]
8186		- mov r0, r10, lsr #5
8187		- add r5, r5, #1
8188		- and r3, r10, #31
8189		- ldr r2, [r1, r0, asl #2]
8190		- uxth r5, r5
8191		- orr r3, r2, r9, asl r3
8192		- str r3, [r1, r0, asl #2]
8193		-.L1455:
8194		- add r10, r10, #1
8195		- uxth r10, r10
8196		- b .L1454
8197		-.L1488:
8198		- sub fp, r8, #1
8199		- sub r9, r8, #50
8200		- mov r10, #1
8201		- uxth fp, fp
8202		-.L1457:
8203		- cmp fp, r9
8204		- ble .L1489
	8486	+ add r9, r9, r3
	8487	+ b .L1430
	8488	+.L1447:
8205	8489	mov r0, fp
8206	8490	bl FlashTestBlk
8207	8491	cmp r0, #0
8208		- beq .L1458
	8492	+ beq .L1446
8209	8493	mov r1, fp
8210		- ldr r0, .L1491+28
	8494	+ mov r0, r9
8211	8495	bl printk
8212		- ldr r1, [r4, #-1868]
8213		- mov r0, fp, lsr #5
	8496	+ ldr r1, [r4, #-1864]
	8497	+ lsr r0, fp, #5
	8498	+ add r6, r6, #1
8214	8499	and r3, fp, #31
8215		- ldr r2, [r1, r0, asl #2]
8216		- orr r3, r2, r10, asl r3
8217		- str r3, [r1, r0, asl #2]
8218		-.L1458:
	8500	+ uxth r6, r6
	8501	+ ldr r2, [r1, r0, lsl #2]
	8502	+ orr r3, r2, r10, lsl r3
	8503	+ str r3, [r1, r0, lsl #2]
	8504	+.L1446:
	8505	+ add fp, fp, #1
	8506	+ uxth fp, fp
	8507	+ b .L1445
	8508	+.L1450:
	8509	+ mov r0, fp
	8510	+ bl FlashTestBlk
	8511	+ cmp r0, #0
	8512	+ beq .L1449
	8513	+ mov r1, fp
	8514	+ mov r0, r9
	8515	+ bl printk
	8516	+ ldr r1, [r4, #-1864]
	8517	+ lsr r0, fp, #5
	8518	+ and r3, fp, #31
	8519	+ ldr r2, [r1, r0, lsl #2]
	8520	+ orr r3, r2, r10, lsl r3
	8521	+ str r3, [r1, r0, lsl #2]
	8522	+.L1449:
8219	8523	sub fp, fp, #1
8220	8524	uxth fp, fp
8221		- b .L1457
8222		-.L1489:
8223		- ldr r3, .L1491+12
8224		- ldr r2, [r4, #-1784]
8225		- ldrb r3, [r3, #1] @ zero_extendqisi2
8226		- rsb r3, r2, r3
8227		- cmp r5, r3
8228		- bcc .L1453
8229		- ldr r3, .L1491+4
8230		- mov r1, #0
8231		- ldr r0, [r4, #-1868]
8232		- ldrh r2, [r3, #20]
8233		- mov r2, r2, asl #9
8234		- bl ftl_memset
8235		-.L1453:
8236		- ldrb r5, [sp, #8] @ zero_extendqisi2
8237		- sub r10, r8, #1
8238		- ldr r9, .L1491+16
8239		- uxth r10, r10
8240		- mul r5, r8, r5
8241		- add r9, r9, r6, asl #1
8242		-.L1461:
8243		- mov r1, r6
8244		- ldr r0, .L1491+32
8245		- mov r2, r10
8246		- bl printk
8247		- ldr r1, [r4, #-1868]
8248		-.L1462:
8249		- mov r2, r10, lsr #5
8250		- and r3, r10, #31
8251		- ldr r2, [r1, r2, asl #2]
8252		- mov r3, r2, lsr r3
8253		- ands r3, r3, #1
8254		- subne r10, r10, #1
8255		- uxthne r10, r10
8256		- bne .L1462
8257		-.L1490:
8258		- ldr r1, [sp, #20]
8259		- add r0, sp, #44
8260		- ldr r2, .L1491+36
8261		- strh r10, [r9] @ movhi
8262		- strh r10, [r1, #2] @ movhi
8263		- strh r2, [r1] @ movhi
8264		- strh r3, [r1, #8] @ movhi
8265		- mov r1, #1
8266		- ldr r3, [r4, #-1868]
8267		- mov r2, r1
8268		- str r3, [sp, #52]
8269		- ldr r3, [r4, #-1772]
8270		- str r3, [sp, #56]
8271		- add r3, r10, r5
8272		- mov r3, r3, asl #10
8273		- str r3, [sp, #48]
8274		- bl FlashEraseBlocks
8275		- mov r1, #1
8276		- mov r3, r1
8277		- mov r2, r1
8278		- add r0, sp, #44
8279		- bl FlashProgPages
8280		- ldr r3, [sp, #44]
8281		- cmp r3, #0
8282		- subne r10, r10, #1
8283		- uxthne r10, r10
8284		- bne .L1461
8285		-.L1467:
	8525	+ b .L1448
	8526	+.L1454:
	8527	+ sub r5, r5, #1
	8528	+ uxth r5, r5
	8529	+ b .L1453
	8530	+.L1429:
8286	8531	ldr r3, [sp, #8]
8287	8532	add r3, r3, #1
8288	8533	str r3, [sp, #8]
8289		- b .L1437
8290		-.L1487:
8291		- add sp, sp, #84
8292		- @ sp needed
8293		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
8294		-.L1492:
	8534	+ b .L1428
	8535	+.L1478:
8295	8536	.align 2
8296		-.L1491:
	8537	+.L1477:
8297	8538	.word .LANCHOR2
8298		- .word .LANCHOR2-2772
8299	8539	.word .LC27
8300	8540	.word .LANCHOR0
8301		- .word .LANCHOR2-1756
8302		- .word .LC28
	8541	+ .word .LANCHOR2-2768
8303	8542	.word .LC29
8304	8543	.word .LC30
	8544	+ .word .LANCHOR2-1754
8305	8545	.word .LC31
8306	8546	.word -3872
	8547	+ .word .LC28
8307	8548	.fnend
8308	8549	.size FlashMakeFactorBbt, .-FlashMakeFactorBbt
8309	8550	.align 2
8310	8551	.global Ftl_log2
	8552	+ .syntax unified
	8553	+ .arm
	8554	+ .fpu softvfp
8311	8555	.type Ftl_log2, %function
8312	8556	Ftl_log2:
8313	8557	.fnstart
..	..	@@ -8316,20 +8560,24 @@
8316	8560	@ link register save eliminated.
8317	8561	mov r1, #0
8318	8562	mov r2, #1
8319		-.L1494:
	8563	+.L1480:
8320	8564	cmp r2, r0
8321	8565	uxth r3, r1
8322	8566	add r1, r1, #1
8323		- movls r2, r2, asl #1
8324		- bls .L1494
8325		-.L1496:
	8567	+ bls .L1481
8326	8568	sub r0, r3, #1
8327	8569	uxth r0, r0
8328	8570	bx lr
	8571	+.L1481:
	8572	+ lsl r2, r2, #1
	8573	+ b .L1480
8329	8574	.fnend
8330	8575	.size Ftl_log2, .-Ftl_log2
8331	8576	.align 2
8332	8577	.global FtlPrintInfo
	8578	+ .syntax unified
	8579	+ .arm
	8580	+ .fpu softvfp
8333	8581	.type FtlPrintInfo, %function
8334	8582	FtlPrintInfo:
8335	8583	.fnstart
..	..	@@ -8341,316 +8589,324 @@
8341	8589	.size FtlPrintInfo, .-FtlPrintInfo
8342	8590	.align 2
8343	8591	.global FtlSysBlkNumInit
	8592	+ .syntax unified
	8593	+ .arm
	8594	+ .fpu softvfp
8344	8595	.type FtlSysBlkNumInit, %function
8345	8596	FtlSysBlkNumInit:
8346	8597	.fnstart
8347	8598	@ args = 0, pretend = 0, frame = 0
8348	8599	@ frame_needed = 0, uses_anonymous_args = 0
8349	8600	@ link register save eliminated.
8350		- ldr r3, .L1500
8351		- cmp r0, #23
8352		- sub ip, r3, #1728
8353		- movls r0, #24
8354		- sub r1, r3, #1712
8355		- str r0, [r3, #-1740]
8356		- ldrh r2, [ip, #-8]
8357		- ldrh r1, [r1, #-14]
8358		- mul r2, r2, r0
8359		- rsb r0, r0, r1
8360		- ldr r1, [r3, #-1720]
8361		- strh r0, [ip] @ movhi
	8601	+ ldr r3, .L1484
	8602	+ cmp r0, #24
	8603	+ movcc r0, #24
	8604	+ sub r2, r3, #1728
	8605	+ sub ip, r3, #1712
	8606	+ ldrh r2, [r2, #-4]
	8607	+ ldrh r1, [ip, #-10]
	8608	+ str r0, [r3, #-1736]
	8609	+ mul r2, r0, r2
	8610	+ sub r0, r1, r0
	8611	+ ldr r1, [r3, #-1716]
	8612	+ strh r0, [ip, #-12] @ movhi
8362	8613	mov r0, #0
8363		- str r2, [r3, #-1732]
8364		- rsb r2, r2, r1
8365		- str r2, [r3, #-1724]
	8614	+ str r2, [r3, #-1728]
	8615	+ sub r2, r1, r2
	8616	+ str r2, [r3, #-1720]
8366	8617	bx lr
8367		-.L1501:
	8618	+.L1485:
8368	8619	.align 2
8369		-.L1500:
	8620	+.L1484:
8370	8621	.word .LANCHOR2
8371	8622	.fnend
8372	8623	.size FtlSysBlkNumInit, .-FtlSysBlkNumInit
8373	8624	.align 2
8374	8625	.global FtlConstantsInit
	8626	+ .syntax unified
	8627	+ .arm
	8628	+ .fpu softvfp
8375	8629	.type FtlConstantsInit, %function
8376	8630	FtlConstantsInit:
8377	8631	.fnstart
8378		- @ args = 0, pretend = 0, frame = 16
	8632	+ @ args = 0, pretend = 0, frame = 24
8379	8633	@ frame_needed = 0, uses_anonymous_args = 0
8380		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	8634	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
8381	8635	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
8382		- .pad #20
8383		- sub sp, sp, #20
8384		- ldr r4, .L1529
8385		- mov ip, r0
8386		- ldrh r8, [r0, #8]
8387		- mov r10, #0
8388		- ldrh r5, [r0, #10]
8389		- add r3, r4, #4
8390		- ldrh r7, [r0, #12]
8391		- ldrh r6, [r0, #14]
8392		- strh r8, [r4, #-4] @ movhi
8393		- strh r5, [r4, #-2] @ movhi
8394		- strh r7, [r4] @ movhi
8395		- strh r6, [r4, #-14] @ movhi
8396		-.L1503:
8397		- strb r10, [r10, r3]
8398		- add r10, r10, #1
8399		- cmp r10, #32
8400		- bne .L1503
8401		- ldrh r2, [ip, #14]
8402		- ldrh r3, [ip, #20]
8403		- cmp r3, r2, lsr #8
8404		- bcs .L1504
8405		- sub r3, r5, #1
8406		- uxtb r9, r7
8407		- mul r3, r7, r3
8408		- mov fp, r9, asl #1
8409		- uxtb fp, fp
8410		- str r3, [sp, #4]
8411		- mov r3, #0
8412		-.L1505:
8413		- cmp r3, r7
8414		- bcs .L1507
8415		- ldr r1, [sp, #4]
8416		- uxtb r2, r3
8417		- ldr r0, .L1529+4
8418		- add r1, r3, r1
8419		- ldr lr, .L1529+4
8420		- add r1, r0, r1
8421		- str r1, [sp, #8]
8422		- mov r1, #0
8423		- rsb r0, r7, r3
8424		- mov r10, r1
8425		- add r0, lr, r0
8426		- str r0, [sp, #12]
8427		-.L1508:
8428		- cmp r10, r5
8429		- add r1, r1, r7
8430		- bcs .L1528
8431		- ldr r0, [sp, #12]
8432		- add r10, r10, #1
8433		- strb r2, [r0, r1]
8434		- add r0, r2, r9
8435		- add r2, r2, fp
8436		- mov lr, r0
8437		- ldr r0, [sp, #8]
8438		- uxtb r2, r2
8439		- strb lr, [r0, r1]
8440		- b .L1508
8441		-.L1528:
8442		- add r3, r3, #1
8443		- b .L1505
8444		-.L1507:
8445		- mov r5, r5, asl #1
8446		- mov r6, r6, lsr #1
8447		- strh r5, [r4, #-2] @ movhi
8448		- strh r6, [r4, #-14] @ movhi
8449		-.L1504:
8450		- ldr r6, .L1529+8
8451		- cmp r8, #1
8452		- mov r3, #5
8453		- ldrh r9, [ip, #16]
8454		- ldr r5, .L1529+12
8455		- strh r3, [r6, #-12] @ movhi
8456		- mov r3, #0
8457		- streqh r8, [r6, #-12] @ movhi
8458		- sub r10, r5, #1728
8459		- ldrh r8, [r4, #-2]
8460		- strh r3, [r6, #-10] @ movhi
8461		- mov r3, #4352
8462		- strh r3, [r6, #-8] @ movhi
8463		- ldr r3, .L1529+16
8464		- smulbb r8, r8, r7
8465		- ldrh r4, [r4, #-14]
8466		- ldrb fp, [r3] @ zero_extendqisi2
8467		- ldrh r1, [ip, #18]
8468		- cmp fp, #0
8469		- strh r9, [r6, #-4] @ movhi
8470		- smulbb r7, r4, r7
8471		- ldrne r3, .L1529+8
8472		- uxth r8, r8
8473		- movne r2, #384
8474		- strh r1, [r6, #-2] @ movhi
8475		- strneh r2, [r3, #-8] @ movhi
8476		- smulbb r3, r8, r9
8477		- ldrh r2, [ip, #20]
8478		- strh r7, [r6, #-6] @ movhi
8479		- sub r7, r5, #1648
8480		- strh r8, [r10, #-8] @ movhi
8481		- mov r0, r2
8482		- strh r2, [r7, #-14] @ movhi
8483		- str r1, [sp, #12]
8484		- strh r3, [r6] @ movhi
8485		- str ip, [sp, #8]
8486		- str r2, [sp, #4]
8487		- bl Ftl_log2
8488		- cmp r4, #1024
8489		- ldr r2, [sp, #4]
8490		- mov r3, r0
8491		- strh r0, [r7, #-12] @ movhi
8492		- ldr ip, [sp, #8]
8493		- mov r0, r2, asl #9
8494		- ldr r1, [sp, #12]
8495		- str r3, [sp, #4]
8496		- uxth r0, r0
8497		- strh r0, [r7, #-10] @ movhi
8498		- mul r1, r1, r2
8499		- mov r0, r0, lsr #8
8500		- strh r0, [r7, #-8] @ movhi
8501		- ldrh r0, [ip, #26]
8502		- subhi ip, r5, #1664
8503		- strh r0, [r7, #-6] @ movhi
8504		- mul r0, r4, r8
8505		- str r0, [r5, #-1720]
8506		- uxtbhi r0, r4
8507		- strhih r0, [ip, #-10] @ movhi
8508		- ldrh r0, [r6, #-10]
8509		- rsb r0, r0, r4
8510		- mov r4, r4, asl #6
8511		- mul r0, r0, r8
8512		- mul r0, r2, r0
8513		- mul r9, r9, r0
8514		- ldrh r0, [r6, #-8]
8515		- mov r0, r0, asl #3
8516		- mov r9, r9, asr #11
8517		- str r9, [r5, #-1652]
8518		- bl __aeabi_idiv
8519		- mov r1, r8
8520		- uxth r0, r0
8521		- ldr r3, [sp, #4]
8522		- cmp r0, #4
8523		- strhih r0, [r7] @ movhi
8524		- movls r2, #4
8525		- strlsh r2, [r7] @ movhi
8526		- cmp fp, #0
8527		- ldr fp, .L1529+12
8528		- ldrh r0, [r7]
8529		- movne r2, #640
8530		- strneh r2, [r6, #-8] @ movhi
8531		- ldrh r2, [r6, #-8]
8532		- sub r9, fp, #1632
8533		- mov r2, r2, asr r3
8534		- add r3, r3, #9
8535		- mov r4, r4, asr r3
8536		- strh r4, [r9, #-12] @ movhi
8537		- add r2, r2, #2
8538		- strh r2, [r9, #-14] @ movhi
8539		- uxth r4, r4
8540		- mul r3, r8, r4
8541		- add r4, r4, #8
8542		- str r3, [r5, #-1640]
8543		- bl __aeabi_uidiv
8544		- cmp r8, #1
8545		- uxtah r0, r4, r0
8546		- strne r0, [fp, #-1740]
8547		- addeq r4, r0, #4
8548		- streq r4, [fp, #-1740]
8549		- ldr r3, [r5, #-1740]
8550		- ldr r4, .L1529+12
8551		- uxth r0, r3
8552		- sub fp, r4, #1648
8553		- bl FtlSysBlkNumInit
8554		- ldr r3, [r5, #-1740]
8555		- ldr r2, [r5, #-1724]
8556		- mov r0, #2048
8557		- ldrh r8, [r7, #-12]
8558		- str r3, [r5, #-1636]
8559		- ldrh r3, [r6, #-4]
8560		- mov r2, r2, asl #2
8561		- add r8, r8, #9
8562		- ldrh r6, [r7, #-14]
8563		- mul r3, r3, r2
8564		- mov r1, r6
8565		- mov r8, r3, lsr r8
8566		- add r8, r8, #2
8567		- uxth r8, r8
8568		- strh r8, [r9] @ movhi
8569		- bl __aeabi_idiv
8570		- mov r3, #0
8571		- ldrb r1, [r5, #-2744] @ zero_extendqisi2
8572		- sub r9, r4, #1616
8573		- str r3, [r5, #-2740]
8574		- ldrh r3, [r7]
8575		- cmp r1, #0
8576		- add r2, r3, #3
8577		- strh r2, [r7] @ movhi
8578		- ldr r7, [r5, #-1640]
8579		- add r2, r7, #3
8580		- str r2, [r5, #-1640]
8581		- strh r0, [r9, #-14] @ movhi
8582		- addne r3, r3, #4
8583		- addne r7, r7, #5
8584		- strneh r3, [fp] @ movhi
8585		- strne r7, [r4, #-1640]
8586		- bne .L1518
8587		-.L1517:
8588		- cmp r2, #7
8589		- movls r3, #8
8590		- strls r3, [r4, #-1640]
8591		-.L1518:
8592		- ldrh r2, [r10]
8593		- mov r3, #0
8594		- strh r3, [r9, #-12] @ movhi
	8636	+ .pad #28
	8637	+ sub sp, sp, #28
	8638	+ ldr ip, .L1514
	8639	+ mov r9, r0
	8640	+ ldrh r4, [r0, #14]
	8641	+ ldrh r5, [r0, #8]
	8642	+ mov r2, ip
	8643	+ ldrh r1, [r0, #10]
	8644	+ ldrh r3, [r0, #12]
8595	8645	mov r0, #0
8596		- mov r3, r2, lsr #3
8597		- add r3, r3, r2, asl #1
	8646	+ strh r4, [ip, #-10] @ movhi
	8647	+ str ip, [sp, #4]
	8648	+ add ip, ip, #6
	8649	+ strh r5, [r2], #16 @ movhi
	8650	+ strh r1, [r2, #-14] @ movhi
	8651	+ strh r3, [r2, #-12] @ movhi
	8652	+ str r2, [sp, #8]
	8653	+.L1487:
	8654	+ strb r0, [r0, ip]
	8655	+ add r0, r0, #1
	8656	+ cmp r0, #32
	8657	+ bne .L1487
	8658	+ ldrh ip, [r9, #14]
	8659	+ ldrh r0, [r9, #20]
	8660	+ cmp r0, ip, lsr #8
	8661	+ bcs .L1488
	8662	+ uxtb r8, r3
	8663	+ ldr r7, .L1514+4
	8664	+ lsl r0, r8, #1
	8665	+ uxtb r0, r0
	8666	+ str r0, [sp, #12]
	8667	+ sub r0, r1, #1
	8668	+ mul r0, r3, r0
	8669	+ str r0, [sp, #20]
	8670	+ mov r0, #0
	8671	+.L1489:
	8672	+ cmp r0, r3
	8673	+ bcs .L1491
	8674	+ ldr r2, [sp, #20]
	8675	+ sub fp, r0, r3
	8676	+ uxtb ip, r0
	8677	+ add fp, r7, fp
	8678	+ add lr, r0, r2
	8679	+ add r2, r7, lr
	8680	+ mov lr, #0
	8681	+ str r2, [sp, #16]
	8682	+ mov r6, lr
	8683	+ b .L1492
	8684	+.L1490:
	8685	+ ldr r2, [sp, #16]
	8686	+ add r10, r8, ip
	8687	+ strb ip, [fp, lr]
	8688	+ add r6, r6, #1
	8689	+ strb r10, [r2, lr]
	8690	+ ldr r2, [sp, #12]
	8691	+ add ip, r2, ip
	8692	+ uxtb ip, ip
	8693	+.L1492:
	8694	+ cmp r6, r1
	8695	+ add lr, lr, r3
	8696	+ bcc .L1490
	8697	+ add r0, r0, #1
	8698	+ b .L1489
	8699	+.L1491:
	8700	+ ldr r2, [sp, #8]
	8701	+ lsl r1, r1, #1
	8702	+ lsr r4, r4, #1
	8703	+ strh r1, [r2, #-14] @ movhi
	8704	+ ldr r2, [sp, #4]
	8705	+ strh r4, [r2, #-10] @ movhi
	8706	+.L1488:
	8707	+ ldr r2, [sp, #8]
	8708	+ cmp r5, #1
	8709	+ ldr r1, .L1514+8
	8710	+ mov r0, #5
	8711	+ ldrh r10, [r9, #16]
	8712	+ ldrh r7, [r2, #-14]
	8713	+ strh r0, [r1, #-10] @ movhi
	8714	+ mov r0, #0
	8715	+ strheq r5, [r1, #-10] @ movhi
	8716	+ ldr r5, .L1514+12
	8717	+ smulbb r7, r7, r3
	8718	+ strh r0, [r1, #-8] @ movhi
	8719	+ mov r0, #4352
	8720	+ sub r2, r5, #1728
	8721	+ strh r0, [r1, #-6] @ movhi
	8722	+ uxth r7, r7
	8723	+ ldr r0, .L1514+16
	8724	+ sub r6, r5, #1664
	8725	+ strh r7, [r2, #-4] @ movhi
	8726	+ sub r8, r5, #1648
	8727	+ ldr r2, [sp, #4]
	8728	+ ldrb fp, [r0, #36] @ zero_extendqisi2
	8729	+ strh r10, [r6, #-2] @ movhi
	8730	+ ldrh r4, [r2, #-10]
	8731	+ cmp fp, #0
	8732	+ ldrh r2, [r9, #20]
	8733	+ movne r0, #384
	8734	+ strhne r0, [r1, #-6] @ movhi
	8735	+ smulbb r3, r3, r4
	8736	+ ldrh r1, [r9, #18]
	8737	+ mov r0, r2
	8738	+ strh r2, [r8, #-12] @ movhi
	8739	+ str r2, [sp, #8]
	8740	+ strh r3, [r6, #-4] @ movhi
	8741	+ smulbb r3, r7, r10
	8742	+ strh r1, [r6] @ movhi
	8743	+ str r1, [sp, #12]
	8744	+ strh r3, [r8, #-14] @ movhi
	8745	+ bl Ftl_log2
	8746	+ ldr r2, [sp, #8]
	8747	+ mov r3, r0
	8748	+ strh r0, [r8, #-10] @ movhi
	8749	+ cmp r4, #1024
	8750	+ ldr r1, [sp, #12]
	8751	+ str r3, [sp, #8]
	8752	+ lsl r0, r2, #9
	8753	+ uxth r0, r0
	8754	+ mul r1, r2, r1
	8755	+ strh r0, [r8, #-8] @ movhi
	8756	+ lsr r0, r0, #8
	8757	+ strh r0, [r8, #-6] @ movhi
	8758	+ ldrh r0, [r9, #26]
	8759	+ ldr r9, .L1514+20
	8760	+ strh r0, [r8, #-4] @ movhi
	8761	+ mul r0, r4, r7
	8762	+ str r0, [r5, #-1716]
	8763	+ uxtbhi r0, r4
	8764	+ strhhi r0, [r6, #-8] @ movhi
	8765	+ ldrh r0, [r6, #-8]
	8766	+ sub r0, r4, r0
	8767	+ lsl r4, r4, #6
	8768	+ mul r0, r7, r0
	8769	+ mul r0, r2, r0
	8770	+ mul r10, r10, r0
	8771	+ ldrh r0, [r6, #-6]
	8772	+ asr r10, r10, #11
	8773	+ lsl r0, r0, #3
	8774	+ str r10, [r5, #-1648]
	8775	+ bl __aeabi_idiv
	8776	+ uxth r0, r0
	8777	+ ldr r3, [sp, #8]
	8778	+ mov r1, r7
	8779	+ cmp r0, #4
	8780	+ movls r2, #4
	8781	+ strhhi r0, [r9, #-12] @ movhi
	8782	+ strhls r2, [r9, #-12] @ movhi
	8783	+ cmp fp, #0
	8784	+ movne r2, #640
	8785	+ ldrh r0, [r9, #-12]
	8786	+ strhne r2, [r6, #-6] @ movhi
	8787	+ ldrh r2, [r6, #-6]
	8788	+ asr r2, r2, r3
	8789	+ add r3, r3, #9
	8790	+ asr r4, r4, r3
	8791	+ add r2, r2, #2
	8792	+ strh r4, [r9, #-8] @ movhi
	8793	+ uxth r4, r4
	8794	+ strh r2, [r9, #-10] @ movhi
	8795	+ mul r3, r4, r7
	8796	+ add r4, r4, #8
	8797	+ str r3, [r5, #-1636]
	8798	+ bl __aeabi_uidiv
	8799	+ uxtah r0, r4, r0
	8800	+ cmp r7, #1
	8801	+ sub r3, r5, #1728
	8802	+ ldr r7, .L1514+24
	8803	+ addeq r0, r0, #4
	8804	+ sub r3, r3, #8
	8805	+ str r0, [r5, #-1736]
	8806	+ ldrh r0, [r3]
	8807	+ bl FtlSysBlkNumInit
	8808	+ ldr r4, [r5, #-1720]
	8809	+ mov r0, #2048
	8810	+ ldr r3, [r5, #-1736]
	8811	+ str r3, [r5, #-1632]
	8812	+ lsl r3, r4, #2
	8813	+ ldrh r4, [r6, #-2]
	8814	+ ldrh r6, [r8, #-12]
	8815	+ mul r4, r4, r3
	8816	+ ldrh r3, [r8, #-10]
	8817	+ mov r1, r6
	8818	+ add r3, r3, #9
	8819	+ lsr r4, r4, r3
	8820	+ add r4, r4, #2
	8821	+ uxth r4, r4
	8822	+ strh r4, [r7, #-12] @ movhi
	8823	+ bl __aeabi_idiv
	8824	+ ldrh r2, [r9, #-12]
	8825	+ mov r3, #0
	8826	+ strh r0, [r7, #-10] @ movhi
	8827	+ str r3, [r5, #-2736]
	8828	+ ldrb r0, [r5, #-2740] @ zero_extendqisi2
	8829	+ add r3, r2, #3
	8830	+ strh r3, [r9, #-12] @ movhi
	8831	+ ldr r3, [r5, #-1636]
	8832	+ cmp r0, #0
	8833	+ addne r2, r2, #4
	8834	+ add r1, r3, #3
	8835	+ strhne r2, [r9, #-12] @ movhi
	8836	+ str r1, [r5, #-1636]
	8837	+ addne r3, r3, #5
	8838	+ bne .L1513
	8839	+ cmp r1, #7
	8840	+ bhi .L1502
	8841	+ mov r3, #8
	8842	+.L1513:
	8843	+ str r3, [r5, #-1636]
	8844	+.L1502:
	8845	+ mov r3, #0
	8846	+ mov r0, #0
	8847	+ strh r3, [r7, #-8] @ movhi
	8848	+ ldr r3, [sp, #4]
	8849	+ ldrh r2, [r3, #-12]
	8850	+ lsr r3, r2, #3
	8851	+ add r3, r3, r2, lsl #1
8598	8852	add r3, r3, #52
8599		- add r8, r3, r8, asl #2
8600		- cmp r8, r6, asl #9
8601		- ldrcc r3, .L1529+20
8602		- movcc r2, #1
8603		- strcch r2, [r3, #-12] @ movhi
8604		- add sp, sp, #20
	8853	+ add r4, r3, r4, lsl #2
	8854	+ cmp r4, r6, lsl #9
	8855	+ movcc r3, #1
	8856	+ strhcc r3, [r7, #-8] @ movhi
	8857	+ add sp, sp, #28
8605	8858	@ sp needed
8606		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
8607		-.L1530:
	8859	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	8860	+.L1515:
8608	8861	.align 2
8609		-.L1529:
	8862	+.L1514:
8610	8863	.word .LANCHOR2-1712
8611		- .word .LANCHOR2-1708
	8864	+ .word .LANCHOR2-1706
8612	8865	.word .LANCHOR2-1664
8613	8866	.word .LANCHOR2
8614	8867	.word .LANCHOR0
	8868	+ .word .LANCHOR2-1632
8615	8869	.word .LANCHOR2-1616
8616	8870	.fnend
8617	8871	.size FtlConstantsInit, .-FtlConstantsInit
8618	8872	.align 2
8619	8873	.global FtlMemInit
	8874	+ .syntax unified
	8875	+ .arm
	8876	+ .fpu softvfp
8620	8877	.type FtlMemInit, %function
8621	8878	FtlMemInit:
8622	8879	.fnstart
8623		- @ args = 0, pretend = 0, frame = 8
	8880	+ @ args = 0, pretend = 0, frame = 0
8624	8881	@ frame_needed = 0, uses_anonymous_args = 0
8625		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
8626		- .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
8627		- .pad #12
	8882	+ push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	8883	+ .save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
8628	8884	movw r3, #65535
8629		- ldr r4, .L1636
	8885	+ ldr r4, .L1619
	8886	+ mvn r2, #0
8630	8887	mov r5, #0
8631	8888	mov r0, #1024
8632		- mov r10, #12
8633		- sub r6, r4, #1520
8634		- sub r2, r4, #1536
8635		- sub r8, r4, #1616
8636		- str r3, [r4, #-1556]
8637		- strh r5, [r6, #-8] @ movhi
8638		- mvn r3, #0
8639		- strh r5, [r6, #-6] @ movhi
8640		- sub r9, r4, #1728
8641		- strh r3, [r2, #-4] @ movhi
8642		- strh r3, [r2, #-2] @ movhi
8643		- strh r3, [r2] @ movhi
8644		- strh r3, [r6, #-14] @ movhi
8645		- mov r3, #32
8646		- strh r5, [r6, #-4] @ movhi
8647		- strh r3, [r6, #-12] @ movhi
8648		- mov r3, #128
8649		- strh r5, [r6, #-2] @ movhi
8650		- strh r3, [r6, #-10] @ movhi
	8889	+ mov r8, #12
	8890	+ mov r10, #36
	8891	+ str r3, [r4, #-1552]
	8892	+ sub r3, r4, #1536
	8893	+ strh r2, [r3] @ movhi
	8894	+ sub r3, r4, #1520
	8895	+ strh r2, [r3, #-14] @ movhi
8651	8896	sub r6, r4, #1648
8652		- strh r5, [r8, #-10] @ movhi
8653		- str r5, [r4, #-1624]
	8897	+ strh r2, [r3, #-12] @ movhi
	8898	+ sub r7, r4, #1616
	8899	+ strh r2, [r3, #-10] @ movhi
	8900	+ mov r2, #32
	8901	+ strh r2, [r3, #-8] @ movhi
	8902	+ mov r2, #128
	8903	+ strh r2, [r3, #-6] @ movhi
	8904	+ sub r9, r4, #1728
	8905	+ strh r5, [r3, #-4] @ movhi
	8906	+ strh r5, [r3, #-2] @ movhi
	8907	+ strh r5, [r3] @ movhi
	8908	+ sub r3, r4, #1504
	8909	+ strh r5, [r7, #-6] @ movhi
8654	8910	str r5, [r4, #-1620]
8655	8911	str r5, [r4, #-1616]
8656	8912	str r5, [r4, #-1612]
..	..	@@ -8667,574 +8923,599 @@
8667	8923	str r5, [r4, #-1568]
8668	8924	str r5, [r4, #-1564]
8669	8925	str r5, [r4, #-1560]
8670		- str r5, [r4, #-1552]
	8926	+ str r5, [r4, #-1556]
8671	8927	str r5, [r4, #-1548]
8672	8928	str r5, [r4, #-1544]
8673		- ldrh r1, [r6, #-14]
	8929	+ str r5, [r4, #-1540]
	8930	+ strh r5, [r3, #-14] @ movhi
	8931	+ ldrh r1, [r6, #-12]
8674	8932	bl __aeabi_idiv
8675		- ldrh r7, [r9, #-8]
8676		- str r5, [r4, #-1516]
8677		- ldr r5, .L1636+4
8678		- mov r7, r7, asl #2
8679		- cmp r0, r7
8680		- str r0, [r4, #-1520]
8681		- ldrh r0, [r5]
8682		- strhi r7, [r4, #-1520]
8683		- mov r7, r5
8684		- mov r0, r0, asl #1
	8933	+ ldrh r3, [r9, #-4]
	8934	+ str r0, [r4, #-1516]
	8935	+ str r5, [r4, #-1512]
	8936	+ lsl r3, r3, #2
	8937	+ cmp r0, r3
	8938	+ ldrh r0, [r6, #-14]
	8939	+ strhi r3, [r4, #-1516]
	8940	+ lsl r0, r0, #1
8685	8941	bl ftl_malloc
8686		- str r0, [r4, #-1512]
8687		- ldrh r0, [r7], #-48
8688		- mul r0, r10, r0
8689		- bl ftl_malloc
8690		- ldrh fp, [r9, #-8]
8691		- mov r3, #36
8692		- mul fp, r3, fp
8693		- mov r2, fp, asl #3
8694	8942	str r0, [r4, #-1508]
8695		- mov r0, r2
8696		- str r3, [sp, #4]
8697		- str r2, [sp]
	8943	+ ldrh r0, [r6, #-14]
	8944	+ mul r0, r8, r0
8698	8945	bl ftl_malloc
	8946	+ ldrh r5, [r9, #-4]
8699	8947	str r0, [r4, #-1504]
	8948	+ mul r5, r10, r5
	8949	+ lsl fp, r5, #3
8700	8950	mov r0, fp
8701	8951	bl ftl_malloc
8702		- ldr r2, [sp]
8703	8952	str r0, [r4, #-1500]
8704		- mov r0, r2
	8953	+ mov r0, r5
8705	8954	bl ftl_malloc
8706	8955	str r0, [r4, #-1496]
8707	8956	mov r0, fp
8708	8957	bl ftl_malloc
8709	8958	str r0, [r4, #-1492]
8710		- mov r0, fp
	8959	+ mov r0, r5
8711	8960	bl ftl_malloc
8712		- ldr r3, [sp, #4]
8713	8961	str r0, [r4, #-1488]
8714		- ldr r0, [r4, #-1520]
8715		- mul r0, r3, r0
	8962	+ mov r0, r5
8716	8963	bl ftl_malloc
8717		- ldrh fp, [r6, #-10]
8718		- ldrh r3, [r9, #-8]
8719		- mov r3, r3, asl #1
8720		- add r3, r3, #1
8721		- str r3, [r4, #-1480]
8722	8964	str r0, [r4, #-1484]
8723		- mov r0, fp
8724		- bl ftl_malloc
8725		- str r0, [r4, #-1476]
8726		- mov r0, fp
8727		- bl ftl_malloc
8728		- str r0, [r4, #-1472]
8729		- mov r0, fp
8730		- bl ftl_malloc
8731		- str r0, [r4, #-1468]
8732		- ldr r0, [r4, #-1480]
8733		- mul r0, r0, fp
8734		- bl ftl_malloc
8735		- str r0, [r4, #-1464]
8736		- ldr r0, [r4, #-1520]
8737		- mul r0, r0, fp
8738		- bl ftl_malloc
8739		- str r0, [r4, #-1460]
8740		- mov r0, fp
8741		- bl ftl_malloc
8742		- str r0, [r4, #-1456]
8743		- mov r0, fp
8744		- bl ftl_malloc
8745		- str r0, [r4, #-1452]
8746		- ldr r0, [r4, #-1480]
	8965	+ ldr r0, [r4, #-1516]
8747	8966	mul r0, r10, r0
8748	8967	bl ftl_malloc
8749		- ldrh r3, [r6, #-8]
8750		- ldrh r9, [r9, #-8]
8751		- mul r9, r9, r3
	8968	+ ldrh r3, [r9, #-4]
	8969	+ ldrh r5, [r6, #-8]
	8970	+ str r0, [r4, #-1480]
	8971	+ lsl r3, r3, #1
	8972	+ mov r0, r5
	8973	+ add r3, r3, #1
	8974	+ str r3, [r4, #-1476]
	8975	+ bl ftl_malloc
	8976	+ str r0, [r4, #-1472]
	8977	+ mov r0, r5
	8978	+ bl ftl_malloc
	8979	+ str r0, [r4, #-1468]
	8980	+ mov r0, r5
	8981	+ bl ftl_malloc
	8982	+ str r0, [r4, #-1464]
	8983	+ ldr r0, [r4, #-1476]
	8984	+ mul r0, r0, r5
	8985	+ bl ftl_malloc
	8986	+ str r0, [r4, #-1460]
	8987	+ ldr r0, [r4, #-1516]
	8988	+ mul r0, r0, r5
	8989	+ bl ftl_malloc
	8990	+ str r0, [r4, #-1456]
	8991	+ mov r0, r5
	8992	+ bl ftl_malloc
	8993	+ str r0, [r4, #-1452]
	8994	+ mov r0, r5
	8995	+ bl ftl_malloc
8752	8996	str r0, [r4, #-1448]
8753		- mov r0, r9
	8997	+ ldr r0, [r4, #-1476]
	8998	+ mul r0, r8, r0
8754	8999	bl ftl_malloc
	9000	+ ldrh r3, [r6, #-6]
	9001	+ ldrh r5, [r9, #-4]
8755	9002	str r0, [r4, #-1444]
8756		- mov r0, r9, asl #3
	9003	+ mul r5, r5, r3
	9004	+ mov r0, r5
8757	9005	bl ftl_malloc
8758		- ldrh r3, [r6, #-8]
8759	9006	str r0, [r4, #-1440]
8760		- ldr r0, [r4, #-1480]
8761		- mul r0, r0, r3
	9007	+ lsl r0, r5, #3
	9008	+ ldr r5, .L1619+4
8762	9009	bl ftl_malloc
8763		- ldrh r3, [r6, #-8]
	9010	+ ldrh r3, [r6, #-6]
8764	9011	str r0, [r4, #-1436]
8765		- ldr r0, [r4, #-1520]
	9012	+ add r9, r5, #288
	9013	+ ldr r0, [r4, #-1476]
8766	9014	mul r0, r0, r3
8767	9015	bl ftl_malloc
	9016	+ ldrh r3, [r6, #-6]
8768	9017	str r0, [r4, #-1432]
8769		- ldrh r0, [r7, #-14]
8770		- mov r0, r0, asl #1
8771		- uxth r0, r0
8772		- strh r0, [r5, #236] @ movhi
	9018	+ ldr r0, [r4, #-1516]
	9019	+ mul r0, r0, r3
8773	9020	bl ftl_malloc
8774		- str r0, [r4, #-1424]
8775		- ldrh r0, [r5, #236]
	9021	+ str r0, [r4, #-1428]
	9022	+ ldrh r0, [r5, #-10]
	9023	+ lsl r0, r0, #1
	9024	+ uxth r0, r0
	9025	+ strh r0, [r9] @ movhi
	9026	+ bl ftl_malloc
	9027	+ str r0, [r4, #-1420]
	9028	+ ldrh r0, [r9]
	9029	+ ldr r3, .L1619+8
8776	9030	add r0, r0, #544
8777	9031	add r0, r0, #3
8778		- mov r0, r0, lsr #9
8779		- strh r0, [r5, #236] @ movhi
8780		- mov r0, r0, asl #9
	9032	+ lsr r0, r0, #9
	9033	+ strh r0, [r9] @ movhi
	9034	+ and r0, r3, r0, lsl #9
8781	9035	bl ftl_malloc
8782		- ldrh r9, [r7, #-14]
8783		- mov r9, r9, asl #1
8784		- str r0, [r4, #-1420]
8785		- add r0, r0, #32
	9036	+ ldrh r9, [r5, #-10]
8786	9037	str r0, [r4, #-1416]
8787		- mov r0, r9
8788		- bl ftl_malloc
	9038	+ add r0, r0, #32
8789	9039	str r0, [r4, #-1412]
	9040	+ lsl r9, r9, #1
8790	9041	mov r0, r9
8791	9042	bl ftl_malloc
8792		- ldr r9, [r4, #-1640]
8793		- mov r9, r9, asl #1
8794	9043	str r0, [r4, #-1408]
8795	9044	mov r0, r9
8796	9045	bl ftl_malloc
	9046	+ ldr r9, [r4, #-1636]
8797	9047	str r0, [r4, #-1404]
	9048	+ lsl r9, r9, #1
8798	9049	mov r0, r9
8799	9050	bl ftl_malloc
8800	9051	str r0, [r4, #-1400]
8801		- ldrh r0, [r7, #-14]
8802		- mov r0, r0, lsr #3
8803		- add r0, r0, #4
	9052	+ mov r0, r9
8804	9053	bl ftl_malloc
8805	9054	str r0, [r4, #-1396]
8806		- ldrh r0, [r6]
8807		- mov r0, r0, asl #1
	9055	+ ldrh r0, [r5, #-10]
	9056	+ lsr r0, r0, #3
	9057	+ add r0, r0, #4
	9058	+ bl ftl_malloc
	9059	+ ldr r3, .L1619+12
	9060	+ str r0, [r3, #32]
	9061	+ ldrh r0, [r5, #68]
	9062	+ lsl r0, r0, #1
8808	9063	bl ftl_malloc
8809	9064	str r0, [r4, #-1392]
8810		- ldrh r0, [r6]
8811		- mov r0, r0, asl #1
	9065	+ ldrh r0, [r5, #68]
	9066	+ lsl r0, r0, #1
8812	9067	bl ftl_malloc
8813	9068	str r0, [r4, #-1388]
8814		- ldrh r0, [r6]
8815		- mov r0, r0, asl #2
	9069	+ ldrh r0, [r5, #68]
	9070	+ lsl r0, r0, #2
8816	9071	bl ftl_malloc
8817	9072	str r0, [r4, #-1384]
8818		- ldrh r0, [r5, #18]
8819		- mov r0, r0, asl #2
	9073	+ ldrh r0, [r5, #70]
	9074	+ lsl r0, r0, #2
8820	9075	bl ftl_malloc
8821		- ldrh r2, [r5, #18]
	9076	+ ldrh r2, [r5, #70]
8822	9077	mov r1, #0
8823		- mov r2, r2, asl #2
8824	9078	str r0, [r4, #-1380]
	9079	+ lsl r2, r2, #2
8825	9080	bl ftl_memset
8826		- ldrh r9, [r5, #32]
8827		- mov r9, r9, asl #2
	9081	+ ldrh r9, [r7, #-12]
	9082	+ lsl r9, r9, #2
8828	9083	mov r0, r9
8829	9084	bl ftl_malloc
8830	9085	str r0, [r4, #-1376]
8831	9086	mov r0, r9
8832	9087	bl ftl_malloc
8833	9088	str r0, [r4, #-1372]
8834		- ldr r0, [r4, #-1640]
8835		- mov r0, r0, asl #2
	9089	+ ldr r0, [r4, #-1636]
	9090	+ lsl r0, r0, #2
8836	9091	bl ftl_malloc
8837	9092	str r0, [r4, #-1368]
8838		- ldrh r0, [r8, #-14]
8839		- mul r0, r10, r0
	9093	+ ldrh r0, [r7, #-10]
	9094	+ mul r0, r8, r0
8840	9095	bl ftl_malloc
8841		- ldrh r3, [r8, #-14]
	9096	+ ldrh r3, [r7, #-10]
	9097	+ add r7, r5, #16
8842	9098	str r0, [r4, #-1364]
8843		- ldrh r0, [r6, #-10]
8844		- add r6, r5, #320
	9099	+ ldrh r0, [r6, #-8]
	9100	+ add r6, r5, #368
8845	9101	mul r0, r0, r3
8846	9102	bl ftl_malloc
8847		- ldrh r3, [r7, #-14]
	9103	+ ldrh r3, [r5, #-10]
8848	9104	str r0, [r4, #-1360]
8849	9105	mov r0, #6
8850	9106	mul r0, r0, r3
8851	9107	bl ftl_malloc
8852		- ldrh r3, [r5, #-6]
8853		- add r5, r5, #344
8854		- add r3, r3, #31
8855		- mov r3, r3, asr #5
8856		- strh r3, [r6, #-8] @ movhi
8857	9108	str r0, [r4, #-1356]
8858		- ldrh r0, [r7, #-2]
	9109	+ ldrh r0, [r5, #44]
	9110	+ ldrh r3, [r5, #2]
	9111	+ add r0, r0, #31
	9112	+ asr r0, r0, #5
	9113	+ strh r0, [r6, #-8] @ movhi
8859	9114	mul r0, r0, r3
8860		- mov r0, r0, asl #2
	9115	+ lsl r0, r0, #2
8861	9116	bl ftl_malloc
8862	9117	ldrh r2, [r6, #-8]
8863		- ldrh ip, [r7, #-2]
8864	9118	mov r3, #1
8865		- mov r2, r2, asl #2
8866		- mov r1, r2
	9119	+ ldrh ip, [r5, #2]
	9120	+ add r5, r5, #392
8867	9121	str r0, [r4, #-1320]
8868		-.L1533:
	9122	+ lsl r2, r2, #2
	9123	+ mov r1, r2
	9124	+.L1518:
8869	9125	cmp r3, ip
8870		- bcs .L1634
	9126	+ bcc .L1519
	9127	+ add r3, r6, r3, lsl #2
	9128	+ mov r2, #0
	9129	+ add r6, r6, #52
	9130	+ add r3, r3, #20
	9131	+.L1520:
	9132	+ cmp r6, r3
	9133	+ bne .L1521
	9134	+ ldr r3, [r4, #-1400]
	9135	+ cmp r3, #0
	9136	+ bne .L1522
	9137	+.L1524:
	9138	+ ldr r1, .L1619+16
	9139	+ ldr r0, .L1619+20
	9140	+ bl printk
	9141	+ mvn r0, #0
	9142	+ pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
	9143	+.L1519:
8871	9144	ldr r0, [r4, #-1320]
8872	9145	add r3, r3, #1
8873	9146	add r0, r0, r1
8874	9147	add r1, r1, r2
8875	9148	str r0, [r5, #4]!
8876		- b .L1533
8877		-.L1634:
8878		- ldr r2, .L1636+8
8879		- mov r1, #0
8880		-.L1535:
8881		- cmp r3, #8
8882		- addne r0, r2, r3, asl #2
8883		- addne r3, r3, #1
8884		- strne r1, [r0, #28]
8885		- bne .L1535
8886		-.L1635:
8887		- ldr r2, [r4, #-1404]
8888		- ldr r3, .L1636
8889		- cmp r2, #0
8890		- bne .L1537
8891		-.L1539:
8892		- ldr r0, .L1636+12
8893		- ldr r1, .L1636+16
8894		- bl printk
8895		- mvn r0, #0
8896		- b .L1538
8897		-.L1537:
8898		- ldr r2, [r3, #-1400]
8899		- cmp r2, #0
8900		- beq .L1539
8901		- ldr r2, [r3, #-1376]
8902		- cmp r2, #0
8903		- beq .L1539
8904		- ldr r2, [r3, #-1368]
8905		- cmp r2, #0
8906		- beq .L1539
8907		- ldr r2, [r3, #-1364]
8908		- cmp r2, #0
8909		- beq .L1539
8910		- ldr r2, [r3, #-1360]
8911		- cmp r2, #0
8912		- beq .L1539
8913		- ldr r2, [r3, #-1356]
8914		- cmp r2, #0
8915		- beq .L1539
8916		- ldr r2, [r3, #-1320]
8917		- cmp r2, #0
8918		- beq .L1539
8919		- ldr r3, [r3, #-1408]
	9149	+ b .L1518
	9150	+.L1521:
	9151	+ str r2, [r3, #4]!
	9152	+ b .L1520
	9153	+.L1522:
	9154	+ ldr r3, [r4, #-1396]
8920	9155	cmp r3, #0
8921		- beq .L1539
8922		- ldr r2, [r4, #-1512]
8923		- ldr r3, .L1636
8924		- cmp r2, #0
8925		- beq .L1539
8926		- ldr r2, [r3, #-1508]
8927		- cmp r2, #0
8928		- beq .L1539
8929		- ldr r2, [r3, #-1504]
8930		- cmp r2, #0
8931		- beq .L1539
8932		- ldr r2, [r3, #-1496]
8933		- cmp r2, #0
8934		- beq .L1539
8935		- ldr r2, [r3, #-1492]
8936		- cmp r2, #0
8937		- beq .L1539
8938		- ldr r2, [r3, #-1488]
8939		- cmp r2, #0
8940		- beq .L1539
8941		- ldr r2, [r3, #-1500]
8942		- cmp r2, #0
8943		- beq .L1539
8944		- ldr r2, [r3, #-1476]
8945		- cmp r2, #0
8946		- beq .L1539
8947		- ldr r2, [r3, #-1472]
8948		- cmp r2, #0
8949		- beq .L1539
8950		- ldr r3, [r3, #-1468]
	9156	+ beq .L1524
	9157	+ ldr r3, [r4, #-1376]
8951	9158	cmp r3, #0
8952		- beq .L1539
8953		- ldr r2, [r4, #-1464]
8954		- ldr r3, .L1636
8955		- cmp r2, #0
8956		- beq .L1539
8957		- ldr r2, [r3, #-1456]
8958		- cmp r2, #0
8959		- beq .L1539
8960		- ldr r2, [r3, #-1452]
8961		- cmp r2, #0
8962		- beq .L1539
8963		- ldr r2, [r3, #-1448]
8964		- cmp r2, #0
8965		- beq .L1539
8966		- ldr r2, [r3, #-1444]
8967		- cmp r2, #0
8968		- beq .L1539
8969		- ldr r2, [r3, #-1440]
8970		- cmp r2, #0
8971		- beq .L1539
8972		- ldr r2, [r3, #-1436]
8973		- cmp r2, #0
8974		- beq .L1539
8975		- ldr r2, [r3, #-1416]
8976		- cmp r2, #0
8977		- beq .L1539
8978		- ldr r2, [r3, #-1424]
8979		- cmp r2, #0
8980		- beq .L1539
8981		- ldr r3, [r3, #-1392]
	9159	+ beq .L1524
	9160	+ ldr r3, [r4, #-1368]
8982	9161	cmp r3, #0
8983		- beq .L1539
8984		- ldr r3, .L1636
	9162	+ beq .L1524
	9163	+ ldr r3, [r4, #-1364]
	9164	+ cmp r3, #0
	9165	+ beq .L1524
	9166	+ ldr r3, [r4, #-1360]
	9167	+ cmp r3, #0
	9168	+ beq .L1524
	9169	+ ldr r3, [r4, #-1356]
	9170	+ cmp r3, #0
	9171	+ beq .L1524
	9172	+ ldr r3, [r4, #-1320]
	9173	+ cmp r3, #0
	9174	+ beq .L1524
	9175	+ ldr r3, [r4, #-1404]
	9176	+ cmp r3, #0
	9177	+ beq .L1524
	9178	+ ldr r3, [r4, #-1508]
	9179	+ cmp r3, #0
	9180	+ beq .L1524
	9181	+ ldr r3, [r4, #-1504]
	9182	+ cmp r3, #0
	9183	+ beq .L1524
	9184	+ ldr r3, [r4, #-1500]
	9185	+ cmp r3, #0
	9186	+ beq .L1524
	9187	+ ldr r3, [r4, #-1492]
	9188	+ cmp r3, #0
	9189	+ beq .L1524
	9190	+ ldr r3, [r4, #-1488]
	9191	+ cmp r3, #0
	9192	+ beq .L1524
	9193	+ ldr r3, [r4, #-1484]
	9194	+ cmp r3, #0
	9195	+ beq .L1524
	9196	+ ldr r3, [r4, #-1496]
	9197	+ cmp r3, #0
	9198	+ beq .L1524
	9199	+ ldr r3, [r4, #-1472]
	9200	+ cmp r3, #0
	9201	+ beq .L1524
	9202	+ ldr r3, [r4, #-1468]
	9203	+ cmp r3, #0
	9204	+ beq .L1524
	9205	+ ldr r3, [r4, #-1464]
	9206	+ cmp r3, #0
	9207	+ beq .L1524
	9208	+ ldr r3, [r4, #-1460]
	9209	+ cmp r3, #0
	9210	+ beq .L1524
	9211	+ ldr r3, [r4, #-1452]
	9212	+ cmp r3, #0
	9213	+ beq .L1524
	9214	+ ldr r3, [r4, #-1448]
	9215	+ cmp r3, #0
	9216	+ beq .L1524
	9217	+ ldr r3, [r4, #-1444]
	9218	+ cmp r3, #0
	9219	+ beq .L1524
	9220	+ ldr r3, [r4, #-1440]
	9221	+ cmp r3, #0
	9222	+ beq .L1524
	9223	+ ldr r3, [r4, #-1436]
	9224	+ cmp r3, #0
	9225	+ beq .L1524
	9226	+ ldr r3, [r4, #-1432]
	9227	+ cmp r3, #0
	9228	+ beq .L1524
	9229	+ ldr r3, [r4, #-1412]
	9230	+ cmp r3, #0
	9231	+ beq .L1524
	9232	+ ldr r3, [r4, #-1420]
	9233	+ cmp r3, #0
	9234	+ beq .L1524
	9235	+ ldr r3, [r4, #-1392]
	9236	+ cmp r3, #0
	9237	+ beq .L1524
	9238	+ ldr r3, .L1619
8985	9239	ldr r2, [r3, #-1388]
8986	9240	cmp r2, #0
8987		- beq .L1539
	9241	+ beq .L1524
8988	9242	ldr r2, [r3, #-1384]
8989	9243	cmp r2, #0
8990		- beq .L1539
	9244	+ beq .L1524
8991	9245	ldr r3, [r3, #-1380]
8992	9246	cmp r3, #0
8993		- beq .L1539
	9247	+ beq .L1524
8994	9248	mov r0, #0
8995		-.L1538:
8996		- add sp, sp, #12
8997		- @ sp needed
8998		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
8999		-.L1637:
	9249	+ pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
	9250	+.L1620:
9000	9251	.align 2
9001		-.L1636:
	9252	+.L1619:
9002	9253	.word .LANCHOR2
9003		- .word .LANCHOR2-1664
9004		- .word .LANCHOR2-1348
	9254	+ .word .LANCHOR2-1712
	9255	+ .word 33553920
	9256	+ .word .LANCHOR0
	9257	+ .word .LANCHOR3+130
9005	9258	.word .LC32
9006		- .word .LANCHOR3+136
9007	9259	.fnend
9008	9260	.size FtlMemInit, .-FtlMemInit
9009	9261	.align 2
9010	9262	.global IsBlkInVendorPart
	9263	+ .syntax unified
	9264	+ .arm
	9265	+ .fpu softvfp
9011	9266	.type IsBlkInVendorPart, %function
9012	9267	IsBlkInVendorPart:
9013	9268	.fnstart
9014	9269	@ args = 0, pretend = 0, frame = 0
9015	9270	@ frame_needed = 0, uses_anonymous_args = 0
9016	9271	@ link register save eliminated.
9017		- ldr r2, .L1645
	9272	+ ldr r2, .L1628
9018	9273	sub r3, r2, #1280
9019	9274	ldrh r3, [r3, #-8]
9020	9275	cmp r3, #0
9021		- beq .L1644
	9276	+ beq .L1627
9022	9277	ldr r3, [r2, #-1392]
9023		- sub r2, r2, #1648
9024		- ldrh r2, [r2]
9025		- add r2, r3, r2, asl #1
9026		-.L1640:
	9278	+ sub r2, r2, #1632
	9279	+ ldrh r2, [r2, #-12]
	9280	+ add r2, r3, r2, lsl #1
	9281	+.L1623:
9027	9282	cmp r3, r2
9028		- beq .L1644
9029		- ldrh r1, [r3], #2
9030		- cmp r1, r0
9031		- bne .L1640
9032		- mov r0, #1
9033		- bx lr
9034		-.L1644:
	9283	+ bne .L1624
	9284	+.L1627:
9035	9285	mov r0, #0
9036	9286	bx lr
9037		-.L1646:
	9287	+.L1624:
	9288	+ ldrh r1, [r3], #2
	9289	+ cmp r0, r1
	9290	+ bne .L1623
	9291	+ mov r0, #1
	9292	+ bx lr
	9293	+.L1629:
9038	9294	.align 2
9039		-.L1645:
	9295	+.L1628:
9040	9296	.word .LANCHOR2
9041	9297	.fnend
9042	9298	.size IsBlkInVendorPart, .-IsBlkInVendorPart
9043	9299	.align 2
9044	9300	.global FtlCacheMetchLpa
	9301	+ .syntax unified
	9302	+ .arm
	9303	+ .fpu softvfp
9045	9304	.type FtlCacheMetchLpa, %function
9046	9305	FtlCacheMetchLpa:
9047	9306	.fnstart
9048	9307	@ args = 0, pretend = 0, frame = 0
9049	9308	@ frame_needed = 0, uses_anonymous_args = 0
9050		- ldr r2, .L1654
9051		- ldr r3, [r2, #-1516]
	9309	+ ldr r2, .L1640
	9310	+ ldr r3, [r2, #-1512]
9052	9311	cmp r3, #0
9053		- beq .L1650
9054		- stmfd sp!, {r4, r5, lr}
	9312	+ beq .L1633
	9313	+ push {r4, r5, lr}
9055	9314	.save {r4, r5, lr}
9056	9315	mov r5, #36
9057		- ldr r4, [r2, #-1484]
	9316	+ ldr r4, [r2, #-1480]
9058	9317	mov r2, #0
9059		-.L1649:
	9318	+.L1632:
9060	9319	mla ip, r5, r2, r4
9061	9320	ldr lr, [ip, #16]
9062		- cmp lr, r0
9063		- movcc ip, #0
9064		- movcs ip, #1
9065	9321	cmp lr, r1
9066	9322	movhi ip, #0
	9323	+ movls ip, #1
	9324	+ cmp lr, r0
	9325	+ movcc ip, #0
9067	9326	cmp ip, #0
9068		- bne .L1651
	9327	+ bne .L1634
9069	9328	add r2, r2, #1
9070		- cmp r2, r3
9071		- bne .L1649
	9329	+ cmp r3, r2
	9330	+ bne .L1632
9072	9331	mov r0, ip
9073		- ldmfd sp!, {r4, r5, pc}
9074		-.L1650:
	9332	+ pop {r4, r5, pc}
	9333	+.L1633:
9075	9334	mov r0, r3
9076	9335	bx lr
9077		-.L1651:
	9336	+.L1634:
9078	9337	mov r0, #1
9079		- ldmfd sp!, {r4, r5, pc}
9080		-.L1655:
	9338	+ pop {r4, r5, pc}
	9339	+.L1641:
9081	9340	.align 2
9082		-.L1654:
	9341	+.L1640:
9083	9342	.word .LANCHOR2
9084	9343	.fnend
9085	9344	.size FtlCacheMetchLpa, .-FtlCacheMetchLpa
9086	9345	.align 2
9087	9346	.global FtlGetCap
	9347	+ .syntax unified
	9348	+ .arm
	9349	+ .fpu softvfp
9088	9350	.type FtlGetCap, %function
9089	9351	FtlGetCap:
9090	9352	.fnstart
9091	9353	@ args = 0, pretend = 0, frame = 0
9092	9354	@ frame_needed = 0, uses_anonymous_args = 0
9093	9355	@ link register save eliminated.
9094		- ldr r3, .L1657
9095		- ldr r0, [r3, #-2740]
	9356	+ ldr r3, .L1643
	9357	+ ldr r0, [r3, #-2736]
9096	9358	bx lr
9097		-.L1658:
	9359	+.L1644:
9098	9360	.align 2
9099		-.L1657:
	9361	+.L1643:
9100	9362	.word .LANCHOR2
9101	9363	.fnend
9102	9364	.size FtlGetCap, .-FtlGetCap
9103	9365	.align 2
9104	9366	.global FtlGetCapacity
	9367	+ .syntax unified
	9368	+ .arm
	9369	+ .fpu softvfp
9105	9370	.type FtlGetCapacity, %function
9106	9371	FtlGetCapacity:
9107	9372	.fnstart
9108	9373	@ args = 0, pretend = 0, frame = 0
9109	9374	@ frame_needed = 0, uses_anonymous_args = 0
9110	9375	@ link register save eliminated.
9111		- ldr r3, .L1660
9112		- ldr r0, [r3, #-2740]
	9376	+ ldr r3, .L1646
	9377	+ ldr r0, [r3, #-2736]
9113	9378	bx lr
9114		-.L1661:
	9379	+.L1647:
9115	9380	.align 2
9116		-.L1660:
	9381	+.L1646:
9117	9382	.word .LANCHOR2
9118	9383	.fnend
9119	9384	.size FtlGetCapacity, .-FtlGetCapacity
9120	9385	.align 2
9121	9386	.global ftl_get_density
	9387	+ .syntax unified
	9388	+ .arm
	9389	+ .fpu softvfp
9122	9390	.type ftl_get_density, %function
9123	9391	ftl_get_density:
9124	9392	.fnstart
9125	9393	@ args = 0, pretend = 0, frame = 0
9126	9394	@ frame_needed = 0, uses_anonymous_args = 0
9127	9395	@ link register save eliminated.
9128		- ldr r3, .L1663
9129		- ldr r0, [r3, #-2740]
	9396	+ ldr r3, .L1649
	9397	+ ldr r0, [r3, #-2736]
9130	9398	bx lr
9131		-.L1664:
	9399	+.L1650:
9132	9400	.align 2
9133		-.L1663:
	9401	+.L1649:
9134	9402	.word .LANCHOR2
9135	9403	.fnend
9136	9404	.size ftl_get_density, .-ftl_get_density
9137	9405	.align 2
9138	9406	.global FtlGetLpn
	9407	+ .syntax unified
	9408	+ .arm
	9409	+ .fpu softvfp
9139	9410	.type FtlGetLpn, %function
9140	9411	FtlGetLpn:
9141	9412	.fnstart
9142	9413	@ args = 0, pretend = 0, frame = 0
9143	9414	@ frame_needed = 0, uses_anonymous_args = 0
9144	9415	@ link register save eliminated.
9145		- ldr r3, .L1666
	9416	+ ldr r3, .L1652
9146	9417	ldr r0, [r3, #-1284]
9147	9418	bx lr
9148		-.L1667:
	9419	+.L1653:
9149	9420	.align 2
9150		-.L1666:
	9421	+.L1652:
9151	9422	.word .LANCHOR2
9152	9423	.fnend
9153	9424	.size FtlGetLpn, .-FtlGetLpn
9154	9425	.align 2
9155	9426	.global FtlBbmMapBadBlock
	9427	+ .syntax unified
	9428	+ .arm
	9429	+ .fpu softvfp
9156	9430	.type FtlBbmMapBadBlock, %function
9157	9431	FtlBbmMapBadBlock:
9158	9432	.fnstart
9159	9433	@ args = 0, pretend = 0, frame = 0
9160	9434	@ frame_needed = 0, uses_anonymous_args = 0
9161		- stmfd sp!, {r0, r1, r4, r5, r6, lr}
9162		- .save {r4, r5, r6, lr}
9163		- .pad #8
9164		- mov r6, r0
9165		- ldr r5, .L1670
9166		- sub r3, r5, #1664
9167		- ldrh r4, [r3, #-6]
9168		- mov r1, r4
	9435	+ push {r0, r1, r2, r4, r5, r6, r7, lr}
	9436	+ .save {r4, r5, r6, r7, lr}
	9437	+ .pad #12
	9438	+ mov r5, r0
	9439	+ ldr r4, .L1656
	9440	+ sub r3, r4, #1664
	9441	+ ldrh r7, [r3, #-4]
	9442	+ mov r1, r7
9169	9443	bl __aeabi_uidiv
9170		- uxth r2, r0
9171		- smulbb r3, r2, r4
9172		- add r1, r5, r2, asl #2
9173		- mov r4, #1
9174		- ldr ip, [r1, #-1320]
9175		- rsb r3, r3, r6
9176		- uxth r3, r3
9177		- and r1, r3, #31
9178		- mov lr, r3, lsr #5
9179		- ldr r0, [ip, lr, asl #2]
9180		- orr r1, r0, r4, asl r1
9181		- ldr r0, .L1670+4
9182		- str r1, [ip, lr, asl #2]
9183		- str r1, [sp]
9184		- mov r1, r6
	9444	+ uxth r6, r0
	9445	+ mov r1, r7
	9446	+ mov r0, r5
	9447	+ bl __aeabi_uidivmod
	9448	+ add r2, r4, r6, lsl #2
	9449	+ uxth r3, r1
	9450	+ ldr r2, [r2, #-1320]
	9451	+ lsr r1, r3, #5
	9452	+ and ip, r3, #31
	9453	+ mov lr, #1
	9454	+ ldr r0, [r2, r1, lsl #2]
	9455	+ orr r0, r0, lr, lsl ip
	9456	+ str r0, [r2, r1, lsl #2]
	9457	+ mov r2, r6
	9458	+ str r0, [sp]
	9459	+ mov r1, r5
	9460	+ ldr r0, .L1656+4
9185	9461	bl printk
9186		- sub r2, r5, #1344
	9462	+ sub r3, r4, #1344
9187	9463	mov r0, #0
9188		- ldrh r3, [r2, #2]
9189		- add r3, r3, r4
9190		- strh r3, [r2, #2] @ movhi
9191		- add sp, sp, #8
	9464	+ ldrh r2, [r3, #2]
	9465	+ add r2, r2, #1
	9466	+ strh r2, [r3, #2] @ movhi
	9467	+ add sp, sp, #12
9192	9468	@ sp needed
9193		- ldmfd sp!, {r4, r5, r6, pc}
9194		-.L1671:
	9469	+ pop {r4, r5, r6, r7, pc}
	9470	+.L1657:
9195	9471	.align 2
9196		-.L1670:
	9472	+.L1656:
9197	9473	.word .LANCHOR2
9198	9474	.word .LC33
9199	9475	.fnend
9200	9476	.size FtlBbmMapBadBlock, .-FtlBbmMapBadBlock
9201		- .global __aeabi_uidivmod
9202	9477	.align 2
9203	9478	.global FtlBbmIsBadBlock
	9479	+ .syntax unified
	9480	+ .arm
	9481	+ .fpu softvfp
9204	9482	.type FtlBbmIsBadBlock, %function
9205	9483	FtlBbmIsBadBlock:
9206	9484	.fnstart
9207	9485	@ args = 0, pretend = 0, frame = 0
9208	9486	@ frame_needed = 0, uses_anonymous_args = 0
9209		- stmfd sp!, {r3, r4, r5, r6, r7, lr}
9210		- .save {r3, r4, r5, r6, r7, lr}
	9487	+ push {r4, r5, r6, r7, r8, lr}
	9488	+ .save {r4, r5, r6, r7, r8, lr}
9211	9489	mov r7, r0
9212		- ldr r5, .L1674
	9490	+ ldr r5, .L1660
9213	9491	sub r3, r5, #1664
9214		- ldrh r6, [r3, #-6]
	9492	+ ldrh r6, [r3, #-4]
9215	9493	mov r1, r6
9216	9494	bl __aeabi_uidivmod
9217	9495	mov r0, r7
9218	9496	uxth r4, r1
9219	9497	mov r1, r6
9220	9498	bl __aeabi_uidiv
9221		- mov r2, r4, lsr #5
9222		- and r4, r4, #31
9223	9499	uxth r0, r0
9224		- add r5, r5, r0, asl #2
	9500	+ lsr r2, r4, #5
	9501	+ add r5, r5, r0, lsl #2
	9502	+ and r4, r4, #31
9225	9503	ldr r3, [r5, #-1320]
9226		- ldr r0, [r3, r2, asl #2]
9227		- mov r0, r0, lsr r4
	9504	+ ldr r0, [r3, r2, lsl #2]
	9505	+ lsr r0, r0, r4
9228	9506	and r0, r0, #1
9229		- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
9230		-.L1675:
	9507	+ pop {r4, r5, r6, r7, r8, pc}
	9508	+.L1661:
9231	9509	.align 2
9232		-.L1674:
	9510	+.L1660:
9233	9511	.word .LANCHOR2
9234	9512	.fnend
9235	9513	.size FtlBbmIsBadBlock, .-FtlBbmIsBadBlock
9236	9514	.align 2
9237	9515	.global FtlBbtInfoPrint
	9516	+ .syntax unified
	9517	+ .arm
	9518	+ .fpu softvfp
9238	9519	.type FtlBbtInfoPrint, %function
9239	9520	FtlBbtInfoPrint:
9240	9521	.fnstart
..	..	@@ -9246,198 +9527,200 @@
9246	9527	.size FtlBbtInfoPrint, .-FtlBbtInfoPrint
9247	9528	.align 2
9248	9529	.global FtlBbt2Bitmap
	9530	+ .syntax unified
	9531	+ .arm
	9532	+ .fpu softvfp
9249	9533	.type FtlBbt2Bitmap, %function
9250	9534	FtlBbt2Bitmap:
9251	9535	.fnstart
9252	9536	@ args = 0, pretend = 0, frame = 0
9253	9537	@ frame_needed = 0, uses_anonymous_args = 0
9254		- stmfd sp!, {r4, r5, r6, lr}
	9538	+ push {r4, r5, r6, lr}
9255	9539	.save {r4, r5, r6, lr}
9256		- mov r4, r0
9257		- ldr r5, .L1683
9258		- mov r0, r1
9259	9540	mov r6, r1
	9541	+ ldr r5, .L1669
	9542	+ mov r4, r0
9260	9543	mov r1, #0
	9544	+ mov r0, r6
	9545	+ ldrh r2, [r5, #-8]
9261	9546	sub r5, r5, #4
9262		- ldrh r2, [r5, #-4]
9263		- mov r2, r2, asl #2
	9547	+ lsl r2, r2, #2
9264	9548	bl ftl_memset
9265		- add r3, r4, #1020
9266		- add r3, r3, #2
9267		- sub r1, r4, #2
9268		- mov lr, #1
	9549	+ add r0, r4, #1020
	9550	+ sub r2, r4, #2
	9551	+ add r0, r0, #2
9269	9552	movw r4, #65535
9270		-.L1679:
9271		- ldrh r2, [r1, #2]!
9272		- cmp r2, r4
9273		- ldmeqfd sp!, {r4, r5, r6, pc}
9274		- mov ip, r2, lsr #5
9275		- and r2, r2, #31
9276		- cmp r1, r3
9277		- ldr r0, [r6, ip, asl #2]
9278		- orr r2, r0, lr, asl r2
9279		- str r2, [r6, ip, asl #2]
9280		- ldrh r2, [r5, #6]
9281		- add r2, r2, #1
9282		- strh r2, [r5, #6] @ movhi
9283		- bne .L1679
9284		- ldmfd sp!, {r4, r5, r6, pc}
9285		-.L1684:
	9553	+ mov lr, #1
	9554	+.L1665:
	9555	+ ldrh r3, [r2, #2]!
	9556	+ cmp r3, r4
	9557	+ popeq {r4, r5, r6, pc}
	9558	+ lsr ip, r3, #5
	9559	+ and r3, r3, #31
	9560	+ cmp r2, r0
	9561	+ ldr r1, [r6, ip, lsl #2]
	9562	+ orr r3, r1, lr, lsl r3
	9563	+ str r3, [r6, ip, lsl #2]
	9564	+ ldrh r3, [r5, #6]
	9565	+ add r3, r3, #1
	9566	+ strh r3, [r5, #6] @ movhi
	9567	+ bne .L1665
	9568	+ pop {r4, r5, r6, pc}
	9569	+.L1670:
9286	9570	.align 2
9287		-.L1683:
	9571	+.L1669:
9288	9572	.word .LANCHOR2-1344
9289	9573	.fnend
9290	9574	.size FtlBbt2Bitmap, .-FtlBbt2Bitmap
9291	9575	.align 2
9292	9576	.global FtlBbmTblFlush
	9577	+ .syntax unified
	9578	+ .arm
	9579	+ .fpu softvfp
9293	9580	.type FtlBbmTblFlush, %function
9294	9581	FtlBbmTblFlush:
9295	9582	.fnstart
9296	9583	@ args = 0, pretend = 0, frame = 0
9297	9584	@ frame_needed = 0, uses_anonymous_args = 0
9298		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
9299		- .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
9300		- .pad #12
9301		- ldr r4, .L1703
9302		- ldr r5, [r4, #-1280]
9303		- cmp r5, #0
9304		- bne .L1687
9305		- ldr r3, [r4, #-1444]
9306		- mov r1, r5
9307		- ldr r0, [r4, #-1476]
9308		- sub r8, r4, #1344
9309		- ldr r6, .L1703+4
9310		- mov r10, r4
9311		- str r3, [r4, #-1264]
9312		- sub r3, r4, #1648
	9585	+ push {r0, r1, r4, r5, r6, r7, r8, r9, r10, lr}
	9586	+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
	9587	+ .pad #8
	9588	+ ldr r4, .L1686
	9589	+ ldr r6, [r4, #-1280]
	9590	+ cmp r6, #0
	9591	+ bne .L1673
	9592	+ ldr r0, [r4, #-1472]
	9593	+ sub r7, r4, #1648
	9594	+ ldr r3, [r4, #-1440]
	9595	+ sub r5, r4, #1344
	9596	+ ldrh r2, [r7, #-8]
	9597	+ add r7, r7, #324
	9598	+ mov r1, r6
9313	9599	str r0, [r4, #-1268]
9314		- sub fp, r6, #28
9315		- ldrh r2, [r3, #-10]
	9600	+ str r3, [r4, #-1264]
9316	9601	bl ftl_memset
9317		- ldr r9, .L1703+8
9318		-.L1688:
9319		- ldrh r3, [r9]
9320		- ldr r7, .L1703
9321		- cmp r5, r3
9322		- bge .L1702
9323		- ldrh r2, [fp]
9324		- ldr r3, [r10, #-1268]
9325		- ldr r1, [r6, #4]!
9326		- mul r0, r2, r5
9327		- mov r2, r2, asl #2
9328		- add r5, r5, #1
9329		- add r0, r3, r0, asl #2
9330		- bl ftl_memcpy
9331		- b .L1688
9332		-.L1702:
9333		- ldr r6, [r7, #-1264]
9334		- mov r1, #255
	9602	+.L1674:
	9603	+ ldr r3, .L1686+4
	9604	+ ldrh r3, [r3]
	9605	+ cmp r6, r3
	9606	+ blt .L1675
	9607	+ ldr r6, [r4, #-1264]
9335	9608	mov r2, #16
9336		- ldr r5, .L1703+12
	9609	+ mov r1, #255
	9610	+ ldr r9, .L1686+8
	9611	+ mov r7, #0
9337	9612	mov r0, r6
	9613	+ mov r8, r7
9338	9614	bl ftl_memset
9339		- ldr r3, .L1703+16
9340		- mov r10, r5
	9615	+ ldr r3, .L1686+12
9341	9616	strh r3, [r6] @ movhi
9342		- ldr r3, [r7, #-1340]
	9617	+ ldr r3, [r4, #-1340]
9343	9618	str r3, [r6, #4]
9344		- ldrh r3, [r8, #-4]
9345		- mov r8, #0
9346		- mov r9, r8
	9619	+ ldrh r3, [r5, #-4]
9347	9620	strh r3, [r6, #2] @ movhi
9348		- ldrh r3, [r5, #4]
	9621	+ ldrh r3, [r5], #-4
9349	9622	strh r3, [r6, #8] @ movhi
9350	9623	ldrh r3, [r5, #6]
9351	9624	strh r3, [r6, #10] @ movhi
9352		- ldr r3, [r7, #-1740]
	9625	+ ldr r3, [r4, #-1736]
9353	9626	strh r3, [r6, #12] @ movhi
9354		-.L1690:
9355		- ldr r3, [r4, #-1476]
9356		- mov fp, #0
9357		- ldrh r1, [r5]
	9627	+.L1676:
	9628	+ ldr r3, [r4, #-1472]
	9629	+ mov r10, #0
9358	9630	ldrh r2, [r5, #2]
	9631	+ ldrh r1, [r5]
9359	9632	str r3, [r4, #-1268]
9360		- ldr r3, [r4, #-1444]
9361		- str fp, [r4, #-1276]
	9633	+ ldr r3, [r4, #-1440]
	9634	+ str r10, [r4, #-1276]
9362	9635	str r3, [r4, #-1264]
9363		- orr r3, r2, r1, asl #10
	9636	+ orr r3, r2, r1, lsl #10
9364	9637	ldrh r0, [r6, #10]
9365	9638	str r3, [r4, #-1272]
9366	9639	ldrh r3, [r5, #4]
9367	9640	str r0, [sp]
9368		- ldr r0, .L1703+20
	9641	+ mov r0, r9
9369	9642	bl printk
9370		- ldr r3, .L1703+24
	9643	+ ldr r3, .L1686+16
9371	9644	ldrh r2, [r5, #2]
9372	9645	ldrh r3, [r3]
9373	9646	sub r3, r3, #1
9374	9647	cmp r2, r3
9375		- blt .L1691
9376		- ldr r3, [r7, #-1340]
9377		- mov r1, #1
	9648	+ blt .L1677
	9649	+ ldr r3, [r4, #-1340]
9378	9650	ldrh r2, [r5]
	9651	+ ldr r0, [r4, #-1488]
9379	9652	add r3, r3, #1
9380		- ldr r0, [r7, #-1492]
9381		- str r3, [r7, #-1340]
	9653	+ strh r10, [r5, #2] @ movhi
	9654	+ str r3, [r4, #-1340]
9382	9655	str r3, [r6, #4]
9383	9656	ldrh r3, [r5, #4]
9384	9657	strh r2, [r6, #8] @ movhi
9385	9658	strh r2, [r5, #4] @ movhi
9386		- mov r2, r1
	9659	+ mov r2, #1
9387	9660	strh r3, [r5] @ movhi
9388		- mov r3, r3, asl #10
9389		- str r3, [r7, #-1272]
	9661	+ mov r1, r2
	9662	+ lsl r3, r3, #10
	9663	+ str r3, [r4, #-1272]
9390	9664	str r3, [r0, #4]
9391		- strh fp, [r5, #2] @ movhi
9392	9665	bl FlashEraseBlocks
9393		-.L1691:
9394		- mov r1, #1
9395		- ldr r0, .L1703+28
9396		- mov r3, r1
9397		- mov r2, r1
	9666	+.L1677:
	9667	+ mov r3, #1
	9668	+ ldr r0, .L1686+20
	9669	+ mov r2, r3
	9670	+ mov r1, r3
9398	9671	bl FlashProgPages
9399		- ldrh r3, [r10, #2]
9400		- ldr fp, .L1703
	9672	+ ldrh r3, [r5, #2]
9401	9673	add r3, r3, #1
9402		- strh r3, [r10, #2] @ movhi
	9674	+ strh r3, [r5, #2] @ movhi
9403	9675	ldr r3, [r4, #-1276]
9404	9676	cmn r3, #1
9405		- bne .L1692
9406		- add r8, r8, #1
9407		- ldr r0, .L1703+32
9408		- ldr r1, [r7, #-1272]
9409		- uxth r8, r8
	9677	+ bne .L1678
	9678	+ add r7, r7, #1
	9679	+ ldr r1, [r4, #-1272]
	9680	+ uxth r7, r7
	9681	+ ldr r0, .L1686+24
9410	9682	bl printk
9411		- cmp r8, #3
9412		- bls .L1690
9413		- ldr r0, .L1703+36
9414		- mov r2, r8
9415		- ldr r1, [fp, #-1272]
	9683	+ cmp r7, #3
	9684	+ bls .L1676
	9685	+ mov r2, r7
	9686	+ ldr r1, [r4, #-1272]
	9687	+ ldr r0, .L1686+28
9416	9688	bl printk
9417	9689	mov r3, #1
9418		- str r3, [fp, #-1280]
9419		- b .L1687
9420		-.L1692:
9421		- add r9, r9, #1
9422		- cmp r9, #1
9423		- beq .L1690
9424		- cmp r3, #256
9425		- beq .L1690
9426		-.L1687:
	9690	+ str r3, [r4, #-1280]
	9691	+.L1673:
9427	9692	mov r0, #0
9428		- add sp, sp, #12
	9693	+ add sp, sp, #8
9429	9694	@ sp needed
9430		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
9431		-.L1704:
	9695	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	9696	+.L1675:
	9697	+ ldrh r2, [r5, #-8]
	9698	+ ldr r3, [r4, #-1268]
	9699	+ ldr r1, [r7, #4]!
	9700	+ mul r0, r6, r2
	9701	+ lsl r2, r2, #2
	9702	+ add r6, r6, #1
	9703	+ add r0, r3, r0, lsl #2
	9704	+ bl ftl_memcpy
	9705	+ b .L1674
	9706	+.L1681:
	9707	+ mov r8, #1
	9708	+ b .L1676
	9709	+.L1678:
	9710	+ add r8, r8, #1
	9711	+ cmp r8, #1
	9712	+ ble .L1681
	9713	+ cmp r3, #256
	9714	+ bne .L1673
	9715	+ b .L1676
	9716	+.L1687:
9432	9717	.align 2
9433		-.L1703:
	9718	+.L1686:
9434	9719	.word .LANCHOR2
9435		- .word .LANCHOR2-1324
9436		- .word .LANCHOR2-1714
9437		- .word .LANCHOR2-1348
9438		- .word -3887
	9720	+ .word .LANCHOR2-1710
9439	9721	.word .LC34
9440		- .word .LANCHOR2-1666
	9722	+ .word -3887
	9723	+ .word .LANCHOR2-1664
9441	9724	.word .LANCHOR2-1276
9442	9725	.word .LC35
9443	9726	.word .LC36
..	..	@@ -9445,376 +9728,393 @@
9445	9728	.size FtlBbmTblFlush, .-FtlBbmTblFlush
9446	9729	.align 2
9447	9730	.global FtlLoadFactoryBbt
	9731	+ .syntax unified
	9732	+ .arm
	9733	+ .fpu softvfp
9448	9734	.type FtlLoadFactoryBbt, %function
9449	9735	FtlLoadFactoryBbt:
9450	9736	.fnstart
9451	9737	@ args = 0, pretend = 0, frame = 0
9452	9738	@ frame_needed = 0, uses_anonymous_args = 0
9453		- ldr r2, .L1717
9454		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
	9739	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
9455	9740	.save {r4, r5, r6, r7, r8, r9, r10, lr}
9456		- mov r5, #0
9457		- ldr r6, .L1717+4
9458		- mov r9, r2
9459		- ldr r3, [r2, #-1476]
9460		- ldr r7, [r2, #-1444]
9461		- sub r8, r6, #376
9462		- str r3, [r2, #-1268]
9463		- str r7, [r2, #-1264]
9464		-.L1706:
9465		- ldrh r3, [r8]
9466		- cmp r5, r3
9467		- bcs .L1716
9468		- ldr r2, .L1717+8
	9741	+ mov r8, #0
	9742	+ ldr r5, .L1699
	9743	+ ldr r3, [r5, #-1472]
	9744	+ sub r7, r5, #1328
	9745	+ ldr r10, [r5, #-1440]
	9746	+ sub r9, r5, #1264
	9747	+ sub r7, r7, #10
	9748	+ sub r9, r9, #12
	9749	+ str r3, [r5, #-1268]
	9750	+ str r10, [r5, #-1264]
	9751	+.L1689:
	9752	+ ldr r6, .L1699+4
	9753	+ ldrh r3, [r6]
	9754	+ cmp r8, r3
	9755	+ bcc .L1694
	9756	+ mov r0, #0
	9757	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	9758	+.L1694:
	9759	+ ldrh r4, [r6, #42]
9469	9760	mvn r3, #0
9470		- strh r3, [r6, #2]! @ movhi
9471		- ldrh r3, [r2]
9472		- mov r10, r2
9473		- sub r3, r3, #1
9474		- uxth r4, r3
9475		-.L1707:
9476		- ldrh r3, [r10]
	9761	+ add r6, r6, #46
	9762	+ strh r3, [r7, #2]! @ movhi
	9763	+ add r4, r4, r3
	9764	+ uxth r4, r4
	9765	+.L1690:
	9766	+ ldrh r3, [r6, #-4]
9477	9767	sub r2, r3, #16
9478	9768	cmp r4, r2
9479		- ble .L1709
9480		- mla r3, r3, r5, r4
9481		- mov r1, #1
9482		- ldr r0, .L1717+12
9483		- mov r2, r1
9484		- mov r3, r3, asl #10
9485		- str r3, [r9, #-1272]
	9769	+ ble .L1692
	9770	+ mla r3, r8, r3, r4
	9771	+ mov r2, #1
	9772	+ mov r1, r2
	9773	+ mov r0, r9
	9774	+ lsl r3, r3, #10
	9775	+ str r3, [r5, #-1272]
9486	9776	bl FlashReadPages
9487		- ldr r3, [r9, #-1276]
	9777	+ ldr r3, [r5, #-1276]
9488	9778	cmn r3, #1
9489		- beq .L1708
9490		- ldrh r2, [r7]
	9779	+ beq .L1691
	9780	+ ldrh r2, [r10]
9491	9781	movw r3, #61664
9492	9782	cmp r2, r3
9493		- streqh r4, [r6] @ movhi
9494		- beq .L1709
9495		-.L1708:
	9783	+ bne .L1691
	9784	+ strh r4, [r7] @ movhi
	9785	+.L1692:
	9786	+ add r8, r8, #1
	9787	+ b .L1689
	9788	+.L1691:
9496	9789	sub r4, r4, #1
9497	9790	uxth r4, r4
9498		- b .L1707
9499		-.L1709:
9500		- add r5, r5, #1
9501		- b .L1706
9502		-.L1716:
9503		- mov r0, #0
9504		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
9505		-.L1718:
	9791	+ b .L1690
	9792	+.L1700:
9506	9793	.align 2
9507		-.L1717:
	9794	+.L1699:
9508	9795	.word .LANCHOR2
9509		- .word .LANCHOR2-1338
9510		- .word .LANCHOR2-1670
9511		- .word .LANCHOR2-1276
	9796	+ .word .LANCHOR2-1710
9512	9797	.fnend
9513	9798	.size FtlLoadFactoryBbt, .-FtlLoadFactoryBbt
9514	9799	.align 2
9515	9800	.global FtlBbtMemInit
	9801	+ .syntax unified
	9802	+ .arm
	9803	+ .fpu softvfp
9516	9804	.type FtlBbtMemInit, %function
9517	9805	FtlBbtMemInit:
9518	9806	.fnstart
9519	9807	@ args = 0, pretend = 0, frame = 0
9520	9808	@ frame_needed = 0, uses_anonymous_args = 0
9521	9809	@ link register save eliminated.
9522		- ldr r0, .L1720
	9810	+ ldr r0, .L1702
9523	9811	mvn r2, #0
9524	9812	mov r1, #255
9525		- add r0, r0, #8
9526		- strh r2, [r0, #-12] @ movhi
	9813	+ strh r2, [r0, #-4] @ movhi
9527	9814	mov r2, #0
9528		- strh r2, [r0, #-6] @ movhi
	9815	+ strh r2, [r0, #2] @ movhi
9529	9816	mov r2, #16
	9817	+ add r0, r0, #8
9530	9818	b ftl_memset
9531		-.L1721:
	9819	+.L1703:
9532	9820	.align 2
9533		-.L1720:
	9821	+.L1702:
9534	9822	.word .LANCHOR2-1344
9535	9823	.fnend
9536	9824	.size FtlBbtMemInit, .-FtlBbtMemInit
9537	9825	.align 2
9538	9826	.global FtlBbtCalcTotleCnt
	9827	+ .syntax unified
	9828	+ .arm
	9829	+ .fpu softvfp
9539	9830	.type FtlBbtCalcTotleCnt, %function
9540	9831	FtlBbtCalcTotleCnt:
9541	9832	.fnstart
9542	9833	@ args = 0, pretend = 0, frame = 0
9543	9834	@ frame_needed = 0, uses_anonymous_args = 0
9544		- stmfd sp!, {r4, r5, r6, lr}
	9835	+ ldr r3, .L1712
	9836	+ push {r4, r5, r6, lr}
9545	9837	.save {r4, r5, r6, lr}
9546	9838	mov r5, #0
9547		- ldr r4, .L1731
9548		- ldrh r6, [r4, #-6]
9549		- ldrh r3, [r4, #-50]
9550	9839	mov r4, r5
9551		- mul r6, r3, r6
9552		-.L1723:
	9840	+ ldrh r2, [r3, #-4]
	9841	+ ldrh r6, [r3, #-46]
	9842	+ mul r6, r6, r2
	9843	+.L1705:
9553	9844	uxth r0, r5
9554	9845	cmp r0, r6
9555		- bge .L1730
	9846	+ blt .L1707
	9847	+ mov r0, r4
	9848	+ pop {r4, r5, r6, pc}
	9849	+.L1707:
9556	9850	bl FtlBbmIsBadBlock
9557		- add r5, r5, #1
9558	9851	cmp r0, #0
	9852	+ add r5, r5, #1
9559	9853	addne r4, r4, #1
9560	9854	uxthne r4, r4
9561		- b .L1723
9562		-.L1730:
9563		- mov r0, r4
9564		- ldmfd sp!, {r4, r5, r6, pc}
9565		-.L1732:
	9855	+ b .L1705
	9856	+.L1713:
9566	9857	.align 2
9567		-.L1731:
	9858	+.L1712:
9568	9859	.word .LANCHOR2-1664
9569	9860	.fnend
9570	9861	.size FtlBbtCalcTotleCnt, .-FtlBbtCalcTotleCnt
9571	9862	.align 2
9572	9863	.global FtlMakeBbt
	9864	+ .syntax unified
	9865	+ .arm
	9866	+ .fpu softvfp
9573	9867	.type FtlMakeBbt, %function
9574	9868	FtlMakeBbt:
9575	9869	.fnstart
9576		- @ args = 0, pretend = 0, frame = 0
	9870	+ @ args = 0, pretend = 0, frame = 8
9577	9871	@ frame_needed = 0, uses_anonymous_args = 0
9578		- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
9579		- .save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
9580		- ldr r7, .L1756
9581		- ldr r5, [r7, #-1280]
9582		- cmp r5, #0
9583		- bne .L1734
	9872	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	9873	+ .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	9874	+ .pad #12
	9875	+ ldr r4, .L1735
	9876	+ ldr r7, [r4, #-1280]
	9877	+ cmp r7, #0
	9878	+ bne .L1715
	9879	+ ldr r10, .L1735+4
	9880	+ sub fp, r4, #1264
	9881	+ sub r8, r4, #1344
	9882	+ sub fp, fp, #12
9584	9883	bl FtlBbtMemInit
9585		- ldr r8, .L1756+4
	9884	+ sub r9, r10, #18
9586	9885	bl FtlLoadFactoryBbt
9587		- mov r4, r7
9588		- sub r9, r8, #18
9589		-.L1735:
9590		- ldr r6, .L1756+8
9591		- ldrh r3, [r6]
	9886	+.L1716:
	9887	+ ldr r5, .L1735+8
	9888	+ ldrh r3, [r5]
	9889	+ cmp r7, r3
	9890	+ bcc .L1722
	9891	+ mov r5, #0
	9892	+.L1723:
	9893	+ ldr r3, .L1735+12
	9894	+ uxth r0, r5
	9895	+ add r5, r5, #1
	9896	+ ldrh r3, [r3]
	9897	+ cmp r3, r0
	9898	+ bhi .L1724
	9899	+ sub r6, r8, #4
	9900	+ ldrh r5, [r6, #12]
	9901	+ movw r7, #65535
	9902	+ sub r5, r5, #1
	9903	+ uxth r5, r5
	9904	+.L1725:
	9905	+ ldrh r3, [r6, #12]
	9906	+ sub r3, r3, #48
9592	9907	cmp r5, r3
9593		- bcs .L1754
9594		- ldrh r3, [r9, #2]!
	9908	+ ble .L1729
	9909	+ mov r0, r5
	9910	+ bl FtlBbmIsBadBlock
	9911	+ cmp r0, #1
	9912	+ beq .L1726
	9913	+ mov r0, r5
	9914	+ bl FlashTestBlk
	9915	+ cmp r0, #0
	9916	+ beq .L1727
	9917	+ mov r0, r5
	9918	+ bl FtlBbmMapBadBlock
	9919	+.L1726:
	9920	+ sub r5, r5, #1
	9921	+ uxth r5, r5
	9922	+ b .L1725
	9923	+.L1722:
	9924	+ ldr r3, [r4, #-1440]
9595	9925	movw r2, #65535
9596		- ldr r0, [r4, #-1476]
9597		- ldr r10, [r4, #-1444]
9598		- cmp r3, r2
	9926	+ ldr r0, [r4, #-1472]
	9927	+ str r3, [sp, #4]
	9928	+ str r3, [r4, #-1264]
	9929	+ ldrh r3, [r9, #2]!
9599	9930	str r0, [r4, #-1268]
9600		- str r10, [r4, #-1264]
9601		- beq .L1736
9602		- ldrh fp, [r6, #44]
9603		- mov r1, #1
9604		- mov r2, r1
9605		- ldr r0, .L1756+12
9606		- mla fp, fp, r5, r3
9607		- mov r3, fp, asl #10
	9931	+ cmp r3, r2
	9932	+ beq .L1717
	9933	+ ldrh r6, [r5, #42]
	9934	+ mov r2, #1
	9935	+ mov r1, r2
	9936	+ mov r0, fp
	9937	+ mla r6, r7, r6, r3
	9938	+ lsl r3, r6, #10
9608	9939	str r3, [r4, #-1272]
9609	9940	bl FlashReadPages
9610		- ldrh r2, [r6, #44]
9611		- ldr r0, [r8]
9612		- add r2, r2, #7
	9941	+ ldrh r2, [r5, #42]
9613	9942	ldr r1, [r4, #-1268]
9614		- mov r2, r2, asr #3
	9943	+ ldr r0, [r10]
	9944	+ add r2, r2, #7
	9945	+ asr r2, r2, #3
9615	9946	bl ftl_memcpy
9616		- b .L1737
9617		-.L1736:
9618		- mov r1, r5
	9947	+.L1718:
	9948	+ uxth r0, r6
	9949	+ add r7, r7, #1
	9950	+ add r10, r10, #4
	9951	+ bl FtlBbmMapBadBlock
	9952	+ b .L1716
	9953	+.L1717:
	9954	+ mov r1, r7
9619	9955	bl FlashGetBadBlockList
	9956	+ ldr r1, [r10]
9620	9957	ldr r0, [r4, #-1268]
9621		- ldr r1, [r8]
9622	9958	bl FtlBbt2Bitmap
9623		- ldrh r6, [r6, #44]
9624		-.L1739:
9625		- sub r6, r6, #1
9626		- uxth r6, r6
9627		-.L1738:
9628		- ldr fp, .L1756+16
9629		- ldrh r0, [fp]
9630		- smlabb r0, r0, r5, r6
	9959	+ ldrh r5, [r5, #42]
	9960	+.L1720:
	9961	+ sub r5, r5, #1
	9962	+ uxth r5, r5
	9963	+.L1719:
	9964	+ ldr r3, .L1735+16
	9965	+ ldrh r0, [r3, #-4]
	9966	+ smlabb r0, r0, r7, r5
9631	9967	uxth r0, r0
9632	9968	bl FtlBbmIsBadBlock
9633	9969	cmp r0, #1
9634		- beq .L1739
9635		- mov r1, #0
	9970	+ beq .L1720
9636	9971	mov r2, #16
9637		- strh r6, [r9] @ movhi
9638		- ldr r0, [r4, #-1444]
	9972	+ mov r1, #0
	9973	+ strh r5, [r9] @ movhi
	9974	+ ldr r0, [r4, #-1440]
9639	9975	bl ftl_memset
9640		- ldr r3, .L1756+20
9641		- strh r3, [r10] @ movhi
	9976	+ ldr r3, [sp, #4]
	9977	+ movw r2, 61664 @ movhi
	9978	+ strh r2, [r3] @ movhi
9642	9979	mov r3, #0
9643		- str r3, [r10, #4]
	9980	+ ldr r2, [sp, #4]
	9981	+ str r3, [r2, #4]
9644	9982	ldrh r3, [r9]
9645		- ldrh fp, [fp]
9646		- strh r3, [r10, #2] @ movhi
	9983	+ strh r3, [r2, #2] @ movhi
	9984	+ ldr r3, .L1735+16
	9985	+ ldrh r2, [r8, #-8]
	9986	+ ldr r1, [r10]
	9987	+ ldrh r6, [r3, #-4]
9647	9988	ldrh r3, [r9]
9648		- ldr r1, [r8]
	9989	+ lsl r2, r2, #2
9649	9990	ldr r0, [r4, #-1268]
9650		- mla fp, fp, r5, r3
9651		- mov r3, fp, asl #10
	9991	+ mla r6, r7, r6, r3
	9992	+ lsl r3, r6, #10
9652	9993	str r3, [r4, #-1272]
9653		- ldr r3, .L1756+24
9654		- ldrh r2, [r3]
9655		- mov r2, r2, asl #2
9656	9994	bl ftl_memcpy
9657		- mov r1, #1
9658		- mov r2, r1
9659		- ldr r0, .L1756+12
	9995	+ mov r2, #1
	9996	+ mov r0, fp
	9997	+ mov r1, r2
9660	9998	bl FlashEraseBlocks
9661		- mov r1, #1
9662		- mov r3, r1
9663		- ldr r0, .L1756+12
9664		- mov r2, r1
	9999	+ mov r3, #1
	10000	+ mov r0, fp
	10001	+ mov r2, r3
	10002	+ mov r1, r3
9665	10003	bl FlashProgPages
9666	10004	ldr r3, [r4, #-1276]
9667	10005	cmn r3, #1
9668		- bne .L1737
9669		- uxth r0, fp
	10006	+ bne .L1718
	10007	+ uxth r0, r6
9670	10008	bl FtlBbmMapBadBlock
9671		- b .L1738
9672		-.L1737:
9673		- uxth r0, fp
9674		- add r5, r5, #1
	10009	+ b .L1719
	10010	+.L1724:
9675	10011	bl FtlBbmMapBadBlock
9676		- add r8, r8, #4
9677		- b .L1735
9678		-.L1754:
9679		- add r6, r6, #60
9680		- mov r4, #0
9681		-.L1742:
	10012	+ b .L1723
	10013	+.L1727:
9682	10014	ldrh r3, [r6]
9683		- uxth r0, r4
9684		- add r4, r4, #1
9685		- cmp r3, r0
9686		- bls .L1755
9687		- bl FtlBbmMapBadBlock
9688		- b .L1742
9689		-.L1755:
9690		- ldr r6, .L1756+28
9691		- movw r8, #65535
9692		- ldrh r4, [r6, #12]
9693		- sub r4, r4, #1
9694		- uxth r4, r4
9695		-.L1744:
9696		- ldrh r3, [r6, #12]
9697		- ldr r5, .L1756+28
9698		- sub r3, r3, #48
9699		- cmp r4, r3
9700		- ble .L1748
9701		- mov r0, r4
9702		- bl FtlBbmIsBadBlock
9703		- cmp r0, #1
9704		- beq .L1745
9705		- mov r0, r4
9706		- bl FlashTestBlk
9707		- cmp r0, #0
9708		- beq .L1746
9709		- mov r0, r4
9710		- bl FtlBbmMapBadBlock
9711		- b .L1745
9712		-.L1746:
9713		- ldrh r3, [r6]
9714		- cmp r3, r8
9715		- streqh r4, [r6] @ movhi
9716		-.L1747:
9717		- strneh r4, [r5, #4] @ movhi
9718		- bne .L1748
9719		-.L1745:
9720		- sub r4, r4, #1
9721		- uxth r4, r4
9722		- b .L1744
9723		-.L1748:
9724		- ldr r3, .L1756+32
9725		- mov r4, #0
9726		- ldr r0, [r7, #-1492]
9727		- mov r1, #1
9728		- str r4, [r7, #-1340]
	10015	+ cmp r3, r7
	10016	+ strheq r5, [r6] @ movhi
	10017	+ beq .L1726
	10018	+.L1728:
	10019	+ strh r5, [r6, #4] @ movhi
	10020	+.L1729:
	10021	+ ldrh r3, [r8, #-4]
	10022	+ sub r5, r8, #4
	10023	+ ldr r0, [r4, #-1488]
	10024	+ mov r6, #0
	10025	+ str r6, [r4, #-1340]
9729	10026	mov r2, #2
9730		- ldrh r3, [r3, #-4]
9731		- strh r4, [r5, #2] @ movhi
9732		- mov r3, r3, asl #10
	10027	+ mov r1, #1
	10028	+ strh r6, [r8, #-2] @ movhi
	10029	+ lsl r3, r3, #10
9733	10030	str r3, [r0, #4]
9734	10031	ldrh r3, [r5, #4]
9735		- mov r3, r3, asl #10
	10032	+ lsl r3, r3, #10
9736	10033	str r3, [r0, #40]
9737	10034	bl FlashEraseBlocks
9738		- ldr r3, .L1756+32
9739		- ldrh r0, [r3, #-4]
	10035	+ ldrh r0, [r8, #-4]
9740	10036	bl FtlBbmMapBadBlock
9741	10037	ldrh r0, [r5, #4]
9742	10038	bl FtlBbmMapBadBlock
9743	10039	bl FtlBbmTblFlush
9744		- ldr r3, [r7, #-1340]
	10040	+ ldr r3, [r4, #-1340]
9745	10041	ldrh r2, [r5, #4]
	10042	+ strh r6, [r8, #-2] @ movhi
9746	10043	add r3, r3, #1
9747		- str r3, [r7, #-1340]
9748		- ldr r3, .L1756+32
9749		- ldr r1, .L1756+32
9750		- strh r4, [r5, #2] @ movhi
9751		- ldrh r3, [r3, #-4]
9752		- strh r2, [r1, #-4] @ movhi
	10044	+ str r3, [r4, #-1340]
	10045	+ ldrh r3, [r8, #-4]
	10046	+ strh r2, [r8, #-4] @ movhi
9753	10047	strh r3, [r5, #4] @ movhi
9754	10048	bl FtlBbmTblFlush
9755		-.L1734:
	10049	+.L1715:
9756	10050	mov r0, #0
9757		- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
9758		-.L1757:
	10051	+ add sp, sp, #12
	10052	+ @ sp needed
	10053	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	10054	+.L1736:
9759	10055	.align 2
9760		-.L1756:
	10056	+.L1735:
9761	10057	.word .LANCHOR2
9762	10058	.word .LANCHOR2-1320
9763		- .word .LANCHOR2-1714
9764		- .word .LANCHOR2-1276
9765		- .word .LANCHOR2-1670
9766		- .word -3872
9767		- .word .LANCHOR2-1352
9768		- .word .LANCHOR2-1348
9769		- .word .LANCHOR2-1344
	10059	+ .word .LANCHOR2-1710
	10060	+ .word .LANCHOR2-1652
	10061	+ .word .LANCHOR2-1664
9770	10062	.fnend
9771	10063	.size FtlMakeBbt, .-FtlMakeBbt
9772	10064	.align 2
9773	10065	.global V2P_block
	10066	+ .syntax unified
	10067	+ .arm
	10068	+ .fpu softvfp
9774	10069	.type V2P_block, %function
9775	10070	V2P_block:
9776	10071	.fnstart
9777	10072	@ args = 0, pretend = 0, frame = 0
9778	10073	@ frame_needed = 0, uses_anonymous_args = 0
9779		- stmfd sp!, {r3, r4, r5, r6, r7, lr}
9780		- .save {r3, r4, r5, r6, r7, lr}
	10074	+ push {r4, r5, r6, r7, r8, lr}
	10075	+ .save {r4, r5, r6, r7, r8, lr}
9781	10076	mov r5, r1
9782		- ldr r4, .L1760
	10077	+ ldr r4, .L1739
9783	10078	mov r7, r0
9784		- sub r3, r4, #1712
	10079	+ sub r3, r4, #1696
9785	10080	sub r4, r4, #1664
9786		- ldrh r6, [r3]
9787		- mov r1, r6
9788		- bl __aeabi_uidivmod
9789		- mov r0, r7
9790		- smlabb r5, r5, r6, r1
	10081	+ ldrh r6, [r3, #-12]
9791	10082	mov r1, r6
9792	10083	bl __aeabi_uidiv
9793		- ldrh r3, [r4, #-6]
9794		- smlabb r0, r3, r0, r5
	10084	+ ldrh r4, [r4, #-4]
	10085	+ smulbb r5, r6, r5
	10086	+ mov r1, r6
	10087	+ smulbb r4, r4, r0
	10088	+ mov r0, r7
	10089	+ bl __aeabi_uidivmod
	10090	+ add r0, r5, r1
	10091	+ add r0, r4, r0
9795	10092	uxth r0, r0
9796		- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
9797		-.L1761:
	10093	+ pop {r4, r5, r6, r7, r8, pc}
	10094	+.L1740:
9798	10095	.align 2
9799		-.L1760:
	10096	+.L1739:
9800	10097	.word .LANCHOR2
9801	10098	.fnend
9802	10099	.size V2P_block, .-V2P_block
9803	10100	.align 2
9804	10101	.global P2V_plane
	10102	+ .syntax unified
	10103	+ .arm
	10104	+ .fpu softvfp
9805	10105	.type P2V_plane, %function
9806	10106	P2V_plane:
9807	10107	.fnstart
9808	10108	@ args = 0, pretend = 0, frame = 0
9809	10109	@ frame_needed = 0, uses_anonymous_args = 0
9810		- ldr r3, .L1764
9811		- stmfd sp!, {r4, r5, r6, lr}
	10110	+ ldr r3, .L1743
	10111	+ push {r4, r5, r6, lr}
9812	10112	.save {r4, r5, r6, lr}
9813		- sub r2, r3, #1712
9814		- sub r3, r3, #1664
9815	10113	mov r6, r0
9816		- ldrh r5, [r2]
9817		- ldrh r1, [r3, #-6]
	10114	+ sub r2, r3, #1696
	10115	+ sub r3, r3, #1664
	10116	+ ldrh r5, [r2, #-12]
	10117	+ ldrh r1, [r3, #-4]
9818	10118	bl __aeabi_uidiv
9819	10119	mov r1, r5
9820	10120	smulbb r4, r0, r5
..	..	@@ -9822,40 +10122,46 @@
9822	10122	bl __aeabi_uidivmod
9823	10123	add r1, r4, r1
9824	10124	uxth r0, r1
9825		- ldmfd sp!, {r4, r5, r6, pc}
9826		-.L1765:
	10125	+ pop {r4, r5, r6, pc}
	10126	+.L1744:
9827	10127	.align 2
9828		-.L1764:
	10128	+.L1743:
9829	10129	.word .LANCHOR2
9830	10130	.fnend
9831	10131	.size P2V_plane, .-P2V_plane
9832	10132	.align 2
9833	10133	.global P2V_block_in_plane
	10134	+ .syntax unified
	10135	+ .arm
	10136	+ .fpu softvfp
9834	10137	.type P2V_block_in_plane, %function
9835	10138	P2V_block_in_plane:
9836	10139	.fnstart
9837	10140	@ args = 0, pretend = 0, frame = 0
9838	10141	@ frame_needed = 0, uses_anonymous_args = 0
9839		- stmfd sp!, {r4, lr}
	10142	+ push {r4, lr}
9840	10143	.save {r4, lr}
9841		- ldr r4, .L1768
	10144	+ ldr r4, .L1747
9842	10145	sub r3, r4, #1664
9843		- sub r4, r4, #1712
9844		- ldrh r1, [r3, #-6]
	10146	+ sub r4, r4, #1696
	10147	+ ldrh r1, [r3, #-4]
9845	10148	bl __aeabi_uidivmod
9846	10149	uxth r0, r1
9847		- ldrh r1, [r4]
	10150	+ ldrh r1, [r4, #-12]
9848	10151	bl __aeabi_uidiv
9849	10152	uxth r0, r0
9850		- ldmfd sp!, {r4, pc}
9851		-.L1769:
	10153	+ pop {r4, pc}
	10154	+.L1748:
9852	10155	.align 2
9853		-.L1768:
	10156	+.L1747:
9854	10157	.word .LANCHOR2
9855	10158	.fnend
9856	10159	.size P2V_block_in_plane, .-P2V_block_in_plane
9857	10160	.align 2
9858	10161	.global ftl_cmp_data_ver
	10162	+ .syntax unified
	10163	+ .arm
	10164	+ .fpu softvfp
9859	10165	.type ftl_cmp_data_ver, %function
9860	10166	ftl_cmp_data_ver:
9861	10167	.fnstart
..	..	@@ -9863,14 +10169,14 @@
9863	10169	@ frame_needed = 0, uses_anonymous_args = 0
9864	10170	@ link register save eliminated.
9865	10171	cmp r0, r1
9866		- bls .L1771
9867		- rsb r0, r1, r0
	10172	+ bls .L1750
	10173	+ sub r0, r0, r1
9868	10174	cmp r0, #-2147483648
9869	10175	movhi r0, #0
9870	10176	movls r0, #1
9871	10177	bx lr
9872		-.L1771:
9873		- rsb r0, r0, r1
	10178	+.L1750:
	10179	+ sub r0, r1, r0
9874	10180	cmp r0, #-2147483648
9875	10181	movls r0, #0
9876	10182	movhi r0, #1
..	..	@@ -9879,843 +10185,863 @@
9879	10185	.size ftl_cmp_data_ver, .-ftl_cmp_data_ver
9880	10186	.align 2
9881	10187	.global FtlGetLastWrittenPage
	10188	+ .syntax unified
	10189	+ .arm
	10190	+ .fpu softvfp
9882	10191	.type FtlGetLastWrittenPage, %function
9883	10192	FtlGetLastWrittenPage:
9884	10193	.fnstart
9885	10194	@ args = 0, pretend = 0, frame = 104
9886	10195	@ frame_needed = 0, uses_anonymous_args = 0
9887		- ldr r3, .L1785
	10196	+ ldr r3, .L1764
9888	10197	cmp r1, #1
9889		- stmfd sp!, {r4, r5, r6, r7, r8, lr}
	10198	+ push {r4, r5, r6, r7, r8, lr}
9890	10199	.save {r4, r5, r6, r7, r8, lr}
	10200	+ lsl r8, r0, #10
9891	10201	.pad #104
9892	10202	sub sp, sp, #104
9893		- ldreqh r4, [r3, #-2]
9894		- mov r8, r1
9895		- ldrneh r4, [r3, #-4]
9896		- mov r6, r0, asl #10
	10203	+ mov r2, r1
	10204	+ mov r7, r1
	10205	+ ldrheq r5, [r3]
	10206	+ mov r6, #0
	10207	+ ldrhne r5, [r3, #-2]
9897	10208	add r3, sp, #40
9898		- add r0, sp, #4
9899		- sub r5, r4, #1
9900	10209	str r3, [sp, #16]
9901	10210	mov r1, #1
9902		- mov r2, r8
9903		- uxth r5, r5
9904		- mov r7, #0
9905		- str r7, [sp, #12]
9906		- sxth r3, r5
9907		- orr r3, r3, r6
9908		- str r3, [sp, #8]
9909		- bl FlashReadPages
9910		- ldr r3, [sp, #40]
9911		- cmn r3, #1
9912		- bne .L1776
9913		-.L1777:
9914		- sxth r4, r7
9915		- sxth r3, r5
9916		- cmp r4, r3
9917		- bgt .L1776
9918		- add r4, r4, r3
9919	10211	add r0, sp, #4
9920		- mov r1, #1
9921		- mov r2, r8
9922		- add r4, r4, r4, lsr #31
9923		- mov r4, r4, asr #1
9924		- sxth r3, r4
9925		- orr r3, r3, r6
	10212	+ str r6, [sp, #12]
	10213	+ sub r5, r5, #1
	10214	+ sxth r5, r5
	10215	+ orr r3, r5, r8
9926	10216	str r3, [sp, #8]
9927	10217	bl FlashReadPages
9928	10218	ldr r3, [sp, #40]
9929	10219	cmn r3, #1
9930		- bne .L1778
	10220	+ bne .L1755
	10221	+.L1756:
	10222	+ cmp r6, r5
	10223	+ ble .L1759
	10224	+.L1755:
	10225	+ mov r0, r5
	10226	+ add sp, sp, #104
	10227	+ @ sp needed
	10228	+ pop {r4, r5, r6, r7, r8, pc}
	10229	+.L1759:
	10230	+ add r3, r6, r5
	10231	+ mov r2, r7
	10232	+ add r3, r3, r3, lsr #31
	10233	+ mov r1, #1
	10234	+ add r0, sp, #4
	10235	+ asr r4, r3, #1
	10236	+ sxth r3, r4
	10237	+ orr r3, r3, r8
	10238	+ str r3, [sp, #8]
	10239	+ bl FlashReadPages
	10240	+ ldr r3, [sp, #40]
	10241	+ cmn r3, #1
	10242	+ bne .L1757
9931	10243	ldr r3, [sp, #44]
9932	10244	cmn r3, #1
9933		- bne .L1778
	10245	+ bne .L1757
9934	10246	ldr r3, [sp, #4]
9935	10247	cmn r3, #1
9936	10248	subne r4, r4, #1
9937		- uxthne r5, r4
9938		- bne .L1777
9939		-.L1778:
9940		- add r3, r4, #1
9941		- uxth r7, r3
9942		- b .L1777
9943		-.L1776:
9944		- sxth r0, r5
9945		- add sp, sp, #104
9946		- @ sp needed
9947		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
9948		-.L1786:
	10249	+ sxthne r5, r4
	10250	+ bne .L1756
	10251	+.L1757:
	10252	+ add r4, r4, #1
	10253	+ sxth r6, r4
	10254	+ b .L1756
	10255	+.L1765:
9949	10256	.align 2
9950		-.L1785:
	10257	+.L1764:
9951	10258	.word .LANCHOR2-1664
9952	10259	.fnend
9953	10260	.size FtlGetLastWrittenPage, .-FtlGetLastWrittenPage
9954	10261	.align 2
9955	10262	.global FtlLoadBbt
	10263	+ .syntax unified
	10264	+ .arm
	10265	+ .fpu softvfp
9956	10266	.type FtlLoadBbt, %function
9957	10267	FtlLoadBbt:
9958	10268	.fnstart
9959	10269	@ args = 0, pretend = 0, frame = 0
9960	10270	@ frame_needed = 0, uses_anonymous_args = 0
9961		- stmfd sp!, {r4, r5, r6, r7, r8, lr}
	10271	+ push {r4, r5, r6, r7, r8, lr}
9962	10272	.save {r4, r5, r6, r7, r8, lr}
9963		- ldr r4, .L1820
9964		- ldr r3, [r4, #-1476]
9965		- mov r7, r4
9966		- ldr r6, [r4, #-1444]
	10273	+ ldr r4, .L1798
	10274	+ ldr r3, [r4, #-1472]
	10275	+ sub r7, r4, #1664
	10276	+ ldr r6, [r4, #-1440]
	10277	+ sub r8, r4, #1264
	10278	+ sub r8, r8, #12
9967	10279	str r3, [r4, #-1268]
9968	10280	str r6, [r4, #-1264]
9969	10281	bl FtlBbtMemInit
9970		- sub r3, r4, #1664
9971		- sub r8, r3, #6
9972		- ldrh r5, [r3, #-6]
	10282	+ ldrh r5, [r7, #-4]
9973	10283	sub r5, r5, #1
9974	10284	uxth r5, r5
9975		-.L1788:
9976		- ldrh r3, [r8]
	10285	+.L1767:
	10286	+ ldrh r3, [r7, #-4]
9977	10287	sub r3, r3, #48
9978	10288	cmp r5, r3
9979		- ble .L1791
9980		- mov r1, #1
9981		- ldr r0, .L1820+4
9982		- mov r2, r1
9983		- mov r3, r5, asl #10
9984		- str r3, [r7, #-1272]
	10289	+ ble .L1770
	10290	+ lsl r3, r5, #10
	10291	+ mov r2, #1
	10292	+ mov r1, r2
	10293	+ mov r0, r8
	10294	+ str r3, [r4, #-1272]
9985	10295	bl FlashReadPages
9986		- ldr r3, [r7, #-1276]
	10296	+ ldr r3, [r4, #-1276]
9987	10297	cmn r3, #1
9988		- bne .L1789
9989		- ldr r3, [r7, #-1272]
9990		- mov r1, #1
9991		- ldr r0, .L1820+4
9992		- mov r2, r1
	10298	+ bne .L1768
	10299	+ ldr r3, [r4, #-1272]
	10300	+ mov r2, #1
	10301	+ mov r1, r2
	10302	+ mov r0, r8
9993	10303	add r3, r3, #1
9994		- str r3, [r7, #-1272]
	10304	+ str r3, [r4, #-1272]
9995	10305	bl FlashReadPages
9996		-.L1789:
9997		- ldr r2, [r4, #-1276]
9998		- ldr r3, .L1820
9999		- cmn r2, #1
10000		- beq .L1790
10001		- ldrh r1, [r6]
10002		- movw r2, #61649
10003		- cmp r1, r2
10004		- bne .L1790
10005		- sub r2, r3, #1344
10006		- strh r5, [r2, #-4] @ movhi
10007		- ldr r2, [r6, #4]
10008		- str r2, [r3, #-1340]
10009		- ldr r3, .L1820+8
10010		- ldrh r2, [r6, #8]
10011		- strh r2, [r3, #4] @ movhi
10012		- b .L1791
10013		-.L1790:
10014		- sub r5, r5, #1
10015		- uxth r5, r5
10016		- b .L1788
10017		-.L1791:
10018		- ldr r8, .L1820
10019		- movw r2, #65535
10020		- sub r7, r8, #1344
10021		- sub r5, r7, #4
10022		- ldrh r3, [r7, #-4]
10023		- cmp r3, r2
10024		- beq .L1805
10025		- ldrh r3, [r5, #4]
10026		- cmp r3, r2
10027		- beq .L1795
10028		- mov r1, #1
10029		- add r0, r5, #72
10030		- mov r2, r1
10031		- mov r3, r3, asl #10
10032		- str r3, [r8, #-1272]
10033		- bl FlashReadPages
10034		- ldr r3, [r8, #-1276]
	10306	+.L1768:
	10307	+ ldr r3, [r4, #-1276]
10035	10308	cmn r3, #1
10036		- beq .L1795
	10309	+ beq .L1769
10037	10310	ldrh r2, [r6]
10038	10311	movw r3, #61649
10039	10312	cmp r2, r3
10040		- bne .L1795
10041		- ldr r3, [r6, #4]
10042		- ldr r2, [r8, #-1340]
	10313	+ bne .L1769
	10314	+ ldr r2, [r6, #4]
	10315	+ ldr r3, .L1798+4
	10316	+ str r2, [r4, #-1340]
	10317	+ ldrh r2, [r6, #8]
	10318	+ strh r5, [r3, #-4] @ movhi
	10319	+ strh r2, [r3] @ movhi
	10320	+.L1770:
	10321	+ ldr r5, .L1798+4
	10322	+ movw r2, #65535
	10323	+ ldrh r3, [r5, #-4]
	10324	+ sub r7, r5, #4
10043	10325	cmp r3, r2
10044		- strhi r3, [r8, #-1340]
10045		- ldrhih r2, [r5, #4]
10046		- ldrhih r3, [r6, #8]
10047		- strhih r2, [r7, #-4] @ movhi
10048		- strhih r3, [r5, #4] @ movhi
10049		-.L1795:
10050		- ldrh r0, [r7, #-4]
10051		- mov r1, #1
10052		- bl FtlGetLastWrittenPage
10053		- movw r8, #61649
10054		- uxth r7, r0
10055		- add r0, r0, #1
10056		- strh r0, [r5, #2] @ movhi
10057		-.L1797:
10058		- sxth r3, r7
10059		- cmp r3, #0
10060		- blt .L1802
10061		- ldrh r2, [r5]
10062		- mov r1, #1
10063		- ldr r0, .L1820+4
10064		- orr r3, r3, r2, asl #10
	10326	+ beq .L1784
	10327	+ ldrh r3, [r7, #4]
	10328	+ cmp r3, r2
	10329	+ beq .L1774
	10330	+ lsl r3, r3, #10
	10331	+ mov r2, #1
	10332	+ mov r1, r2
	10333	+ add r0, r5, #68
10065	10334	str r3, [r4, #-1272]
10066		- ldr r3, [r4, #-1476]
10067		- mov r2, r1
	10335	+ bl FlashReadPages
	10336	+ ldr r3, [r4, #-1276]
	10337	+ cmn r3, #1
	10338	+ beq .L1774
	10339	+ ldrh r2, [r6]
	10340	+ movw r3, #61649
	10341	+ cmp r2, r3
	10342	+ bne .L1774
	10343	+ ldr r3, [r6, #4]
	10344	+ ldr r2, [r4, #-1340]
	10345	+ cmp r3, r2
	10346	+ ldrhhi r2, [r7, #4]
	10347	+ strhi r3, [r4, #-1340]
	10348	+ ldrhhi r3, [r6, #8]
	10349	+ strhhi r2, [r5, #-4] @ movhi
	10350	+ strhhi r3, [r7, #4] @ movhi
	10351	+.L1774:
	10352	+ ldr r8, .L1798+8
	10353	+ mov r1, #1
	10354	+ ldrh r0, [r5, #-4]
	10355	+ bl FtlGetLastWrittenPage
	10356	+ sxth r7, r0
	10357	+ add r0, r0, #1
	10358	+ strh r0, [r5, #-2] @ movhi
	10359	+.L1776:
	10360	+ cmp r7, #0
	10361	+ blt .L1781
	10362	+ ldrh r3, [r5, #-4]
	10363	+ mov r2, #1
	10364	+ mov r1, r2
	10365	+ mov r0, r8
	10366	+ orr r3, r7, r3, lsl #10
	10367	+ str r3, [r4, #-1272]
	10368	+ ldr r3, [r4, #-1472]
10068	10369	str r3, [r4, #-1268]
10069	10370	bl FlashReadPages
10070	10371	ldr r3, [r4, #-1276]
10071	10372	cmn r3, #1
10072		- beq .L1798
10073		- ldrh r3, [r6]
10074		- cmp r3, r8
10075		- bne .L1798
10076		-.L1802:
10077		- ldrh r2, [r6, #10]
	10373	+ beq .L1777
	10374	+ ldrh r2, [r6]
	10375	+ movw r3, #61649
	10376	+ cmp r2, r3
	10377	+ bne .L1777
	10378	+.L1781:
	10379	+ ldrh r3, [r6, #10]
10078	10380	ldrh r0, [r6, #12]
10079		- ldr r3, .L1820
10080		- strh r2, [r5, #6] @ movhi
10081		- movw r2, #65535
10082		- cmp r0, r2
10083		- bne .L1799
10084		- b .L1800
10085		-.L1798:
10086		- sub r7, r7, #1
10087		- uxth r7, r7
10088		- b .L1797
10089		-.L1799:
10090		- ldr r2, [r3, #-1740]
10091		- cmp r0, r2
10092		- beq .L1800
10093		- sub r3, r3, #1712
10094		- ldrh r3, [r3, #-14]
10095		- mov r3, r3, lsr #2
	10381	+ strh r3, [r5, #2] @ movhi
	10382	+ movw r3, #65535
10096	10383	cmp r0, r3
10097		- cmpcc r2, r3
10098		- bcs .L1800
10099		- bl FtlSysBlkNumInit
10100		-.L1800:
10101		- ldr r5, .L1820+12
10102		- mov r4, #0
10103		- ldr r7, .L1820
10104		- ldr r6, .L1820+16
10105		- sub r8, r5, #28
10106		-.L1803:
10107		- ldrh r3, [r6]
10108		- cmp r4, r3
10109		- bcs .L1819
10110		- ldrh r2, [r8]
10111		- ldr r1, [r7, #-1268]
10112		- ldr r0, [r5, #4]!
10113		- mov r2, r2, asl #2
10114		- mla r1, r4, r2, r1
10115		- bl ftl_memcpy
10116		- add r4, r4, #1
10117		- b .L1803
10118		-.L1819:
	10384	+ bne .L1778
	10385	+.L1779:
	10386	+ add r7, r5, #20
	10387	+ mov r6, #0
	10388	+.L1782:
	10389	+ ldr r3, .L1798+12
	10390	+ ldrh r3, [r3]
	10391	+ cmp r6, r3
	10392	+ bcc .L1783
10119	10393	mov r0, #0
10120		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
10121		-.L1805:
	10394	+ pop {r4, r5, r6, r7, r8, pc}
	10395	+.L1769:
	10396	+ sub r5, r5, #1
	10397	+ uxth r5, r5
	10398	+ b .L1767
	10399	+.L1777:
	10400	+ sub r7, r7, #1
	10401	+ sxth r7, r7
	10402	+ b .L1776
	10403	+.L1778:
	10404	+ ldr r2, [r4, #-1736]
	10405	+ cmp r0, r2
	10406	+ beq .L1779
	10407	+ ldr r3, .L1798+16
	10408	+ ldrh r3, [r3, #-10]
	10409	+ lsr r3, r3, #2
	10410	+ cmp r2, r3
	10411	+ cmpcc r0, r3
	10412	+ bcs .L1779
	10413	+ bl FtlSysBlkNumInit
	10414	+ b .L1779
	10415	+.L1783:
	10416	+ ldrh r2, [r5, #-8]
	10417	+ ldr r1, [r4, #-1268]
	10418	+ ldr r0, [r7, #4]!
	10419	+ lsl r2, r2, #2
	10420	+ mla r1, r6, r2, r1
	10421	+ add r6, r6, #1
	10422	+ bl ftl_memcpy
	10423	+ b .L1782
	10424	+.L1784:
10122	10425	mvn r0, #0
10123		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
10124		-.L1821:
	10426	+ pop {r4, r5, r6, r7, r8, pc}
	10427	+.L1799:
10125	10428	.align 2
10126		-.L1820:
	10429	+.L1798:
10127	10430	.word .LANCHOR2
	10431	+ .word .LANCHOR2-1344
10128	10432	.word .LANCHOR2-1276
10129		- .word .LANCHOR2-1348
10130		- .word .LANCHOR2-1324
10131		- .word .LANCHOR2-1714
	10433	+ .word .LANCHOR2-1710
	10434	+ .word .LANCHOR2-1712
10132	10435	.fnend
10133	10436	.size FtlLoadBbt, .-FtlLoadBbt
10134	10437	.align 2
10135	10438	.global FtlFreeSysBlkQueueInit
	10439	+ .syntax unified
	10440	+ .arm
	10441	+ .fpu softvfp
10136	10442	.type FtlFreeSysBlkQueueInit, %function
10137	10443	FtlFreeSysBlkQueueInit:
10138	10444	.fnstart
10139	10445	@ args = 0, pretend = 0, frame = 0
10140	10446	@ frame_needed = 0, uses_anonymous_args = 0
10141		- ldr r3, .L1824
	10447	+ ldr r3, .L1802
10142	10448	mov r2, #2048
10143		- stmfd sp!, {r4, lr}
	10449	+ push {r4, lr}
10144	10450	.save {r4, lr}
10145	10451	mov r4, #0
10146		- strh r0, [r3, #-8] @ movhi
10147	10452	mov r1, r4
	10453	+ strh r0, [r3, #-8] @ movhi
10148	10454	mov r0, r3
10149	10455	strh r4, [r3, #-6] @ movhi
10150	10456	strh r4, [r3, #-4] @ movhi
10151	10457	strh r4, [r3, #-2] @ movhi
10152	10458	bl ftl_memset
10153	10459	mov r0, r4
10154		- ldmfd sp!, {r4, pc}
10155		-.L1825:
	10460	+ pop {r4, pc}
	10461	+.L1803:
10156	10462	.align 2
10157		-.L1824:
	10463	+.L1802:
10158	10464	.word .LANCHOR2-1232
10159	10465	.fnend
10160	10466	.size FtlFreeSysBlkQueueInit, .-FtlFreeSysBlkQueueInit
10161	10467	.align 2
10162	10468	.global FtlFreeSysBlkQueueEmpty
	10469	+ .syntax unified
	10470	+ .arm
	10471	+ .fpu softvfp
10163	10472	.type FtlFreeSysBlkQueueEmpty, %function
10164	10473	FtlFreeSysBlkQueueEmpty:
10165	10474	.fnstart
10166	10475	@ args = 0, pretend = 0, frame = 0
10167	10476	@ frame_needed = 0, uses_anonymous_args = 0
10168	10477	@ link register save eliminated.
10169		- ldr r3, .L1827
	10478	+ ldr r3, .L1805
10170	10479	ldrh r0, [r3, #6]
10171	10480	clz r0, r0
10172		- mov r0, r0, lsr #5
	10481	+ lsr r0, r0, #5
10173	10482	bx lr
10174		-.L1828:
	10483	+.L1806:
10175	10484	.align 2
10176		-.L1827:
	10485	+.L1805:
10177	10486	.word .LANCHOR2-1240
10178	10487	.fnend
10179	10488	.size FtlFreeSysBlkQueueEmpty, .-FtlFreeSysBlkQueueEmpty
10180	10489	.align 2
10181	10490	.global FtlFreeSysBlkQueueFull
	10491	+ .syntax unified
	10492	+ .arm
	10493	+ .fpu softvfp
10182	10494	.type FtlFreeSysBlkQueueFull, %function
10183	10495	FtlFreeSysBlkQueueFull:
10184	10496	.fnstart
10185	10497	@ args = 0, pretend = 0, frame = 0
10186	10498	@ frame_needed = 0, uses_anonymous_args = 0
10187	10499	@ link register save eliminated.
10188		- ldr r3, .L1830
	10500	+ ldr r3, .L1808
10189	10501	ldrh r0, [r3, #6]
10190	10502	sub r0, r0, #1024
10191	10503	clz r0, r0
10192		- mov r0, r0, lsr #5
	10504	+ lsr r0, r0, #5
10193	10505	bx lr
10194		-.L1831:
	10506	+.L1809:
10195	10507	.align 2
10196		-.L1830:
	10508	+.L1808:
10197	10509	.word .LANCHOR2-1240
10198	10510	.fnend
10199	10511	.size FtlFreeSysBlkQueueFull, .-FtlFreeSysBlkQueueFull
10200	10512	.align 2
10201	10513	.global FtlFreeSysBlkQueueIn
	10514	+ .syntax unified
	10515	+ .arm
	10516	+ .fpu softvfp
10202	10517	.type FtlFreeSysBlkQueueIn, %function
10203	10518	FtlFreeSysBlkQueueIn:
10204	10519	.fnstart
10205	10520	@ args = 0, pretend = 0, frame = 0
10206	10521	@ frame_needed = 0, uses_anonymous_args = 0
10207		- stmfd sp!, {r3, r4, r5, r6, r7, lr}
10208		- .save {r3, r4, r5, r6, r7, lr}
10209	10522	sub r3, r0, #1
10210	10523	movw r2, #65533
10211		- mov r7, r0
10212	10524	uxth r3, r3
10213	10525	cmp r3, r2
10214		- ldmhifd sp!, {r3, r4, r5, r6, r7, pc}
10215		- ldr r4, .L1842
10216		- ldr r5, .L1842+4
10217		- ldrh r3, [r4, #6]
10218		- cmp r3, #1024
10219		- ldmeqfd sp!, {r3, r4, r5, r6, r7, pc}
	10526	+ bxhi lr
	10527	+ push {r4, r5, r6, r7, r8, lr}
	10528	+ .save {r4, r5, r6, r7, r8, lr}
	10529	+ ldr r5, .L1823
	10530	+ sub r3, r5, #1232
	10531	+ ldrh r2, [r3, #-2]
	10532	+ mov r4, r3
	10533	+ cmp r2, #1024
	10534	+ popeq {r4, r5, r6, r7, r8, pc}
10220	10535	cmp r1, #0
10221		- beq .L1834
	10536	+ mov r6, r0
	10537	+ beq .L1812
10222	10538	ldr r3, [r5, #-1280]
10223	10539	cmp r3, #0
10224		- bne .L1834
	10540	+ bne .L1812
10225	10541	bl P2V_block_in_plane
10226		- mov r1, #1
10227		- mov r3, r7, asl #10
10228		- mov r2, r1
10229		- mov r6, r0
10230		- ldr r0, [r5, #-1492]
	10542	+ mov r7, r0
	10543	+ ldr r0, [r5, #-1488]
	10544	+ lsl r3, r6, #10
	10545	+ mov r2, #1
	10546	+ mov r1, r2
10231	10547	str r3, [r0, #4]
10232	10548	bl FlashEraseBlocks
10233		- ldr r1, [r5, #-1416]
10234		- mov r3, r6, asl #1
10235		- ldrh r2, [r1, r3]
	10549	+ ldr r2, [r5, #-1412]
	10550	+ lsl r0, r7, #1
	10551	+ ldrh r3, [r2, r0]
	10552	+ add r3, r3, #1
	10553	+ strh r3, [r2, r0] @ movhi
	10554	+ ldr r3, [r5, #-1572]
	10555	+ add r3, r3, #1
	10556	+ str r3, [r5, #-1572]
	10557	+.L1812:
	10558	+ ldrh r2, [r4, #-2]
	10559	+ sub r3, r4, #8
10236	10560	add r2, r2, #1
10237		- strh r2, [r1, r3] @ movhi
10238		- ldr r3, [r5, #-1576]
10239		- add r3, r3, #1
10240		- str r3, [r5, #-1576]
10241		-.L1834:
10242		- ldrh r3, [r4, #6]
10243		- add r3, r3, #1
10244		- strh r3, [r4, #6] @ movhi
10245		- ldrh r3, [r4, #4]
10246		- add r2, r4, r3, asl #1
10247		- add r3, r3, #1
10248		- ubfx r3, r3, #0, #10
10249		- strh r3, [r4, #4] @ movhi
10250		- strh r7, [r2, #8] @ movhi
10251		- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
10252		-.L1843:
	10561	+ strh r2, [r4, #-2] @ movhi
	10562	+ ldrh r2, [r4, #-4]
	10563	+ add r1, r3, r2, lsl #1
	10564	+ add r2, r2, #1
	10565	+ ubfx r2, r2, #0, #10
	10566	+ strh r6, [r1, #8] @ movhi
	10567	+ strh r2, [r4, #-4] @ movhi
	10568	+ pop {r4, r5, r6, r7, r8, pc}
	10569	+.L1824:
10253	10570	.align 2
10254		-.L1842:
10255		- .word .LANCHOR2-1240
	10571	+.L1823:
10256	10572	.word .LANCHOR2
10257	10573	.fnend
10258	10574	.size FtlFreeSysBlkQueueIn, .-FtlFreeSysBlkQueueIn
10259	10575	.align 2
10260	10576	.global FtlLowFormatEraseBlock
	10577	+ .syntax unified
	10578	+ .arm
	10579	+ .fpu softvfp
10261	10580	.type FtlLowFormatEraseBlock, %function
10262	10581	FtlLowFormatEraseBlock:
10263	10582	.fnstart
10264	10583	@ args = 0, pretend = 0, frame = 24
10265	10584	@ frame_needed = 0, uses_anonymous_args = 0
10266		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	10585	+ ldr r3, .L1870
	10586	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
10267	10587	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
10268	10588	.pad #28
10269	10589	sub sp, sp, #28
10270		- ldr r9, .L1894
10271		- ldr r5, [r9, #-1280]
10272		- ldrb r3, [r9, #-1874] @ zero_extendqisi2
10273		- cmp r5, #0
10274		- str r3, [sp, #16]
10275		- movne r0, #0
10276		- bne .L1845
10277		- ldrb r3, [r9, #-2744] @ zero_extendqisi2
10278		- mov fp, r1
10279		- mov r10, r5
10280		- mov r4, r5
10281		- mov r7, r9
10282		- mov r8, #36
	10590	+ ldr r2, [r3, #-1280]
	10591	+ cmp r2, #0
	10592	+ movne r4, #0
	10593	+ bne .L1825
	10594	+ mov r10, r3
	10595	+ ldrb r3, [r3, #-1870] @ zero_extendqisi2
	10596	+ ldrb r8, [r10, #-2740] @ zero_extendqisi2
	10597	+ mov r7, r1
	10598	+ mov fp, r2
	10599	+ mov r5, r2
	10600	+ mov r4, r2
	10601	+ mov r9, #36
10283	10602	str r0, [sp, #4]
10284		- str r3, [sp, #8]
10285		- str r0, [r9, #-1544]
10286		-.L1846:
10287		- ldr r3, .L1894+4
10288		- uxth r1, r10
10289		- ldr r6, .L1894
10290		- ldrh r0, [r3]
	10603	+ str r3, [sp, #16]
	10604	+ str r0, [r10, #-1540]
	10605	+.L1827:
	10606	+ ldr r1, .L1870+4
	10607	+ ldrh r0, [r1]
	10608	+ uxth r1, fp
10291	10609	cmp r0, r1
10292		- bls .L1889
10293		- mul r0, r8, r1
10294		- ldr ip, [r7, #-1492]
10295		- add r1, r7, r1
	10610	+ bhi .L1831
	10611	+ cmp r5, #0
	10612	+ beq .L1825
	10613	+ adds r8, r8, #0
	10614	+ mov r6, #0
	10615	+ movne r8, #1
	10616	+ mov r2, r5
	10617	+ mov r1, r8
	10618	+ ldr r0, [r10, #-1488]
	10619	+ strb r6, [r10, #-1870]
	10620	+ mov r9, #36
	10621	+ bl FlashEraseBlocks
	10622	+ ldrb r3, [sp, #16] @ zero_extendqisi2
	10623	+ strb r3, [r10, #-1870]
	10624	+.L1833:
	10625	+ uxth r2, r6
	10626	+ cmp r5, r2
	10627	+ bhi .L1835
	10628	+ cmp r7, #0
	10629	+ bne .L1836
	10630	+ uxth r8, r8
	10631	+ mov r3, #6
	10632	+ str r3, [sp, #12]
	10633	+ mov r3, #1
	10634	+ str r3, [sp, #8]
	10635	+.L1837:
	10636	+ ldr r5, .L1870
	10637	+ mov fp, #0
	10638	+.L1846:
	10639	+ mov r10, #0
	10640	+ mov r6, r10
	10641	+.L1838:
	10642	+ ldr r3, .L1870+8
	10643	+ ldrh r1, [r3, #-4]
	10644	+ uxth r3, r10
	10645	+ cmp r1, r3
	10646	+ bhi .L1841
	10647	+ cmp r6, #0
	10648	+ beq .L1825
	10649	+ mov r3, #1
	10650	+ mov r2, r8
	10651	+ mov r9, #0
	10652	+ mov r1, r6
	10653	+ ldr r0, [r5, #-1488]
	10654	+ strb r9, [r5, #-1870]
	10655	+ bl FlashProgPages
	10656	+ ldrb r3, [sp, #16] @ zero_extendqisi2
	10657	+ mov r2, #36
	10658	+ strb r3, [r5, #-1870]
	10659	+.L1843:
	10660	+ uxth r3, r9
	10661	+ cmp r6, r3
	10662	+ bhi .L1845
	10663	+ ldr r3, [sp, #12]
	10664	+ add fp, fp, r3
	10665	+ ldr r3, [sp, #8]
	10666	+ uxth fp, fp
	10667	+ cmp r3, fp
	10668	+ bhi .L1846
	10669	+ mov r9, #0
	10670	+ mov fp, #36
	10671	+.L1847:
	10672	+ uxth r3, r9
	10673	+ cmp r6, r3
	10674	+ bhi .L1849
	10675	+ ldr r3, [sp, #4]
	10676	+ adds r7, r7, #0
	10677	+ movne r7, #1
	10678	+ cmp r3, #63
	10679	+ movhi r10, r7
	10680	+ orrls r10, r7, #1
	10681	+ cmp r10, #0
	10682	+ beq .L1825
	10683	+ mov r2, r6
	10684	+ mov r1, r8
	10685	+ ldr r0, [r5, #-1488]
	10686	+ bl FlashEraseBlocks
	10687	+.L1825:
	10688	+ mov r0, r4
	10689	+ add sp, sp, #28
	10690	+ @ sp needed
	10691	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	10692	+.L1831:
	10693	+ uxth r1, fp
	10694	+ ldr ip, [r10, #-1488]
10296	10695	mov r3, #0
	10696	+ mul r0, r9, r1
10297	10697	str r3, [ip, r0]
10298		- ldrb r0, [r1, #-1708] @ zero_extendqisi2
	10698	+ add r0, r10, r1
	10699	+ ldrb r0, [r0, #-1706] @ zero_extendqisi2
10299	10700	ldr r1, [sp, #4]
10300	10701	bl V2P_block
10301		- cmp fp, #0
	10702	+ cmp r7, #0
10302	10703	mov r6, r0
10303		- beq .L1847
	10704	+ beq .L1828
10304	10705	bl IsBlkInVendorPart
10305	10706	cmp r0, #0
10306		- bne .L1848
10307		-.L1847:
	10707	+ bne .L1829
	10708	+.L1828:
10308	10709	mov r0, r6
10309	10710	bl FtlBbmIsBadBlock
10310	10711	cmp r0, #0
10311	10712	addne r4, r4, #1
10312	10713	uxthne r4, r4
10313		- bne .L1848
10314		- ldr r3, .L1894+8
10315		- mov r6, r6, asl #10
10316		- ldr ip, [r9, #-1492]
10317		- ldrh r1, [r3]
10318		- mla ip, r8, r5, ip
10319		- mul r1, r1, r5
	10714	+ bne .L1829
	10715	+ ldr r1, .L1870+12
	10716	+ lsl r6, r6, #10
	10717	+ ldr ip, [r10, #-1488]
	10718	+ ldrh r1, [r1]
	10719	+ mla ip, r9, r5, ip
	10720	+ mul r1, r5, r1
10320	10721	add r5, r5, #1
10321	10722	uxth r5, r5
10322		- cmp r1, #0
10323	10723	str r0, [ip, #8]
10324		- add r0, r1, #3
10325	10724	str r6, [ip, #4]
	10725	+ add r0, r1, #3
	10726	+ cmp r1, #0
10326	10727	movlt r1, r0
10327		- ldr r0, [r9, #-1440]
	10728	+ ldr r0, [r10, #-1436]
10328	10729	bic r1, r1, #3
10329	10730	add r1, r0, r1
10330	10731	str r1, [ip, #12]
10331		-.L1848:
10332		- add r10, r10, #1
10333		- b .L1846
10334		-.L1889:
10335		- cmp r5, #0
10336		- beq .L1869
10337		- ldr r3, [sp, #8]
10338		- mov r2, r5
10339		- ldr r0, [r6, #-1492]
10340		- mov r8, #0
10341		- adds r7, r3, #0
10342		- strb r8, [r6, #-1874]
10343		- movne r7, #1
10344		- mov r1, r7
10345		- bl FlashEraseBlocks
10346		- ldrb r3, [sp, #16] @ zero_extendqisi2
10347		- strb r3, [r6, #-1874]
10348		- mov r6, #36
10349		-.L1852:
10350		- uxth r2, r8
10351		- cmp r2, r5
10352		- bcs .L1890
10353		- mul r2, r6, r8
10354		- ldr r1, [r9, #-1492]
10355		- add r0, r1, r2
	10732	+.L1829:
	10733	+ add fp, fp, #1
	10734	+ b .L1827
	10735	+.L1835:
	10736	+ mul r2, r9, r6
	10737	+ ldr r1, [r10, #-1488]
	10738	+ add ip, r1, r2
10356	10739	ldr r2, [r1, r2]
10357	10740	cmn r2, #1
10358		- bne .L1853
10359		- ldr r0, [r0, #4]
	10741	+ bne .L1834
	10742	+ ldr r0, [ip, #4]
10360	10743	add r4, r4, #1
10361		- ubfx r0, r0, #10, #16
10362	10744	uxth r4, r4
	10745	+ ubfx r0, r0, #10, #16
10363	10746	bl FtlBbmMapBadBlock
10364		-.L1853:
10365		- add r8, r8, #1
10366		- b .L1852
10367		-.L1890:
10368		- cmp fp, #0
10369		- bne .L1855
10370		- mov r3, #6
10371		- uxth r6, r7
10372		- str r3, [sp, #12]
10373		- mov r3, #1
	10747	+.L1834:
	10748	+ add r6, r6, #1
	10749	+ b .L1833
	10750	+.L1836:
	10751	+ ldr r2, .L1870+16
	10752	+ ldrh r3, [r2]
10374	10753	str r3, [sp, #8]
10375		- b .L1856
10376		-.L1855:
10377		- ldr r2, .L1894+12
10378		- ldrh r3, [r2, #-2]
10379		- str r3, [sp, #8]
10380		- ldrb r3, [r9, #-2744] @ zero_extendqisi2
	10754	+ ldrb r3, [r10, #-2740] @ zero_extendqisi2
10381	10755	cmp r3, #0
10382	10756	ldreq r3, [sp, #8]
10383		- moveq r6, #1
10384		- movne r6, #1
10385		- strne r6, [sp, #12]
10386		- moveq r3, r3, lsr #2
	10757	+ movne r8, #1
	10758	+ moveq r8, #1
	10759	+ strne r8, [sp, #12]
	10760	+ lsreq r3, r3, #2
10387	10761	streq r3, [sp, #12]
10388		-.L1856:
10389		- ldr r10, .L1894
10390		- mov r7, #0
10391		-.L1865:
10392		- mov r8, #0
10393		- mov r5, r8
10394		-.L1857:
10395		- ldr r3, .L1894+4
10396		- ldr r9, .L1894
10397		- ldrh r2, [r3]
10398		- uxth r3, r8
10399		- cmp r2, r3
10400		- bls .L1891
	10762	+ b .L1837
	10763	+.L1841:
	10764	+ uxth r3, r10
10401	10765	mov r2, #36
10402		- ldr r1, [r10, #-1492]
10403		- mul r2, r2, r3
10404		- add r3, r10, r3
10405		- mov r0, #0
10406		- str r0, [r1, r2]
	10766	+ ldr r0, [r5, #-1488]
	10767	+ mul r1, r2, r3
	10768	+ mov r2, #0
	10769	+ add r3, r5, r3
	10770	+ str r2, [r0, r1]
10407	10771	ldr r1, [sp, #4]
10408		- ldrb r0, [r3, #-1708] @ zero_extendqisi2
	10772	+ ldrb r0, [r3, #-1706] @ zero_extendqisi2
10409	10773	bl V2P_block
10410		- cmp fp, #0
	10774	+ cmp r7, #0
10411	10775	mov r9, r0
10412		- beq .L1858
	10776	+ beq .L1839
10413	10777	bl IsBlkInVendorPart
10414	10778	cmp r0, #0
10415		- bne .L1859
10416		-.L1858:
	10779	+ bne .L1840
	10780	+.L1839:
10417	10781	mov r0, r9
10418	10782	bl FtlBbmIsBadBlock
10419	10783	cmp r0, #0
10420		- bne .L1859
10421		- ldr r2, [r10, #-1492]
	10784	+ bne .L1840
	10785	+ ldr r1, [r5, #-1488]
10422	10786	mov r3, #36
10423		- add r9, r7, r9, asl #10
10424		- mla r2, r3, r5, r2
10425		- ldr r3, [r10, #-1456]
10426		- str r3, [r2, #8]
10427		- ldr r3, .L1894+8
10428		- str r9, [r2, #4]
10429		- ldrh r3, [r3]
10430		- mul r3, r3, r5
10431		- add r5, r5, #1
10432		- uxth r5, r5
10433		- add r1, r3, #3
	10787	+ add r9, fp, r9, lsl #10
	10788	+ mla r1, r3, r6, r1
	10789	+ ldr r3, [r5, #-1452]
	10790	+ str r3, [r1, #8]
	10791	+ ldr r3, .L1870+20
	10792	+ str r9, [r1, #4]
	10793	+ ldrh r3, [r3, #-6]
	10794	+ mul r3, r6, r3
	10795	+ add r6, r6, #1
	10796	+ uxth r6, r6
	10797	+ add r0, r3, #3
10434	10798	cmp r3, #0
10435		- movlt r3, r1
10436		- ldr r1, [r10, #-1452]
	10799	+ movlt r3, r0
	10800	+ ldr r0, [r5, #-1448]
10437	10801	bic r3, r3, #3
10438		- add r3, r1, r3
10439		- str r3, [r2, #12]
10440		-.L1859:
10441		- add r8, r8, #1
10442		- b .L1857
10443		-.L1891:
10444		- cmp r5, #0
10445		- beq .L1869
10446		- ldr r2, .L1894
10447		- mov r3, #0
10448		- mov r1, r5
10449		- mov r8, #0
10450		- strb r3, [r2, #-1874]
10451		- mov r3, #1
10452		- ldr r0, [r2, #-1492]
10453		- mov r2, r6
10454		- bl FlashProgPages
10455		- ldr r3, .L1894
10456		- mov r1, #36
10457		- ldrb r2, [sp, #16] @ zero_extendqisi2
10458		- strb r2, [r3, #-1874]
10459		-.L1862:
10460		- uxth r3, r8
10461		- cmp r3, r5
10462		- bcs .L1892
10463		- mul r3, r1, r8
10464		- ldr r2, .L1894
10465		- ldr r2, [r2, #-1492]
10466		- add r0, r2, r3
10467		- ldr r3, [r2, r3]
	10802	+ add r3, r0, r3
	10803	+ str r3, [r1, #12]
	10804	+.L1840:
	10805	+ add r10, r10, #1
	10806	+ b .L1838
	10807	+.L1845:
	10808	+ mul r3, r2, r9
	10809	+ ldr r1, [r5, #-1488]
	10810	+ add ip, r1, r3
	10811	+ ldr r3, [r1, r3]
10468	10812	cmp r3, #0
10469		- beq .L1863
10470		- ldr r0, [r0, #4]
	10813	+ beq .L1844
	10814	+ ldr r0, [ip, #4]
10471	10815	add r4, r4, #1
10472		- str r1, [sp, #20]
10473		- ubfx r0, r0, #10, #16
	10816	+ str r2, [sp, #20]
10474	10817	uxth r4, r4
	10818	+ ubfx r0, r0, #10, #16
10475	10819	bl FtlBbmMapBadBlock
10476		- ldr r1, [sp, #20]
10477		-.L1863:
10478		- add r8, r8, #1
10479		- b .L1862
10480		-.L1892:
10481		- ldr r3, [sp, #12]
10482		- add r7, r7, r3
10483		- ldr r3, [sp, #8]
10484		- uxth r7, r7
10485		- cmp r7, r3
10486		- bcc .L1865
10487		- mov r7, #0
10488		- mov r8, #36
10489		-.L1866:
10490		- uxth r3, r7
10491		- cmp r3, r5
10492		- bcs .L1893
10493		- cmp fp, #0
10494		- beq .L1867
10495		- mul r3, r8, r7
10496		- ldr r2, [r9, #-1492]
	10820	+ ldr r2, [sp, #20]
	10821	+.L1844:
	10822	+ add r9, r9, #1
	10823	+ b .L1843
	10824	+.L1849:
	10825	+ cmp r7, #0
	10826	+ beq .L1848
	10827	+ mul r3, fp, r9
	10828	+ ldr r2, [r5, #-1488]
10497	10829	add r1, r2, r3
10498	10830	ldr r3, [r2, r3]
10499	10831	cmp r3, #0
10500		- bne .L1867
	10832	+ bne .L1848
10501	10833	ldr r0, [r1, #4]
10502	10834	mov r1, #1
10503	10835	ubfx r0, r0, #10, #16
10504	10836	bl FtlFreeSysBlkQueueIn
10505		-.L1867:
10506		- add r7, r7, #1
10507		- b .L1866
10508		-.L1893:
10509		- adds r3, fp, #0
10510		- ldr r2, [sp, #4]
10511		- movne r3, #1
10512		- cmp r2, #63
10513		- orrls r3, r3, #1
10514		- cmp r3, #0
10515		- beq .L1869
10516		- ldr r0, [r9, #-1492]
10517		- mov r1, r6
10518		- mov r2, r5
10519		- bl FlashEraseBlocks
10520		-.L1869:
10521		- mov r0, r4
10522		-.L1845:
10523		- add sp, sp, #28
10524		- @ sp needed
10525		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
10526		-.L1895:
	10837	+.L1848:
	10838	+ add r9, r9, #1
	10839	+ b .L1847
	10840	+.L1871:
10527	10841	.align 2
10528		-.L1894:
	10842	+.L1870:
10529	10843	.word .LANCHOR2
10530		- .word .LANCHOR2-1736
10531		- .word .LANCHOR2-1656
	10844	+ .word .LANCHOR2-1732
	10845	+ .word .LANCHOR2-1728
	10846	+ .word .LANCHOR2-1654
10532	10847	.word .LANCHOR2-1664
	10848	+ .word .LANCHOR2-1648
10533	10849	.fnend
10534	10850	.size FtlLowFormatEraseBlock, .-FtlLowFormatEraseBlock
10535	10851	.align 2
10536	10852	.global FtlFreeSysBLkSort
	10853	+ .syntax unified
	10854	+ .arm
	10855	+ .fpu softvfp
10537	10856	.type FtlFreeSysBLkSort, %function
10538	10857	FtlFreeSysBLkSort:
10539	10858	.fnstart
10540	10859	@ args = 0, pretend = 0, frame = 0
10541	10860	@ frame_needed = 0, uses_anonymous_args = 0
10542		- ldr r3, .L1909
10543		- ldrh ip, [r3, #28]
10544		- ldr r3, .L1909+4
	10861	+ ldr r3, .L1885
10545	10862	ldrh r2, [r3, #6]
10546	10863	cmp r2, #0
10547	10864	bxeq lr
10548		- stmfd sp!, {r4, lr}
10549		- .save {r4, lr}
10550		- mov r0, #0
10551		- ldrh r1, [r3, #2]
10552		- and ip, ip, #31
	10865	+ push {r4, r5, lr}
	10866	+ .save {r4, r5, lr}
	10867	+ add lr, r3, #8
	10868	+ add r2, lr, #2048
	10869	+ ldrh ip, [r3, #2]
	10870	+ mov r4, #0
	10871	+ ldrh r5, [r2, #28]
	10872	+ mov r0, r4
10553	10873	ldrh r2, [r3, #4]
10554		- mov r4, r0
10555		-.L1898:
10556		- uxth lr, r0
10557		- add r0, r0, #1
10558		- cmp lr, ip
10559		- bge .L1908
10560		- add lr, r3, r1, asl #1
10561		- add r1, r1, #1
10562		- ubfx r1, r1, #0, #10
10563		- ldrh r4, [lr, #8]
10564		- add lr, r3, r2, asl #1
10565		- strh r4, [lr, #8] @ movhi
10566		- mov r4, #1
10567		- add r2, r2, r4
	10874	+ and r5, r5, #31
	10875	+.L1874:
	10876	+ uxth r1, r4
	10877	+ add r4, r4, #1
	10878	+ cmp r5, r1
	10879	+ bgt .L1875
	10880	+ cmp r0, #0
	10881	+ strhne ip, [lr, #-6] @ movhi
	10882	+ strhne r2, [lr, #-4] @ movhi
	10883	+ pop {r4, r5, pc}
	10884	+.L1875:
	10885	+ add r1, r3, ip, lsl #1
	10886	+ add ip, ip, #1
	10887	+ ubfx ip, ip, #0, #10
	10888	+ ldrh r0, [r1, #8]
	10889	+ add r1, r3, r2, lsl #1
	10890	+ strh r0, [r1, #8] @ movhi
	10891	+ mov r0, #1
	10892	+ add r2, r2, r0
10568	10893	ubfx r2, r2, #0, #10
10569		- b .L1898
10570		-.L1908:
10571		- cmp r4, #0
10572		- strneh r1, [r3, #2] @ movhi
10573		- strneh r2, [r3, #4] @ movhi
10574		- ldmfd sp!, {r4, pc}
10575		-.L1910:
	10894	+ b .L1874
	10895	+.L1886:
10576	10896	.align 2
10577		-.L1909:
10578		- .word .LANCHOR2+816
	10897	+.L1885:
10579	10898	.word .LANCHOR2-1240
10580	10899	.fnend
10581	10900	.size FtlFreeSysBLkSort, .-FtlFreeSysBLkSort
10582	10901	.align 2
10583	10902	.global FtlFreeSysBlkQueueOut
	10903	+ .syntax unified
	10904	+ .arm
	10905	+ .fpu softvfp
10584	10906	.type FtlFreeSysBlkQueueOut, %function
10585	10907	FtlFreeSysBlkQueueOut:
10586	10908	.fnstart
10587	10909	@ args = 0, pretend = 0, frame = 0
10588	10910	@ frame_needed = 0, uses_anonymous_args = 0
10589		- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
10590		- .save {r3, r4, r5, r6, r7, r8, r9, lr}
10591		- ldr r6, .L1922
10592		- ldr r5, .L1922+4
10593		- mov r7, r6
10594		-.L1912:
10595		- ldrh r1, [r5, #6]
	10911	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
	10912	+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
	10913	+ ldr r4, .L1898
	10914	+ sub r6, r4, #1232
	10915	+ sub r7, r6, #8
	10916	+.L1888:
	10917	+ ldrh r1, [r6, #-2]
	10918	+ sub r2, r6, #8
10596	10919	cmp r1, #0
10597		- beq .L1913
10598		- ldrh r3, [r5, #2]
	10920	+ beq .L1889
	10921	+ ldrh r3, [r6, #-6]
10599	10922	sub r1, r1, #1
10600		- ldr r9, [r6, #-1280]
10601		- strh r1, [r5, #6] @ movhi
10602		- add r2, r5, r3, asl #1
	10923	+ ldr r9, [r4, #-1280]
	10924	+ strh r1, [r6, #-2] @ movhi
	10925	+ add r0, r2, r3, lsl #1
10603	10926	cmp r9, #0
10604	10927	add r3, r3, #1
10605	10928	ubfx r3, r3, #0, #10
10606		- ldrh r4, [r2, #8]
10607		- strh r3, [r5, #2] @ movhi
10608		- bne .L1914
10609		- mov r0, r4
	10929	+ ldrh r5, [r0, #8]
	10930	+ strh r3, [r6, #-6] @ movhi
	10931	+ bne .L1890
	10932	+ mov r0, r5
10610	10933	bl P2V_block_in_plane
10611		- mov r3, r4, asl #10
10612	10934	mov r8, r0
10613		- ldr r0, [r6, #-1492]
	10935	+ ldr r0, [r4, #-1488]
	10936	+ lsl r3, r5, #10
10614	10937	str r3, [r0, #4]
10615		- ldrb r3, [r6, #-2744] @ zero_extendqisi2
	10938	+ ldrb r3, [r4, #-2740] @ zero_extendqisi2
10616	10939	cmp r3, #0
10617		- beq .L1915
10618		- mov r1, r9
	10940	+ beq .L1891
10619	10941	mov r2, #1
	10942	+ mov r1, r9
10620	10943	bl FlashEraseBlocks
10621		-.L1915:
10622		- mov r1, #1
10623		- ldr r0, [r7, #-1492]
10624		- mov r2, r1
	10944	+.L1891:
	10945	+ mov r2, #1
	10946	+ ldr r0, [r4, #-1488]
	10947	+ mov r1, r2
10625	10948	bl FlashEraseBlocks
10626		- ldr r1, [r7, #-1416]
10627		- mov r3, r8, asl #1
10628		- ldrh r2, [r1, r3]
10629		- add r2, r2, #1
10630		- strh r2, [r1, r3] @ movhi
10631		- ldr r3, [r7, #-1576]
	10949	+ ldr r2, [r4, #-1412]
	10950	+ lsl r0, r8, #1
	10951	+ ldrh r3, [r2, r0]
10632	10952	add r3, r3, #1
10633		- str r3, [r7, #-1576]
10634		- b .L1914
10635		-.L1913:
10636		- ldr r0, .L1922+8
10637		- bl printk
10638		-.L1916:
10639		- b .L1916
10640		-.L1914:
10641		- sub r3, r4, #1
	10953	+ strh r3, [r2, r0] @ movhi
	10954	+ ldr r3, [r4, #-1572]
	10955	+ add r3, r3, #1
	10956	+ str r3, [r4, #-1572]
	10957	+.L1890:
	10958	+ sub r3, r5, #1
10642	10959	movw r2, #65533
10643	10960	uxth r3, r3
10644	10961	cmp r3, r2
10645		- bls .L1917
10646		- ldr r3, .L1922+4
10647		- mov r1, r4
10648		- ldr r0, .L1922+12
10649		- ldrh r2, [r3, #6]
	10962	+ bls .L1893
	10963	+ ldrh r2, [r7, #6]
	10964	+ mov r1, r5
	10965	+ ldr r0, .L1898+4
10650	10966	bl printk
10651		- b .L1912
10652		-.L1917:
10653		- mov r0, r4
10654		- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
10655		-.L1923:
	10967	+ b .L1888
	10968	+.L1889:
	10969	+ ldr r0, .L1898+8
	10970	+ bl printk
	10971	+.L1892:
	10972	+ b .L1892
	10973	+.L1893:
	10974	+ mov r0, r5
	10975	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	10976	+.L1899:
10656	10977	.align 2
10657		-.L1922:
	10978	+.L1898:
10658	10979	.word .LANCHOR2
10659		- .word .LANCHOR2-1240
10660		- .word .LC37
10661	10980	.word .LC38
	10981	+ .word .LC37
10662	10982	.fnend
10663	10983	.size FtlFreeSysBlkQueueOut, .-FtlFreeSysBlkQueueOut
10664	10984	.align 2
10665	10985	.global test_node_in_list
	10986	+ .syntax unified
	10987	+ .arm
	10988	+ .fpu softvfp
10666	10989	.type test_node_in_list, %function
10667	10990	test_node_in_list:
10668	10991	.fnstart
10669	10992	@ args = 0, pretend = 0, frame = 0
10670	10993	@ frame_needed = 0, uses_anonymous_args = 0
10671		- ldr r3, .L1930
	10994	+ ldr r3, .L1906
10672	10995	str lr, [sp, #-4]!
10673	10996	.save {lr}
10674	10997	movw lr, #65535
10675		- ldr ip, [r3, #-1356]
10676	10998	ldr r2, [r0]
10677		- ldr r3, .L1930+4
10678		- rsb r0, ip, r2
10679		- mov r0, r0, asr #1
	10999	+ ldr ip, [r3, #-1356]
	11000	+ sub r3, r2, ip
	11001	+ asr r0, r3, #1
	11002	+ ldr r3, .L1906+4
10680	11003	mul r3, r3, r0
10681	11004	mov r0, #6
10682	11005	uxth r3, r3
10683		-.L1926:
10684		- cmp r1, r3
10685		- beq .L1927
	11006	+.L1902:
	11007	+ cmp r3, r1
	11008	+ beq .L1903
10686	11009	ldrh r3, [r2]
10687	11010	cmp r3, lr
10688		- beq .L1928
	11011	+ beq .L1904
10689	11012	mla r2, r0, r3, ip
10690		- b .L1926
10691		-.L1927:
	11013	+ b .L1902
	11014	+.L1903:
10692	11015	mov r0, #1
10693	11016	ldr pc, [sp], #4
10694		-.L1928:
	11017	+.L1904:
10695	11018	mov r0, #0
10696	11019	ldr pc, [sp], #4
10697		-.L1931:
	11020	+.L1907:
10698	11021	.align 2
10699		-.L1930:
	11022	+.L1906:
10700	11023	.word .LANCHOR2
10701	11024	.word -1431655765
10702	11025	.fnend
10703	11026	.size test_node_in_list, .-test_node_in_list
10704	11027	.align 2
10705	11028	.global insert_data_list
	11029	+ .syntax unified
	11030	+ .arm
	11031	+ .fpu softvfp
10706	11032	.type insert_data_list, %function
10707	11033	insert_data_list:
10708	11034	.fnstart
10709	11035	@ args = 0, pretend = 0, frame = 8
10710	11036	@ frame_needed = 0, uses_anonymous_args = 0
10711		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	11037	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
10712	11038	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
10713	11039	.pad #12
10714		- ldr r2, .L1949
10715		- sub r5, r2, #1728
10716		- ldrh r3, [r5]
	11040	+ ldr r2, .L1924
	11041	+ sub r4, r2, #1712
	11042	+ ldrh r3, [r4, #-12]
10717	11043	cmp r3, r0
10718		- bls .L1934
	11044	+ bls .L1910
10719	11045	mov lr, #6
10720	11046	ldr r6, [r2, #-1356]
10721	11047	mul lr, lr, r0
..	..	@@ -10725,29 +11051,30 @@
10725	11051	strh ip, [r6, lr] @ movhi
10726	11052	ldr r3, [r2, #864]
10727	11053	cmp r3, #0
10728		- beq .L1948
10729		- ldr r8, [r2, #-1408]
10730		- mov r4, r0, asl #1
10731		- mov r10, r2
	11054	+ streq r1, [r2, #864]
	11055	+ beq .L1910
	11056	+ ldr r8, [r2, #-1404]
	11057	+ lsl r10, r0, #1
	11058	+ mov r5, r2
10732	11059	ldrh r2, [r1, #4]
10733		- ldrh r5, [r5]
10734		- ldrh r7, [r8, r4]
	11060	+ ldrh r4, [r4, #-12]
	11061	+ ldrh r7, [r8, r10]
10735	11062	cmp r2, #0
10736		- str r5, [sp]
	11063	+ str r4, [sp]
10737	11064	mulne ip, r2, r7
10738		- ldr r7, [r10, #-1356]
10739		- ldr r2, .L1949+4
10740		- rsb r9, r7, r3
10741		- mov r9, r9, asr #1
	11065	+ ldr r7, [r5, #-1356]
	11066	+ sub r2, r3, r7
	11067	+ asr r9, r2, #1
	11068	+ ldr r2, .L1924+4
10742	11069	mul r2, r2, r9
10743		- ldr r9, [r10, #-1416]
10744		- add r4, r9, r4
	11070	+ ldr r9, [r5, #-1412]
	11071	+ add r4, r9, r10
	11072	+ uxth r2, r2
10745	11073	str r4, [sp, #4]
10746	11074	mov r4, #0
10747		- uxth r2, r2
10748		-.L1943:
10749		- add r4, r4, #1
	11075	+.L1919:
10750	11076	ldr r5, [sp]
	11077	+ add r4, r4, #1
10751	11078	uxth r4, r4
10752	11079	cmp r4, r5
10753	11080	movls r5, #0
..	..	@@ -10755,244 +11082,253 @@
10755	11082	cmp r0, r2
10756	11083	orreq r5, r5, #1
10757	11084	cmp r5, #0
10758		- bne .L1934
10759		- mov r10, r2, asl #1
	11085	+ bne .L1910
	11086	+ lsl r10, r2, #1
10760	11087	ldrh r5, [r3, #4]
10761	11088	ldrh fp, [r8, r10]
10762	11089	cmp r5, #0
10763	11090	mvneq r5, #0
10764	11091	mulne r5, r5, fp
10765		- cmp r5, ip
10766		- bne .L1939
	11092	+ cmp ip, r5
	11093	+ bne .L1915
10767	11094	ldr r5, [sp, #4]
10768	11095	ldrh r10, [r9, r10]
10769	11096	ldrh r5, [r5]
10770	11097	cmp r10, r5
10771		- bcc .L1941
10772		- b .L1940
10773		-.L1939:
10774		- bhi .L1940
10775		-.L1941:
	11098	+ bcc .L1917
	11099	+.L1916:
	11100	+ strh r2, [r6, lr] @ movhi
	11101	+ ldr ip, .L1924
	11102	+ ldrh r2, [r3, #2]
	11103	+ strh r2, [r1, #2] @ movhi
	11104	+ ldr r2, [ip, #864]
	11105	+ cmp r3, r2
	11106	+ ldrhne lr, [r3, #2]
	11107	+ movne r2, #6
	11108	+ ldrne r1, [ip, #-1356]
	11109	+ strheq r0, [r3, #2] @ movhi
	11110	+ streq r1, [ip, #864]
	11111	+ mulne r2, r2, lr
	11112	+ strhne r0, [r1, r2] @ movhi
	11113	+ strhne r0, [r3, #2] @ movhi
	11114	+ b .L1910
	11115	+.L1915:
	11116	+ bcc .L1916
	11117	+.L1917:
10776	11118	ldrh r5, [r3]
10777	11119	movw r10, #65535
10778	11120	cmp r5, r10
10779		- streqh r2, [r1, #2] @ movhi
10780		- streqh r0, [r3] @ movhi
10781		- ldreq r3, .L1949
10782		- streq r1, [r3, #868]
10783		- beq .L1934
10784		-.L1942:
10785		- mov r3, #6
10786		- mov r2, r5
10787		- mla r3, r3, r5, r7
10788		- b .L1943
10789		-.L1940:
10790		- strh r2, [r6, lr] @ movhi
10791		- ldrh r2, [r3, #2]
	11121	+ bne .L1918
10792	11122	strh r2, [r1, #2] @ movhi
10793		- ldr r2, .L1949
10794		- ldr ip, [r2, #864]
10795		- cmp r3, ip
10796		- bne .L1944
10797		- strh r0, [r3, #2] @ movhi
10798		-.L1948:
10799		- str r1, [r2, #864]
10800		- b .L1934
10801		-.L1944:
10802		- ldrh ip, [r3, #2]
10803		- ldr r1, [r2, #-1356]
10804		- mov r2, #6
10805		- mul r2, r2, ip
10806		- strh r0, [r1, r2] @ movhi
10807		- strh r0, [r3, #2] @ movhi
10808		-.L1934:
	11123	+ strh r0, [r3] @ movhi
	11124	+ ldr r3, .L1924
	11125	+ str r1, [r3, #868]
	11126	+.L1910:
10809	11127	mov r0, #0
10810	11128	add sp, sp, #12
10811	11129	@ sp needed
10812		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
10813		-.L1950:
	11130	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	11131	+.L1918:
	11132	+ mov r3, #6
	11133	+ mov r2, r5
	11134	+ mla r3, r3, r5, r7
	11135	+ b .L1919
	11136	+.L1925:
10814	11137	.align 2
10815		-.L1949:
	11138	+.L1924:
10816	11139	.word .LANCHOR2
10817	11140	.word -1431655765
10818	11141	.fnend
10819	11142	.size insert_data_list, .-insert_data_list
10820	11143	.align 2
10821	11144	.global INSERT_DATA_LIST
	11145	+ .syntax unified
	11146	+ .arm
	11147	+ .fpu softvfp
10822	11148	.type INSERT_DATA_LIST, %function
10823	11149	INSERT_DATA_LIST:
10824	11150	.fnstart
10825	11151	@ args = 0, pretend = 0, frame = 0
10826	11152	@ frame_needed = 0, uses_anonymous_args = 0
10827		- stmfd sp!, {r3, lr}
10828		- .save {r3, lr}
	11153	+ push {r4, lr}
	11154	+ .save {r4, lr}
10829	11155	bl insert_data_list
10830		- ldr r2, .L1953
	11156	+ ldr r2, .L1928
10831	11157	ldrh r3, [r2]
10832	11158	add r3, r3, #1
10833	11159	strh r3, [r2] @ movhi
10834		- ldmfd sp!, {r3, pc}
10835		-.L1954:
	11160	+ pop {r4, pc}
	11161	+.L1929:
10836	11162	.align 2
10837		-.L1953:
	11163	+.L1928:
10838	11164	.word .LANCHOR2+872
10839	11165	.fnend
10840	11166	.size INSERT_DATA_LIST, .-INSERT_DATA_LIST
10841	11167	.align 2
10842	11168	.global insert_free_list
	11169	+ .syntax unified
	11170	+ .arm
	11171	+ .fpu softvfp
10843	11172	.type insert_free_list, %function
10844	11173	insert_free_list:
10845	11174	.fnstart
10846	11175	@ args = 0, pretend = 0, frame = 0
10847	11176	@ frame_needed = 0, uses_anonymous_args = 0
10848		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
	11177	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
10849	11178	.save {r4, r5, r6, r7, r8, r9, r10, lr}
10850	11179	movw r4, #65535
10851	11180	cmp r0, r4
10852		- beq .L1956
10853		- ldr r2, .L1964
10854		- mov lr, #6
10855		- mul r6, lr, r0
	11181	+ beq .L1931
	11182	+ ldr r2, .L1938
	11183	+ mov r1, #6
	11184	+ mul r5, r1, r0
10856	11185	mvn r3, #0
10857		- ldr r7, [r2, #-1356]
10858		- mov r5, r2
10859		- add ip, r7, r6
10860		- strh r3, [ip, #2] @ movhi
10861		- strh r3, [r7, r6] @ movhi
	11186	+ ldr r6, [r2, #-1356]
	11187	+ mov ip, r2
	11188	+ add lr, r6, r5
	11189	+ strh r3, [lr, #2] @ movhi
	11190	+ strh r3, [r6, r5] @ movhi
10862	11191	ldr r3, [r2, #876]
10863	11192	cmp r3, #0
10864		- beq .L1963
10865		- ldr r9, [r2, #-1416]
10866		- mov r2, r0, asl #1
10867		- ldr r8, [r5, #-1356]
10868		- rsb r1, r8, r3
10869		- ldrh r10, [r9, r2]
10870		- ldr r2, .L1964+4
10871		- mov r1, r1, asr #1
10872		- mul r1, r2, r1
10873		- uxth r2, r1
10874		-.L1960:
10875		- mov r1, r2, asl #1
10876		- ldrh r1, [r9, r1]
10877		- cmp r1, r10
10878		- bcs .L1958
	11193	+ streq lr, [r2, #876]
	11194	+ beq .L1931
	11195	+ ldr r8, [r2, #-1412]
	11196	+ lsl r2, r0, #1
	11197	+ ldr r7, [ip, #-1356]
	11198	+ ldrh r9, [r8, r2]
	11199	+ sub r2, r3, r7
	11200	+ asr r10, r2, #1
	11201	+ ldr r2, .L1938+4
	11202	+ mul r2, r2, r10
	11203	+ mov r10, r1
	11204	+ uxth r2, r2
	11205	+.L1935:
	11206	+ lsl r1, r2, #1
	11207	+ ldrh r1, [r8, r1]
	11208	+ cmp r1, r9
	11209	+ bcs .L1933
10879	11210	ldrh r1, [r3]
10880	11211	cmp r1, r4
10881		- streqh r2, [ip, #2] @ movhi
10882		- streqh r0, [r3] @ movhi
10883		- beq .L1956
10884		-.L1959:
10885		- mla r3, lr, r1, r8
10886		- mov r2, r1
10887		- b .L1960
10888		-.L1958:
10889		- ldrh r1, [r3, #2]
10890		- strh r1, [ip, #2] @ movhi
10891		- strh r2, [r7, r6] @ movhi
10892		- ldr r1, [r5, #876]
10893		- ldr r2, .L1964
10894		- cmp r3, r1
10895		- bne .L1961
10896		- strh r0, [r3, #2] @ movhi
10897		-.L1963:
10898		- str ip, [r2, #876]
10899		- b .L1956
10900		-.L1961:
10901		- ldrh ip, [r3, #2]
10902		- ldr r1, [r2, #-1356]
10903		- mov r2, #6
10904		- mul r2, r2, ip
10905		- strh r0, [r1, r2] @ movhi
10906		- strh r0, [r3, #2] @ movhi
10907		-.L1956:
	11212	+ bne .L1934
	11213	+ strh r2, [lr, #2] @ movhi
	11214	+ strh r0, [r3] @ movhi
	11215	+.L1931:
10908	11216	mov r0, #0
10909		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
10910		-.L1965:
	11217	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	11218	+.L1934:
	11219	+ mla r3, r10, r1, r7
	11220	+ mov r2, r1
	11221	+ b .L1935
	11222	+.L1933:
	11223	+ ldrh r1, [r3, #2]
	11224	+ strh r1, [lr, #2] @ movhi
	11225	+ strh r2, [r6, r5] @ movhi
	11226	+ ldr r2, [ip, #876]
	11227	+ cmp r3, r2
	11228	+ ldrhne lr, [r3, #2]
	11229	+ movne r2, #6
	11230	+ ldrne r1, [ip, #-1356]
	11231	+ strheq r0, [r3, #2] @ movhi
	11232	+ streq lr, [ip, #876]
	11233	+ mulne r2, r2, lr
	11234	+ strhne r0, [r1, r2] @ movhi
	11235	+ strhne r0, [r3, #2] @ movhi
	11236	+ b .L1931
	11237	+.L1939:
10911	11238	.align 2
10912		-.L1964:
	11239	+.L1938:
10913	11240	.word .LANCHOR2
10914	11241	.word -1431655765
10915	11242	.fnend
10916	11243	.size insert_free_list, .-insert_free_list
10917	11244	.align 2
10918	11245	.global INSERT_FREE_LIST
	11246	+ .syntax unified
	11247	+ .arm
	11248	+ .fpu softvfp
10919	11249	.type INSERT_FREE_LIST, %function
10920	11250	INSERT_FREE_LIST:
10921	11251	.fnstart
10922	11252	@ args = 0, pretend = 0, frame = 0
10923	11253	@ frame_needed = 0, uses_anonymous_args = 0
10924		- stmfd sp!, {r3, lr}
10925		- .save {r3, lr}
	11254	+ push {r4, lr}
	11255	+ .save {r4, lr}
10926	11256	bl insert_free_list
10927		- ldr r2, .L1968
	11257	+ ldr r2, .L1942
10928	11258	ldrh r3, [r2]
10929	11259	add r3, r3, #1
10930	11260	strh r3, [r2] @ movhi
10931		- ldmfd sp!, {r3, pc}
10932		-.L1969:
	11261	+ pop {r4, pc}
	11262	+.L1943:
10933	11263	.align 2
10934		-.L1968:
	11264	+.L1942:
10935	11265	.word .LANCHOR2+880
10936	11266	.fnend
10937	11267	.size INSERT_FREE_LIST, .-INSERT_FREE_LIST
10938	11268	.align 2
10939	11269	.global List_remove_node
	11270	+ .syntax unified
	11271	+ .arm
	11272	+ .fpu softvfp
10940	11273	.type List_remove_node, %function
10941	11274	List_remove_node:
10942	11275	.fnstart
10943	11276	@ args = 0, pretend = 0, frame = 0
10944	11277	@ frame_needed = 0, uses_anonymous_args = 0
10945		- stmfd sp!, {r4, r5, lr}
	11278	+ push {r4, r5, lr}
10946	11279	.save {r4, r5, lr}
10947	11280	mov ip, #6
10948		- ldr r4, .L1976
10949		- movw r5, #65535
	11281	+ ldr r4, .L1950
10950	11282	mul r1, ip, r1
	11283	+ movw r5, #65535
10951	11284	ldr r3, [r0]
10952	11285	ldr r2, [r4, #-1356]
10953	11286	add lr, r2, r1
10954	11287	cmp lr, r3
10955	11288	ldrh r3, [r2, r1]
10956		- bne .L1971
	11289	+ bne .L1945
10957	11290	cmp r3, r5
10958	11291	mlane r3, ip, r3, r2
10959	11292	moveq r3, #0
10960	11293	streq r3, [r0]
10961	11294	strne r3, [r0]
10962	11295	mvnne r0, #0
10963		- strneh r0, [r3, #2] @ movhi
10964		- b .L1973
10965		-.L1971:
10966		- cmp r3, r5
10967		- ldrh r0, [lr, #2]
10968		- bne .L1974
10969		- cmp r0, r3
10970		- mulne r0, ip, r0
10971		- mvnne r3, #0
10972		- strneh r3, [r2, r0] @ movhi
10973		- b .L1973
10974		-.L1974:
10975		- mla r3, ip, r3, r2
10976		- strh r0, [r3, #2] @ movhi
10977		- ldrh r5, [lr, #2]
10978		- ldrh r0, [r2, r1]
10979		- ldr r3, [r4, #-1356]
10980		- mul ip, ip, r5
10981		- strh r0, [r3, ip] @ movhi
10982		-.L1973:
	11296	+ strhne r0, [r3, #2] @ movhi
	11297	+.L1947:
10983	11298	mvn r3, #0
10984	11299	mov r0, #0
10985	11300	strh r3, [r2, r1] @ movhi
10986	11301	strh r3, [lr, #2] @ movhi
10987		- ldmfd sp!, {r4, r5, pc}
10988		-.L1977:
	11302	+ pop {r4, r5, pc}
	11303	+.L1945:
	11304	+ cmp r3, r5
	11305	+ ldrh r0, [lr, #2]
	11306	+ bne .L1948
	11307	+ cmp r0, r3
	11308	+ mulne r3, ip, r0
	11309	+ mvnne r0, #0
	11310	+ strhne r0, [r2, r3] @ movhi
	11311	+ b .L1947
	11312	+.L1948:
	11313	+ mla r3, ip, r3, r2
	11314	+ strh r0, [r3, #2] @ movhi
	11315	+ ldrh r3, [lr, #2]
	11316	+ ldrh r5, [r2, r1]
	11317	+ ldr r0, [r4, #-1356]
	11318	+ mul r3, ip, r3
	11319	+ strh r5, [r0, r3] @ movhi
	11320	+ b .L1947
	11321	+.L1951:
10989	11322	.align 2
10990		-.L1976:
	11323	+.L1950:
10991	11324	.word .LANCHOR2
10992	11325	.fnend
10993	11326	.size List_remove_node, .-List_remove_node
10994	11327	.align 2
10995	11328	.global List_pop_index_node
	11329	+ .syntax unified
	11330	+ .arm
	11331	+ .fpu softvfp
10996	11332	.type List_pop_index_node, %function
10997	11333	List_pop_index_node:
10998	11334	.fnstart
..	..	@@ -11000,106 +11336,113 @@
11000	11336	@ frame_needed = 0, uses_anonymous_args = 0
11001	11337	ldr r3, [r0]
11002	11338	cmp r3, #0
11003		- beq .L1984
11004		- ldr r2, .L1987
11005		- movw ip, #65535
11006		- stmfd sp!, {r4, lr}
	11339	+ beq .L1958
	11340	+ ldr r2, .L1963
	11341	+ push {r4, lr}
11007	11342	.save {r4, lr}
11008		- mov lr, #6
11009		- ldr r4, [r2, #-1356]
11010		-.L1980:
	11343	+ movw lr, #65535
	11344	+ mov r4, #6
	11345	+ ldr r2, [r2, #-1356]
	11346	+.L1954:
11011	11347	cmp r1, #0
11012		- bne .L1981
11013		-.L1983:
11014		- rsb r4, r4, r3
11015		- ldr r3, .L1987+4
11016		- mov r4, r4, asr #1
11017		- mul r4, r3, r4
11018		- uxth r4, r4
11019		- mov r1, r4
	11348	+ bne .L1955
	11349	+.L1957:
	11350	+ ldr r4, .L1963+4
	11351	+ sub r3, r3, r2
	11352	+ asr r3, r3, #1
	11353	+ mul r4, r4, r3
	11354	+ uxth r1, r4
11020	11355	bl List_remove_node
11021		- mov r0, r4
11022		- ldmfd sp!, {r4, pc}
11023		-.L1981:
11024		- ldrh r2, [r3]
11025		- cmp r2, ip
11026		- beq .L1983
	11356	+ uxth r0, r4
	11357	+ pop {r4, pc}
	11358	+.L1955:
	11359	+ ldrh ip, [r3]
	11360	+ cmp ip, lr
	11361	+ beq .L1957
11027	11362	sub r1, r1, #1
11028		- mla r3, lr, r2, r4
	11363	+ mla r3, r4, ip, r2
11029	11364	uxth r1, r1
11030		- b .L1980
11031		-.L1984:
	11365	+ b .L1954
	11366	+.L1958:
11032	11367	movw r0, #65535
11033	11368	bx lr
11034		-.L1988:
	11369	+.L1964:
11035	11370	.align 2
11036		-.L1987:
	11371	+.L1963:
11037	11372	.word .LANCHOR2
11038	11373	.word -1431655765
11039	11374	.fnend
11040	11375	.size List_pop_index_node, .-List_pop_index_node
11041	11376	.align 2
11042	11377	.global List_get_gc_head_node
	11378	+ .syntax unified
	11379	+ .arm
	11380	+ .fpu softvfp
11043	11381	.type List_get_gc_head_node, %function
11044	11382	List_get_gc_head_node:
11045	11383	.fnstart
11046	11384	@ args = 0, pretend = 0, frame = 0
11047	11385	@ frame_needed = 0, uses_anonymous_args = 0
11048	11386	@ link register save eliminated.
11049		- ldr r2, .L1996
	11387	+ ldr r2, .L1971
11050	11388	ldr r3, [r2, #864]
11051	11389	cmp r3, #0
11052	11390	ldrne r1, [r2, #-1356]
11053	11391	movne ip, #6
11054	11392	movwne r2, #65535
11055		- beq .L1994
11056		-.L1991:
11057		- cmp r0, #0
11058		- beq .L1992
11059		- ldrh r3, [r3]
11060		- cmp r3, r2
11061		- subne r0, r0, #1
11062		- mlane r3, ip, r3, r1
11063		- uxthne r0, r0
11064		- bne .L1991
11065		-.L1994:
	11393	+ bne .L1967
	11394	+.L1970:
11066	11395	movw r0, #65535
11067	11396	bx lr
11068		-.L1992:
11069		- rsb r3, r1, r3
11070		- ldr r0, .L1996+4
11071		- mov r3, r3, asr #1
11072		- mul r0, r0, r3
	11397	+.L1969:
	11398	+ sub r0, r0, #1
	11399	+ mla r3, ip, r3, r1
11073	11400	uxth r0, r0
	11401	+.L1967:
	11402	+ cmp r0, #0
	11403	+ beq .L1968
	11404	+ ldrh r3, [r3]
	11405	+ cmp r3, r2
	11406	+ bne .L1969
	11407	+ b .L1970
	11408	+.L1968:
	11409	+ ldr r0, .L1971+4
	11410	+ sub r3, r3, r1
	11411	+ asr r3, r3, #1
	11412	+ mul r3, r0, r3
	11413	+ uxth r0, r3
11074	11414	bx lr
11075		-.L1997:
	11415	+.L1972:
11076	11416	.align 2
11077		-.L1996:
	11417	+.L1971:
11078	11418	.word .LANCHOR2
11079	11419	.word -1431655765
11080	11420	.fnend
11081	11421	.size List_get_gc_head_node, .-List_get_gc_head_node
11082	11422	.align 2
11083	11423	.global List_update_data_list
	11424	+ .syntax unified
	11425	+ .arm
	11426	+ .fpu softvfp
11084	11427	.type List_update_data_list, %function
11085	11428	List_update_data_list:
11086	11429	.fnstart
11087	11430	@ args = 0, pretend = 0, frame = 0
11088	11431	@ frame_needed = 0, uses_anonymous_args = 0
11089		- ldr r3, .L2007
	11432	+ ldr r3, .L1984
11090	11433	add r2, r3, #884
11091	11434	ldrh r2, [r2]
11092	11435	cmp r2, r0
11093		- beq .L2006
	11436	+ beq .L1981
11094	11437	add r2, r3, #932
11095	11438	ldrh r2, [r2]
11096	11439	cmp r2, r0
11097		- beq .L2006
	11440	+ beq .L1981
11098	11441	add r2, r3, #980
11099	11442	ldrh r2, [r2]
11100	11443	cmp r2, r0
11101		- beq .L2006
11102		- stmfd sp!, {r4, lr}
	11444	+ beq .L1981
	11445	+ push {r4, lr}
11103	11446	.save {r4, lr}
11104	11447	mov lr, #6
11105	11448	mul lr, lr, r0
..	..	@@ -11107,55 +11450,55 @@
11107	11450	ldr r2, [r3, #864]
11108	11451	add ip, r1, lr
11109	11452	cmp ip, r2
11110		- beq .L1999
11111		- ldr r4, [r3, #-1408]
11112		- mov r3, r0, asl #1
11113		- ldrh r2, [r4, r3]
11114		- ldrh r3, [ip, #4]
11115		- ldrh ip, [ip, #2]
11116		- cmp r3, #0
11117		- mulne r2, r3, r2
	11453	+ beq .L1974
	11454	+ ldr r4, [r3, #-1404]
	11455	+ lsl r3, r0, #1
	11456	+ ldrh r2, [ip, #4]
	11457	+ ldrh r3, [r4, r3]
	11458	+ cmp r2, #0
11118	11459	mvneq r2, #0
11119		- movw r3, #65535
11120		- cmp ip, r3
11121		- bne .L2001
11122		- ldrh r3, [r1, lr]
	11460	+ mulne r2, r2, r3
	11461	+ ldrh r3, [ip, #2]
	11462	+ movw ip, #65535
11123	11463	cmp r3, ip
11124		- beq .L1999
11125		-.L2001:
11126		- mov r3, #6
11127		- mul ip, r3, ip
11128		- ldr r3, .L2007+4
	11464	+ bne .L1976
	11465	+ ldrh ip, [r1, lr]
	11466	+ cmp ip, r3
	11467	+ beq .L1974
	11468	+.L1976:
	11469	+ mov ip, #6
	11470	+ mul ip, ip, r3
	11471	+ ldr r3, .L1984+4
	11472	+ asr lr, ip, #1
11129	11473	add r1, r1, ip
11130		- mov lr, ip, asr #1
11131	11474	mul r3, r3, lr
11132		- mov r3, r3, asl #1
	11475	+ lsl r3, r3, #1
11133	11476	ldrh lr, [r4, r3]
11134	11477	ldrh r3, [r1, #4]
11135	11478	cmp r3, #0
11136	11479	mulne r3, r3, lr
11137	11480	mvneq r3, #0
11138	11481	cmp r2, r3
11139		- bcs .L1999
	11482	+ bcs .L1974
11140	11483	mov r4, r0
11141		- ldr r0, .L2007+8
11142		- mov r1, r4
	11484	+ mov r1, r0
	11485	+ ldr r0, .L1984+8
11143	11486	bl List_remove_node
11144		- ldr r2, .L2007+12
	11487	+ ldr r2, .L1984+12
11145	11488	mov r0, r4
11146	11489	ldrh r3, [r2]
11147	11490	sub r3, r3, #1
11148	11491	strh r3, [r2] @ movhi
11149	11492	bl INSERT_DATA_LIST
11150		-.L1999:
	11493	+.L1974:
11151	11494	mov r0, #0
11152		- ldmfd sp!, {r4, pc}
11153		-.L2006:
	11495	+ pop {r4, pc}
	11496	+.L1981:
11154	11497	mov r0, #0
11155	11498	bx lr
11156		-.L2008:
	11499	+.L1985:
11157	11500	.align 2
11158		-.L2007:
	11501	+.L1984:
11159	11502	.word .LANCHOR2
11160	11503	.word -1431655765
11161	11504	.word .LANCHOR2+864
..	..	@@ -11164,12 +11507,15 @@
11164	11507	.size List_update_data_list, .-List_update_data_list
11165	11508	.align 2
11166	11509	.global ftl_free_no_use_map_blk
	11510	+ .syntax unified
	11511	+ .arm
	11512	+ .fpu softvfp
11167	11513	.type ftl_free_no_use_map_blk, %function
11168	11514	ftl_free_no_use_map_blk:
11169	11515	.fnstart
11170	11516	@ args = 0, pretend = 0, frame = 0
11171	11517	@ frame_needed = 0, uses_anonymous_args = 0
11172		- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	11518	+ push {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
11173	11519	.save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
11174	11520	mov r1, #0
11175	11521	ldrh r2, [r0, #10]
..	..	@@ -11177,284 +11523,284 @@
11177	11523	ldr r5, [r0, #20]
11178	11524	ldr r7, [r0, #12]
11179	11525	ldr r6, [r0, #24]
11180		- mov r2, r2, asl #1
	11526	+ lsl r2, r2, #1
11181	11527	mov r0, r5
11182	11528	bl ftl_memset
11183	11529	mov r2, #0
11184		-.L2010:
	11530	+.L1987:
11185	11531	ldrh r1, [r4, #6]
11186	11532	uxth r3, r2
11187	11533	cmp r1, r3
11188		- bls .L2030
11189		- ldr r0, [r6, r3, asl #2]
	11534	+ bhi .L1991
	11535	+ ldr r3, .L2007
	11536	+ mov r6, #0
	11537	+ mov r8, r6
	11538	+ mov r10, r6
	11539	+ ldrh r2, [r3]
	11540	+ ldrh r3, [r4]
	11541	+ lsl r3, r3, #1
	11542	+ strh r2, [r5, r3] @ movhi
	11543	+ ldrh r9, [r5]
	11544	+.L1992:
	11545	+ ldrh r3, [r4, #10]
	11546	+ uxth r1, r6
	11547	+ cmp r3, r1
	11548	+ bhi .L1996
	11549	+ mov r0, r8
	11550	+ pop {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
	11551	+.L1991:
	11552	+ uxth r3, r2
11190	11553	mov r1, #0
	11554	+ ldr r0, [r6, r3, lsl #2]
11191	11555	ubfx r0, r0, #10, #16
11192		-.L2011:
	11556	+.L1988:
11193	11557	ldrh ip, [r4, #10]
11194	11558	uxth r3, r1
11195	11559	cmp ip, r3
11196		- bls .L2031
11197		- mov r3, r3, asl #1
	11560	+ addls r2, r2, #1
	11561	+ bls .L1987
	11562	+.L1990:
	11563	+ uxth r3, r1
11198	11564	add r1, r1, #1
	11565	+ lsl r3, r3, #1
11199	11566	ldrh ip, [r7, r3]
11200		- rsb lr, ip, r0
11201		- cmp ip, #0
11202		- clz lr, lr
11203		- mov lr, lr, lsr #5
11204		- moveq lr, #0
	11567	+ adds lr, ip, #0
	11568	+ movne lr, #1
	11569	+ cmp r0, ip
	11570	+ movne lr, #0
11205	11571	cmp lr, #0
11206		- ldrneh ip, [r5, r3]
	11572	+ ldrhne ip, [r5, r3]
11207	11573	addne ip, ip, #1
11208		- strneh ip, [r5, r3] @ movhi
11209		- b .L2011
11210		-.L2031:
11211		- add r2, r2, #1
11212		- b .L2010
11213		-.L2030:
11214		- ldr r3, .L2033
11215		- mov r8, #0
11216		- mov r1, r8
11217		- mov fp, r8
11218		- ldrh r2, [r3, #-2]
11219		- ldrh r3, [r4]
11220		- mov r3, r3, asl #1
11221		- strh r2, [r5, r3] @ movhi
11222		- ldrh r9, [r5]
11223		-.L2015:
11224		- ldrh r3, [r4, #10]
11225		- uxth r6, r8
11226		- cmp r3, r6
11227		- bls .L2032
11228		- mov r2, r6, asl #1
11229		- ldrh r3, [r5, r2]
11230		- cmp r9, r3
11231		- bls .L2016
11232		- ldrh r0, [r7, r2]
11233		- add r10, r7, r2
	11574	+ strhne ip, [r5, r3] @ movhi
	11575	+ b .L1988
	11576	+.L1996:
	11577	+ uxth r3, r6
	11578	+ lsl r3, r3, #1
	11579	+ ldrh r2, [r5, r3]
	11580	+ cmp r9, r2
	11581	+ bls .L1993
	11582	+ ldrh r0, [r7, r3]
	11583	+ add fp, r7, r3
11234	11584	cmp r0, #0
11235		- bne .L2017
11236		- b .L2018
11237		-.L2016:
11238		- cmp r3, #0
11239		- bne .L2018
11240		- ldrh r0, [r7, r2]
11241		- add r10, r7, r2
	11585	+ bne .L1994
	11586	+.L1995:
	11587	+ add r6, r6, #1
	11588	+ b .L1992
	11589	+.L1993:
	11590	+ cmp r2, #0
	11591	+ bne .L1995
	11592	+ ldrh r0, [r7, r3]
	11593	+ add fp, r7, r3
11242	11594	cmp r0, #0
11243		- movne r6, r1
11244		- beq .L2018
11245		- b .L2020
11246		-.L2017:
11247		- cmp r3, #0
11248		- movne r1, r6
11249		- movne r9, r3
11250		- bne .L2018
11251		- mov r9, r3
11252		-.L2020:
	11595	+ beq .L1995
	11596	+.L1997:
11253	11597	mov r1, #1
11254	11598	bl FtlFreeSysBlkQueueIn
11255		- strh fp, [r10] @ movhi
	11599	+ strh r10, [fp] @ movhi
11256	11600	ldrh r3, [r4, #8]
11257		- mov r1, r6
11258	11601	sub r3, r3, #1
11259	11602	strh r3, [r4, #8] @ movhi
11260		-.L2018:
11261		- add r8, r8, #1
11262		- b .L2015
11263		-.L2032:
11264		- mov r0, r1
11265		- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
11266		-.L2034:
	11603	+ b .L1995
	11604	+.L1994:
	11605	+ subs r9, r2, #0
	11606	+ mov r8, r1
	11607	+ beq .L1997
	11608	+ b .L1995
	11609	+.L2008:
11267	11610	.align 2
11268		-.L2033:
	11611	+.L2007:
11269	11612	.word .LANCHOR2-1664
11270	11613	.fnend
11271	11614	.size ftl_free_no_use_map_blk, .-ftl_free_no_use_map_blk
11272	11615	.align 2
11273	11616	.global ftl_map_blk_alloc_new_blk
	11617	+ .syntax unified
	11618	+ .arm
	11619	+ .fpu softvfp
11274	11620	.type ftl_map_blk_alloc_new_blk, %function
11275	11621	ftl_map_blk_alloc_new_blk:
11276	11622	.fnstart
11277	11623	@ args = 0, pretend = 0, frame = 0
11278	11624	@ frame_needed = 0, uses_anonymous_args = 0
11279		- stmfd sp!, {r3, r4, r5, r6, r7, lr}
11280		- .save {r3, r4, r5, r6, r7, lr}
	11625	+ push {r4, r5, r6, r7, r8, lr}
	11626	+ .save {r4, r5, r6, r7, r8, lr}
11281	11627	mov r3, #0
11282	11628	ldrh r1, [r0, #10]
11283	11629	ldr r2, [r0, #12]
11284		-.L2036:
	11630	+.L2010:
11285	11631	uxth r5, r3
11286	11632	cmp r5, r1
11287		- bcs .L2039
	11633	+ bcs .L2013
11288	11634	mov r7, r2
11289	11635	add r3, r3, #1
11290	11636	ldrh r6, [r7]
11291	11637	add r2, r2, #2
11292	11638	cmp r6, #0
11293		- bne .L2036
	11639	+ bne .L2010
11294	11640	mov r4, r0
11295	11641	bl FtlFreeSysBlkQueueOut
11296		- movw r2, #65533
11297	11642	sub r3, r0, #1
	11643	+ movw r2, #65533
	11644	+ uxth r3, r3
11298	11645	mov r1, r0
11299	11646	strh r0, [r7] @ movhi
11300		- uxth r3, r3
11301	11647	cmp r3, r2
11302		- bls .L2037
11303		- ldr r3, .L2043
11304		- ldr r0, .L2043+4
	11648	+ bls .L2011
	11649	+ ldr r3, .L2017
	11650	+ ldr r0, .L2017+4
11305	11651	ldrh r2, [r3, #6]
11306	11652	bl printk
11307		-.L2038:
11308		- b .L2038
11309		-.L2037:
	11653	+.L2012:
	11654	+ b .L2012
	11655	+.L2011:
11310	11656	ldr r3, [r4, #28]
11311	11657	strh r6, [r4, #2] @ movhi
	11658	+ strh r5, [r4] @ movhi
11312	11659	add r3, r3, #1
11313	11660	str r3, [r4, #28]
11314	11661	ldrh r3, [r4, #8]
11315		- strh r5, [r4] @ movhi
11316	11662	add r3, r3, #1
11317	11663	strh r3, [r4, #8] @ movhi
11318		-.L2039:
	11664	+.L2013:
11319	11665	mov r0, #0
11320		- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
11321		-.L2044:
	11666	+ pop {r4, r5, r6, r7, r8, pc}
	11667	+.L2018:
11322	11668	.align 2
11323		-.L2043:
	11669	+.L2017:
11324	11670	.word .LANCHOR2-1240
11325	11671	.word .LC39
11326	11672	.fnend
11327	11673	.size ftl_map_blk_alloc_new_blk, .-ftl_map_blk_alloc_new_blk
11328	11674	.align 2
11329	11675	.global FtlMapWritePage
	11676	+ .syntax unified
	11677	+ .arm
	11678	+ .fpu softvfp
11330	11679	.type FtlMapWritePage, %function
11331	11680	FtlMapWritePage:
11332	11681	.fnstart
11333	11682	@ args = 0, pretend = 0, frame = 8
11334	11683	@ frame_needed = 0, uses_anonymous_args = 0
11335		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	11684	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
11336	11685	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
11337	11686	.pad #12
11338	11687	mov r4, r0
11339		- ldr fp, .L2064
	11688	+ ldr r5, .L2038
11340	11689	mov r8, r1
11341		- ldr r9, .L2064+4
11342		- mov r5, #0
11343		- str r2, [sp]
11344		- mov r10, fp
11345		-.L2046:
11346		- ldr r3, [fp, #-1592]
11347		- ldr r6, .L2064
	11690	+ mov r10, r2
	11691	+ mov r6, #0
	11692	+ sub r9, r5, #1664
	11693	+ mov fp, r9
	11694	+.L2020:
	11695	+ ldr r3, [r5, #-1588]
11348	11696	add r3, r3, #1
11349		- str r3, [fp, #-1592]
	11697	+ str r3, [r5, #-1588]
11350	11698	ldrh r3, [r9]
11351	11699	ldrh r2, [r4, #2]
11352	11700	sub r3, r3, #1
11353	11701	cmp r2, r3
11354		- bge .L2047
	11702	+ bge .L2021
11355	11703	ldrh r2, [r4]
11356	11704	movw r3, #65535
11357	11705	cmp r2, r3
11358		- bne .L2048
11359		-.L2047:
	11706	+ bne .L2022
	11707	+.L2021:
11360	11708	mov r0, r4
11361	11709	bl Ftl_write_map_blk_to_last_page
11362		-.L2048:
11363		- ldr r1, [r10, #-1280]
	11710	+.L2022:
	11711	+ ldr r1, [r5, #-1280]
11364	11712	cmp r1, #0
11365		- bne .L2049
	11713	+ bne .L2023
11366	11714	ldrh r3, [r4]
11367	11715	ldr r2, [r4, #12]
11368		- ldr r0, [fp, #-1444]
11369		- mov r3, r3, asl #1
	11716	+ ldr r0, [r5, #-1440]
	11717	+ lsl r3, r3, #1
11370	11718	ldrh r7, [r2, r3]
11371	11719	mov r2, #16
11372	11720	ldrh r3, [r4, #2]
11373		- str r0, [fp, #-1264]
11374		- orr r3, r3, r7, asl #10
11375		- str r3, [fp, #-1272]
11376		- ldr r3, [sp]
11377		- str r3, [fp, #-1268]
	11721	+ str r10, [r5, #-1268]
	11722	+ str r0, [r5, #-1264]
	11723	+ orr r3, r3, r7, lsl #10
	11724	+ str r3, [r5, #-1272]
11378	11725	bl ftl_memset
	11726	+ ldr r3, [r5, #-1264]
11379	11727	ldr r2, [r4, #28]
11380		- ldr r3, [fp, #-1264]
11381		- str r2, [r3, #4]
11382	11728	strh r8, [r3, #8] @ movhi
	11729	+ str r2, [r3, #4]
11383	11730	ldrh r2, [r4, #4]
	11731	+ str r3, [sp, #4]
11384	11732	strh r7, [r3, #2] @ movhi
11385	11733	strh r2, [r3] @ movhi
11386		- ldr r2, .L2064+8
11387		- ldrb r2, [r2] @ zero_extendqisi2
	11734	+ ldr r2, .L2038+4
	11735	+ ldrb r2, [r2, #36] @ zero_extendqisi2
11388	11736	cmp r2, #0
11389		- beq .L2050
11390		- ldr r2, .L2064+12
11391		- ldr r0, [fp, #-1268]
11392		- str r3, [sp, #4]
	11737	+ beq .L2024
	11738	+ ldr r2, .L2038+8
	11739	+ ldr r0, [r5, #-1268]
11393	11740	ldrh r1, [r2]
11394	11741	bl js_hash
11395	11742	ldr r3, [sp, #4]
11396	11743	str r0, [r3, #12]
11397		-.L2050:
11398		- mov r1, #1
11399		- ldr r0, .L2064+16
11400		- mov r2, r1
11401		- mov r3, r1
	11744	+.L2024:
	11745	+ mov r3, #1
	11746	+ ldr r0, .L2038+12
	11747	+ mov r2, r3
	11748	+ mov r1, r3
11402	11749	bl FlashProgPages
11403	11750	ldrh r3, [r4, #2]
11404	11751	add r3, r3, #1
11405	11752	uxth r3, r3
11406	11753	strh r3, [r4, #2] @ movhi
11407		- ldr r2, [r10, #-1276]
	11754	+ ldr r2, [r5, #-1276]
11408	11755	cmn r2, #1
11409		- bne .L2051
11410		- ldr r0, .L2064+20
11411		- add r5, r5, #1
11412		- ldr r1, [fp, #-1272]
	11756	+ bne .L2025
	11757	+ ldr r1, [r5, #-1272]
	11758	+ add r6, r6, #1
	11759	+ ldr r0, .L2038+16
	11760	+ uxth r6, r6
11413	11761	bl printk
11414	11762	ldrh r3, [r4, #2]
11415		- uxth r5, r5
11416	11763	cmp r3, #2
11417		- ldrlsh r3, [r9]
	11764	+ ldrhls r3, [fp]
11418	11765	subls r3, r3, #1
11419		- strlsh r3, [r4, #2] @ movhi
11420		- cmp r5, #3
11421		- bls .L2046
11422		- ldr r0, .L2064+24
11423		- mov r2, r5
11424		- ldr r1, [r6, #-1272]
	11766	+ strhls r3, [r4, #2] @ movhi
	11767	+ cmp r6, #3
	11768	+ bls .L2020
	11769	+ mov r2, r6
	11770	+ ldr r1, [r5, #-1272]
	11771	+ ldr r0, .L2038+20
11425	11772	bl printk
11426	11773	mov r3, #1
11427		- str r3, [r6, #-1280]
11428		- b .L2049
11429		-.L2051:
11430		- cmp r2, #0
11431		- strneh r7, [r4, #40] @ movhi
11432		- cmp r2, #256
11433		- cmpne r3, #1
11434		- beq .L2055
11435		- ldr r3, [r4, #36]
11436		- cmp r3, #0
11437		- beq .L2056
11438		-.L2055:
11439		- mov r3, #0
11440		- str r3, [r4, #36]
11441		- b .L2046
11442		-.L2056:
11443		- ldr r2, [r6, #-1272]
11444		- ldr r3, [r4, #24]
11445		- str r2, [r3, r8, asl #2]
11446		-.L2049:
	11774	+ str r3, [r5, #-1280]
	11775	+.L2023:
11447	11776	mov r0, #0
11448	11777	add sp, sp, #12
11449	11778	@ sp needed
11450		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
11451		-.L2065:
	11779	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	11780	+.L2025:
	11781	+ cmp r2, #0
	11782	+ strhne r7, [r4, #40] @ movhi
	11783	+ cmp r3, #1
	11784	+ cmpne r2, #256
	11785	+ beq .L2029
	11786	+ ldr r3, [r4, #36]
	11787	+ cmp r3, #0
	11788	+ beq .L2030
	11789	+.L2029:
	11790	+ mov r3, #0
	11791	+ str r3, [r4, #36]
	11792	+ b .L2020
	11793	+.L2030:
	11794	+ ldr r2, [r5, #-1272]
	11795	+ ldr r3, [r4, #24]
	11796	+ str r2, [r3, r8, lsl #2]
	11797	+ b .L2023
	11798	+.L2039:
11452	11799	.align 2
11453		-.L2064:
	11800	+.L2038:
11454	11801	.word .LANCHOR2
11455		- .word .LANCHOR2-1666
11456	11802	.word .LANCHOR0
11457		- .word .LANCHOR2-1658
	11803	+ .word .LANCHOR2-1656
11458	11804	.word .LANCHOR2-1276
11459	11805	.word .LC40
11460	11806	.word .LC41
..	..	@@ -11462,32 +11808,34 @@
11462	11808	.size FtlMapWritePage, .-FtlMapWritePage
11463	11809	.align 2
11464	11810	.global ftl_map_blk_gc
	11811	+ .syntax unified
	11812	+ .arm
	11813	+ .fpu softvfp
11465	11814	.type ftl_map_blk_gc, %function
11466	11815	ftl_map_blk_gc:
11467	11816	.fnstart
11468	11817	@ args = 0, pretend = 0, frame = 8
11469	11818	@ frame_needed = 0, uses_anonymous_args = 0
11470		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	11819	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
11471	11820	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
11472	11821	.pad #12
11473	11822	mov r4, r0
11474	11823	ldr r5, [r0, #12]
11475		- ldr r7, [r0, #24]
	11824	+ ldr r10, [r0, #24]
11476	11825	bl ftl_free_no_use_map_blk
11477	11826	ldrh r3, [r4, #10]
11478	11827	ldrh r2, [r4, #8]
11479	11828	sub r3, r3, #4
11480		- ldr r8, .L2080
11481	11829	cmp r2, r3
11482		- blt .L2067
	11830	+ blt .L2041
11483	11831	uxth r0, r0
11484		- mov r0, r0, asl #1
11485		- ldrh r10, [r5, r0]
11486		- cmp r10, #0
11487		- beq .L2067
	11832	+ lsl r0, r0, #1
	11833	+ ldrh r9, [r5, r0]
	11834	+ cmp r9, #0
	11835	+ beq .L2041
11488	11836	ldr r3, [r4, #32]
11489	11837	cmp r3, #0
11490		- bne .L2067
	11838	+ bne .L2041
11491	11839	mov r2, #1
11492	11840	str r2, [r4, #32]
11493	11841	strh r3, [r5, r0] @ movhi
..	..	@@ -11495,112 +11843,118 @@
11495	11843	ldrh r2, [r4, #2]
11496	11844	sub r3, r3, #1
11497	11845	strh r3, [r4, #8] @ movhi
11498		- ldrh r3, [r8, #-2]
	11846	+ ldr r3, .L2053
	11847	+ ldrh r3, [r3]
11499	11848	cmp r2, r3
11500		- bcc .L2068
	11849	+ bcc .L2042
11501	11850	mov r0, r4
11502	11851	bl ftl_map_blk_alloc_new_blk
11503		-.L2068:
11504		- ldr r5, .L2080+4
11505		- mov fp, #0
11506		-.L2069:
11507		- ldrh r3, [r4, #6]
11508		- uxth r6, fp
11509		- cmp r3, r6
11510		- bls .L2079
11511		- ldr r3, [r7, r6, asl #2]
11512		- add ip, r7, r6, asl #2
11513		- cmp r10, r3, lsr #10
11514		- bne .L2070
11515		- ldr r3, [r5, #-1472]
	11852	+.L2042:
	11853	+ ldr r5, .L2053+4
	11854	+ mov r6, #0
	11855	+ sub fp, r5, #1264
	11856	+ sub fp, fp, #12
	11857	+.L2043:
	11858	+ ldrh r2, [r4, #6]
	11859	+ uxth r3, r6
	11860	+ cmp r2, r3
	11861	+ bhi .L2048
11516	11862	mov r1, #1
11517		- ldr r9, [r5, #-1444]
11518		- mov r2, r1
11519		- ldr r0, .L2080+8
11520		- str r3, [r5, #-1268]
11521		- str r9, [r5, #-1264]
11522		- ldr r3, [r7, r6, asl #2]
11523		- str ip, [sp, #4]
11524		- str r3, [r5, #-1272]
11525		- bl FlashReadPages
11526		- ldr r3, [r5, #-1276]
11527		- cmn r3, #1
11528		- ldr r3, .L2080+4
11529		- ldr ip, [sp, #4]
11530		- bne .L2071
11531		-.L2073:
11532		- mov r2, #0
11533		- ldr r0, .L2080+12
11534		- str r2, [ip]
11535		- ldr r1, [r3, #-1272]
11536		- ldrh r2, [r9, #8]
11537		- str r3, [sp, #4]
11538		- bl printk
11539		- mov r2, #1
11540		- ldr r3, [sp, #4]
11541		- str r2, [r3, #-1280]
11542		- b .L2072
11543		-.L2071:
11544		- ldrh r1, [r9, #8]
11545		- cmp r1, r6
11546		- bne .L2073
11547		- ldrh r0, [r9]
11548		- ldrh r2, [r4, #4]
11549		- cmp r0, r2
11550		- bne .L2073
11551		- mov r0, r4
11552		- ldr r2, [r5, #-1268]
11553		- bl FtlMapWritePage
11554		-.L2070:
11555		- add fp, fp, #1
11556		- b .L2069
11557		-.L2079:
11558		- mov r0, r10
11559		- mov r1, #1
	11863	+ mov r0, r9
11560	11864	bl FtlFreeSysBlkQueueIn
11561	11865	mov r3, #0
11562	11866	str r3, [r4, #32]
11563		-.L2067:
	11867	+.L2041:
	11868	+ ldr r3, .L2053
11564	11869	ldrh r2, [r4, #2]
11565		- ldrh r3, [r8, #-2]
	11870	+ ldrh r3, [r3]
11566	11871	cmp r2, r3
11567		- bcc .L2072
	11872	+ bcc .L2046
11568	11873	mov r0, r4
11569	11874	bl ftl_map_blk_alloc_new_blk
11570		-.L2072:
	11875	+ b .L2046
	11876	+.L2048:
	11877	+ uxth r7, r6
	11878	+ add r2, r10, r7, lsl #2
	11879	+ str r2, [sp]
	11880	+ ldr r2, [r10, r7, lsl #2]
	11881	+ cmp r9, r2, lsr #10
	11882	+ bne .L2044
	11883	+ ldr r2, [r5, #-1468]
	11884	+ mov r0, fp
	11885	+ ldr r8, [r5, #-1440]
	11886	+ str r3, [sp, #4]
	11887	+ str r2, [r5, #-1268]
	11888	+ str r8, [r5, #-1264]
	11889	+ ldr r2, [r10, r7, lsl #2]
	11890	+ str r2, [r5, #-1272]
	11891	+ mov r2, #1
	11892	+ mov r1, r2
	11893	+ bl FlashReadPages
	11894	+ ldr r2, [r5, #-1276]
	11895	+ ldr r3, [sp, #4]
	11896	+ cmn r2, #1
	11897	+ bne .L2045
	11898	+.L2047:
	11899	+ ldr r2, [sp]
	11900	+ mov r3, #0
	11901	+ ldr r0, .L2053+8
	11902	+ str r3, [r2]
	11903	+ ldrh r2, [r8, #8]
	11904	+ ldr r1, [r5, #-1272]
	11905	+ bl printk
	11906	+ mov r3, #1
	11907	+ str r3, [r5, #-1280]
	11908	+.L2046:
11571	11909	mov r0, #0
11572	11910	add sp, sp, #12
11573	11911	@ sp needed
11574		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
11575		-.L2081:
	11912	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	11913	+.L2045:
	11914	+ ldrh r2, [r8, #8]
	11915	+ cmp r2, r3
	11916	+ bne .L2047
	11917	+ ldrh r2, [r8]
	11918	+ ldrh r3, [r4, #4]
	11919	+ cmp r2, r3
	11920	+ bne .L2047
	11921	+ ldr r2, [r5, #-1268]
	11922	+ mov r1, r7
	11923	+ mov r0, r4
	11924	+ bl FtlMapWritePage
	11925	+.L2044:
	11926	+ add r6, r6, #1
	11927	+ b .L2043
	11928	+.L2054:
11576	11929	.align 2
11577		-.L2080:
	11930	+.L2053:
11578	11931	.word .LANCHOR2-1664
11579	11932	.word .LANCHOR2
11580		- .word .LANCHOR2-1276
11581	11933	.word .LC42
11582	11934	.fnend
11583	11935	.size ftl_map_blk_gc, .-ftl_map_blk_gc
11584	11936	.align 2
11585	11937	.global Ftl_write_map_blk_to_last_page
	11938	+ .syntax unified
	11939	+ .arm
	11940	+ .fpu softvfp
11586	11941	.type Ftl_write_map_blk_to_last_page, %function
11587	11942	Ftl_write_map_blk_to_last_page:
11588	11943	.fnstart
11589	11944	@ args = 0, pretend = 0, frame = 0
11590	11945	@ frame_needed = 0, uses_anonymous_args = 0
11591		- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
11592		- .save {r3, r4, r5, r6, r7, r8, r9, lr}
11593		- ldr r5, .L2094
11594		- ldr r7, [r0, #12]
11595		- ldr r8, [r0, #24]
	11946	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
	11947	+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
	11948	+ ldr r5, .L2066
11596	11949	ldr r6, [r5, #-1280]
11597	11950	cmp r6, #0
11598		- bne .L2083
	11951	+ bne .L2056
11599	11952	ldrh r3, [r0]
11600	11953	movw r2, #65535
11601	11954	mov r4, r0
	11955	+ ldr r7, [r0, #12]
11602	11956	cmp r3, r2
11603		- bne .L2084
	11957	+ bne .L2057
11604	11958	ldrh r3, [r0, #8]
11605	11959	add r3, r3, #1
11606	11960	strh r3, [r0, #8] @ movhi
..	..	@@ -11608,80 +11962,83 @@
11608	11962	strh r0, [r7] @ movhi
11609	11963	ldr r3, [r4, #28]
11610	11964	strh r6, [r4, #2] @ movhi
11611		- add r3, r3, #1
11612	11965	strh r6, [r4] @ movhi
	11966	+ add r3, r3, #1
11613	11967	str r3, [r4, #28]
11614		- b .L2083
11615		-.L2084:
11616		- mov r3, r3, asl #1
	11968	+.L2056:
	11969	+ mov r0, #0
	11970	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	11971	+.L2057:
	11972	+ lsl r3, r3, #1
	11973	+ ldr r8, [r0, #24]
11617	11974	mov r1, #255
11618	11975	ldrh r9, [r7, r3]
11619	11976	ldrh r3, [r0, #2]
11620		- ldr r7, [r5, #-1444]
11621		- orr r3, r3, r9, asl #10
11622		- str r3, [r5, #-1272]
11623		- ldr r3, [r5, #-1476]
	11977	+ ldr r7, [r5, #-1440]
	11978	+ orr r3, r3, r9, lsl #10
11624	11979	str r7, [r5, #-1264]
	11980	+ str r3, [r5, #-1272]
	11981	+ ldr r3, [r5, #-1472]
11625	11982	str r3, [r5, #-1268]
11626	11983	ldr r3, [r0, #28]
11627	11984	str r3, [r7, #4]
11628		- ldr r3, .L2094+4
	11985	+ ldr r3, .L2066+4
11629	11986	strh r3, [r7, #8] @ movhi
11630	11987	ldrh r3, [r0, #4]
11631	11988	strh r9, [r7, #2] @ movhi
11632	11989	strh r3, [r7] @ movhi
11633	11990	sub r3, r5, #1664
11634		- ldr r0, [r5, #-1476]
11635		- ldrh r2, [r3, #-2]
11636		- mov r2, r2, asl #3
	11991	+ ldrh r2, [r3]
	11992	+ ldr r0, [r5, #-1472]
	11993	+ lsl r2, r2, #3
11637	11994	bl ftl_memset
	11995	+ mov r2, r6
11638	11996	mov r3, r6
11639		-.L2085:
11640		- ldrh r1, [r4, #6]
11641		- uxth r2, r6
11642		- cmp r1, r2
11643		- bls .L2093
11644		- ldr r1, [r8, r2, asl #2]
11645		- cmp r9, r1, lsr #10
11646		- bne .L2086
11647		- add r3, r3, #1
11648		- ldr r1, [r5, #-1476]
11649		- uxth r3, r3
11650		- str r2, [r1, r3, asl #3]
11651		- ldr r1, [r8, r2, asl #2]
11652		- ldr r2, [r5, #-1476]
11653		- add r2, r2, r3, asl #3
11654		- str r1, [r2, #4]
11655		-.L2086:
11656		- add r6, r6, #1
11657		- b .L2085
11658		-.L2093:
11659		- ldr r3, .L2094+8
11660		- ldrb r3, [r3] @ zero_extendqisi2
	11997	+.L2058:
	11998	+ ldrh r0, [r4, #6]
	11999	+ uxth r1, r2
	12000	+ cmp r0, r1
	12001	+ bhi .L2060
	12002	+ ldr r3, .L2066+8
	12003	+ ldrb r3, [r3, #36] @ zero_extendqisi2
11661	12004	cmp r3, #0
11662		- beq .L2088
11663		- ldr r3, .L2094+12
	12005	+ beq .L2061
	12006	+ ldr r3, .L2066+12
11664	12007	ldr r0, [r5, #-1268]
11665		- ldrh r1, [r3, #-10]
	12008	+ ldrh r1, [r3, #-8]
11666	12009	bl js_hash
11667	12010	str r0, [r7, #12]
11668		-.L2088:
11669		- mov r1, #1
	12011	+.L2061:
	12012	+ mov r2, #1
11670	12013	mov r3, #0
11671		- ldr r0, .L2094+16
11672		- mov r2, r1
	12014	+ mov r1, r2
	12015	+ ldr r0, .L2066+16
11673	12016	bl FlashProgPages
11674	12017	ldrh r3, [r4, #2]
11675	12018	mov r0, r4
11676	12019	add r3, r3, #1
11677	12020	strh r3, [r4, #2] @ movhi
11678	12021	bl ftl_map_blk_gc
11679		-.L2083:
11680		- mov r0, #0
11681		- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
11682		-.L2095:
	12022	+ b .L2056
	12023	+.L2060:
	12024	+ uxth r1, r2
	12025	+ ldr r0, [r8, r1, lsl #2]
	12026	+ cmp r9, r0, lsr #10
	12027	+ bne .L2059
	12028	+ ldr r0, [r5, #-1472]
	12029	+ add r3, r3, #1
	12030	+ uxth r3, r3
	12031	+ str r1, [r0, r3, lsl #3]
	12032	+ ldr r0, [r8, r1, lsl #2]
	12033	+ ldr r1, [r5, #-1472]
	12034	+ add r1, r1, r3, lsl #3
	12035	+ str r0, [r1, #4]
	12036	+.L2059:
	12037	+ add r2, r2, #1
	12038	+ b .L2058
	12039	+.L2067:
11683	12040	.align 2
11684		-.L2094:
	12041	+.L2066:
11685	12042	.word .LANCHOR2
11686	12043	.word -1291
11687	12044	.word .LANCHOR0
..	..	@@ -11691,18 +12048,21 @@
11691	12048	.size Ftl_write_map_blk_to_last_page, .-Ftl_write_map_blk_to_last_page
11692	12049	.align 2
11693	12050	.global flush_l2p_region
	12051	+ .syntax unified
	12052	+ .arm
	12053	+ .fpu softvfp
11694	12054	.type flush_l2p_region, %function
11695	12055	flush_l2p_region:
11696	12056	.fnstart
11697	12057	@ args = 0, pretend = 0, frame = 0
11698	12058	@ frame_needed = 0, uses_anonymous_args = 0
11699		- stmfd sp!, {r3, r4, r5, lr}
11700		- .save {r3, r4, r5, lr}
	12059	+ push {r4, r5, r6, lr}
	12060	+ .save {r4, r5, r6, lr}
11701	12061	mov r4, #12
11702		- ldr r5, .L2098
	12062	+ ldr r5, .L2070
11703	12063	mul r4, r4, r0
11704		- add r0, r5, #1024
11705	12064	ldr r3, [r5, #-1364]
	12065	+ add r0, r5, #1024
11706	12066	add r0, r0, #4
11707	12067	add r2, r3, r4
11708	12068	ldrh r1, [r3, r4]
..	..	@@ -11714,195 +12074,195 @@
11714	12074	ldr r3, [r4, #4]
11715	12075	bic r3, r3, #-2147483648
11716	12076	str r3, [r4, #4]
11717		- ldmfd sp!, {r3, r4, r5, pc}
11718		-.L2099:
	12077	+ pop {r4, r5, r6, pc}
	12078	+.L2071:
11719	12079	.align 2
11720		-.L2098:
	12080	+.L2070:
11721	12081	.word .LANCHOR2
11722	12082	.fnend
11723	12083	.size flush_l2p_region, .-flush_l2p_region
11724	12084	.align 2
11725	12085	.global select_l2p_ram_region
	12086	+ .syntax unified
	12087	+ .arm
	12088	+ .fpu softvfp
11726	12089	.type select_l2p_ram_region, %function
11727	12090	select_l2p_ram_region:
11728	12091	.fnstart
11729	12092	@ args = 0, pretend = 0, frame = 0
11730	12093	@ frame_needed = 0, uses_anonymous_args = 0
11731		- ldr r3, .L2116
	12094	+ ldr r3, .L2083
11732	12095	mov r1, #0
11733		- stmfd sp!, {r4, r5, r6, lr}
	12096	+ push {r4, r5, r6, lr}
11734	12097	.save {r4, r5, r6, lr}
11735		- sub r2, r3, #1616
11736		- ldr r3, [r3, #-1364]
11737	12098	mov ip, #12
11738		- ldrh r2, [r2, #-14]
11739	12099	movw lr, #65535
11740		-.L2101:
	12100	+ sub r2, r3, #1616
	12101	+ ldrh r2, [r2, #-10]
	12102	+ ldr r3, [r3, #-1364]
	12103	+.L2073:
11741	12104	uxth r0, r1
11742	12105	cmp r0, r2
11743		- bcs .L2113
11744		- add r1, r1, #1
11745		- mla r4, ip, r1, r3
11746		- ldrh r4, [r4, #-12]
11747		- cmp r4, lr
11748		- bne .L2101
11749		- ldmfd sp!, {r4, r5, r6, pc}
11750		-.L2113:
	12106	+ bcc .L2075
11751	12107	mov r0, r2
11752	12108	mov r1, #0
11753	12109	mov ip, #-2147483648
11754	12110	mov r5, #12
11755		-.L2104:
	12111	+.L2076:
11756	12112	uxth r4, r1
11757	12113	cmp r4, r2
11758		- bcs .L2114
11759		- mla lr, r5, r1, r3
11760		- add r1, r1, #1
11761		- ldr lr, [lr, #4]
11762		- cmp lr, ip
11763		- mvn r6, lr
11764		- mov r6, r6, lsr #31
11765		- movcs r6, #0
11766		- cmp r6, #0
11767		- movne ip, lr
11768		- movne r0, r4
11769		- b .L2104
11770		-.L2114:
	12114	+ bcc .L2078
11771	12115	cmp r0, r2
11772		- ldmccfd sp!, {r4, r5, r6, pc}
11773		- ldr r1, .L2116+4
	12116	+ popcc {r4, r5, r6, pc}
	12117	+ ldr r1, .L2083+4
11774	12118	mov r0, r2
11775	12119	mvn ip, #0
11776	12120	ldrh r5, [r1]
11777	12121	mov r1, #0
11778		-.L2107:
	12122	+.L2079:
11779	12123	uxth lr, r1
11780	12124	cmp lr, r2
11781		- bcs .L2115
	12125	+ bcc .L2081
	12126	+ pop {r4, r5, r6, pc}
	12127	+.L2075:
	12128	+ add r1, r1, #1
	12129	+ mla r4, ip, r1, r3
	12130	+ ldrh r4, [r4, #-12]
	12131	+ cmp r4, lr
	12132	+ bne .L2073
	12133	+ pop {r4, r5, r6, pc}
	12134	+.L2078:
	12135	+ mla lr, r5, r1, r3
	12136	+ add r1, r1, #1
	12137	+ ldr lr, [lr, #4]
	12138	+ cmp ip, lr
	12139	+ movls r6, #0
	12140	+ movhi r6, #1
	12141	+ cmp lr, #0
	12142	+ movlt r6, #0
	12143	+ cmp r6, #0
	12144	+ movne ip, lr
	12145	+ movne r0, r4
	12146	+ b .L2076
	12147	+.L2081:
11782	12148	ldr r4, [r3, #4]
11783		- cmp r4, ip
11784		- bcs .L2108
	12149	+ cmp ip, r4
	12150	+ bls .L2080
11785	12151	ldrh r6, [r3]
11786	12152	cmp r6, r5
11787	12153	movne ip, r4
11788	12154	movne r0, lr
11789		-.L2108:
	12155	+.L2080:
11790	12156	add r1, r1, #1
11791	12157	add r3, r3, #12
11792		- b .L2107
11793		-.L2115:
11794		- ldmfd sp!, {r4, r5, r6, pc}
11795		-.L2117:
	12158	+ b .L2079
	12159	+.L2084:
11796	12160	.align 2
11797		-.L2116:
	12161	+.L2083:
11798	12162	.word .LANCHOR2
11799	12163	.word .LANCHOR2+1072
11800	12164	.fnend
11801	12165	.size select_l2p_ram_region, .-select_l2p_ram_region
11802	12166	.align 2
11803	12167	.global log2phys
	12168	+ .syntax unified
	12169	+ .arm
	12170	+ .fpu softvfp
11804	12171	.type log2phys, %function
11805	12172	log2phys:
11806	12173	.fnstart
11807	12174	@ args = 0, pretend = 0, frame = 16
11808	12175	@ frame_needed = 0, uses_anonymous_args = 0
11809		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	12176	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
11810	12177	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
11811	12178	.pad #20
11812	12179	sub sp, sp, #20
11813		- ldr r6, .L2135
11814		- sub r3, r6, #1648
11815		- str r3, [sp, #8]
11816		- ldr ip, [r6, #-1284]
11817		- ldrh r10, [r3, #-12]
11818		- cmp r0, ip
11819		- bcs .L2119
11820		- add r10, r10, #7
11821		- mov fp, r6
11822		- mov r6, r0, lsr r10
11823		- sub r3, fp, #1616
11824		- str r2, [sp, #12]
11825		- mov r9, r1
11826		- ldrh r2, [r3, #-14]
11827		- uxth r6, r6
11828		- str r0, [sp, #4]
	12180	+ ldr r4, .L2101
	12181	+ ldr r3, [r4, #-1284]
	12182	+ cmp r0, r3
	12183	+ bcs .L2086
	12184	+ sub fp, r4, #1648
	12185	+ mov r9, r0
	12186	+ ldrh r0, [fp, #-10]
	12187	+ mov r10, r1
	12188	+ str r2, [sp, #8]
	12189	+ mov r5, #12
	12190	+ ldr r2, [r4, #-1364]
	12191	+ add r3, r0, #7
	12192	+ str fp, [sp, #4]
	12193	+ lsr r6, r9, r3
	12194	+ str r3, [sp]
	12195	+ sub r3, r4, #1616
	12196	+ uxth r8, r6
	12197	+ ldrh r1, [r3, #-10]
11829	12198	mov r3, #0
11830		- ldr r4, [fp, #-1364]
11831		- mov r1, #12
11832		- b .L2120
11833		-.L2119:
	12199	+.L2087:
	12200	+ uxth r7, r3
	12201	+ cmp r7, r1
	12202	+ bcc .L2092
	12203	+ str r2, [sp, #12]
	12204	+ bl select_l2p_ram_region
	12205	+ mul r5, r5, r0
	12206	+ ldr r2, [sp, #12]
	12207	+ mov r7, r0
	12208	+ ldrh r1, [r2, r5]
	12209	+ add r3, r2, r5
	12210	+ movw r2, #65535
	12211	+ cmp r1, r2
	12212	+ beq .L2093
	12213	+ ldr r3, [r3, #4]
	12214	+ cmp r3, #0
	12215	+ bge .L2093
	12216	+ bl flush_l2p_region
	12217	+.L2093:
	12218	+ ldr r3, [r4, #-1376]
	12219	+ uxth r6, r6
	12220	+ ldr fp, [r3, r6, lsl #2]
	12221	+ cmp fp, #0
	12222	+ bne .L2094
	12223	+ ldr r0, [r4, #-1364]
	12224	+ mov r1, #255
	12225	+ ldr r3, [sp, #4]
	12226	+ add r0, r0, r5
	12227	+ ldrh r2, [r3, #-8]
	12228	+ ldr r0, [r0, #8]
	12229	+ bl ftl_memset
	12230	+ ldr r2, [r4, #-1364]
	12231	+ strh r8, [r2, r5] @ movhi
	12232	+ ldr r2, [r4, #-1364]
	12233	+ add r5, r2, r5
	12234	+ str fp, [r5, #4]
	12235	+ b .L2089
	12236	+.L2086:
11834	12237	cmp r2, #0
11835	12238	mvn r0, #0
11836	12239	streq r0, [r1]
11837		- b .L2121
11838		-.L2125:
	12240	+.L2085:
	12241	+ add sp, sp, #20
	12242	+ @ sp needed
	12243	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	12244	+.L2092:
11839	12245	add r3, r3, #1
11840		- mla r0, r1, r3, r4
	12246	+ mla r0, r5, r3, r2
11841	12247	ldrh r0, [r0, #-12]
11842		- cmp r0, r6
11843		- beq .L2122
11844		-.L2120:
11845		- uxth r7, r3
11846		- cmp r7, r2
11847		- bcc .L2125
11848		- bl select_l2p_ram_region
11849		- mov r5, #12
11850		- movw r2, #65535
11851		- mul r5, r5, r0
11852		- mov r7, r0
11853		- add r3, r4, r5
11854		- ldrh r1, [r4, r5]
11855		- cmp r1, r2
11856		- bne .L2134
11857		-.L2126:
11858		- ldr r3, [fp, #-1376]
11859		- ldr r4, .L2135
11860		- ldr r8, [r3, r6, asl #2]
11861		- cmp r8, #0
11862		- bne .L2127
11863		- ldr r2, [r4, #-1364]
11864		- mov r1, #255
	12248	+ cmp r0, r8
	12249	+ bne .L2087
	12250	+.L2089:
	12251	+ ldr r3, [sp]
	12252	+ mvn r0, #0
	12253	+ bic r9, r9, r0, lsl r3
11865	12254	ldr r3, [sp, #8]
11866		- add r2, r2, r5
11867		- ldr r0, [r2, #8]
11868		- ldrh r2, [r3, #-10]
11869		- bl ftl_memset
11870		- ldr r2, [r4, #-1364]
11871		- strh r6, [r2, r5] @ movhi
11872		- ldr r2, [r4, #-1364]
11873		- add r5, r2, r5
11874		- str r8, [r5, #4]
11875		-.L2122:
11876		- ldr r3, [sp, #4]
11877		- mvn r2, #0
11878		- bic r10, r3, r2, asl r10
11879		- ldr r3, [sp, #12]
	12255	+ uxth r9, r9
11880	12256	cmp r3, #0
11881		- uxth r10, r10
11882	12257	mov r3, #12
11883		- bne .L2123
11884		- ldr r2, [fp, #-1364]
	12258	+ bne .L2090
	12259	+ ldr r2, [r4, #-1364]
11885	12260	mla r3, r3, r7, r2
11886	12261	ldr r3, [r3, #8]
11887		- ldr r3, [r3, r10, asl #2]
11888		- str r3, [r9]
11889		- b .L2124
11890		-.L2123:
11891		- mul r3, r3, r7
11892		- ldr r2, [fp, #-1364]
11893		- ldr r1, [r9]
11894		- add r2, r2, r3
11895		- ldr r2, [r2, #8]
11896		- str r1, [r2, r10, asl #2]
11897		- ldr r2, [fp, #-1364]
11898		- add r3, r2, r3
11899		- ldr r2, [r3, #4]
11900		- orr r2, r2, #-2147483648
11901		- str r2, [r3, #4]
11902		- ldr r3, .L2135+4
11903		- strh r6, [r3] @ movhi
11904		-.L2124:
11905		- ldr r2, [fp, #-1364]
	12262	+ ldr r3, [r3, r9, lsl #2]
	12263	+ str r3, [r10]
	12264	+.L2091:
	12265	+ ldr r2, [r4, #-1364]
11906	12266	mov r3, #12
11907	12267	mov r0, #0
11908	12268	mla r7, r3, r7, r2
..	..	@@ -11910,80 +12270,86 @@
11910	12270	cmn r3, #1
11911	12271	addne r3, r3, #1
11912	12272	strne r3, [r7, #4]
11913		- b .L2121
11914		-.L2134:
11915		- ldr r3, [r3, #4]
11916		- cmp r3, #0
11917		- bge .L2126
11918		- bl flush_l2p_region
11919		- b .L2126
11920		-.L2127:
	12273	+ b .L2085
	12274	+.L2090:
	12275	+ mul r3, r3, r7
11921	12276	ldr r2, [r4, #-1364]
11922		- mov r1, #1
11923		- ldr r0, .L2135+8
	12277	+ ldr r1, [r10]
	12278	+ add r2, r2, r3
	12279	+ ldr r2, [r2, #8]
	12280	+ str r1, [r2, r9, lsl #2]
	12281	+ ldr r2, [r4, #-1364]
	12282	+ add r3, r2, r3
	12283	+ ldr r2, [r3, #4]
	12284	+ orr r2, r2, #-2147483648
	12285	+ str r2, [r3, #4]
	12286	+ ldr r3, .L2101+4
	12287	+ strh r8, [r3] @ movhi
	12288	+ b .L2091
	12289	+.L2094:
	12290	+ ldr r2, [r4, #-1364]
	12291	+ ldr r0, .L2101+8
	12292	+ str fp, [r4, #-1272]
11924	12293	add r2, r2, r5
11925		- str r8, [r4, #-1272]
11926	12294	ldr r2, [r2, #8]
11927	12295	str r2, [r4, #-1268]
11928		- ldr r2, [r4, #-1444]
	12296	+ ldr r2, [r4, #-1440]
11929	12297	str r2, [r4, #-1264]
11930		- mov r2, r1
	12298	+ mov r2, #1
	12299	+ mov r1, r2
11931	12300	bl FlashReadPages
11932	12301	ldr r2, [r4, #-1264]
11933	12302	ldrh r2, [r2, #8]
11934		- cmp r2, r6
11935		- beq .L2128
	12303	+ cmp r2, r8
	12304	+ beq .L2095
	12305	+ mov r2, fp
11936	12306	mov r1, r6
11937		- mov r2, r8
11938		- ldr r0, .L2135+12
	12307	+ ldr r0, .L2101+12
11939	12308	bl printk
11940		- mov r2, #4
11941		- mov r3, r2
11942		- ldr r0, .L2135+16
	12309	+ mov r3, #4
11943	12310	ldr r1, [r4, #-1264]
	12311	+ mov r2, r3
	12312	+ ldr r0, .L2101+16
11944	12313	bl rknand_print_hex
11945		- sub r3, r4, #1632
11946		- ldr r0, .L2135+20
	12314	+ ldr r3, .L2101+20
11947	12315	mov r2, #4
11948		- ldrh r3, [r3]
11949	12316	ldr r1, [r4, #-1376]
	12317	+ ldr r0, .L2101+24
	12318	+ ldrh r3, [r3, #-12]
11950	12319	bl rknand_print_hex
11951	12320	mov r3, #1
11952	12321	str r3, [r4, #-1280]
11953		- b .L2129
11954		-.L2128:
11955		- ldr r2, [r4, #-1276]
11956		- cmp r2, #256
11957		- bne .L2129
11958		- mov r1, r6
11959		- mov r2, r8
11960		- ldr r0, .L2135+24
11961		- bl printk
	12322	+.L2096:
11962	12323	ldr r3, [r4, #-1364]
11963		- ldr r0, .L2135+28
11964		- mov r1, r6
11965		- add r3, r3, r5
11966		- ldr r2, [r3, #8]
11967		- bl FtlMapWritePage
11968		-.L2129:
11969		- ldr r3, [fp, #-1364]
11970	12324	mov r1, #0
11971	12325	add r2, r3, r5
11972	12326	str r1, [r2, #4]
11973		- strh r6, [r3, r5] @ movhi
11974		- b .L2122
11975		-.L2121:
11976		- add sp, sp, #20
11977		- @ sp needed
11978		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
11979		-.L2136:
	12327	+ strh r8, [r3, r5] @ movhi
	12328	+ b .L2089
	12329	+.L2095:
	12330	+ ldr r2, [r4, #-1276]
	12331	+ cmp r2, #256
	12332	+ bne .L2096
	12333	+ mov r2, fp
	12334	+ mov r1, r6
	12335	+ ldr r0, .L2101+28
	12336	+ bl printk
	12337	+ ldr r3, [r4, #-1364]
	12338	+ mov r1, r6
	12339	+ ldr r0, .L2101+32
	12340	+ add r3, r3, r5
	12341	+ ldr r2, [r3, #8]
	12342	+ bl FtlMapWritePage
	12343	+ b .L2096
	12344	+.L2102:
11980	12345	.align 2
11981		-.L2135:
	12346	+.L2101:
11982	12347	.word .LANCHOR2
11983	12348	.word .LANCHOR2+1072
11984	12349	.word .LANCHOR2-1276
11985	12350	.word .LC43
11986	12351	.word .LC18
	12352	+ .word .LANCHOR2-1616
11987	12353	.word .LC44
11988	12354	.word .LC45
11989	12355	.word .LANCHOR2+1028
..	..	@@ -11991,1376 +12357,1387 @@
11991	12357	.size log2phys, .-log2phys
11992	12358	.align 2
11993	12359	.global FtlVendorPartWrite
	12360	+ .syntax unified
	12361	+ .arm
	12362	+ .fpu softvfp
11994	12363	.type FtlVendorPartWrite, %function
11995	12364	FtlVendorPartWrite:
11996	12365	.fnstart
11997	12366	@ args = 0, pretend = 0, frame = 56
11998	12367	@ frame_needed = 0, uses_anonymous_args = 0
11999		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	12368	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
12000	12369	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
12001		- mov fp, r2
12002		- ldr r6, .L2148
	12370	+ mov r10, r2
	12371	+ ldr r4, .L2113
12003	12372	add r2, r0, r1
12004		- mov r7, r0
12005	12373	.pad #60
12006	12374	sub sp, sp, #60
12007		- mov r4, r1
12008		- ldrh r3, [r6, #-24]
12009		- ldrh r5, [r6, #-12]
	12375	+ ldrh r3, [r4, #-6]
12010	12376	cmp r2, r3
12011		- mvnhi r0, #0
12012		- bhi .L2138
12013		- mov r5, r7, lsr r5
12014		- mov r3, #0
12015		- str r3, [sp]
12016		- add r3, r6, #1648
12017		- mov r10, r5, asl #2
	12377	+ mvnhi r8, #0
	12378	+ bhi .L2103
	12379	+ add r4, r4, #1664
	12380	+ mov r9, r0
	12381	+ sub r3, r4, #1648
	12382	+ mov r6, r1
	12383	+ ldrh r7, [r3, #-10]
	12384	+ mov r8, #0
12018	12385	str r3, [sp, #4]
12019		- mov r8, r3
12020		-.L2139:
12021		- cmp r4, #0
12022		- beq .L2147
12023		- ldr r3, [sp, #4]
12024		- mov r0, r7
12025		- ldr r3, [r3, #-1380]
12026		- ldr ip, [r3, r10]
12027		- ldr r3, .L2148+4
12028		- str ip, [sp, #12]
12029		- ldrh r2, [r3]
12030		- mov r1, r2
12031		- str r2, [sp, #8]
12032		- bl __aeabi_uidivmod
12033		- ldr r2, [sp, #8]
12034		- mov r9, r1
12035		- ldr ip, [sp, #12]
12036		- rsb r3, r1, r2
12037		- uxth r6, r3
12038		- cmp r6, r4
12039		- uxthhi r6, r4
12040		- cmp r6, r2
12041		- cmpne ip, #0
12042		- movne r1, #1
12043		- moveq r1, #0
12044		- beq .L2141
12045		- ldr r2, [r8, #-1468]
12046		- mov r1, #1
12047		- add r0, sp, #20
12048		- str ip, [sp, #24]
12049		- str r2, [sp, #28]
12050		- mov r2, #0
12051		- str r2, [sp, #32]
12052		- mov r2, r1
12053		- bl FlashReadPages
12054		- b .L2142
12055		-.L2141:
12056		- ldr r2, .L2148+8
12057		- ldr r0, [r8, #-1468]
12058		- ldrh r2, [r2]
12059		- bl ftl_memset
12060		-.L2142:
12061		- mov ip, r6, asl #9
12062		- ldr r0, [r8, #-1468]
12063		- uxth r9, r9
12064		- mov r1, fp
12065		- mov r2, ip
12066		- str ip, [sp, #8]
12067		- add r0, r0, r9, asl #9
12068		- rsb r4, r6, r4
12069		- bl ftl_memcpy
12070		- mov r1, r5
12071		- ldr r0, .L2148+12
12072		- add r5, r5, #1
12073		- ldr r2, [r8, #-1468]
12074		- add r7, r7, r6
12075		- bl FtlMapWritePage
12076		- add r10, r10, #4
12077		- ldr r3, [sp]
12078		- cmn r0, #1
12079		- ldr ip, [sp, #8]
12080		- mvneq r3, #0
12081		- add fp, fp, ip
12082		- str r3, [sp]
12083		- b .L2139
12084		-.L2147:
12085		- ldr r0, [sp]
12086		-.L2138:
	12386	+ lsr r7, r0, r7
	12387	+ lsl fp, r7, #2
	12388	+.L2105:
	12389	+ cmp r6, #0
	12390	+ bne .L2110
	12391	+.L2103:
	12392	+ mov r0, r8
12087	12393	add sp, sp, #60
12088	12394	@ sp needed
12089		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
12090		-.L2149:
	12395	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	12396	+.L2110:
	12397	+ ldr r3, [r4, #-1380]
	12398	+ mov r0, r9
	12399	+ ldr r2, [r3, fp]
	12400	+ ldr r3, [sp, #4]
	12401	+ str r2, [sp, #12]
	12402	+ ldrh r3, [r3, #-12]
	12403	+ mov r1, r3
	12404	+ str r3, [sp, #8]
	12405	+ bl __aeabi_uidivmod
	12406	+ ldr r3, [sp, #8]
	12407	+ ldr r2, [sp, #12]
	12408	+ str r1, [sp]
	12409	+ sub r5, r3, r1
	12410	+ uxth r5, r5
	12411	+ cmp r6, r5
	12412	+ uxthcc r5, r6
	12413	+ cmp r2, #0
	12414	+ cmpne r5, r3
	12415	+ movne r1, #1
	12416	+ moveq r1, #0
	12417	+ beq .L2107
	12418	+ ldr r3, [r4, #-1464]
	12419	+ add r0, sp, #20
	12420	+ str r2, [sp, #24]
	12421	+ mov r2, #1
	12422	+ mov r1, r2
	12423	+ str r3, [sp, #28]
	12424	+ mov r3, #0
	12425	+ str r3, [sp, #32]
	12426	+ bl FlashReadPages
	12427	+.L2108:
	12428	+ lsl r3, r5, #9
	12429	+ ldr r0, [r4, #-1464]
	12430	+ mov r1, r10
	12431	+ mov r2, r3
	12432	+ str r3, [sp, #8]
	12433	+ ldr r3, [sp]
	12434	+ sub r6, r6, r5
	12435	+ add r9, r9, r5
	12436	+ add fp, fp, #4
	12437	+ add r0, r0, r3, lsl #9
	12438	+ bl ftl_memcpy
	12439	+ mov r1, r7
	12440	+ ldr r2, [r4, #-1464]
	12441	+ ldr r0, .L2113+4
	12442	+ add r7, r7, #1
	12443	+ bl FtlMapWritePage
	12444	+ ldr r3, [sp, #8]
	12445	+ cmn r0, #1
	12446	+ mvneq r8, #0
	12447	+ add r10, r10, r3
	12448	+ b .L2105
	12449	+.L2107:
	12450	+ ldr r3, [sp, #4]
	12451	+ ldr r0, [r4, #-1464]
	12452	+ ldrh r2, [r3, #-8]
	12453	+ bl ftl_memset
	12454	+ b .L2108
	12455	+.L2114:
12091	12456	.align 2
12092		-.L2148:
12093		- .word .LANCHOR2-1648
12094		- .word .LANCHOR2-1662
12095		- .word .LANCHOR2-1658
	12457	+.L2113:
	12458	+ .word .LANCHOR2-1664
12096	12459	.word .LANCHOR2+1076
12097	12460	.fnend
12098	12461	.size FtlVendorPartWrite, .-FtlVendorPartWrite
12099	12462	.align 2
12100	12463	.global FtlVendorPartRead
	12464	+ .syntax unified
	12465	+ .arm
	12466	+ .fpu softvfp
12101	12467	.type FtlVendorPartRead, %function
12102	12468	FtlVendorPartRead:
12103	12469	.fnstart
12104	12470	@ args = 0, pretend = 0, frame = 56
12105	12471	@ frame_needed = 0, uses_anonymous_args = 0
12106		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	12472	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
12107	12473	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
12108		- mov r9, r2
12109		- ldr r6, .L2162
	12474	+ mov r10, r2
	12475	+ ldr r5, .L2126
12110	12476	add r2, r0, r1
12111		- mov r8, r0
12112	12477	.pad #60
12113	12478	sub sp, sp, #60
12114		- mov r7, r1
12115		- ldrh r3, [r6, #-24]
12116		- ldrh r5, [r6, #-12]
	12479	+ ldrh r3, [r5, #-6]
12117	12480	cmp r2, r3
12118		- mvnhi r0, #0
12119		- bhi .L2151
12120		- add r6, r6, #1648
12121		- mov r5, r8, lsr r5
12122		- mov r10, r6
12123		- mov r3, r5, asl #2
12124		- str r3, [sp, #4]
12125		- mov r3, #0
12126		- str r3, [sp]
12127		-.L2152:
	12481	+ mvnhi r8, #0
	12482	+ bhi .L2115
	12483	+ add r5, r5, #1664
	12484	+ mov r9, r0
	12485	+ sub r3, r5, #1648
	12486	+ mov r7, r1
	12487	+ ldrh r6, [r3, #-10]
	12488	+ mov r8, #0
	12489	+ str r3, [sp, #8]
	12490	+ lsr r6, r0, r6
	12491	+ lsl fp, r6, #2
	12492	+.L2117:
12128	12493	cmp r7, #0
12129		- beq .L2161
12130		- ldr r2, [sp, #4]
	12494	+ bne .L2123
	12495	+.L2115:
12131	12496	mov r0, r8
12132		- ldr r3, [r6, #-1380]
12133		- ldr r3, [r3, r2]
	12497	+ add sp, sp, #60
	12498	+ @ sp needed
	12499	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	12500	+.L2123:
	12501	+ ldr r3, [r5, #-1380]
	12502	+ mov r0, r9
	12503	+ ldr r3, [r3, fp]
12134	12504	str r3, [sp, #12]
12135		- ldr r3, .L2162+4
12136		- ldrh r4, [r3]
	12505	+ ldr r3, [sp, #8]
	12506	+ ldrh r4, [r3, #-12]
12137	12507	mov r1, r4
12138	12508	bl __aeabi_uidivmod
12139		- rsb r4, r1, r4
	12509	+ sub r4, r4, r1
12140	12510	ldr r3, [sp, #12]
12141		- str r1, [sp, #8]
12142	12511	uxth r4, r4
12143		- cmp r4, r7
12144		- uxthhi r4, r7
	12512	+ str r1, [sp, #4]
	12513	+ cmp r7, r4
	12514	+ uxthcc r4, r7
12145	12515	cmp r3, #0
12146		- mov fp, r4, asl #9
12147		- beq .L2154
12148		- ldr r2, [r10, #-1468]
12149		- mov r1, #1
	12516	+ lsl r2, r4, #9
	12517	+ str r2, [sp, #12]
	12518	+ beq .L2119
	12519	+ ldr r2, [r5, #-1464]
12150	12520	add r0, sp, #20
12151	12521	str r3, [sp, #24]
12152	12522	str r3, [sp, #12]
	12523	+ mov r3, #0
12153	12524	str r2, [sp, #28]
12154		- mov r2, #0
12155		- str r2, [sp, #32]
12156		- mov r2, r1
	12525	+ mov r2, #1
	12526	+ mov r1, r2
	12527	+ str r3, [sp, #32]
12157	12528	bl FlashReadPages
12158	12529	ldr r2, [sp, #20]
12159		- ldr r3, [sp]
12160		- cmn r2, #1
12161		- ldr r2, [r10, #-1276]
12162		- mvneq r3, #0
12163		- cmp r2, #256
12164		- str r3, [sp]
12165	12530	ldr r3, [sp, #12]
12166		- bne .L2156
12167		- mov r1, r5
	12531	+ cmn r2, #1
	12532	+ ldr r2, [r5, #-1276]
	12533	+ mvneq r8, #0
	12534	+ cmp r2, #256
	12535	+ bne .L2121
12168	12536	mov r2, r3
12169		- ldr r0, .L2162+8
	12537	+ mov r1, r6
	12538	+ ldr r0, .L2126+4
12170	12539	bl printk
12171		- ldr r0, .L2162+12
12172		- mov r1, r5
12173		- ldr r2, [r6, #-1468]
	12540	+ ldr r2, [r5, #-1464]
	12541	+ mov r1, r6
	12542	+ ldr r0, .L2126+8
12174	12543	bl FtlMapWritePage
12175		-.L2156:
12176		- ldrh r3, [sp, #8]
12177		- mov r0, r9
12178		- ldr r1, [r10, #-1468]
12179		- mov r2, fp
12180		- add r1, r1, r3, asl #9
12181		- bl ftl_memcpy
12182		- b .L2157
12183		-.L2154:
12184		- mov r0, r9
12185		- mov r1, r3
12186		- mov r2, fp
12187		- bl ftl_memset
12188		-.L2157:
	12544	+.L2121:
	12545	+ ldr r1, [r5, #-1464]
	12546	+ lsl r2, r4, #9
12189	12547	ldr r3, [sp, #4]
12190		- add r5, r5, #1
12191		- rsb r7, r4, r7
12192		- add r8, r8, r4
12193		- add r3, r3, #4
12194		- add r9, r9, fp
12195		- str r3, [sp, #4]
12196		- b .L2152
12197		-.L2161:
12198		- ldr r0, [sp]
12199		-.L2151:
12200		- add sp, sp, #60
12201		- @ sp needed
12202		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
12203		-.L2163:
	12548	+ mov r0, r10
	12549	+ add r1, r1, r3, lsl #9
	12550	+ bl ftl_memcpy
	12551	+.L2122:
	12552	+ add r6, r6, #1
	12553	+ sub r7, r7, r4
	12554	+ add r9, r9, r4
	12555	+ add r10, r10, r4, lsl #9
	12556	+ add fp, fp, #4
	12557	+ b .L2117
	12558	+.L2119:
	12559	+ lsl r2, r4, #9
	12560	+ mov r1, r3
	12561	+ mov r0, r10
	12562	+ bl ftl_memset
	12563	+ b .L2122
	12564	+.L2127:
12204	12565	.align 2
12205		-.L2162:
12206		- .word .LANCHOR2-1648
12207		- .word .LANCHOR2-1662
	12566	+.L2126:
	12567	+ .word .LANCHOR2-1664
12208	12568	.word .LC46
12209	12569	.word .LANCHOR2+1076
12210	12570	.fnend
12211	12571	.size FtlVendorPartRead, .-FtlVendorPartRead
12212	12572	.align 2
12213	12573	.global FtlUpdateVaildLpn
	12574	+ .syntax unified
	12575	+ .arm
	12576	+ .fpu softvfp
12214	12577	.type FtlUpdateVaildLpn, %function
12215	12578	FtlUpdateVaildLpn:
12216	12579	.fnstart
12217	12580	@ args = 0, pretend = 0, frame = 0
12218	12581	@ frame_needed = 0, uses_anonymous_args = 0
12219		- ldr r3, .L2172
	12582	+ ldr r3, .L2137
12220	12583	add r1, r3, #1120
12221	12584	ldrh r2, [r1]
12222	12585	cmp r2, #4
12223	12586	cmpls r0, #0
12224		- addeq r2, r2, #1
12225		- streqh r2, [r1] @ movhi
12226		- bxeq lr
	12587	+ bne .L2129
	12588	+ add r2, r2, #1
	12589	+ strh r2, [r1] @ movhi
	12590	+ bx lr
	12591	+.L2129:
	12592	+ mov r2, #0
12227	12593	str lr, [sp, #-4]!
12228	12594	.save {lr}
12229		- mov r2, #0
12230	12595	strh r2, [r1] @ movhi
12231		- sub r1, r3, #1728
	12596	+ sub r1, r3, #1712
	12597	+ movw lr, #65535
12232	12598	str r2, [r3, #1124]
12233		- movw ip, #65535
12234		- ldrh r0, [r1]
12235		- ldr r2, [r3, #-1408]
12236		- add r0, r2, r0, asl #1
12237		-.L2166:
12238		- cmp r2, r0
12239		- beq .L2171
12240		- ldrh r1, [r2], #2
12241		- cmp r1, ip
12242		- ldrne lr, [r3, #1124]
12243		- addne r1, r1, lr
12244		- strne r1, [r3, #1124]
12245		- b .L2166
12246		-.L2171:
	12599	+ ldrh r1, [r1, #-12]
	12600	+ ldr r2, [r3, #-1404]
	12601	+ add r1, r2, r1, lsl #1
	12602	+.L2130:
	12603	+ cmp r2, r1
	12604	+ bne .L2132
12247	12605	ldr pc, [sp], #4
12248		-.L2173:
	12606	+.L2132:
	12607	+ ldrh ip, [r2], #2
	12608	+ cmp ip, lr
	12609	+ ldrne r0, [r3, #1124]
	12610	+ addne r0, r0, ip
	12611	+ strne r0, [r3, #1124]
	12612	+ b .L2130
	12613	+.L2138:
12249	12614	.align 2
12250		-.L2172:
	12615	+.L2137:
12251	12616	.word .LANCHOR2
12252	12617	.fnend
12253	12618	.size FtlUpdateVaildLpn, .-FtlUpdateVaildLpn
12254	12619	.align 2
12255	12620	.global FtlMapBlkWriteDumpData
	12621	+ .syntax unified
	12622	+ .arm
	12623	+ .fpu softvfp
12256	12624	.type FtlMapBlkWriteDumpData, %function
12257	12625	FtlMapBlkWriteDumpData:
12258	12626	.fnstart
12259	12627	@ args = 0, pretend = 0, frame = 0
12260	12628	@ frame_needed = 0, uses_anonymous_args = 0
12261		- stmfd sp!, {r4, r5, r6, lr}
	12629	+ ldr r3, [r0, #36]
	12630	+ cmp r3, #0
	12631	+ bxeq lr
	12632	+ push {r4, r5, r6, lr}
12262	12633	.save {r4, r5, r6, lr}
12263		- ldr r2, [r0, #36]
12264		- ldrh r5, [r0, #6]
12265		- cmp r2, #0
12266		- ldr r3, [r0, #24]
12267		- ldmeqfd sp!, {r4, r5, r6, pc}
12268		- ldr r4, .L2181
12269	12634	mov r2, #0
	12635	+ ldr r4, .L2149
12270	12636	str r2, [r0, #36]
12271	12637	ldr r2, [r4, #-1280]
	12638	+ ldrh r5, [r0, #6]
	12639	+ ldr r3, [r0, #24]
12272	12640	cmp r2, #0
12273		- ldmnefd sp!, {r4, r5, r6, pc}
12274		- sub r5, r5, #1
	12641	+ popne {r4, r5, r6, pc}
12275	12642	mov r6, r0
12276		- ldr r2, [r4, #-1444]
12277		- ldr r0, [r4, #-1472]
	12643	+ ldr r2, [r4, #-1440]
	12644	+ ldr r0, [r4, #-1468]
	12645	+ sub r5, r5, #1
12278	12646	uxth r5, r5
12279	12647	str r2, [r4, #-1264]
12280	12648	str r0, [r4, #-1268]
12281		- ldr r3, [r3, r5, asl #2]
	12649	+ ldr r3, [r3, r5, lsl #2]
12282	12650	cmp r3, #0
12283	12651	str r3, [r4, #-1272]
12284		- beq .L2178
12285		- mov r1, #1
12286		- ldr r0, .L2181+4
12287		- mov r2, r1
	12652	+ beq .L2143
	12653	+ mov r2, #1
	12654	+ ldr r0, .L2149+4
	12655	+ mov r1, r2
12288	12656	bl FlashReadPages
12289		- b .L2179
12290		-.L2178:
	12657	+.L2144:
	12658	+ ldr r2, [r4, #-1268]
	12659	+ mov r1, r5
	12660	+ mov r0, r6
	12661	+ pop {r4, r5, r6, lr}
	12662	+ b FtlMapWritePage
	12663	+.L2143:
12291	12664	sub r3, r4, #1648
12292	12665	mov r1, #255
12293		- ldrh r2, [r3, #-10]
	12666	+ ldrh r2, [r3, #-8]
12294	12667	bl ftl_memset
12295		-.L2179:
12296		- mov r0, r6
12297		- mov r1, r5
12298		- ldr r2, [r4, #-1268]
12299		- ldmfd sp!, {r4, r5, r6, lr}
12300		- b FtlMapWritePage
12301		-.L2182:
	12668	+ b .L2144
	12669	+.L2150:
12302	12670	.align 2
12303		-.L2181:
	12671	+.L2149:
12304	12672	.word .LANCHOR2
12305	12673	.word .LANCHOR2-1276
12306	12674	.fnend
12307	12675	.size FtlMapBlkWriteDumpData, .-FtlMapBlkWriteDumpData
12308	12676	.align 2
12309	12677	.global FtlVpcTblFlush
	12678	+ .syntax unified
	12679	+ .arm
	12680	+ .fpu softvfp
12310	12681	.type FtlVpcTblFlush, %function
12311	12682	FtlVpcTblFlush:
12312	12683	.fnstart
12313		- @ args = 0, pretend = 0, frame = 0
	12684	+ @ args = 0, pretend = 0, frame = 8
12314	12685	@ frame_needed = 0, uses_anonymous_args = 0
12315		- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
12316		- .save {r3, r4, r5, r6, r7, r8, r9, r10, fp, lr}
12317		- ldr r4, .L2201
	12686	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	12687	+ .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	12688	+ .pad #12
	12689	+ ldr r4, .L2169
12318	12690	ldr r3, [r4, #-1280]
12319	12691	cmp r3, #0
12320		- bne .L2185
12321		- ldr r2, [r4, #-1476]
12322		- add r5, r4, #816
12323		- ldr r6, [r4, #-1444]
	12692	+ bne .L2153
	12693	+ ldr r2, [r4, #-1472]
	12694	+ add r7, r4, #816
	12695	+ ldr r6, [r4, #-1440]
	12696	+ sub r9, r4, #1648
	12697	+ ldr r5, .L2169+4
12324	12698	mov r1, #255
12325		- ldr r7, .L2201+4
12326	12699	str r2, [r4, #-1268]
12327	12700	movw r2, #1128
12328	12701	ldrh r2, [r4, r2]
12329	12702	str r6, [r4, #-1264]
12330	12703	str r3, [r6, #12]
12331	12704	strh r2, [r6, #2] @ movhi
12332		- ldr r2, .L2201+8
	12705	+ ldr r2, .L2169+8
	12706	+ ldr r8, .L2169+12
12333	12707	strh r2, [r6] @ movhi
12334	12708	ldr r2, [r4, #1136]
12335	12709	stmib r6, {r2, r3}
12336		- ldr r3, .L2201+12
	12710	+ ldr r3, .L2169+16
12337	12711	str r3, [r4, #816]
12338		- ldr r3, .L2201+16
	12712	+ ldr r3, .L2169+20
12339	12713	str r3, [r4, #820]
12340		- ldrh r3, [r7, #6]
12341		- strh r3, [r5, #8] @ movhi
12342		- sub r3, r4, #1712
12343		- ldrh r3, [r3, #-2]
	12714	+ ldrh r3, [r5, #6]
	12715	+ strh r3, [r7, #8] @ movhi
	12716	+ sub r3, r4, #1696
	12717	+ ldrh r3, [r3, #-14]
12344	12718	strb r3, [r4, #826]
12345	12719	add r3, r4, #884
12346	12720	ldrh r2, [r3]
12347		- strh r2, [r5, #14] @ movhi
	12721	+ strh r2, [r7, #14] @ movhi
12348	12722	ldrh r2, [r3, #2]
12349	12723	ldrb r3, [r4, #890] @ zero_extendqisi2
12350		- orr r3, r3, r2, asl #6
12351		- strh r3, [r5, #16] @ movhi
	12724	+ orr r3, r3, r2, lsl #6
	12725	+ strh r3, [r7, #16] @ movhi
12352	12726	ldrb r3, [r4, #892] @ zero_extendqisi2
12353	12727	strb r3, [r4, #827]
12354	12728	add r3, r4, #932
12355	12729	ldrh r2, [r3]
12356		- strh r2, [r5, #18] @ movhi
	12730	+ strh r2, [r7, #18] @ movhi
12357	12731	ldrh r2, [r3, #2]
12358	12732	ldrb r3, [r4, #938] @ zero_extendqisi2
12359		- orr r3, r3, r2, asl #6
12360		- strh r3, [r5, #20] @ movhi
	12733	+ orr r3, r3, r2, lsl #6
	12734	+ strh r3, [r7, #20] @ movhi
12361	12735	ldrb r3, [r4, #940] @ zero_extendqisi2
12362	12736	strb r3, [r4, #828]
12363	12737	add r3, r4, #980
12364	12738	ldrh r2, [r3]
12365		- strh r2, [r5, #22] @ movhi
	12739	+ strh r2, [r7, #22] @ movhi
12366	12740	ldrh r2, [r3, #2]
12367	12741	ldrb r3, [r4, #986] @ zero_extendqisi2
12368	12742	ldr r0, [r4, #-1268]
12369		- orr r3, r3, r2, asl #6
12370		- strh r3, [r5, #24] @ movhi
	12743	+ orr r3, r3, r2, lsl #6
	12744	+ ldrh r2, [r9, #-8]
	12745	+ strh r3, [r7, #24] @ movhi
12371	12746	ldrb r3, [r4, #988] @ zero_extendqisi2
12372	12747	strb r3, [r4, #829]
12373		- ldr r3, [r4, #-1584]
	12748	+ ldr r3, [r4, #-1580]
12374	12749	str r3, [r4, #848]
12375		- ldr r3, [r4, #-1616]
12376		- str r3, [r4, #856]
12377	12750	ldr r3, [r4, #-1612]
	12751	+ str r3, [r4, #856]
	12752	+ ldr r3, [r4, #-1608]
12378	12753	str r3, [r4, #852]
12379	12754	sub r3, r4, #1536
12380		- ldrh r2, [r3, #-4]
12381		- ldrh r3, [r3, #-2]
12382		- strh r2, [r5, #44] @ movhi
12383		- strh r3, [r5, #46] @ movhi
12384		- sub r3, r4, #1648
12385		- ldrh r2, [r3, #-10]
	12755	+ ldrh r3, [r3]
	12756	+ strh r3, [r7, #44] @ movhi
	12757	+ sub r3, r4, #1520
	12758	+ ldrh r3, [r3, #-14]
	12759	+ strh r3, [r7, #46] @ movhi
12386	12760	bl ftl_memset
12387		- mov r1, r5
12388		- sub r5, r4, #1728
	12761	+ mov r1, r7
12389	12762	mov r2, #48
	12763	+ sub r7, r4, #1712
12390	12764	ldr r0, [r4, #-1268]
12391	12765	bl ftl_memcpy
12392		- ldrh r2, [r5]
	12766	+ ldrh r2, [r7, #-12]
12393	12767	ldr r0, [r4, #-1268]
12394		- ldr r1, [r4, #-1408]
12395		- mov r2, r2, asl #1
	12768	+ ldr r1, [r4, #-1404]
	12769	+ lsl r2, r2, #1
12396	12770	add r0, r0, #48
12397	12771	bl ftl_memcpy
12398		- ldrh r2, [r5]
12399		- ldr r0, [r4, #-1268]
12400		- ldr r1, [r4, #-1396]
12401		- mov r3, r2, asl #1
12402		- mov r2, r2, lsr #3
12403		- add r3, r3, #51
	12772	+ ldrh r0, [r7, #-12]
	12773	+ ldr r3, [r4, #-1268]
	12774	+ ldr r1, [r8, #32]
	12775	+ lsr r2, r0, #3
	12776	+ lsl r0, r0, #1
	12777	+ add r0, r0, #51
12404	12778	add r2, r2, #4
12405		- bic r3, r3, #3
12406		- add r0, r0, r3
	12779	+ bic r0, r0, #3
	12780	+ add r0, r3, r0
12407	12781	bl ftl_memcpy
12408	12782	sub r3, r4, #1616
12409		- ldrh r3, [r3, #-12]
12410		- cmp r3, #0
12411		- beq .L2186
12412		- ldrh r2, [r5]
12413		- ldr r0, [r4, #-1268]
	12783	+ str r9, [sp, #4]
	12784	+ ldrh r2, [r3, #-8]
	12785	+ cmp r2, #0
	12786	+ beq .L2154
	12787	+ ldrh r0, [r7, #-12]
	12788	+ ldrh r2, [r3, #-12]
12414	12789	ldr r1, [r4, #-1376]
12415		- mov r3, r2, lsr #3
12416		- add r3, r3, r2, asl #1
12417		- sub r2, r4, #1632
	12790	+ lsr r3, r0, #3
	12791	+ lsl r2, r2, #2
	12792	+ add r3, r3, r0, lsl #1
	12793	+ ldr r0, [r4, #-1268]
12418	12794	add r3, r3, #52
12419		- ldrh r2, [r2]
12420	12795	ubfx r3, r3, #2, #14
12421		- add r0, r0, r3, asl #2
12422		- mov r2, r2, asl #2
	12796	+ add r0, r0, r3, lsl #2
12423	12797	bl ftl_memcpy
12424		-.L2186:
	12798	+.L2154:
	12799	+ ldr r10, .L2169+24
	12800	+ mov r7, #0
	12801	+ movw r9, #65535
12425	12802	mov r0, #0
12426		- ldr r9, .L2201
12427	12803	bl FtlUpdateVaildLpn
12428		- ldr fp, .L2201+4
12429		- mov r8, #0
12430		- movw r10, #65535
12431		-.L2187:
12432		- ldr r3, [r4, #-1476]
12433		- ldrh r2, [r7]
12434		- ldrh r1, [r7, #2]
	12804	+ mov fp, r10
	12805	+.L2155:
	12806	+ ldr r3, [r4, #-1472]
	12807	+ ldrh r1, [r5, #2]
	12808	+ ldrh r2, [r5]
12435	12809	str r3, [r4, #-1268]
12436		- ldr r3, [r4, #-1444]
	12810	+ ldr r3, [r4, #-1440]
12437	12811	str r3, [r4, #-1264]
12438		- orr r3, r1, r2, asl #10
	12812	+ orr r3, r1, r2, lsl #10
12439	12813	str r3, [r4, #-1272]
12440		- ldr r3, .L2201+20
12441		- ldrh r3, [r3]
	12814	+ ldrh r3, [r10]
12442	12815	sub r3, r3, #1
12443	12816	cmp r1, r3
12444		- blt .L2188
	12817	+ blt .L2156
12445	12818	mov r3, #0
12446		- ldrh r10, [fp, #4]
12447		- strh r3, [fp, #2] @ movhi
12448		- strh r2, [fp, #4] @ movhi
	12819	+ ldrh r9, [r5, #4]
	12820	+ strh r3, [r5, #2] @ movhi
	12821	+ strh r2, [r5, #4] @ movhi
12449	12822	bl FtlFreeSysBlkQueueOut
12450		- ldr r3, [r9, #-1616]
	12823	+ ldr r3, [r4, #-1612]
	12824	+ strh r0, [r5] @ movhi
12451	12825	add r2, r3, #1
12452		- str r2, [r9, #-1616]
12453		- str r3, [r9, #1136]
12454		- mov r2, r0, asl #10
12455		- strh r0, [fp] @ movhi
12456		- str r2, [r9, #-1272]
	12826	+ str r3, [r4, #1136]
	12827	+ str r2, [r4, #-1612]
	12828	+ lsl r2, r0, #10
	12829	+ str r2, [r4, #-1272]
12457	12830	str r3, [r6, #4]
12458	12831	strh r0, [r6, #2] @ movhi
12459		-.L2188:
12460		- ldr r3, .L2201+24
12461		- ldrb r3, [r3] @ zero_extendqisi2
	12832	+.L2156:
	12833	+ ldrb r3, [r8, #36] @ zero_extendqisi2
12462	12834	cmp r3, #0
12463		- beq .L2189
12464		- ldr r3, .L2201+28
12465		- ldr r0, [r4, #-1476]
12466		- ldrh r1, [r3]
	12835	+ beq .L2157
	12836	+ ldr r3, [sp, #4]
	12837	+ ldr r0, [r4, #-1472]
	12838	+ ldrh r1, [r3, #-8]
12467	12839	bl js_hash
12468	12840	str r0, [r6, #12]
12469		-.L2189:
12470		- mov r1, #1
12471		- ldr r0, .L2201+32
12472		- mov r3, r1
12473		- mov r2, r1
	12841	+.L2157:
	12842	+ mov r3, #1
	12843	+ ldr r0, .L2169+28
	12844	+ mov r2, r3
	12845	+ mov r1, r3
12474	12846	bl FlashProgPages
12475		- ldrh r5, [r7, #2]
12476		- ldr r3, [r4, #-1276]
12477		- add r5, r5, #1
12478		- cmn r3, #1
12479		- uxth r5, r5
12480		- strh r5, [r7, #2] @ movhi
12481		- bne .L2190
12482		- cmp r5, #1
12483		- add r8, r8, #1
12484		- ldreq r3, .L2201+20
12485		- uxth r8, r8
12486		- ldreqh r3, [r3]
	12847	+ ldrh r3, [r5, #2]
	12848	+ ldr r2, [r4, #-1276]
	12849	+ add r3, r3, #1
	12850	+ uxth r3, r3
	12851	+ cmn r2, #1
	12852	+ strh r3, [r5, #2] @ movhi
	12853	+ bne .L2158
	12854	+ cmp r3, #1
	12855	+ add r7, r7, #1
	12856	+ ldrheq r3, [fp]
	12857	+ uxth r7, r7
12487	12858	subeq r3, r3, #1
12488		- streqh r3, [fp, #2] @ movhi
12489		- cmp r8, #3
12490		- bls .L2187
12491		- ldr r0, .L2201+36
12492		- mov r2, r8
	12859	+ strheq r3, [r5, #2] @ movhi
	12860	+ cmp r7, #3
	12861	+ bls .L2155
	12862	+ mov r2, r7
12493	12863	ldr r1, [r4, #-1272]
	12864	+ ldr r0, .L2169+32
12494	12865	bl printk
12495	12866	mov r3, #1
12496	12867	str r3, [r4, #-1280]
12497		- b .L2185
12498		-.L2190:
12499		- cmp r3, #256
12500		- cmpne r5, #1
12501		- beq .L2187
12502		- movw r3, #65535
12503		- cmp r10, r3
12504		- beq .L2185
12505		- mov r0, r10
12506		- mov r1, #1
12507		- bl FtlFreeSysBlkQueueIn
12508		-.L2185:
	12868	+.L2153:
12509	12869	mov r0, #0
12510		- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, r10, fp, pc}
12511		-.L2202:
	12870	+ add sp, sp, #12
	12871	+ @ sp needed
	12872	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	12873	+.L2158:
	12874	+ cmp r3, #1
	12875	+ cmpne r2, #256
	12876	+ beq .L2155
	12877	+ movw r3, #65535
	12878	+ cmp r9, r3
	12879	+ beq .L2153
	12880	+ mov r1, #1
	12881	+ mov r0, r9
	12882	+ bl FtlFreeSysBlkQueueIn
	12883	+ b .L2153
	12884	+.L2170:
12512	12885	.align 2
12513		-.L2201:
	12886	+.L2169:
12514	12887	.word .LANCHOR2
12515	12888	.word .LANCHOR2+1128
12516	12889	.word -3932
	12890	+ .word .LANCHOR0
12517	12891	.word 1179929683
12518	12892	.word 1342177379
12519		- .word .LANCHOR2-1666
12520		- .word .LANCHOR0
12521		- .word .LANCHOR2-1658
	12893	+ .word .LANCHOR2-1664
12522	12894	.word .LANCHOR2-1276
12523	12895	.word .LC47
12524	12896	.fnend
12525	12897	.size FtlVpcTblFlush, .-FtlVpcTblFlush
12526	12898	.align 2
12527	12899	.global FtlScanSysBlk
	12900	+ .syntax unified
	12901	+ .arm
	12902	+ .fpu softvfp
12528	12903	.type FtlScanSysBlk, %function
12529	12904	FtlScanSysBlk:
12530	12905	.fnstart
12531		- @ args = 0, pretend = 0, frame = 32
	12906	+ @ args = 0, pretend = 0, frame = 24
12532	12907	@ frame_needed = 0, uses_anonymous_args = 0
12533		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	12908	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
12534	12909	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	12910	+ mov r5, #0
	12911	+ ldr r4, .L2250
12535	12912	movw r3, #1144
12536		- ldr r9, .L2289
12537		- mov r10, #0
12538		- mov r1, r10
12539		- .pad #36
12540		- sub sp, sp, #36
12541		- sub r5, r9, #1648
12542		- ldr r2, [r9, #-1640]
12543		- mov r4, r9
12544		- strh r10, [r9, r3] @ movhi
12545		- sub r3, r9, #1280
12546		- ldr r0, [r9, #-1368]
12547		- mov r6, r9
12548		- mov r2, r2, asl #2
12549		- strh r10, [r3, #-8] @ movhi
	12913	+ mov r1, r5
	12914	+ .pad #28
	12915	+ sub sp, sp, #28
	12916	+ ldr r2, [r4, #-1636]
	12917	+ sub r7, r4, #1280
	12918	+ ldr r0, [r4, #-1368]
	12919	+ sub r6, r4, #1632
	12920	+ strh r5, [r4, r3] @ movhi
	12921	+ strh r5, [r7, #-8] @ movhi
	12922	+ lsl r2, r2, #2
12550	12923	bl ftl_memset
12551		- ldr r2, [r9, #-1640]
12552		- mov r1, r10
12553		- ldr r0, [r9, #-1404]
12554		- mov r2, r2, asl #1
	12924	+ ldr r2, [r4, #-1636]
	12925	+ mov r1, r5
	12926	+ ldr r0, [r4, #-1400]
	12927	+ lsl r2, r2, #1
12555	12928	bl ftl_memset
12556		- ldrh r2, [r5]
12557		- mov r1, r10
12558		- ldr r0, [r9, #-1384]
12559		- mov r2, r2, asl #2
	12929	+ ldrh r2, [r6, #-12]
	12930	+ mov r1, r5
	12931	+ ldr r0, [r4, #-1384]
	12932	+ lsl r2, r2, #2
12560	12933	bl ftl_memset
12561		- ldrh r2, [r5]
12562		- mov r1, r10
12563		- ldr r0, [r9, #-1392]
12564		- mov r2, r2, asl #1
	12934	+ ldrh r2, [r6, #-12]
	12935	+ mov r1, r5
	12936	+ ldr r0, [r4, #-1392]
	12937	+ lsl r2, r2, #1
12565	12938	bl ftl_memset
12566		- ldr r0, .L2289+4
12567		- mov r1, #255
12568	12939	mov r2, #16
	12940	+ mov r1, #255
	12941	+ ldr r0, .L2250+4
12569	12942	bl ftl_memset
12570		- sub r3, r9, #1728
12571		- ldrh r3, [r3]
12572		- str r5, [sp, #16]
12573		- mov r5, r9
12574		- str r3, [sp, #8]
12575		-.L2204:
12576		- ldr r3, .L2289+8
12577		- ldr r2, [sp, #8]
12578		- ldr r1, .L2289
12579		- ldrh r3, [r3]
12580		- cmp r3, r2
12581		- bls .L2245
12582		- ldr r3, .L2289+12
	12943	+ sub r3, r4, #1712
	12944	+ str r7, [sp, #8]
	12945	+ ldrh r3, [r3, #-12]
	12946	+ str r6, [sp, #12]
	12947	+ str r3, [sp]
	12948	+ sub r3, r4, #1696
	12949	+ sub r3, r3, #10
	12950	+ str r3, [sp, #16]
	12951	+.L2172:
	12952	+ ldr r2, .L2250+8
	12953	+ ldr r1, [sp]
	12954	+ ldrh r3, [r2]
	12955	+ cmp r3, r1
	12956	+ bls .L2212
	12957	+ mov r5, #0
	12958	+ ldrh r3, [r2, #-10]
	12959	+ ldr r6, [r4, #-1500]
	12960	+ mov r7, r5
	12961	+ ldr fp, [r4, #-1460]
12583	12962	mov r8, #36
12584		- ldr r1, .L2289+16
12585		- mov r7, #0
12586		- ldr r2, [r5, #-1504]
12587		- ldrh ip, [r3]
12588		- sub r9, r1, #52
12589		- ldr r3, [r5, #-1464]
12590		- ldr fp, [r5, #-1436]
12591		- ldrh r10, [r1]
12592		- str r7, [sp, #4]
12593		-.L2246:
12594		- uxth r1, r7
12595		- cmp r1, ip
12596		- bcs .L2284
12597		- ldr r1, [sp, #8]
12598		- ldrb r0, [r9, r7] @ zero_extendqisi2
12599		- str r3, [sp, #28]
12600		- str r2, [sp, #24]
12601		- str ip, [sp, #20]
	12963	+ ldr r10, [r4, #-1432]
	12964	+ ldrh r9, [r2, #68]
	12965	+ b .L2213
	12966	+.L2174:
	12967	+ str r3, [sp, #20]
	12968	+ ldr r3, [sp, #16]
	12969	+ ldr r1, [sp]
	12970	+ ldrb r0, [r3, r5] @ zero_extendqisi2
12602	12971	bl V2P_block
12603		- str r0, [sp, #12]
	12972	+ str r0, [sp, #4]
12604	12973	bl FtlBbmIsBadBlock
12605	12974	cmp r0, #0
12606		- ldr r1, [sp, #12]
12607		- ldr ip, [sp, #20]
12608		- ldr r2, [sp, #24]
12609		- ldr r3, [sp, #28]
12610		- bne .L2205
12611		- ldr r0, [sp, #4]
12612		- mov r1, r1, asl #10
12613		- mla r0, r8, r0, r2
12614		- stmib r0, {r1, r3}
12615		- ldr r1, [sp, #4]
12616		- mul r1, r10, r1
12617		- add lr, r1, #3
12618		- cmp r1, #0
12619		- movlt r1, lr
12620		- bic r1, r1, #3
12621		- add r1, fp, r1
12622		- str r1, [r0, #12]
12623		- ldr r1, [sp, #4]
12624		- add r1, r1, #1
12625		- uxth r1, r1
12626		- str r1, [sp, #4]
12627		-.L2205:
12628		- add r7, r7, #1
12629		- b .L2246
12630		-.L2284:
12631		- ldr r3, [sp, #4]
12632		- cmp r3, #0
12633		- beq .L2208
12634		- mov r1, r3
12635		- ldr r0, [r4, #-1504]
12636		- mov r2, #1
12637		- bl FlashReadPages
12638		- mov r3, #0
12639		-.L2282:
12640		- str r3, [sp, #12]
	12975	+ ldr r3, [sp, #20]
	12976	+ bne .L2173
12641	12977	ldr r2, [sp, #4]
12642		- ldrh r3, [sp, #12]
	12978	+ mla r1, r8, r7, r6
	12979	+ lsl r2, r2, #10
	12980	+ stmib r1, {r2, fp}
	12981	+ mul r2, r9, r7
	12982	+ add r7, r7, #1
	12983	+ uxth r7, r7
	12984	+ add r0, r2, #3
	12985	+ cmp r2, #0
	12986	+ movlt r2, r0
	12987	+ bic r2, r2, #3
	12988	+ add r2, r10, r2
	12989	+ str r2, [r1, #12]
	12990	+.L2173:
	12991	+ add r5, r5, #1
	12992	+.L2213:
	12993	+ uxth r2, r5
12643	12994	cmp r3, r2
12644		- bcs .L2208
12645		- ldr r3, [sp, #12]
12646		- mov r9, #36
12647		- mul r9, r9, r3
12648		- ldr r3, [r4, #-1504]
12649		- add r2, r3, r9
12650		- ldr r3, [r3, r9]
12651		- ldr r7, [r2, #4]
12652		- cmn r3, #1
12653		- ldr r8, [r2, #12]
12654		- ubfx r7, r7, #10, #16
12655		- bne .L2211
12656		- mov r10, #16
12657		- movw fp, #65535
12658		-.L2210:
12659		- ldr r0, [r4, #-1504]
12660		- mov r1, #1
12661		- mov r2, r1
12662		- add r0, r0, r9
12663		- ldr r3, [r0, #4]
12664		- add r3, r3, #1
12665		- str r3, [r0, #4]
12666		- bl FlashReadPages
12667		- ldrh r3, [r8]
12668		- cmp r3, fp
12669		- ldreq r3, [r6, #-1504]
12670		- mvneq r2, #0
12671		- streq r2, [r3, r9]
12672		- beq .L2211
12673		-.L2212:
12674		- ldr r3, [r5, #-1504]
12675		- ldr r3, [r3, r9]
12676		- cmn r3, #1
12677		- bne .L2211
12678		- sub r10, r10, #1
12679		- uxth r10, r10
12680		- cmp r10, #0
12681		- bne .L2210
	12995	+ bhi .L2174
	12996	+ cmp r7, #0
	12997	+ bne .L2175
12682	12998	.L2211:
12683		- ldr r3, [r5, #-1504]
12684		- ldr r3, [r3, r9]
	12999	+ ldr r3, [sp]
	13000	+ add r3, r3, #1
	13001	+ uxth r3, r3
	13002	+ str r3, [sp]
	13003	+ b .L2172
	13004	+.L2175:
	13005	+ ldr r8, .L2250+4
	13006	+ mov r2, #1
	13007	+ mov r1, r7
	13008	+ mov r0, r6
	13009	+ bl FlashReadPages
	13010	+ add r9, r8, #16
	13011	+ mov r3, #0
	13012	+ str r3, [sp, #4]
	13013	+.L2176:
	13014	+ ldrh r3, [sp, #4]
	13015	+ cmp r7, r3
	13016	+ bls .L2211
	13017	+ ldr r3, [sp, #4]
	13018	+ mov r10, #36
	13019	+ mul r10, r10, r3
	13020	+ ldr r3, [r4, #-1500]
	13021	+ add r2, r3, r10
	13022	+ ldr r3, [r3, r10]
	13023	+ ldr r5, [r2, #4]
	13024	+ ldr r6, [r2, #12]
12685	13025	cmn r3, #1
12686		- beq .L2214
12687		- ldr r2, [r5, #-1616]
12688		- ldr r3, [r8, #4]
12689		- cmn r2, #1
12690		- beq .L2215
	13026	+ ubfx r5, r5, #10, #16
	13027	+ bne .L2179
	13028	+ mov fp, #16
	13029	+ movw r3, #65535
	13030	+.L2181:
	13031	+ ldr r0, [r4, #-1500]
	13032	+ str r3, [sp, #20]
	13033	+ add r0, r0, r10
	13034	+ ldr r2, [r0, #4]
	13035	+ add r2, r2, #1
	13036	+ str r2, [r0, #4]
	13037	+ mov r2, #1
	13038	+ mov r1, r2
	13039	+ bl FlashReadPages
	13040	+ ldrh r2, [r6]
	13041	+ ldr r3, [sp, #20]
12691	13042	cmp r2, r3
12692		- bhi .L2216
12693		-.L2215:
	13043	+ bne .L2178
	13044	+ ldr r3, [r4, #-1500]
	13045	+ mvn r2, #0
	13046	+ str r2, [r3, r10]
	13047	+ ldr r3, [r4, #-1500]
	13048	+ ldr r3, [r3, r10]
	13049	+ cmp r3, r2
	13050	+ beq .L2180
	13051	+.L2179:
	13052	+ ldr r2, [r4, #-1612]
	13053	+ ldr r3, [r6, #4]
	13054	+ cmn r2, #1
	13055	+ beq .L2182
	13056	+ cmp r2, r3
	13057	+ bhi .L2183
	13058	+.L2182:
12694	13059	cmn r3, #1
12695	13060	addne r2, r3, #1
12696		- strne r2, [r6, #-1616]
12697		-.L2216:
12698		- ldrh r2, [r8]
	13061	+ strne r2, [r4, #-1612]
	13062	+.L2183:
	13063	+ ldrh r2, [r6]
12699	13064	movw r1, #61604
12700	13065	cmp r2, r1
12701		- beq .L2218
12702		- bhi .L2219
	13066	+ beq .L2185
	13067	+ bhi .L2186
12703	13068	movw r3, #61574
12704	13069	cmp r2, r3
12705		- bne .L2217
12706		- ldr r3, [sp, #16]
12707		- ldr r2, .L2289+20
12708		- ldr lr, [r4, #-1384]
12709		- ldrh ip, [r3]
12710		- ldrh r1, [r2]
12711		- sub r0, ip, #1
12712		- uxth r3, r0
12713		- rsb r0, r1, r0
12714		- b .L2232
12715		-.L2219:
	13070	+ beq .L2187
	13071	+.L2184:
	13072	+ ldr r3, [sp, #4]
	13073	+ add r3, r3, #1
	13074	+ str r3, [sp, #4]
	13075	+ b .L2176
	13076	+.L2178:
	13077	+ ldr r2, [r4, #-1500]
	13078	+ ldr r2, [r2, r10]
	13079	+ cmn r2, #1
	13080	+ bne .L2179
	13081	+ sub fp, fp, #1
	13082	+ uxth fp, fp
	13083	+ cmp fp, #0
	13084	+ bne .L2181
	13085	+.L2180:
	13086	+ ldrb r1, [r4, #-2740] @ zero_extendqisi2
	13087	+ cmp r1, #0
	13088	+ bne .L2249
	13089	+.L2209:
	13090	+ mov r0, r5
	13091	+ bl FtlFreeSysBlkQueueIn
	13092	+ b .L2184
	13093	+.L2186:
12716	13094	movw r3, #61634
12717	13095	cmp r2, r3
12718		- beq .L2221
	13096	+ beq .L2188
12719	13097	movw r3, #65535
12720	13098	cmp r2, r3
12721		- moveq r0, r7
12722		- beq .L2283
12723		- b .L2217
12724		-.L2221:
12725		- ldr ip, [r4, #-1640]
12726		- ldr fp, .L2289+24
12727		- ldr lr, [r4, #-1368]
12728		- uxth r1, ip
12729		- ldrh r2, [fp]
12730		- sub r3, r1, #1
12731		- rsb r1, r2, r1
12732		- uxth r3, r3
12733		- sub r1, r1, #1
12734		- sxth r1, r1
12735		- str r1, [sp, #20]
12736		-.L2223:
12737		- ldr r1, [sp, #20]
12738		- sxth r0, r3
12739		- cmp r0, r1
12740		- ble .L2285
12741		- ldr r9, [lr, r0, asl #2]
12742		- mov r10, r0, asl #2
12743		- ldr r1, [r8, #4]
12744		- cmp r1, r9
12745		- bls .L2224
12746		- ldr r1, [lr]
12747		- cmp r1, #0
12748		- bne .L2225
12749		- cmp r2, ip
12750		- addne r2, r2, #1
12751		- ldrne r1, .L2289+24
12752		- strneh r2, [r1] @ movhi
12753		-.L2225:
12754		- uxth lr, r3
	13099	+ bne .L2184
	13100	+.L2249:
12755	13101	mov r1, #0
12756		-.L2226:
12757		- uxth r2, r1
12758		- cmp r2, lr
12759		- bcs .L2286
12760		- ldr ip, [r5, #-1368]
12761		- sxth r2, r2
12762		- add r1, r1, #1
12763		- add r9, ip, r2, asl #2
12764		- ldr r9, [r9, #4]
12765		- str r9, [ip, r2, asl #2]
12766		- mov r2, r2, asl #1
12767		- ldr ip, [r5, #-1404]
12768		- add r9, ip, r2
12769		- ldrh r9, [r9, #2]
12770		- strh r9, [ip, r2] @ movhi
12771		- b .L2226
12772		-.L2286:
12773		- ldr r2, [r6, #-1368]
12774		- mov r0, r0, asl #1
12775		- ldr r1, [r8, #4]
12776		- str r1, [r2, r10]
12777		- ldr r2, [r6, #-1404]
12778		- strh r7, [r2, r0] @ movhi
12779		- sxth r0, r3
12780		- cmp r0, #0
12781		- bge .L2228
12782		- b .L2217
12783		-.L2224:
12784		- sub r3, r3, #1
12785		- uxth r3, r3
12786		- b .L2223
12787		-.L2285:
12788		- cmp r0, #0
12789		- bge .L2259
12790		- b .L2217
12791		-.L2228:
12792		- ldr r2, .L2289+24
12793		- ldr r1, [r5, #-1640]
12794		- ldrh r2, [r2]
12795		- rsb r1, r2, r1
	13102	+ b .L2209
	13103	+.L2188:
	13104	+ ldr r0, [r4, #-1636]
	13105	+ ldrh r2, [r9]
	13106	+ ldr ip, [r4, #-1368]
	13107	+ uxth r1, r0
	13108	+ sub r3, r1, #1
	13109	+ sub r1, r1, r2
	13110	+ sub r1, r1, #1
	13111	+ sxth r3, r3
	13112	+ sxth r1, r1
	13113	+.L2190:
	13114	+ cmp r3, r1
	13115	+ bgt .L2196
	13116	+ cmp r3, #0
	13117	+ bge .L2226
	13118	+ b .L2184
	13119	+.L2196:
	13120	+ ldr fp, [r6, #4]
	13121	+ lsl lr, r3, #2
	13122	+ ldr r10, [ip, r3, lsl #2]
	13123	+ cmp fp, r10
	13124	+ bls .L2191
	13125	+ ldr r1, [ip]
	13126	+ cmp r1, #0
	13127	+ bne .L2192
	13128	+ cmp r0, r2
	13129	+ addne r2, r2, #1
	13130	+ strhne r2, [r9] @ movhi
	13131	+.L2192:
	13132	+ uxth ip, r3
	13133	+ mov r1, #0
	13134	+.L2193:
	13135	+ uxth r0, r1
	13136	+ sxth r2, r1
	13137	+ cmp r0, ip
	13138	+ bcc .L2194
	13139	+ ldr r1, [r6, #4]
	13140	+ cmp r3, #0
	13141	+ ldr r2, [r4, #-1368]
	13142	+ str r1, [r2, lr]
	13143	+ lsl r2, r3, #1
	13144	+ ldr r1, [r4, #-1400]
	13145	+ strh r5, [r1, r2] @ movhi
	13146	+ blt .L2184
	13147	+ ldrh r2, [r9]
	13148	+ ldr r1, [r4, #-1636]
	13149	+ sub r1, r1, r2
12796	13150	sub r1, r1, #1
12797	13151	sxth r1, r1
12798		- cmp r0, r1
12799		- bgt .L2217
12800		-.L2259:
	13152	+ cmp r3, r1
	13153	+ bgt .L2184
	13154	+.L2226:
12801	13155	add r2, r2, #1
12802		- ldr r1, [r8, #4]
12803		- strh r2, [fp] @ movhi
12804		- sxth r3, r3
	13156	+ ldr r1, [r6, #4]
	13157	+ strh r2, [r9] @ movhi
12805	13158	ldr r2, [r4, #-1368]
12806		- str r1, [r2, r3, asl #2]
12807		- mov r3, r3, asl #1
12808		- ldr r2, [r4, #-1404]
12809		- b .L2280
12810		-.L2238:
12811		- ldr r10, [r8, #4]
12812		- mov fp, r2, asl #2
12813		- ldr r9, [lr, r2, asl #2]
12814		- cmp r10, r9
12815		- bhi .L2287
	13159	+ str r1, [r2, r3, lsl #2]
	13160	+ lsl r3, r3, #1
	13161	+ ldr r2, [r4, #-1400]
	13162	+.L2247:
	13163	+ strh r5, [r2, r3] @ movhi
	13164	+ b .L2184
	13165	+.L2194:
	13166	+ ldr r0, [r4, #-1368]
	13167	+ add r1, r1, #1
	13168	+ add r10, r0, r2, lsl #2
	13169	+ ldr r10, [r10, #4]
	13170	+ str r10, [r0, r2, lsl #2]
	13171	+ lsl r2, r2, #1
	13172	+ ldr r0, [r4, #-1400]
	13173	+ add r10, r0, r2
	13174	+ ldrh r10, [r10, #2]
	13175	+ strh r10, [r0, r2] @ movhi
	13176	+ b .L2193
	13177	+.L2191:
12816	13178	sub r3, r3, #1
12817		- uxth r3, r3
12818		-.L2232:
12819		- sxth r2, r3
12820		- cmp r2, r0
12821		- bgt .L2238
12822		- b .L2237
12823		-.L2287:
12824		- ldr r0, [lr]
12825		- cmp r0, #0
12826		- bne .L2234
12827		- cmp r1, ip
12828		- addne r1, r1, #1
12829		- ldrne r0, .L2289+20
12830		- strneh r1, [r0] @ movhi
12831		-.L2234:
12832		- uxth lr, r3
12833		- mov r0, #0
12834		-.L2235:
12835		- uxth r1, r0
12836		- cmp r1, lr
12837		- bcs .L2288
12838		- ldr ip, [r5, #-1384]
12839		- sxth r1, r1
12840		- add r0, r0, #1
12841		- add r9, ip, r1, asl #2
12842		- ldr r9, [r9, #4]
12843		- str r9, [ip, r1, asl #2]
12844		- mov r1, r1, asl #1
12845		- ldr ip, [r5, #-1392]
12846		- add r9, ip, r1
12847		- ldrh r9, [r9, #2]
12848		- strh r9, [ip, r1] @ movhi
12849		- b .L2235
12850		-.L2288:
12851		- ldr r1, [r6, #-1384]
12852		- mov r2, r2, asl #1
12853		- ldr r0, [r8, #4]
12854		- str r0, [r1, fp]
12855		- ldr r1, [r6, #-1392]
12856		- strh r7, [r1, r2] @ movhi
12857		-.L2237:
12858	13179	sxth r3, r3
	13180	+ b .L2190
	13181	+.L2187:
	13182	+ ldr r3, [sp, #12]
	13183	+ ldr r1, [sp, #8]
	13184	+ ldr ip, [r4, #-1384]
	13185	+ ldrh r2, [r3, #-12]
	13186	+ ldrh r1, [r1, #-8]
	13187	+ sub r0, r2, #1
	13188	+ sxth r3, r0
	13189	+ sub r0, r0, r1
	13190	+.L2199:
	13191	+ cmp r3, r0
	13192	+ ble .L2204
	13193	+ ldr fp, [r6, #4]
	13194	+ lsl lr, r3, #2
	13195	+ ldr r10, [ip, r3, lsl #2]
	13196	+ cmp fp, r10
	13197	+ bls .L2200
	13198	+ sub r2, r2, r1
	13199	+ ldr r0, [ip]
	13200	+ clz r2, r2
	13201	+ uxth ip, r3
	13202	+ lsr r2, r2, #5
	13203	+ cmp r0, #0
	13204	+ orrne r2, r2, #1
	13205	+ cmp r2, #0
	13206	+ ldreq r2, .L2250+12
	13207	+ addeq r1, r1, #1
	13208	+ strheq r1, [r2] @ movhi
	13209	+ mov r1, #0
	13210	+.L2202:
	13211	+ uxth r0, r1
	13212	+ sxth r2, r1
	13213	+ cmp r0, ip
	13214	+ bcc .L2203
	13215	+ ldr r1, [r6, #4]
	13216	+ ldr r2, [r4, #-1384]
	13217	+ str r1, [r2, lr]
	13218	+ lsl r2, r3, #1
	13219	+ ldr r1, [r4, #-1392]
	13220	+ strh r5, [r1, r2] @ movhi
	13221	+.L2204:
12859	13222	cmp r3, #0
12860		- blt .L2217
12861		- ldr r0, .L2289+20
12862		- sub r2, r0, #360
12863		- ldrh r1, [r0]
	13223	+ blt .L2184
	13224	+ ldr r2, [sp, #8]
	13225	+ ldrh r1, [r2, #-8]
	13226	+ ldr r2, .L2250+16
12864	13227	ldrh r2, [r2]
12865	13228	sub r2, r2, #1
12866		- rsb r2, r1, r2
	13229	+ sub r2, r2, r1
12867	13230	sxth r2, r2
12868	13231	cmp r3, r2
12869		- bgt .L2217
	13232	+ bgt .L2184
	13233	+ ldr r2, [sp, #8]
12870	13234	add r1, r1, #1
12871		- ldr r2, [r5, #-1384]
12872		- strh r1, [r0] @ movhi
12873		- ldr r1, [r8, #4]
12874		- str r1, [r2, r3, asl #2]
12875		- mov r3, r3, asl #1
12876		- ldr r2, [r5, #-1392]
12877		-.L2280:
12878		- strh r7, [r2, r3] @ movhi
12879		- b .L2217
12880		-.L2218:
12881		- ldr r2, .L2289+4
12882		- ldr r9, .L2289+4
12883		- ldrh r1, [r2]
	13235	+ strh r1, [r2, #-8] @ movhi
	13236	+ ldr r2, [r4, #-1384]
	13237	+ ldr r1, [r6, #4]
	13238	+ str r1, [r2, r3, lsl #2]
	13239	+ lsl r3, r3, #1
	13240	+ ldr r2, [r4, #-1392]
	13241	+ b .L2247
	13242	+.L2203:
	13243	+ ldr r0, [r4, #-1384]
	13244	+ add r1, r1, #1
	13245	+ add r10, r0, r2, lsl #2
	13246	+ ldr r10, [r10, #4]
	13247	+ str r10, [r0, r2, lsl #2]
	13248	+ lsl r2, r2, #1
	13249	+ ldr r0, [r4, #-1392]
	13250	+ add r10, r0, r2
	13251	+ ldrh r10, [r10, #2]
	13252	+ strh r10, [r0, r2] @ movhi
	13253	+ b .L2202
	13254	+.L2200:
	13255	+ sub r3, r3, #1
	13256	+ sxth r3, r3
	13257	+ b .L2199
	13258	+.L2185:
	13259	+ ldrh r1, [r8]
12884	13260	movw r2, #65535
12885	13261	cmp r1, r2
12886		- moveq r2, r9
12887		- streqh r7, [r2] @ movhi
12888		- beq .L2281
12889		- ldr r3, .L2289+4
12890		- ldrh r0, [r3, #4]
	13262	+ strheq r5, [r8] @ movhi
	13263	+ beq .L2248
	13264	+ ldrh r0, [r8, #4]
12891	13265	cmp r0, r2
12892		- beq .L2240
	13266	+ beq .L2207
12893	13267	mov r1, #1
12894	13268	bl FtlFreeSysBlkQueueIn
12895		-.L2240:
12896		- ldr r3, [r8, #4]
12897		- ldr r2, [r6, #1136]
	13269	+.L2207:
	13270	+ ldr r3, [r6, #4]
	13271	+ ldr r2, [r4, #1136]
12898	13272	cmp r2, r3
12899		- strcsh r7, [r9, #4] @ movhi
12900		- bcs .L2217
12901		- ldrh r3, [r9]
12902		- strh r7, [r9] @ movhi
12903		- strh r3, [r9, #4] @ movhi
12904		- ldr r3, [r8, #4]
12905		-.L2281:
12906		- str r3, [r5, #1136]
12907		- b .L2217
12908		-.L2214:
12909		- ldrb r1, [r5, #-2744] @ zero_extendqisi2
12910		- mov r0, r7
12911		- cmp r1, #0
12912		- beq .L2242
12913		-.L2283:
12914		- mov r1, #0
12915		-.L2242:
12916		- bl FtlFreeSysBlkQueueIn
12917		-.L2217:
12918		- ldr r3, [sp, #12]
12919		- add r3, r3, #1
12920		- b .L2282
12921		-.L2208:
12922		- ldr r3, [sp, #8]
12923		- add r7, r3, #1
12924		- uxth r3, r7
12925		- str r3, [sp, #8]
12926		- b .L2204
12927		-.L2245:
12928		- ldr ip, [r1, #-1404]
12929		- ldrh r2, [ip]
12930		- cmp r2, #0
12931		- beq .L2247
12932		-.L2250:
12933		- ldr ip, [r1, #-1392]
12934		- ldrh r2, [ip]
12935		- cmp r2, #0
12936		- beq .L2248
12937		- b .L2271
12938		-.L2247:
12939		- movw r3, #1144
12940		- ldrh r3, [r1, r3]
12941		- cmp r3, #0
12942		- ldrne lr, [r1, #-1640]
12943		- beq .L2250
12944		-.L2251:
12945		- uxth r3, r2
12946		- sxth r0, r3
12947		- cmp r0, lr
12948		- bcs .L2250
12949		- mov r4, r0, asl #1
12950		- add r2, r2, #1
12951		- ldrh r4, [ip, r4]
12952		- cmp r4, #0
12953		- beq .L2251
12954		- ldr ip, .L2289
12955		- mov r6, #0
12956		-.L2252:
12957		- ldr lr, [r1, #-1640]
12958		- sxth r2, r3
12959		- cmp r2, lr
12960		- bcs .L2250
12961		- ldr r4, [ip, #-1404]
12962		- mov lr, r2, asl #1
12963		- rsb r5, r0, r2
12964		- add r3, r3, #1
12965		- ldrh r8, [r4, lr]
12966		- mov r7, r5, asl #1
12967		- uxth r3, r3
12968		- strh r8, [r4, r7] @ movhi
12969		- ldr r4, [ip, #-1368]
12970		- ldr r2, [r4, r2, asl #2]
12971		- str r2, [r4, r5, asl #2]
12972		- ldr r2, [ip, #-1404]
12973		- strh r6, [r2, lr] @ movhi
12974		- b .L2252
	13273	+ strhcs r5, [r8, #4] @ movhi
	13274	+ bcs .L2184
	13275	+ ldrh r3, [r8]
	13276	+ strh r5, [r8] @ movhi
	13277	+ strh r3, [r8, #4] @ movhi
	13278	+ ldr r3, [r6, #4]
12975	13279	.L2248:
12976		- ldr r1, .L2289+28
12977		- ldrh r3, [r1, #-8]
	13280	+ str r3, [r4, #1136]
	13281	+ b .L2184
	13282	+.L2212:
	13283	+ ldr r1, [r4, #-1400]
	13284	+ ldrh r3, [r1]
12978	13285	cmp r3, #0
12979		- subne r1, r1, #368
12980		- ldrneh lr, [r1]
12981		- beq .L2271
12982		-.L2255:
12983		- uxth r3, r2
12984		- sxth r0, r3
12985		- cmp r0, lr
12986		- bge .L2271
12987		- mov r4, r0, asl #1
12988		- add r2, r2, #1
12989		- ldrh r4, [ip, r4]
12990		- cmp r4, #0
12991		- beq .L2255
12992		- ldr ip, .L2289
12993		- mov r6, #0
12994		-.L2256:
12995		- ldrh lr, [r1]
12996		- sxth r2, r3
12997		- cmp r2, lr
12998		- bge .L2271
12999		- ldr r4, [ip, #-1392]
13000		- mov lr, r2, asl #1
13001		- rsb r5, r0, r2
13002		- add r3, r3, #1
13003		- ldrh r8, [r4, lr]
13004		- mov r7, r5, asl #1
13005		- uxth r3, r3
13006		- strh r8, [r4, r7] @ movhi
13007		- ldr r4, [ip, #-1384]
13008		- ldr r2, [r4, r2, asl #2]
13009		- str r2, [r4, r5, asl #2]
13010		- ldr r2, [ip, #-1392]
13011		- strh r6, [r2, lr] @ movhi
13012		- b .L2256
13013		-.L2271:
	13286	+ beq .L2214
	13287	+.L2217:
	13288	+ ldr r1, [r4, #-1392]
	13289	+ ldrh r2, [r1]
	13290	+ cmp r2, #0
	13291	+ beq .L2215
	13292	+.L2237:
13014	13293	mov r0, #0
13015		- add sp, sp, #36
	13294	+ add sp, sp, #28
13016	13295	@ sp needed
13017		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
13018		-.L2290:
	13296	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	13297	+.L2214:
	13298	+ movw r2, #1144
	13299	+ ldrh r2, [r4, r2]
	13300	+ cmp r2, #0
	13301	+ ldrne r0, [r4, #-1636]
	13302	+ beq .L2217
	13303	+.L2218:
	13304	+ sxth r2, r3
	13305	+ cmp r2, r0
	13306	+ bcs .L2217
	13307	+ lsl ip, r2, #1
	13308	+ add r3, r3, #1
	13309	+ ldrh ip, [r1, ip]
	13310	+ cmp ip, #0
	13311	+ beq .L2218
	13312	+ mov r3, r2
	13313	+ mov lr, #0
	13314	+.L2219:
	13315	+ ldr r1, [r4, #-1636]
	13316	+ cmp r3, r1
	13317	+ bcs .L2217
	13318	+ ldr r0, [r4, #-1400]
	13319	+ lsl r1, r3, #1
	13320	+ sub ip, r3, r2
	13321	+ lsl r5, ip, #1
	13322	+ ldrh r6, [r0, r1]
	13323	+ strh r6, [r0, r5] @ movhi
	13324	+ ldr r0, [r4, #-1368]
	13325	+ ldr r5, [r0, r3, lsl #2]
	13326	+ add r3, r3, #1
	13327	+ sxth r3, r3
	13328	+ str r5, [r0, ip, lsl #2]
	13329	+ ldr r0, [r4, #-1400]
	13330	+ strh lr, [r0, r1] @ movhi
	13331	+ b .L2219
	13332	+.L2215:
	13333	+ ldr r3, .L2250+20
	13334	+ ldrh r0, [r3, #-8]
	13335	+ cmp r0, #0
	13336	+ subne r3, r3, #352
	13337	+ ldrhne r0, [r3, #-12]
	13338	+ beq .L2237
	13339	+.L2222:
	13340	+ sxth r3, r2
	13341	+ cmp r3, r0
	13342	+ mov lr, r3
	13343	+ bge .L2237
	13344	+ lsl ip, r3, #1
	13345	+ add r2, r2, #1
	13346	+ ldrh ip, [r1, ip]
	13347	+ cmp ip, #0
	13348	+ beq .L2222
	13349	+ mov ip, #0
	13350	+.L2223:
	13351	+ ldr r2, [sp, #12]
	13352	+ ldrh r2, [r2, #-12]
	13353	+ cmp r3, r2
	13354	+ bge .L2237
	13355	+ ldr r1, [r4, #-1392]
	13356	+ lsl r2, r3, #1
	13357	+ sub r0, r3, lr
	13358	+ lsl r5, r0, #1
	13359	+ ldrh r6, [r1, r2]
	13360	+ strh r6, [r1, r5] @ movhi
	13361	+ ldr r1, [r4, #-1384]
	13362	+ ldr r5, [r1, r3, lsl #2]
	13363	+ add r3, r3, #1
	13364	+ sxth r3, r3
	13365	+ str r5, [r1, r0, lsl #2]
	13366	+ ldr r1, [r4, #-1392]
	13367	+ strh ip, [r1, r2] @ movhi
	13368	+ b .L2223
	13369	+.L2251:
13019	13370	.align 2
13020		-.L2289:
	13371	+.L2250:
13021	13372	.word .LANCHOR2
13022	13373	.word .LANCHOR2+1128
13023		- .word .LANCHOR2-1726
13024		- .word .LANCHOR2-1736
13025		- .word .LANCHOR2-1656
	13374	+ .word .LANCHOR2-1722
13026	13375	.word .LANCHOR2-1288
13027		- .word .LANCHOR2+1144
	13376	+ .word .LANCHOR2-1644
13028	13377	.word .LANCHOR2-1280
13029	13378	.fnend
13030	13379	.size FtlScanSysBlk, .-FtlScanSysBlk
13031	13380	.align 2
13032	13381	.global FtlLoadEctTbl
	13382	+ .syntax unified
	13383	+ .arm
	13384	+ .fpu softvfp
13033	13385	.type FtlLoadEctTbl, %function
13034	13386	FtlLoadEctTbl:
13035	13387	.fnstart
13036	13388	@ args = 0, pretend = 0, frame = 0
13037	13389	@ frame_needed = 0, uses_anonymous_args = 0
13038		- stmfd sp!, {r3, r4, r5, lr}
13039		- .save {r3, r4, r5, lr}
	13390	+ push {r4, r5, r6, lr}
	13391	+ .save {r4, r5, r6, lr}
13040	13392	mov r0, #64
13041		- ldr r4, .L2294
	13393	+ ldr r4, .L2255
13042	13394	sub r5, r4, #1424
13043		- ldr r2, [r4, #-1420]
13044		- ldrh r1, [r5, #-4]
	13395	+ ldr r2, [r4, #-1416]
	13396	+ ldrh r1, [r5]
13045	13397	bl FtlVendorPartRead
13046		- ldr r3, [r4, #-1420]
	13398	+ ldr r3, [r4, #-1416]
13047	13399	ldr r2, [r3]
13048		- ldr r3, .L2294+4
	13400	+ ldr r3, .L2255+4
13049	13401	cmp r2, r3
13050		- beq .L2292
13051		- ldr r1, .L2294+8
13052		- ldr r0, .L2294+12
	13402	+ beq .L2253
	13403	+ ldr r1, .L2255+8
	13404	+ ldr r0, .L2255+12
13053	13405	bl printk
13054		- ldrh r2, [r5, #-4]
13055		- ldr r0, [r4, #-1420]
	13406	+ ldrh r2, [r5]
13056	13407	mov r1, #0
13057		- mov r2, r2, asl #9
	13408	+ ldr r0, [r4, #-1416]
	13409	+ lsl r2, r2, #9
13058	13410	bl ftl_memset
13059		-.L2292:
	13411	+.L2253:
13060	13412	mov r0, #0
13061		- ldmfd sp!, {r3, r4, r5, pc}
13062		-.L2295:
	13413	+ pop {r4, r5, r6, pc}
	13414	+.L2256:
13063	13415	.align 2
13064		-.L2294:
	13416	+.L2255:
13065	13417	.word .LANCHOR2
13066	13418	.word 1112818501
13067		- .word .LC49
13068	13419	.word .LC48
	13420	+ .word .LC49
13069	13421	.fnend
13070	13422	.size FtlLoadEctTbl, .-FtlLoadEctTbl
13071	13423	.align 2
13072	13424	.global ftl_set_blk_mode
	13425	+ .syntax unified
	13426	+ .arm
	13427	+ .fpu softvfp
13073	13428	.type ftl_set_blk_mode, %function
13074	13429	ftl_set_blk_mode:
13075	13430	.fnstart
13076	13431	@ args = 0, pretend = 0, frame = 0
13077	13432	@ frame_needed = 0, uses_anonymous_args = 0
13078	13433	@ link register save eliminated.
13079		- ldr r2, .L2300
13080		- mov r3, r0, lsr #5
13081	13434	cmp r1, #0
13082		- and r0, r0, #31
13083		- uxth r3, r3
	13435	+ mov r3, r0
	13436	+ beq .L2258
	13437	+ b ftl_set_blk_mode.part.17
	13438	+.L2258:
	13439	+ ldr r2, .L2259
	13440	+ lsr r0, r0, #5
	13441	+ and r3, r3, #31
13084	13442	mov ip, #1
13085		- ldr r1, [r2, #-1396]
13086		- ldr r2, [r1, r3, asl #2]
13087		- orrne r0, r2, ip, asl r0
13088		- biceq r0, r2, ip, asl r0
13089		- str r0, [r1, r3, asl #2]
	13443	+ ldr r1, [r2, #32]
	13444	+ ldr r2, [r1, r0, lsl #2]
	13445	+ bic r3, r2, ip, lsl r3
	13446	+ str r3, [r1, r0, lsl #2]
13090	13447	bx lr
13091		-.L2301:
	13448	+.L2260:
13092	13449	.align 2
13093		-.L2300:
13094		- .word .LANCHOR2
	13450	+.L2259:
	13451	+ .word .LANCHOR0
13095	13452	.fnend
13096	13453	.size ftl_set_blk_mode, .-ftl_set_blk_mode
13097	13454	.align 2
13098	13455	.global ftl_get_blk_mode
	13456	+ .syntax unified
	13457	+ .arm
	13458	+ .fpu softvfp
13099	13459	.type ftl_get_blk_mode, %function
13100	13460	ftl_get_blk_mode:
13101	13461	.fnstart
13102	13462	@ args = 0, pretend = 0, frame = 0
13103	13463	@ frame_needed = 0, uses_anonymous_args = 0
13104	13464	@ link register save eliminated.
13105		- ldr r3, .L2303
13106		- mov r2, r0, lsr #5
	13465	+ ldr r3, .L2262
	13466	+ lsr r2, r0, #5
13107	13467	and r0, r0, #31
13108		- ldr r3, [r3, #-1396]
13109		- ldr r3, [r3, r2, asl #2]
13110		- mov r0, r3, lsr r0
	13468	+ ldr r3, [r3, #32]
	13469	+ ldr r3, [r3, r2, lsl #2]
	13470	+ lsr r0, r3, r0
13111	13471	and r0, r0, #1
13112	13472	bx lr
13113		-.L2304:
	13473	+.L2263:
13114	13474	.align 2
13115		-.L2303:
13116		- .word .LANCHOR2
	13475	+.L2262:
	13476	+ .word .LANCHOR0
13117	13477	.fnend
13118	13478	.size ftl_get_blk_mode, .-ftl_get_blk_mode
13119	13479	.align 2
13120	13480	.global FtlCheckVpc
	13481	+ .syntax unified
	13482	+ .arm
	13483	+ .fpu softvfp
13121	13484	.type FtlCheckVpc, %function
13122	13485	FtlCheckVpc:
13123	13486	.fnstart
13124	13487	@ args = 0, pretend = 0, frame = 8
13125	13488	@ frame_needed = 0, uses_anonymous_args = 0
13126		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
13127		- .save {r4, r5, r6, r7, r8, r9, lr}
	13489	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	13490	+ .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13128	13491	.pad #12
13129	13492	mov r4, #0
13130		- ldr r1, .L2328
13131		- ldr r0, .L2328+4
	13493	+ ldr r6, .L2285
	13494	+ ldr r7, .L2285+4
	13495	+ ldr r1, .L2285+8
	13496	+ mov r5, r6
	13497	+ ldr r0, .L2285+12
13132	13498	bl printk
13133		- ldr r0, .L2328+8
13134		- mov r1, #0
13135	13499	mov r2, #8192
	13500	+ mov r1, #0
	13501	+ ldr r0, .L2285+4
13136	13502	bl memset
13137		- ldr r7, .L2328+12
13138		- ldr r5, .L2328+8
13139		-.L2306:
13140		- ldr r3, [r7, #-1284]
13141		- ldr r6, .L2328+12
	13503	+.L2265:
	13504	+ ldr r3, [r6, #-1284]
13142	13505	cmp r4, r3
13143		- bcs .L2326
13144		- mov r0, r4
13145		- add r1, sp, #4
13146		- mov r2, #0
13147		- bl log2phys
13148		- ldr r0, [sp, #4]
13149		- cmn r0, #1
13150		- beq .L2307
13151		- ubfx r0, r0, #10, #16
13152		- bl P2V_block_in_plane
13153		- mov r0, r0, asl #1
13154		- ldrh r3, [r5, r0]
13155		- add r3, r3, #1
13156		- strh r3, [r5, r0] @ movhi
13157		-.L2307:
13158		- add r4, r4, #1
13159		- b .L2306
13160		-.L2326:
13161		- ldr r9, .L2328+8
	13506	+ bcc .L2267
	13507	+ ldr r8, .L2285+4
13162	13508	mov r4, #0
13163		- mov r5, r4
13164		- mov r8, r6
13165		-.L2309:
13166		- ldr r2, .L2328+12
13167		- uxth r1, r4
13168		- sub r3, r2, #1728
13169		- ldrh r3, [r3]
13170		- cmp r3, r1
13171		- bls .L2327
13172		- ldr r3, [r8, #-1408]
13173		- mov r7, r1, asl #1
13174		- ldrh r2, [r3, r7]
13175		- ldrh r3, [r9, r7]
	13509	+ ldr r9, .L2285+16
	13510	+ mov r6, r4
	13511	+.L2268:
	13512	+ ldr r3, .L2285+20
	13513	+ ldrh r2, [r3]
	13514	+ uxth r3, r4
13176	13515	cmp r2, r3
13177		- beq .L2310
13178		- ldr r0, .L2328+16
13179		- bl printk
13180		- ldr r3, [r8, #-1408]
13181		- movw r2, #65535
13182		- ldrh r3, [r3, r7]
13183		- cmp r3, r2
13184		- beq .L2310
13185		- ldrh r2, [r9, r7]
13186		- cmp r2, r3
13187		- movhi r5, #1
13188		-.L2310:
13189		- add r4, r4, #1
13190		- b .L2309
13191		-.L2327:
13192		- ldr r3, [r2, #876]
13193		- cmp r3, #0
13194		- beq .L2312
13195		- add r1, r2, #880
13196		- ldr r2, [r2, #-1356]
13197		- add r9, r1, #268
13198		- mov r8, #0
13199		- rsb r3, r2, r3
13200		- ldr r2, .L2328+20
13201		- ldrh r7, [r1]
13202		- mov r3, r3, asr #1
13203		- mul r3, r2, r3
13204		- uxth r4, r3
13205		-.L2313:
13206		- uxth r3, r8
13207		- cmp r3, r7
13208		- bcs .L2312
13209		- ldr r2, [r6, #-1408]
13210		- mov r3, r4, asl #1
	13516	+ bhi .L2270
	13517	+ ldr r4, [r5, #876]
	13518	+ cmp r4, #0
	13519	+ beq .L2271
	13520	+ ldr r3, .L2285+24
	13521	+ mov r7, #0
	13522	+ ldr r9, .L2285+4
	13523	+ mov fp, #6
	13524	+ ldr r10, .L2285+28
	13525	+ ldrh r8, [r3]
	13526	+ ldr r3, [r5, #-1356]
	13527	+ sub r4, r4, r3
	13528	+ ldr r3, .L2285+32
	13529	+ asr r4, r4, #1
	13530	+ mul r4, r3, r4
	13531	+ uxth r4, r4
	13532	+.L2272:
	13533	+ uxth r3, r7
	13534	+ cmp r8, r3
	13535	+ bls .L2271
	13536	+ ldr r2, [r5, #-1404]
	13537	+ lsl r3, r4, #1
13211	13538	ldrh r2, [r2, r3]
13212	13539	cmp r2, #0
13213		- beq .L2314
13214		- ldr r0, .L2328+24
13215		- mov r1, r4
	13540	+ beq .L2273
	13541	+ mov r6, #1
13216	13542	ldrh r3, [r9, r3]
13217		- mov r5, #1
	13543	+ mov r1, r4
	13544	+ mov r0, r10
13218	13545	bl printk
13219		-.L2314:
13220		- mov r3, #6
13221		- ldr r2, [r6, #-1356]
13222		- mul r4, r3, r4
	13546	+.L2273:
	13547	+ mul r4, fp, r4
	13548	+ ldr r3, [r5, #-1356]
	13549	+ add r7, r7, #1
	13550	+ ldrh r4, [r3, r4]
13223	13551	movw r3, #65535
13224		- add r8, r8, #1
13225		- ldrh r4, [r2, r4]
13226	13552	cmp r4, r3
13227		- bne .L2313
13228		-.L2312:
13229		- mov r1, r5
13230		- ldr r0, .L2328+28
	13553	+ bne .L2272
	13554	+.L2271:
	13555	+ mov r1, r6
	13556	+ ldr r0, .L2285+36
13231	13557	bl printk
13232	13558	add sp, sp, #12
13233	13559	@ sp needed
13234		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, pc}
13235		-.L2329:
	13560	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	13561	+.L2267:
	13562	+ mov r2, #0
	13563	+ add r1, sp, #4
	13564	+ mov r0, r4
	13565	+ bl log2phys
	13566	+ ldr r0, [sp, #4]
	13567	+ cmn r0, #1
	13568	+ beq .L2266
	13569	+ ubfx r0, r0, #10, #16
	13570	+ bl P2V_block_in_plane
	13571	+ lsl r0, r0, #1
	13572	+ ldrh r3, [r7, r0]
	13573	+ add r3, r3, #1
	13574	+ strh r3, [r7, r0] @ movhi
	13575	+.L2266:
	13576	+ add r4, r4, #1
	13577	+ b .L2265
	13578	+.L2270:
	13579	+ uxth r1, r4
	13580	+ ldr r3, [r5, #-1404]
	13581	+ lsl r7, r1, #1
	13582	+ ldrh r2, [r3, r7]
	13583	+ ldrh r3, [r8, r7]
	13584	+ cmp r2, r3
	13585	+ beq .L2269
	13586	+ mov r0, r9
	13587	+ bl printk
	13588	+ ldr r3, [r5, #-1404]
	13589	+ movw r2, #65535
	13590	+ ldrh r3, [r3, r7]
	13591	+ cmp r3, r2
	13592	+ beq .L2269
	13593	+ ldrh r2, [r8, r7]
	13594	+ cmp r2, r3
	13595	+ movhi r6, #1
	13596	+.L2269:
	13597	+ add r4, r4, #1
	13598	+ b .L2268
	13599	+.L2286:
13236	13600	.align 2
13237		-.L2328:
13238		- .word .LANCHOR3+148
13239		- .word .LC50
13240		- .word .LANCHOR2+1148
	13601	+.L2285:
13241	13602	.word .LANCHOR2
	13603	+ .word check_valid_page_count_table
	13604	+ .word .LANCHOR3+141
	13605	+ .word .LC50
13242	13606	.word .LC51
13243		- .word -1431655765
	13607	+ .word .LANCHOR2-1724
	13608	+ .word .LANCHOR2+880
13244	13609	.word .LC52
	13610	+ .word -1431655765
13245	13611	.word .LC53
13246	13612	.fnend
13247	13613	.size FtlCheckVpc, .-FtlCheckVpc
13248	13614	.align 2
13249	13615	.global FtlDumpSysBlock
	13616	+ .syntax unified
	13617	+ .arm
	13618	+ .fpu softvfp
13250	13619	.type FtlDumpSysBlock, %function
13251	13620	FtlDumpSysBlock:
13252	13621	.fnstart
13253	13622	@ args = 0, pretend = 0, frame = 0
13254	13623	@ frame_needed = 0, uses_anonymous_args = 0
13255		- stmfd sp!, {r4, r5, r6, r7, r8, lr}
13256		- .save {r4, r5, r6, r7, r8, lr}
13257		- mov r7, r0, asl #10
13258		- ldr r4, .L2339
13259		- .pad #24
13260		- sub sp, sp, #24
13261		- ldr r8, .L2339+4
13262		- mov r6, r0
	13624	+ push {r4, r5, r6, r7, r8, r9, lr}
	13625	+ .save {r4, r5, r6, r7, r8, r9, lr}
	13626	+ lsl r8, r0, #10
	13627	+ ldr r4, .L2295
	13628	+ .pad #28
	13629	+ sub sp, sp, #28
	13630	+ mov r7, r0
13263	13631	mov r5, #0
13264		- ldr r3, [r4, #-1476]
	13632	+ ldr r3, [r4, #-1472]
	13633	+ sub r6, r4, #1264
	13634	+ sub r9, r4, #1664
	13635	+ sub r6, r6, #12
13265	13636	str r3, [r4, #-1268]
13266		- ldr r3, [r4, #-1444]
	13637	+ ldr r3, [r4, #-1440]
13267	13638	str r3, [r4, #-1264]
13268		-.L2331:
13269		- ldrh r2, [r8]
	13639	+.L2288:
	13640	+ ldrh r2, [r9]
13270	13641	sxth r3, r5
13271	13642	cmp r3, r2
13272		- bge .L2338
13273		- mov r1, #1
13274		- ldr r0, .L2339+8
13275		- mov r2, r1
13276		- orr r3, r3, r7
	13643	+ blt .L2290
	13644	+ add sp, sp, #28
	13645	+ @ sp needed
	13646	+ pop {r4, r5, r6, r7, r8, r9, pc}
	13647	+.L2290:
	13648	+ mov r2, #1
	13649	+ orr r3, r3, r8
	13650	+ mov r1, r2
	13651	+ mov r0, r6
13277	13652	str r3, [r4, #-1272]
13278	13653	bl FlashReadPages
	13654	+ ldr r2, [r4, #-1268]
	13655	+ mov r1, r7
13279	13656	ldr r3, [r4, #-1264]
13280		- mov r1, r6
13281		- ldr r0, .L2339+12
13282		- ldr r2, [r3]
13283		- str r2, [sp]
13284		- ldr r2, [r3, #4]
13285		- str r2, [sp, #4]
	13657	+ ldr r0, .L2295+4
	13658	+ ldr r2, [r2]
	13659	+ str r2, [sp, #16]
	13660	+ ldr r2, [r3, #12]
	13661	+ str r2, [sp, #12]
13286	13662	ldr r2, [r3, #8]
13287	13663	str r2, [sp, #8]
13288		- ldr r3, [r3, #12]
13289		- ldr r2, [r4, #-1276]
13290		- str r3, [sp, #12]
13291		- ldr r3, [r4, #-1268]
	13664	+ ldr r2, [r3, #4]
	13665	+ str r2, [sp, #4]
13292	13666	ldr r3, [r3]
13293		- str r3, [sp, #16]
	13667	+ ldr r2, [r4, #-1276]
	13668	+ str r3, [sp]
13294	13669	ldr r3, [r4, #-1272]
13295	13670	bl printk
13296	13671	ldr r3, [r4, #-1264]
13297	13672	ldr r3, [r3]
13298	13673	cmn r3, #1
13299		- beq .L2332
13300		- ldr r0, .L2339+16
13301		- mov r2, #4
13302		- ldr r1, [r4, #-1476]
	13674	+ beq .L2289
13303	13675	mov r3, #768
	13676	+ mov r2, #4
	13677	+ ldr r1, [r4, #-1472]
	13678	+ ldr r0, .L2295+8
13304	13679	bl rknand_print_hex
13305		-.L2332:
	13680	+.L2289:
13306	13681	add r5, r5, #1
13307		- b .L2331
13308		-.L2338:
13309		- add sp, sp, #24
13310		- @ sp needed
13311		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
13312		-.L2340:
	13682	+ b .L2288
	13683	+.L2296:
13313	13684	.align 2
13314		-.L2339:
	13685	+.L2295:
13315	13686	.word .LANCHOR2
13316		- .word .LANCHOR2-1666
13317		- .word .LANCHOR2-1276
13318	13687	.word .LC54
13319	13688	.word .LC55
13320	13689	.fnend
13321	13690	.size FtlDumpSysBlock, .-FtlDumpSysBlock
13322	13691	.align 2
13323	13692	.global Ftlscanalldata
	13693	+ .syntax unified
	13694	+ .arm
	13695	+ .fpu softvfp
13324	13696	.type Ftlscanalldata, %function
13325	13697	Ftlscanalldata:
13326	13698	.fnstart
13327	13699	@ args = 0, pretend = 0, frame = 8
13328	13700	@ frame_needed = 0, uses_anonymous_args = 0
13329		- stmfd sp!, {r4, r5, r6, r7, lr}
13330		- .save {r4, r5, r6, r7, lr}
13331		- mov r1, #0
13332		- .pad #36
13333		- sub sp, sp, #36
13334		- ldr r0, .L2351
13335		- bl printk
13336		- ldr r6, .L2351+4
	13701	+ push {r4, r5, r6, r7, r8, lr}
	13702	+ .save {r4, r5, r6, r7, r8, lr}
13337	13703	mov r5, #0
	13704	+ ldr r6, .L2306
	13705	+ .pad #32
	13706	+ sub sp, sp, #32
	13707	+ mov r1, #0
	13708	+ ldr r8, .L2306+4
13338	13709	mov r4, r6
13339		-.L2342:
	13710	+ ldr r0, .L2306+8
	13711	+ bl printk
	13712	+.L2298:
13340	13713	ldr r3, [r6, #-1284]
13341	13714	cmp r5, r3
13342		- bcs .L2350
13343		- mov r0, r5
13344		- add r1, sp, #28
	13715	+ bcc .L2304
	13716	+ add sp, sp, #32
	13717	+ @ sp needed
	13718	+ pop {r4, r5, r6, r7, r8, pc}
	13719	+.L2304:
13345	13720	mov r2, #0
	13721	+ add r1, sp, #28
	13722	+ mov r0, r5
13346	13723	bl log2phys
13347	13724	ubfx r3, r5, #0, #11
13348	13725	cmp r3, #0
13349		- bne .L2343
13350		- ldr r0, .L2351+8
13351		- mov r1, r5
	13726	+ bne .L2299
13352	13727	ldr r2, [sp, #28]
	13728	+ mov r1, r5
	13729	+ mov r0, r8
13353	13730	bl printk
13354		-.L2343:
	13731	+.L2299:
13355	13732	ldr r3, [sp, #28]
13356	13733	cmn r3, #1
13357		- beq .L2345
	13734	+ beq .L2301
13358	13735	str r3, [r4, #-1272]
13359	13736	mov r2, #0
13360		- ldr r3, [r4, #-1476]
	13737	+ ldr r3, [r4, #-1472]
13361	13738	mov r1, #1
13362		- ldr r7, [r4, #-1444]
13363		- ldr r0, .L2351+12
	13739	+ ldr r7, [r4, #-1440]
	13740	+ ldr r0, .L2306+12
13364	13741	str r3, [r4, #-1268]
13365	13742	str r5, [r4, #-1260]
13366	13743	str r7, [r4, #-1264]
..	..	@@ -13369,229 +13746,227 @@
13369	13746	ldr r3, [r4, #-1276]
13370	13747	cmn r3, #1
13371	13748	cmpne r3, #256
13372		- beq .L2346
	13749	+ beq .L2302
13373	13750	ldr r3, [r7, #8]
13374		- cmp r3, r5
13375		- beq .L2345
13376		-.L2346:
13377		- ldr r3, [r4, #-1264]
	13751	+ cmp r5, r3
	13752	+ beq .L2301
	13753	+.L2302:
13378	13754	ldr r2, [r4, #-1268]
13379		- ldr r0, .L2351+16
13380		- ldr r1, [r3, #4]
13381		- str r1, [sp]
13382		- ldr r1, [r3, #8]
13383		- str r1, [sp, #4]
13384		- ldr r1, [r3, #12]
13385		- str r1, [sp, #8]
13386		- ldr r1, [r2]
13387		- str r1, [sp, #12]
	13755	+ ldr r3, [r4, #-1264]
	13756	+ ldr r0, .L2306+16
	13757	+ ldr r1, [r2, #4]
	13758	+ str r1, [sp, #16]
13388	13759	mov r1, r5
13389		- ldr r2, [r2, #4]
13390		- str r2, [sp, #16]
13391		- ldr r2, [r4, #-1272]
	13760	+ ldr r2, [r2]
	13761	+ str r2, [sp, #12]
	13762	+ ldr r2, [r3, #12]
	13763	+ str r2, [sp, #8]
	13764	+ ldr r2, [r3, #8]
	13765	+ str r2, [sp, #4]
	13766	+ ldr r2, [r3, #4]
	13767	+ str r2, [sp]
13392	13768	ldr r3, [r3]
	13769	+ ldr r2, [r4, #-1272]
13393	13770	bl printk
13394		-.L2345:
	13771	+.L2301:
13395	13772	add r5, r5, #1
13396		- b .L2342
13397		-.L2350:
13398		- add sp, sp, #36
13399		- @ sp needed
13400		- ldmfd sp!, {r4, r5, r6, r7, pc}
13401		-.L2352:
	13773	+ b .L2298
	13774	+.L2307:
13402	13775	.align 2
13403		-.L2351:
13404		- .word .LC56
	13776	+.L2306:
13405	13777	.word .LANCHOR2
13406	13778	.word .LC57
	13779	+ .word .LC56
13407	13780	.word .LANCHOR2-1276
13408	13781	.word .LC58
13409	13782	.fnend
13410	13783	.size Ftlscanalldata, .-Ftlscanalldata
13411	13784	.align 2
13412	13785	.global dump_map_info
	13786	+ .syntax unified
	13787	+ .arm
	13788	+ .fpu softvfp
13413	13789	.type dump_map_info, %function
13414	13790	dump_map_info:
13415	13791	.fnstart
13416		- @ args = 0, pretend = 0, frame = 24
	13792	+ @ args = 0, pretend = 0, frame = 16
13417	13793	@ frame_needed = 0, uses_anonymous_args = 0
13418		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	13794	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13419	13795	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13420		- .pad #52
13421		- sub sp, sp, #52
13422		- ldr r5, .L2371
13423		- ldr fp, .L2371+4
13424		- ldrh r6, [r5]
13425		- add r5, r5, #1728
13426		- mov r8, r5
13427		-.L2354:
13428		- ldrh r3, [fp]
	13796	+ .pad #44
	13797	+ sub sp, sp, #44
	13798	+ ldr r8, .L2323
	13799	+ ldrh r6, [r8, #-12]
	13800	+ add fp, r8, #6
	13801	+.L2309:
	13802	+ ldrh r3, [r8, #-10]
	13803	+ ldr r1, .L2323+4
13429	13804	cmp r3, r6
13430		- bls .L2367
13431		- ldr r1, .L2371+8
	13805	+ mov r4, r1
	13806	+ bhi .L2316
	13807	+ sub r8, r1, #1264
13432	13808	mov r7, #0
13433		- ldr r2, [r5, #-1504]
13434		- mov r4, r7
13435		- ldr r3, [r5, #-1464]
13436		- add r1, r1, #28
13437		- ldr r10, [r5, #-1436]
13438		- ldrh ip, [r1, #-28]
13439		- ldrh r9, [r1, #52]
13440		- str r1, [sp, #28]
13441		-.L2363:
13442		- uxth r1, r7
13443		- cmp r1, ip
13444		- bcs .L2369
13445		- str r3, [sp, #44]
	13809	+ sub r8, r8, #12
	13810	+.L2317:
	13811	+ ldr r3, .L2323+8
	13812	+ sxth r5, r7
	13813	+ ldrh r3, [r3]
	13814	+ cmp r5, r3
	13815	+ bge .L2320
	13816	+ lsl r5, r5, #1
	13817	+ mov r6, #0
	13818	+ ldr r9, .L2323+12
	13819	+ b .L2321
	13820	+.L2311:
13446	13821	mov r1, r6
13447		- ldr r3, [sp, #28]
13448		- str r2, [sp, #40]
13449		- str ip, [sp, #36]
13450		- ldrb r0, [r3, r7] @ zero_extendqisi2
	13822	+ ldrb r0, [fp, r7] @ zero_extendqisi2
	13823	+ str r3, [sp, #36]
	13824	+ str r2, [sp, #32]
13451	13825	bl V2P_block
13452		- str r0, [sp, #32]
	13826	+ str r0, [sp, #28]
13453	13827	bl FtlBbmIsBadBlock
13454	13828	cmp r0, #0
13455		- ldr r1, [sp, #32]
13456		- ldr ip, [sp, #36]
13457		- ldr r2, [sp, #40]
13458		- ldr r3, [sp, #44]
13459		- bne .L2355
13460		- mov r0, #36
13461		- mov r1, r1, asl #10
13462		- mla r0, r0, r4, r2
	13829	+ ldr r2, [sp, #32]
	13830	+ ldr r3, [sp, #36]
	13831	+ bne .L2310
	13832	+ mov r1, #36
	13833	+ mla r0, r1, r5, r9
	13834	+ ldr r1, [sp, #28]
	13835	+ lsl r1, r1, #10
13463	13836	stmib r0, {r1, r3}
13464		- mul r1, r9, r4
13465		- add r4, r4, #1
13466		- uxth r4, r4
13467		- add lr, r1, #3
	13837	+ ldr r1, [sp, #24]
	13838	+ mul r1, r1, r5
	13839	+ add r5, r5, #1
	13840	+ uxth r5, r5
	13841	+ add ip, r1, #3
13468	13842	cmp r1, #0
13469		- movlt r1, lr
	13843	+ movlt r1, ip
13470	13844	bic r1, r1, #3
13471	13845	add r1, r10, r1
13472	13846	str r1, [r0, #12]
13473		-.L2355:
	13847	+.L2310:
13474	13848	add r7, r7, #1
13475		- b .L2363
13476		-.L2369:
13477		- cmp r4, #0
13478		- beq .L2358
13479		- ldr r0, [r8, #-1504]
13480		- mov r1, r4
13481		- mov r2, #1
13482		- mov r7, #0
13483		- bl FlashReadPages
13484		- mov r9, #36
13485		-.L2359:
13486		- uxth r3, r7
13487		- cmp r3, r4
13488		- bcs .L2358
13489		- ldr r3, [r8, #-1504]
13490		- ldr r0, .L2371+12
13491		- mla r3, r9, r7, r3
13492		- add r7, r7, #1
13493		- ldmib r3, {r2, r3, ip}
13494		- ldr r1, [ip, #4]
13495		- str r1, [sp]
13496		- ldr r1, [ip, #8]
13497		- str r1, [sp, #4]
13498		- ldr r1, [ip, #12]
13499		- str r1, [sp, #8]
13500		- ldr r1, [r3]
13501		- str r1, [sp, #12]
13502		- ubfx r1, r2, #10, #16
13503		- ldr r3, [r3, #4]
13504		- str r3, [sp, #16]
13505		- ldr r3, [ip]
13506		- bl printk
13507		- b .L2359
13508		-.L2358:
	13849	+.L2318:
	13850	+ uxth r1, r7
	13851	+ cmp r2, r1
	13852	+ bhi .L2311
	13853	+ cmp r5, #0
	13854	+ bne .L2312
	13855	+.L2315:
13509	13856	add r6, r6, #1
13510	13857	uxth r6, r6
13511		- b .L2354
13512		-.L2367:
13513		- ldr r4, .L2371+16
	13858	+ b .L2309
	13859	+.L2312:
	13860	+ ldr r10, .L2323+16
	13861	+ mov r0, r9
13514	13862	mov r7, #0
13515		- ldr r8, .L2371+20
13516		-.L2362:
13517		- ldrh r3, [r8]
13518		- sxth r6, r7
13519		- ldr r5, .L2371+16
13520		- cmp r6, r3
13521		- bge .L2365
13522		- ldr r9, .L2371+24
13523		- mov r6, r6, asl #1
13524		- mov r5, #0
13525		-.L2366:
13526		- ldrh r2, [r9]
13527		- sxth r3, r5
13528		- add r5, r5, #1
13529		- cmp r3, r2
13530		- bge .L2370
13531		- ldr r2, [r4, #-1404]
13532		- mov r1, #1
13533		- ldr r0, .L2371+28
13534		- ldrh r2, [r2, r6]
13535		- orr r3, r3, r2, asl #10
13536		- mov r2, r1
	13863	+ mov r9, #36
	13864	+ mov r2, #1
	13865	+ mov r1, r5
	13866	+ bl FlashReadPages
	13867	+.L2313:
	13868	+ uxth r3, r7
	13869	+ cmp r5, r3
	13870	+ bls .L2315
	13871	+ ldr r3, [r4, #-1500]
	13872	+ mla r3, r9, r7, r3
	13873	+ add r7, r7, #1
	13874	+ ldr r1, [r3, #12]
	13875	+ ldr r2, [r3, #4]
	13876	+ ldr r3, [r3, #8]
	13877	+ ldr r0, [r3, #4]
	13878	+ str r0, [sp, #16]
	13879	+ mov r0, r10
	13880	+ ldr r3, [r3]
	13881	+ str r3, [sp, #12]
	13882	+ ldr r3, [r1, #12]
	13883	+ str r3, [sp, #8]
	13884	+ ldr r3, [r1, #8]
	13885	+ str r3, [sp, #4]
	13886	+ ldr r3, [r1, #4]
	13887	+ str r3, [sp]
	13888	+ ldr r3, [r1]
	13889	+ ubfx r1, r2, #10, #16
	13890	+ bl printk
	13891	+ b .L2313
	13892	+.L2316:
	13893	+ sub r0, r1, #1728
	13894	+ ldr r9, [r1, #-1500]
	13895	+ ldr r3, [r1, #-1460]
	13896	+ mov r7, #0
	13897	+ ldr r10, [r1, #-1432]
	13898	+ mov r5, r7
	13899	+ ldrh r1, [r0, #74]
	13900	+ ldrh r2, [r0, #-4]
	13901	+ str r1, [sp, #24]
	13902	+ b .L2318
	13903	+.L2319:
	13904	+ ldr r2, [r4, #-1400]
	13905	+ mov r0, r8
	13906	+ ldrh r2, [r2, r5]
	13907	+ orr r3, r3, r2, lsl #10
	13908	+ mov r2, #1
	13909	+ mov r1, r2
13537	13910	str r3, [r4, #-1272]
13538	13911	bl FlashReadPages
13539		- ldr r3, [r4, #-1264]
13540		- ldr r1, [r4, #-1404]
13541	13912	ldr r2, [r4, #-1268]
13542		- ldr r0, [r3]
13543		- ldrh r1, [r1, r6]
13544		- str r0, [sp]
13545		- ldr r0, [r3, #4]
13546		- str r0, [sp, #4]
13547		- ldr r0, [r3, #8]
13548		- str r0, [sp, #8]
13549		- ldr r3, [r3, #12]
13550		- ldr r0, .L2371+32
13551		- str r3, [sp, #12]
13552		- ldr r3, [r2]
13553		- str r3, [sp, #16]
13554		- ldr r3, [r2, #4]
13555		- str r3, [sp, #20]
13556		- ldr r2, [r4, #-1276]
	13913	+ ldr r1, [r4, #-1400]
	13914	+ ldr r3, [r4, #-1264]
	13915	+ ldr r0, [r2, #4]
	13916	+ ldrh r1, [r1, r5]
	13917	+ str r0, [sp, #20]
	13918	+ ldr r2, [r2]
	13919	+ ldr r0, .L2323+20
	13920	+ str r2, [sp, #16]
	13921	+ ldr r2, [r3, #12]
	13922	+ str r2, [sp, #12]
	13923	+ ldr r2, [r3, #8]
	13924	+ str r2, [sp, #8]
	13925	+ ldr r2, [r3, #4]
	13926	+ str r2, [sp, #4]
	13927	+ ldr r3, [r3]
	13928	+ str r3, [sp]
13557	13929	ldr r3, [r4, #-1272]
	13930	+ ldr r2, [r4, #-1276]
13558	13931	bl printk
13559		- b .L2366
13560		-.L2370:
	13932	+.L2321:
	13933	+ ldrh r2, [r9]
	13934	+ sxth r3, r6
	13935	+ add r6, r6, #1
	13936	+ cmp r3, r2
	13937	+ blt .L2319
13561	13938	add r7, r7, #1
13562		- b .L2362
13563		-.L2365:
13564		- sub r4, r5, #1632
13565		- ldr r1, [r5, #-1404]
13566		- ldr r3, [r5, #-1640]
	13939	+ b .L2317
	13940	+.L2320:
	13941	+ ldr r5, .L2323+24
13567	13942	mov r2, #2
13568		- ldr r0, .L2371+36
	13943	+ ldr r3, [r4, #-1636]
	13944	+ ldr r1, [r4, #-1400]
	13945	+ ldr r0, .L2323+28
13569	13946	bl rknand_print_hex
13570		- ldr r1, [r5, #-1376]
13571		- ldrh r3, [r4]
	13947	+ ldrh r3, [r5, #-12]
13572	13948	mov r2, #4
13573		- ldr r0, .L2371+40
	13949	+ ldr r1, [r4, #-1376]
	13950	+ ldr r0, .L2323+32
13574	13951	bl rknand_print_hex
13575		- ldr r0, .L2371+44
13576		- ldr r1, [r5, #-1372]
	13952	+ ldrh r3, [r5, #-12]
13577	13953	mov r2, #4
13578		- ldrh r3, [r4]
13579		- add sp, sp, #52
	13954	+ ldr r1, [r4, #-1372]
	13955	+ ldr r0, .L2323+36
	13956	+ add sp, sp, #44
13580	13957	@ sp needed
13581		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	13958	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13582	13959	b rknand_print_hex
13583		-.L2372:
	13960	+.L2324:
13584	13961	.align 2
13585		-.L2371:
13586		- .word .LANCHOR2-1728
13587		- .word .LANCHOR2-1726
13588		- .word .LANCHOR2-1736
13589		- .word .LC59
	13962	+.L2323:
	13963	+ .word .LANCHOR2-1712
13590	13964	.word .LANCHOR2
13591	13965	.word .LANCHOR2+1144
13592		- .word .LANCHOR2-1666
13593		- .word .LANCHOR2-1276
	13966	+ .word .LANCHOR2-1664
	13967	+ .word .LC59
13594	13968	.word .LC60
	13969	+ .word .LANCHOR2-1616
13595	13970	.word .LC61
13596	13971	.word .LC62
13597	13972	.word .LC63
..	..	@@ -13599,517 +13974,538 @@
13599	13974	.size dump_map_info, .-dump_map_info
13600	13975	.align 2
13601	13976	.global FtlMapTblRecovery
	13977	+ .syntax unified
	13978	+ .arm
	13979	+ .fpu softvfp
13602	13980	.type FtlMapTblRecovery, %function
13603	13981	FtlMapTblRecovery:
13604	13982	.fnstart
13605		- @ args = 0, pretend = 0, frame = 24
	13983	+ @ args = 0, pretend = 0, frame = 32
13606	13984	@ frame_needed = 0, uses_anonymous_args = 0
13607		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	13985	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13608	13986	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
13609		- .pad #28
13610		- sub sp, sp, #28
13611		- ldr r3, [r0, #16]
	13987	+ .pad #36
	13988	+ sub sp, sp, #36
	13989	+ ldr r3, [r0, #24]
13612	13990	mov r4, r0
13613		- ldrh r9, [r0, #6]
13614	13991	mov r1, #0
13615		- ldr r7, [r0, #24]
	13992	+ mov r6, #0
	13993	+ ldrh fp, [r0, #6]
	13994	+ str r3, [sp, #4]
	13995	+ ldr r3, [r0, #16]
	13996	+ ldr r5, .L2367
	13997	+ ldr r10, [r0, #12]
	13998	+ lsl r2, fp, #2
13616	13999	str r3, [sp, #12]
13617	14000	ldrh r3, [r0, #8]
13618		- mov r2, r9, asl #2
13619		- ldr r8, [r0, #12]
13620		- mov r0, r7
13621		- ldr r5, .L2416
	14001	+ mov r8, r5
	14002	+ ldr r0, [sp, #4]
13622	14003	str r3, [sp, #8]
13623	14004	bl ftl_memset
13624		- mov r1, #0
13625		- str r1, [r4, #32]
13626		- ldr r3, [r5, #-1476]
13627		- mov r10, r5
13628		- ldr r6, [r5, #-1444]
13629		- str r1, [r4, #28]
	14005	+ ldr r3, [r5, #-1472]
	14006	+ ldr r7, [r5, #-1440]
	14007	+ str r6, [r4, #32]
13630	14008	str r3, [r5, #-1268]
13631	14009	mvn r3, #0
13632		- str r6, [r5, #-1264]
	14010	+ str r7, [r5, #-1264]
13633	14011	strh r3, [r4] @ movhi
13634	14012	strh r3, [r4, #2] @ movhi
13635	14013	mov r3, #1
13636	14014	str r3, [r4, #36]
13637		- str r1, [sp, #4]
13638		-.L2374:
13639		- ldrh r2, [sp, #4]
13640		- ldr r3, [sp, #8]
13641		- sxth fp, r2
13642		- cmp fp, r3
13643		- bge .L2392
13644		- ldr r3, [sp, #8]
13645		- sub r1, r3, #1
13646		- cmp fp, r1
13647		- mov r1, fp, asl #1
13648		- bne .L2375
13649		- ldrh r0, [r8, r1]
13650		- add r10, r8, r1
13651		- mov r1, #1
13652		- str r2, [sp, #4]
13653		- bl FtlGetLastWrittenPage
13654		- mov r8, #0
13655		- ldr r2, [sp, #4]
13656		- add r3, r0, #1
13657		- strh r3, [r4, #2] @ movhi
13658		- sxth r0, r0
13659		- ldr r3, [sp, #12]
13660		- strh r2, [r4] @ movhi
13661		- ldr r3, [r3, fp, asl #2]
13662		- ldr fp, .L2416
13663		- str r3, [r4, #28]
13664		- add r3, r0, #1
13665		- str r3, [sp, #4]
13666		-.L2376:
13667		- ldr r2, [sp, #4]
13668		- sxth r3, r8
	14015	+ sub r3, r5, #1664
	14016	+ add r3, r3, #388
	14017	+ str r6, [r4, #28]
	14018	+ str r3, [sp, #20]
	14019	+.L2326:
	14020	+ ldr r2, [sp, #8]
	14021	+ sxth r3, r6
13669	14022	cmp r3, r2
13670		- bge .L2392
13671		- ldrh r2, [r10]
	14023	+ bge .L2345
	14024	+ ldr r2, [sp, #8]
	14025	+ sub r2, r2, #1
	14026	+ cmp r3, r2
	14027	+ lsl r2, r3, #1
	14028	+ bne .L2327
	14029	+ ldrh r0, [r10, r2]
13672	14030	mov r1, #1
13673		- ldr r0, .L2416+4
13674		- orr r3, r3, r2, asl #10
13675		- mov r2, r1
13676		- str r3, [r5, #-1272]
13677		- bl FlashReadPages
13678		- ldr r3, .L2416+8
13679		- ldrb r3, [r3] @ zero_extendqisi2
13680		- cmp r3, #0
13681		- beq .L2377
13682		- ldr r3, [fp, #-1264]
13683		- ldr r3, [r3, #12]
13684		- cmp r3, #0
13685		- beq .L2377
13686		- ldr r2, .L2416+12
13687		- ldr r0, [fp, #-1268]
	14031	+ str r3, [sp, #16]
	14032	+ add r3, r10, r2
13688	14033	str r3, [sp, #8]
13689		- ldrh r1, [r2]
13690		- bl js_hash
13691		- ldr r3, [sp, #8]
13692		- cmp r3, r0
13693		- mvnne r3, #0
13694		- strne r3, [fp, #-1276]
13695		-.L2377:
13696		- ldr r3, [fp, #-1276]
13697		- cmn r3, #1
13698		- beq .L2378
13699		- ldrh r3, [r6, #8]
13700		- cmp r3, r9
13701		- bcs .L2378
13702		- ldrh r2, [r4, #4]
13703		- ldrh r1, [r6]
13704		- cmp r1, r2
13705		- ldreq r2, [fp, #-1272]
13706		- streq r2, [r7, r3, asl #2]
13707		-.L2378:
13708		- add r8, r8, #1
13709		- b .L2376
13710		-.L2392:
	14034	+ mov r8, #0
	14035	+ bl FtlGetLastWrittenPage
	14036	+ ldr r2, [sp, #12]
	14037	+ sxth r9, r0
	14038	+ ldr r3, [sp, #16]
	14039	+ add r0, r0, #1
	14040	+ strh r6, [r4] @ movhi
	14041	+ ldr r10, .L2367+4
	14042	+ ldr r6, .L2367+8
	14043	+ strh r0, [r4, #2] @ movhi
	14044	+ ldr r3, [r2, r3, lsl #2]
	14045	+ str r3, [r4, #28]
	14046	+.L2328:
	14047	+ sxth r2, r8
	14048	+ add r1, r9, #1
	14049	+ cmp r2, r1
	14050	+ blt .L2331
	14051	+.L2345:
13711	14052	mov r0, r4
13712	14053	bl ftl_free_no_use_map_blk
13713		- ldr r3, .L2416+16
	14054	+ ldr r3, .L2367+12
13714	14055	ldrh r2, [r4, #2]
13715		- ldrh r3, [r3, #-2]
	14056	+ ldrh r3, [r3]
13716	14057	cmp r2, r3
13717		- bne .L2381
	14058	+ bne .L2333
13718	14059	mov r0, r4
13719	14060	bl ftl_map_blk_alloc_new_blk
13720		- b .L2381
13721		-.L2375:
13722		- ldr r2, [r5, #-1476]
13723		- add r3, r8, r1
13724		- str r3, [sp, #16]
13725		- ldr r3, .L2416+20
13726		- str r2, [r5, #-1268]
13727		- ldrh r1, [r8, r1]
13728		- ldrh r2, [r3]
13729		- ldr r0, .L2416+4
13730		- sub r2, r2, #1
13731		- orr r2, r2, r1, asl #10
13732		- mov r1, #1
13733		- str r2, [r5, #-1272]
13734		- mov r2, r1
13735		- bl FlashReadPages
13736		- ldr r2, [r5, #-1276]
13737		- cmn r2, #1
13738		- beq .L2394
13739		- ldrh r1, [r6]
13740		- ldrh r2, [r4, #4]
13741		- cmp r1, r2
13742		- bne .L2394
13743		- ldrh r1, [r6, #8]
13744		- movw r2, #64245
13745		- cmp r1, r2
13746		- bne .L2394
	14061	+.L2333:
	14062	+ mov r0, r4
	14063	+ bl ftl_map_blk_gc
	14064	+ mov r0, r4
	14065	+ bl ftl_map_blk_gc
13747	14066	mov r0, #0
13748		- mov fp, #8
13749		- mov lr, #4
13750		-.L2383:
13751		- ldr r3, .L2416+20
13752		- uxth r2, r0
13753		- sxth r1, r2
13754		- ldrh ip, [r3]
13755		- sub ip, ip, #1
13756		- cmp r1, ip
13757		- bge .L2386
13758		- ldr ip, [r10, #-1476]
13759		- add r0, r0, #1
13760		- ldr r1, [ip, r1, asl #3]
13761		- uxth r1, r1
13762		- cmp r1, r9
13763		- smlabbcc r2, r2, fp, lr
13764		- ldrcc r2, [ip, r2]
13765		- strcc r2, [r7, r1, asl #2]
13766		- b .L2383
13767		-.L2394:
13768		- mov fp, #0
13769		-.L2414:
13770		- ldr r3, .L2416+20
13771		- sxth r2, fp
	14067	+ add sp, sp, #36
	14068	+ @ sp needed
	14069	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	14070	+.L2331:
	14071	+ ldr r3, [sp, #8]
	14072	+ mov r0, r6
13772	14073	ldrh r1, [r3]
13773		- cmp r2, r1
13774		- bge .L2386
13775		- ldr r3, [sp, #16]
13776		- ldr r0, .L2416+4
13777		- ldrh r1, [r3]
13778		- orr r2, r2, r1, asl #10
13779		- mov r1, #1
13780		- str r2, [r10, #-1272]
13781		- mov r2, r1
	14074	+ orr r2, r2, r1, lsl #10
	14075	+ str r2, [r5, #-1272]
	14076	+ mov r2, #1
	14077	+ mov r1, r2
13782	14078	bl FlashReadPages
13783		- ldr r2, .L2416+8
13784		- ldrb r2, [r2] @ zero_extendqisi2
	14079	+ ldrb r2, [r10, #36] @ zero_extendqisi2
13785	14080	cmp r2, #0
13786		- beq .L2387
13787		- ldr r2, [r10, #-1264]
	14081	+ beq .L2329
	14082	+ ldr r2, [r5, #-1264]
13788	14083	ldr r2, [r2, #12]
13789	14084	cmp r2, #0
13790		- beq .L2387
13791		- ldr r1, .L2416+12
13792		- ldr r0, [r10, #-1268]
13793		- str r2, [sp, #20]
	14085	+ str r2, [sp, #12]
	14086	+ beq .L2329
	14087	+ sub r1, r6, #380
	14088	+ ldr r0, [r5, #-1268]
13794	14089	ldrh r1, [r1]
13795	14090	bl js_hash
13796		- ldr r2, [sp, #20]
	14091	+ ldr r2, [sp, #12]
13797	14092	cmp r2, r0
13798	14093	mvnne r2, #0
13799		- strne r2, [r10, #-1276]
13800		-.L2387:
13801		- ldr r2, [r10, #-1276]
	14094	+ strne r2, [r5, #-1276]
	14095	+.L2329:
	14096	+ ldr r1, .L2367
	14097	+ ldr r2, [r1, #-1276]
13802	14098	cmn r2, #1
13803		- beq .L2388
13804		- ldrh r2, [r6, #8]
13805		- cmp r2, r9
13806		- bcs .L2388
13807		- ldrh r1, [r4, #4]
13808		- ldrh r0, [r6]
13809		- cmp r0, r1
13810		- ldreq r1, [r10, #-1272]
13811		- streq r1, [r7, r2, asl #2]
13812		-.L2388:
13813		- add fp, fp, #1
13814		- b .L2414
13815		-.L2386:
13816		- ldr r3, [sp, #4]
13817		- add r3, r3, #1
13818		- str r3, [sp, #4]
13819		- b .L2374
13820		-.L2381:
13821		- mov r0, r4
13822		- bl ftl_map_blk_gc
13823		- mov r0, r4
13824		- bl ftl_map_blk_gc
13825		- mov r0, #0
13826		- add sp, sp, #28
13827		- @ sp needed
13828		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
13829		-.L2417:
	14099	+ beq .L2330
	14100	+ ldrh r2, [r7, #8]
	14101	+ cmp fp, r2
	14102	+ bls .L2330
	14103	+ ldrh ip, [r7]
	14104	+ ldrh r0, [r4, #4]
	14105	+ cmp ip, r0
	14106	+ ldreq r1, [r1, #-1272]
	14107	+ ldreq r3, [sp, #4]
	14108	+ streq r1, [r3, r2, lsl #2]
	14109	+.L2330:
	14110	+ add r8, r8, #1
	14111	+ b .L2328
	14112	+.L2327:
	14113	+ ldr r3, [r5, #-1472]
	14114	+ ldr r0, [sp, #20]
	14115	+ str r3, [r5, #-1268]
	14116	+ add r3, r10, r2
	14117	+ str r3, [sp, #16]
	14118	+ ldr r3, .L2367+12
	14119	+ ldrh r2, [r10, r2]
	14120	+ ldrh r3, [r3]
	14121	+ sub r3, r3, #1
	14122	+ orr r3, r3, r2, lsl #10
	14123	+ mov r2, #1
	14124	+ mov r1, r2
	14125	+ str r3, [r5, #-1272]
	14126	+ bl FlashReadPages
	14127	+ ldr r3, [r5, #-1276]
	14128	+ cmn r3, #1
	14129	+ beq .L2347
	14130	+ ldrh r2, [r7]
	14131	+ ldrh r3, [r4, #4]
	14132	+ cmp r2, r3
	14133	+ bne .L2347
	14134	+ ldrh r2, [r7, #8]
	14135	+ movw r3, #64245
	14136	+ cmp r2, r3
	14137	+ beq .L2335
	14138	+.L2347:
	14139	+ mov r9, #0
	14140	+.L2336:
	14141	+ ldr r2, .L2367+12
	14142	+ sxth r3, r9
	14143	+ ldrh r2, [r2]
	14144	+ cmp r3, r2
	14145	+ bge .L2343
	14146	+ ldr r2, [sp, #16]
	14147	+ ldrh r2, [r2]
	14148	+ orr r3, r3, r2, lsl #10
	14149	+ mov r2, #1
	14150	+ mov r1, r2
	14151	+ str r3, [r8, #-1272]
	14152	+ ldr r3, .L2367+8
	14153	+ mov r0, r3
	14154	+ str r3, [sp, #28]
	14155	+ bl FlashReadPages
	14156	+ ldr r2, .L2367+4
	14157	+ ldrb r2, [r2, #36] @ zero_extendqisi2
	14158	+ cmp r2, #0
	14159	+ beq .L2340
	14160	+ ldr r2, [r8, #-1264]
	14161	+ ldr r2, [r2, #12]
	14162	+ cmp r2, #0
	14163	+ str r2, [sp, #24]
	14164	+ beq .L2340
	14165	+ ldr r3, [sp, #28]
	14166	+ ldr r0, [r8, #-1268]
	14167	+ sub r3, r3, #380
	14168	+ ldrh r1, [r3]
	14169	+ bl js_hash
	14170	+ ldr r2, [sp, #24]
	14171	+ cmp r2, r0
	14172	+ mvnne r3, #0
	14173	+ strne r3, [r8, #-1276]
	14174	+.L2340:
	14175	+ ldr r3, [r8, #-1276]
	14176	+ cmn r3, #1
	14177	+ beq .L2341
	14178	+ ldrh r3, [r7, #8]
	14179	+ cmp fp, r3
	14180	+ bls .L2341
	14181	+ ldrh r1, [r7]
	14182	+ ldrh r2, [r4, #4]
	14183	+ cmp r1, r2
	14184	+ ldreq r2, [r8, #-1272]
	14185	+ ldreq r1, [sp, #4]
	14186	+ streq r2, [r1, r3, lsl #2]
	14187	+.L2341:
	14188	+ add r9, r9, #1
	14189	+ b .L2336
	14190	+.L2335:
	14191	+ mov r1, #0
	14192	+ mov ip, #4
	14193	+.L2337:
	14194	+ ldr r2, .L2367+12
	14195	+ sxth r3, r1
	14196	+ ldrh r2, [r2]
	14197	+ sub r2, r2, #1
	14198	+ cmp r3, r2
	14199	+ blt .L2339
	14200	+.L2343:
	14201	+ add r6, r6, #1
	14202	+ b .L2326
	14203	+.L2339:
	14204	+ ldr r0, [r8, #-1472]
	14205	+ add r1, r1, #1
	14206	+ ldr r2, [r0, r3, lsl #3]
	14207	+ uxth lr, r2
	14208	+ cmp fp, lr
	14209	+ addhi r3, ip, r3, lsl #3
	14210	+ movhi r2, lr
	14211	+ ldrhi r3, [r0, r3]
	14212	+ ldrhi r0, [sp, #4]
	14213	+ strhi r3, [r0, r2, lsl #2]
	14214	+ b .L2337
	14215	+.L2368:
13830	14216	.align 2
13831		-.L2416:
	14217	+.L2367:
13832	14218	.word .LANCHOR2
13833		- .word .LANCHOR2-1276
13834	14219	.word .LANCHOR0
13835		- .word .LANCHOR2-1658
	14220	+ .word .LANCHOR2-1276
13836	14221	.word .LANCHOR2-1664
13837		- .word .LANCHOR2-1666
13838	14222	.fnend
13839	14223	.size FtlMapTblRecovery, .-FtlMapTblRecovery
13840	14224	.align 2
13841	14225	.global FtlLoadVonderInfo
	14226	+ .syntax unified
	14227	+ .arm
	14228	+ .fpu softvfp
13842	14229	.type FtlLoadVonderInfo, %function
13843	14230	FtlLoadVonderInfo:
13844	14231	.fnstart
13845	14232	@ args = 0, pretend = 0, frame = 0
13846	14233	@ frame_needed = 0, uses_anonymous_args = 0
13847		- stmfd sp!, {r3, lr}
13848		- .save {r3, lr}
13849		- ldr r3, .L2420
13850		- sub r2, r3, #1648
13851		- add r0, r3, #1072
13852		- add r0, r0, #4
13853		- ldrh r2, [r2]
13854		- strh r2, [r0, #10] @ movhi
13855		- ldr r2, .L2420+4
13856		- strh r2, [r0, #4] @ movhi
13857		- sub r2, r3, #1280
13858		- ldrh r2, [r2, #-8]
13859		- strh r2, [r0, #8] @ movhi
	14234	+ ldr r3, .L2371
	14235	+ push {r4, lr}
	14236	+ .save {r4, lr}
13860	14237	sub r2, r3, #1632
13861		- ldrh r2, [r2, #-14]
	14238	+ add r0, r3, #1072
	14239	+ ldrh r1, [r2, #-12]
	14240	+ add r0, r0, #4
	14241	+ ldrh r2, [r2, #-10]
	14242	+ strh r1, [r0, #10] @ movhi
13862	14243	strh r2, [r0, #6] @ movhi
13863	14244	ldr r2, [r3, #-1392]
	14245	+ ldr r1, .L2371+4
13864	14246	str r2, [r3, #1088]
13865	14247	ldr r2, [r3, #-1384]
	14248	+ strh r1, [r0, #4] @ movhi
	14249	+ sub r1, r3, #1280
	14250	+ ldrh r1, [r1, #-8]
13866	14251	str r2, [r3, #1092]
13867	14252	ldr r2, [r3, #-1388]
	14253	+ strh r1, [r0, #8] @ movhi
13868	14254	str r2, [r3, #1096]
13869	14255	ldr r2, [r3, #-1380]
13870	14256	str r2, [r3, #1100]
13871	14257	bl FtlMapTblRecovery
13872	14258	mov r0, #0
13873		- ldmfd sp!, {r3, pc}
13874		-.L2421:
	14259	+ pop {r4, pc}
	14260	+.L2372:
13875	14261	.align 2
13876		-.L2420:
	14262	+.L2371:
13877	14263	.word .LANCHOR2
13878	14264	.word -3962
13879	14265	.fnend
13880	14266	.size FtlLoadVonderInfo, .-FtlLoadVonderInfo
13881	14267	.align 2
13882	14268	.global FtlL2PDataInit
	14269	+ .syntax unified
	14270	+ .arm
	14271	+ .fpu softvfp
13883	14272	.type FtlL2PDataInit, %function
13884	14273	FtlL2PDataInit:
13885	14274	.fnstart
13886	14275	@ args = 0, pretend = 0, frame = 0
13887	14276	@ frame_needed = 0, uses_anonymous_args = 0
13888		- stmfd sp!, {r4, r5, r6, r7, r8, lr}
	14277	+ push {r4, r5, r6, r7, r8, lr}
13889	14278	.save {r4, r5, r6, r7, r8, lr}
13890	14279	mov r1, #0
13891		- ldr r4, .L2427
13892		- mvn r6, #0
13893		- ldr r2, [r4, #-1640]
13894		- ldr r0, [r4, #-1400]
13895		- mov r2, r2, asl #1
	14280	+ ldr r4, .L2377
	14281	+ ldr r2, [r4, #-1636]
	14282	+ sub r6, r4, #1648
	14283	+ sub r5, r4, #1616
	14284	+ ldr r0, [r4, #-1396]
	14285	+ lsl r2, r2, #1
13896	14286	bl ftl_memset
13897		- sub r3, r4, #1648
13898		- sub r2, r4, #1616
	14287	+ ldrh r3, [r6, #-8]
13899	14288	mov r1, #255
13900		- ldrh r3, [r3, #-10]
13901		- ldrh r2, [r2, #-14]
	14289	+ ldrh r2, [r5, #-10]
13902	14290	ldr r0, [r4, #-1360]
13903	14291	mul r2, r2, r3
13904	14292	bl ftl_memset
13905		- ldr r0, .L2427+4
13906		- mov r1, #0
13907		- mov lr, #12
13908		- sub r7, r0, #28
13909		- mov r5, r1
13910		-.L2423:
13911		- ldrh r2, [r0]
13912		- add ip, r1, #1
13913		- uxth r1, r1
13914		- ldr r3, .L2427
13915		- cmp r2, r1
13916		- bls .L2426
13917		- mul r8, lr, r1
13918		- ldr r3, [r4, #-1364]
13919		- add r2, r3, r8
13920		- str r5, [r2, #4]
13921		- strh r6, [r3, r8] @ movhi
13922		- ldrh r2, [r7]
13923		- ldr r3, [r4, #-1364]
13924		- mul r2, r1, r2
13925		- add r3, r3, r8
13926		- ldr r1, [r4, #-1360]
13927		- bic r2, r2, #3
13928		- add r2, r1, r2
13929		- mov r1, ip
13930		- str r2, [r3, #8]
13931		- b .L2423
13932		-.L2426:
13933		- ldr r2, .L2427+8
13934		- movw r0, #1028
13935		- mvn r1, #0
13936		- strh r1, [r3, r0] @ movhi
13937		- strh r1, [r2, #2] @ movhi
13938		- ldr r1, [r3, #-1640]
13939		- strh r1, [r2, #10] @ movhi
13940		- ldr r1, .L2427+12
13941		- strh r1, [r2, #4] @ movhi
13942		- movw r1, #1144
13943		- ldrh r1, [r3, r1]
13944		- strh r1, [r2, #8] @ movhi
13945		- sub r1, r3, #1632
13946		- ldrh r1, [r1]
	14293	+ mov r2, #0
	14294	+ mov r3, r4
	14295	+ mov r0, r6
	14296	+ mov r1, r5
	14297	+ mov r4, #12
	14298	+ mov r5, r2
	14299	+ mvn r6, #0
	14300	+.L2374:
	14301	+ ldrh r7, [r1, #-10]
	14302	+ uxth ip, r2
	14303	+ add lr, r2, #1
	14304	+ cmp r7, ip
	14305	+ bhi .L2375
	14306	+ ldr r2, .L2377+4
	14307	+ mvn r0, #0
	14308	+ movw ip, #1028
	14309	+ ldrh r1, [r1, #-12]
	14310	+ strh r0, [r3, ip] @ movhi
	14311	+ strh r0, [r2, #2] @ movhi
	14312	+ ldr r0, [r3, #-1636]
13947	14313	strh r1, [r2, #6] @ movhi
13948		- ldr r2, [r3, #-1404]
	14314	+ strh r0, [r2, #10] @ movhi
	14315	+ ldr r0, .L2377+8
	14316	+ strh r0, [r2, #4] @ movhi
	14317	+ movw r0, #1144
	14318	+ ldrh r0, [r3, r0]
	14319	+ strh r0, [r2, #8] @ movhi
	14320	+ ldr r2, [r3, #-1400]
13949	14321	str r2, [r3, #1040]
13950	14322	ldr r2, [r3, #-1368]
13951	14323	str r2, [r3, #1044]
13952		- ldr r2, [r3, #-1400]
	14324	+ ldr r2, [r3, #-1396]
13953	14325	str r2, [r3, #1048]
13954	14326	ldr r2, [r3, #-1376]
13955	14327	str r2, [r3, #1052]
13956		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
13957		-.L2428:
	14328	+ pop {r4, r5, r6, r7, r8, pc}
	14329	+.L2375:
	14330	+ uxth r2, r2
	14331	+ ldr ip, [r3, #-1364]
	14332	+ mul r7, r4, r2
	14333	+ add r8, ip, r7
	14334	+ str r5, [r8, #4]
	14335	+ strh r6, [ip, r7] @ movhi
	14336	+ ldr ip, [r3, #-1364]
	14337	+ add ip, ip, r7
	14338	+ ldrh r7, [r0, #-8]
	14339	+ mul r2, r2, r7
	14340	+ ldr r7, [r3, #-1360]
	14341	+ bic r2, r2, #3
	14342	+ add r2, r7, r2
	14343	+ str r2, [ip, #8]
	14344	+ mov r2, lr
	14345	+ b .L2374
	14346	+.L2378:
13958	14347	.align 2
13959		-.L2427:
	14348	+.L2377:
13960	14349	.word .LANCHOR2
13961		- .word .LANCHOR2-1630
13962	14350	.word .LANCHOR2+1028
13963	14351	.word -3902
13964	14352	.fnend
13965	14353	.size FtlL2PDataInit, .-FtlL2PDataInit
13966	14354	.align 2
13967	14355	.global FtlLoadMapInfo
	14356	+ .syntax unified
	14357	+ .arm
	14358	+ .fpu softvfp
13968	14359	.type FtlLoadMapInfo, %function
13969	14360	FtlLoadMapInfo:
13970	14361	.fnstart
13971	14362	@ args = 0, pretend = 0, frame = 0
13972	14363	@ frame_needed = 0, uses_anonymous_args = 0
13973		- stmfd sp!, {r3, lr}
13974		- .save {r3, lr}
	14364	+ push {r4, lr}
	14365	+ .save {r4, lr}
13975	14366	bl FtlL2PDataInit
13976		- ldr r0, .L2431
	14367	+ ldr r0, .L2381
13977	14368	bl FtlMapTblRecovery
13978	14369	mov r0, #0
13979		- ldmfd sp!, {r3, pc}
13980		-.L2432:
	14370	+ pop {r4, pc}
	14371	+.L2382:
13981	14372	.align 2
13982		-.L2431:
	14373	+.L2381:
13983	14374	.word .LANCHOR2+1028
13984	14375	.fnend
13985	14376	.size FtlLoadMapInfo, .-FtlLoadMapInfo
13986	14377	.align 2
13987	14378	.global ftl_sb_update_avl_pages
	14379	+ .syntax unified
	14380	+ .arm
	14381	+ .fpu softvfp
13988	14382	.type ftl_sb_update_avl_pages, %function
13989	14383	ftl_sb_update_avl_pages:
13990	14384	.fnstart
13991	14385	@ args = 0, pretend = 0, frame = 0
13992	14386	@ frame_needed = 0, uses_anonymous_args = 0
13993	14387	mov r3, #0
	14388	+ push {r4, lr}
	14389	+ .save {r4, lr}
13994	14390	strh r3, [r0, #4] @ movhi
13995		- ldr r3, .L2443
13996		- stmfd sp!, {r4, r5, lr}
13997		- .save {r4, r5, lr}
13998	14391	movw r4, #65535
13999		- ldrh lr, [r3, #-8]
14000		- add r3, r2, #7
14001		- add r3, r0, r3, asl #1
14002		-.L2434:
	14392	+ ldr r3, .L2391
	14393	+ ldrh lr, [r3, #-4]
	14394	+ add r3, r0, r2, lsl #1
	14395	+ add r3, r3, #14
	14396	+.L2384:
14003	14397	cmp r2, lr
14004		- bcs .L2441
	14398	+ bcc .L2386
	14399	+ ldr r3, .L2391+4
	14400	+ add ip, r0, #16
	14401	+ movw r4, #65535
	14402	+ ldrh r3, [r3, #-2]
	14403	+ sub r3, r3, #1
	14404	+ sub r1, r3, r1
	14405	+ mov r3, #0
	14406	+ uxth r1, r1
	14407	+.L2387:
	14408	+ uxth r2, r3
	14409	+ cmp lr, r2
	14410	+ bhi .L2389
	14411	+ pop {r4, pc}
	14412	+.L2386:
14005	14413	ldrh ip, [r3, #2]!
14006	14414	add r2, r2, #1
14007		- cmp ip, r4
14008	14415	uxth r2, r2
14009		- ldrneh ip, [r0, #4]
	14416	+ cmp ip, r4
	14417	+ ldrhne ip, [r0, #4]
14010	14418	addne ip, ip, #1
14011		- strneh ip, [r0, #4] @ movhi
14012		- b .L2434
14013		-.L2441:
14014		- ldr r3, .L2443+4
14015		- add ip, r0, #14
14016		- mov r2, #0
14017		- movw r5, #65535
14018		- ldrh r4, [r3, #-4]
14019		-.L2437:
14020		- uxth r3, r2
14021		- cmp r3, lr
14022		- bcs .L2442
14023		- ldrh r3, [ip, #2]!
14024		- add r2, r2, #1
14025		- cmp r3, r5
14026		- ldrneh r3, [r0, #4]
14027		- addne r3, r4, r3
14028		- subne r3, r3, #1
14029		- rsbne r3, r1, r3
14030		- strneh r3, [r0, #4] @ movhi
14031		- b .L2437
14032		-.L2442:
14033		- ldmfd sp!, {r4, r5, pc}
14034		-.L2444:
	14419	+ strhne ip, [r0, #4] @ movhi
	14420	+ b .L2384
	14421	+.L2389:
	14422	+ ldrh r2, [ip], #2
	14423	+ add r3, r3, #1
	14424	+ cmp r2, r4
	14425	+ ldrhne r2, [r0, #4]
	14426	+ addne r2, r1, r2
	14427	+ strhne r2, [r0, #4] @ movhi
	14428	+ b .L2387
	14429	+.L2392:
14035	14430	.align 2
14036		-.L2443:
	14431	+.L2391:
14037	14432	.word .LANCHOR2-1728
14038	14433	.word .LANCHOR2-1664
14039	14434	.fnend
14040	14435	.size ftl_sb_update_avl_pages, .-ftl_sb_update_avl_pages
14041	14436	.align 2
14042	14437	.global FtlReUsePrevPpa
	14438	+ .syntax unified
	14439	+ .arm
	14440	+ .fpu softvfp
14043	14441	.type FtlReUsePrevPpa, %function
14044	14442	FtlReUsePrevPpa:
14045	14443	.fnstart
14046	14444	@ args = 0, pretend = 0, frame = 8
14047	14445	@ frame_needed = 0, uses_anonymous_args = 0
14048		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
	14446	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
14049	14447	.save {r4, r5, r6, r7, r8, r9, lr}
14050	14448	.pad #12
14051	14449	mov r5, r0
	14450	+ ldr r6, .L2403
14052	14451	ubfx r0, r1, #10, #16
14053	14452	str r1, [sp, #4]
14054	14453	bl P2V_block_in_plane
14055		- ldr r6, .L2455
14056		- ldr r4, [r6, #-1408]
14057		- mov r7, r0, asl #1
14058		- ldrh r3, [r4, r7]
	14454	+ ldr r2, [r6, #-1404]
	14455	+ lsl r7, r0, #1
	14456	+ ldrh r3, [r2, r7]
14059	14457	cmp r3, #0
14060		- addne r3, r3, #1
14061		- strneh r3, [r4, r7] @ movhi
14062		- bne .L2447
	14458	+ bne .L2394
14063	14459	ldr r4, [r6, #876]
14064	14460	cmp r4, #0
14065		- beq .L2447
14066		- ldr r1, [r6, #-1356]
14067		- add r2, r6, #880
14068		- ldr lr, .L2455+4
14069		- movw r9, #65535
14070		- rsb r4, r1, r4
14071		- ldrh ip, [r2]
14072		- mov r8, r2
14073		- mov r4, r4, asr #1
14074		- mul r4, lr, r4
	14461	+ beq .L2395
	14462	+ ldr r2, [r6, #-1356]
	14463	+ add r8, r6, #880
	14464	+ ldr ip, .L2403+4
14075	14465	mov lr, #6
	14466	+ ldrh r1, [r8]
	14467	+ movw r9, #65535
	14468	+ sub r4, r4, r2
	14469	+ asr r4, r4, #1
	14470	+ mul r4, ip, r4
14076	14471	uxth r4, r4
14077		-.L2448:
14078		- uxth r2, r3
14079		- cmp r2, ip
14080		- bcs .L2447
	14472	+.L2396:
	14473	+ uxth ip, r3
	14474	+ cmp r1, ip
	14475	+ bls .L2395
14081	14476	cmp r4, r0
14082		- bne .L2449
	14477	+ bne .L2397
14083	14478	mov r1, r4
14084		- ldr r0, .L2455+8
	14479	+ ldr r0, .L2403+8
14085	14480	bl List_remove_node
14086	14481	ldrh r3, [r8]
14087	14482	mov r0, r4
14088	14483	sub r3, r3, #1
14089	14484	strh r3, [r8] @ movhi
14090	14485	bl INSERT_DATA_LIST
14091		- ldr r2, [r6, #-1408]
	14486	+ ldr r2, [r6, #-1404]
14092	14487	ldrh r3, [r2, r7]
	14488	+.L2394:
14093	14489	add r3, r3, #1
14094	14490	strh r3, [r2, r7] @ movhi
14095		- b .L2447
14096		-.L2449:
	14491	+ b .L2395
	14492	+.L2397:
14097	14493	mul r4, lr, r4
14098	14494	add r3, r3, #1
14099		- ldrh r4, [r1, r4]
	14495	+ ldrh r4, [r2, r4]
14100	14496	cmp r4, r9
14101		- bne .L2448
14102		-.L2447:
14103		- mov r0, r5
14104		- add r1, sp, #4
	14497	+ bne .L2396
	14498	+.L2395:
14105	14499	mov r2, #1
	14500	+ add r1, sp, #4
	14501	+ mov r0, r5
14106	14502	bl log2phys
14107	14503	add sp, sp, #12
14108	14504	@ sp needed
14109		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, pc}
14110		-.L2456:
	14505	+ pop {r4, r5, r6, r7, r8, r9, pc}
	14506	+.L2404:
14111	14507	.align 2
14112		-.L2455:
	14508	+.L2403:
14113	14509	.word .LANCHOR2
14114	14510	.word -1431655765
14115	14511	.word .LANCHOR2+876
..	..	@@ -14117,70 +14513,73 @@
14117	14513	.size FtlReUsePrevPpa, .-FtlReUsePrevPpa
14118	14514	.align 2
14119	14515	.global make_superblock
	14516	+ .syntax unified
	14517	+ .arm
	14518	+ .fpu softvfp
14120	14519	.type make_superblock, %function
14121	14520	make_superblock:
14122	14521	.fnstart
14123	14522	@ args = 0, pretend = 0, frame = 0
14124	14523	@ frame_needed = 0, uses_anonymous_args = 0
14125		- ldr r3, .L2471
14126		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
	14524	+ ldr r3, .L2418
	14525	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
14127	14526	.save {r4, r5, r6, r7, r8, r9, r10, lr}
14128		- add r6, r0, #16
14129		- ldrh r8, [r3, #-8]
14130		- add r7, r3, #20
14131	14527	mov r4, r0
	14528	+ add r7, r0, #16
14132	14529	mvn r9, #0
	14530	+ add r6, r3, #22
14133	14531	mov r5, #0
	14532	+ ldrh r8, [r3, #-4]
14134	14533	strh r5, [r0, #4] @ movhi
14135	14534	strb r5, [r0, #7]
14136		-.L2458:
	14535	+.L2406:
14137	14536	uxth r3, r5
14138		- cmp r3, r8
14139		- bcs .L2470
14140		- ldrb r0, [r7, r5] @ zero_extendqisi2
14141		- add r6, r6, #2
14142		- ldrh r1, [r4]
14143		- add r5, r5, #1
14144		- bl V2P_block
14145		- strh r9, [r6, #-2] @ movhi
14146		- mov r10, r0
14147		- bl FtlBbmIsBadBlock
14148		- cmp r0, #0
14149		- streqh r10, [r6, #-2] @ movhi
14150		- ldreqb r3, [r4, #7] @ zero_extendqisi2
14151		- addeq r3, r3, #1
14152		- streqb r3, [r4, #7]
14153		- b .L2458
14154		-.L2470:
14155		- ldr r2, .L2471+4
14156		- ldrb r1, [r4, #7] @ zero_extendqisi2
14157		- sub r3, r2, #1664
14158		- ldrh r3, [r3, #-4]
14159		- smulbb r3, r1, r3
	14537	+ cmp r8, r3
	14538	+ bhi .L2408
	14539	+ ldr r2, .L2418+4
	14540	+ ldrb r3, [r4, #7] @ zero_extendqisi2
	14541	+ sub r1, r2, #1664
	14542	+ ldrh r1, [r1, #-2]
	14543	+ smulbb r3, r3, r1
14160	14544	strh r3, [r4, #4] @ movhi
14161	14545	mov r3, #0
14162	14546	strb r3, [r4, #9]
14163		- ldr r3, [r2, #-1872]
	14547	+ ldr r3, [r2, #-1868]
14164	14548	cmp r3, #0
14165		- beq .L2461
	14549	+ beq .L2409
14166	14550	ldrh r3, [r4]
14167		- ldr r2, [r2, #-1416]
14168		- mov r3, r3, asl #1
	14551	+ ldr r2, [r2, #-1412]
	14552	+ lsl r3, r3, #1
14169	14553	ldrh r3, [r2, r3]
14170	14554	cmp r3, #79
14171	14555	movls r3, #1
14172		- strlsb r3, [r4, #9]
14173		-.L2461:
14174		- ldr r3, .L2471+8
	14556	+ strbls r3, [r4, #9]
	14557	+.L2409:
	14558	+ ldr r3, .L2418+8
14175	14559	mov r0, #0
14176		- ldrb r3, [r3] @ zero_extendqisi2
	14560	+ ldrb r3, [r3, #36] @ zero_extendqisi2
14177	14561	cmp r3, #0
14178	14562	movne r3, #1
14179		- strneb r3, [r4, #9]
14180		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
14181		-.L2472:
	14563	+ strbne r3, [r4, #9]
	14564	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	14565	+.L2408:
	14566	+ ldrb r0, [r6, r5] @ zero_extendqisi2
	14567	+ add r7, r7, #2
	14568	+ ldrh r1, [r4]
	14569	+ add r5, r5, #1
	14570	+ bl V2P_block
	14571	+ strh r9, [r7, #-2] @ movhi
	14572	+ mov r10, r0
	14573	+ bl FtlBbmIsBadBlock
	14574	+ cmp r0, #0
	14575	+ strheq r10, [r7, #-2] @ movhi
	14576	+ ldrbeq r3, [r4, #7] @ zero_extendqisi2
	14577	+ addeq r3, r3, #1
	14578	+ strbeq r3, [r4, #7]
	14579	+ b .L2406
	14580	+.L2419:
14182	14581	.align 2
14183		-.L2471:
	14582	+.L2418:
14184	14583	.word .LANCHOR2-1728
14185	14584	.word .LANCHOR2
14186	14585	.word .LANCHOR0
..	..	@@ -14188,538 +14587,553 @@
14188	14587	.size make_superblock, .-make_superblock
14189	14588	.align 2
14190	14589	.global FtlLoadSysInfo
	14590	+ .syntax unified
	14591	+ .arm
	14592	+ .fpu softvfp
14191	14593	.type FtlLoadSysInfo, %function
14192	14594	FtlLoadSysInfo:
14193	14595	.fnstart
14194		- @ args = 0, pretend = 0, frame = 16
	14596	+ @ args = 0, pretend = 0, frame = 8
14195	14597	@ frame_needed = 0, uses_anonymous_args = 0
14196		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	14598	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14197	14599	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14198	14600	mov r1, #0
14199		- ldr r4, .L2502
14200		- .pad #44
14201		- sub sp, sp, #44
14202		- movw r7, #1128
14203		- ldr r9, .L2502+4
14204		- sub r6, r4, #1728
14205		- ldr r3, [r4, #-1476]
14206		- ldrh r2, [r6]
14207		- ldr r0, [r4, #-1408]
	14601	+ ldr r4, .L2449
	14602	+ .pad #36
	14603	+ sub sp, sp, #36
	14604	+ movw r8, #1128
	14605	+ ldr r3, [r4, #-1472]
	14606	+ sub r6, r4, #1712
	14607	+ ldrh r2, [r6, #-12]
	14608	+ ldr r0, [r4, #-1404]
14208	14609	str r3, [r4, #-1268]
14209		- ldr r3, [r4, #-1444]
14210		- mov r2, r2, asl #1
	14610	+ ldr r3, [r4, #-1440]
	14611	+ lsl r2, r2, #1
14211	14612	str r3, [r4, #-1264]
14212	14613	bl ftl_memset
14213		- ldrh r0, [r4, r7]
	14614	+ ldrh r0, [r4, r8]
14214	14615	movw r3, #65535
14215	14616	cmp r0, r3
14216		- bne .L2474
14217		-.L2485:
	14617	+ bne .L2421
	14618	+.L2432:
14218	14619	mvn r0, #0
14219		- b .L2475
14220		-.L2474:
	14620	+.L2420:
	14621	+ add sp, sp, #36
	14622	+ @ sp needed
	14623	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	14624	+.L2421:
14221	14625	mov r1, #1
	14626	+ ldr r7, .L2449+4
14222	14627	bl FtlGetLastWrittenPage
14223		- ldrh r3, [r4, r7]
14224		- mov r7, r4
14225		- uxth r5, r0
14226		- str r3, [sp, #28]
	14628	+ ldrsh r10, [r4, r8]
	14629	+ sub r8, r4, #1264
	14630	+ sub r8, r8, #12
	14631	+ sxth r5, r0
14227	14632	add r0, r0, #1
14228		- strh r0, [r9, #2] @ movhi
14229		-.L2476:
14230		- sxth r3, r5
14231		- cmp r3, #0
14232		- blt .L2484
14233		- ldrsh fp, [sp, #28]
14234		- mov r1, #1
14235		- ldr r0, .L2502+8
14236		- mov r2, r1
14237		- orr r3, r3, fp, asl #10
	14633	+ strh r0, [r7, #2] @ movhi
	14634	+.L2423:
	14635	+ cmp r5, #0
	14636	+ ldr fp, .L2449+8
	14637	+ blt .L2431
	14638	+ orr r3, r5, r10, lsl #10
	14639	+ mov r2, #1
	14640	+ mov r1, r2
14238	14641	str r3, [r4, #-1272]
14239		- ldr r3, [r4, #-1476]
	14642	+ mov r0, r8
	14643	+ ldr r3, [r4, #-1472]
14240	14644	str r3, [r4, #-1268]
14241	14645	bl FlashReadPages
14242		- ldr r3, .L2502+12
14243		- ldrb r3, [r3] @ zero_extendqisi2
	14646	+ ldrb r3, [fp, #36] @ zero_extendqisi2
14244	14647	cmp r3, #0
14245		- beq .L2477
14246		- ldr r8, [r7, #-1264]
14247		- ldr r3, [r8, #12]
	14648	+ beq .L2424
	14649	+ ldr r9, [r4, #-1264]
	14650	+ ldr r3, [r9, #12]
14248	14651	cmp r3, #0
14249		- beq .L2477
14250		- ldr r2, [r7, #-1268]
14251		- ldr r10, .L2502+16
14252		- str r3, [sp, #36]
14253		- mov r0, r2
14254		- str r2, [sp, #32]
14255		- ldrh r1, [r10]
14256		- bl js_hash
14257		- ldr r3, [sp, #36]
14258		- cmp r3, r0
14259		- beq .L2477
14260		- cmp r5, #0
14261		- ldr r2, [sp, #32]
14262		- bne .L2478
14263		- ldrh r1, [r9, #4]
14264		- ldr ip, .L2502+4
14265		- cmp fp, r1
14266		- beq .L2478
14267		- ldr r0, [r8]
14268		- ldrh r1, [ip]
14269		- str ip, [sp, #28]
14270		- str r0, [sp]
14271		- ldr r0, [r8, #4]
14272		- str r0, [sp, #4]
14273		- ldr r0, [r8, #8]
14274		- str r3, [sp, #12]
14275		- str r0, [sp, #8]
14276		- ldr r3, [r2]
14277		- ldr r0, .L2502+20
14278		- str r3, [sp, #16]
14279		- ldr r3, [r7, #-1272]
14280		- ldr r2, [r7, #-1276]
14281		- bl printk
14282		- ldrh r5, [r10, #-8]
14283		- ldr ip, [sp, #28]
14284		- ldrh r3, [ip, #4]
14285	14652	str r3, [sp, #28]
14286		- b .L2480
14287		-.L2478:
	14653	+ beq .L2424
	14654	+ ldr r2, [r4, #-1268]
	14655	+ sub r1, r8, #380
	14656	+ ldrh r1, [r1]
	14657	+ mov r0, r2
	14658	+ str r2, [sp, #24]
	14659	+ bl js_hash
	14660	+ ldr r3, [sp, #28]
	14661	+ cmp r3, r0
	14662	+ beq .L2424
	14663	+ cmp r5, #0
	14664	+ bne .L2425
	14665	+ ldrh r1, [r7, #4]
	14666	+ ldr r2, [sp, #24]
	14667	+ cmp r10, r1
	14668	+ beq .L2425
	14669	+ ldr r2, [r2]
	14670	+ str r3, [sp, #12]
	14671	+ ldrh r1, [r7]
	14672	+ str r2, [sp, #16]
	14673	+ ldr r3, [r9, #8]
	14674	+ ldr r2, [r4, #-1276]
	14675	+ ldr r0, .L2449+12
	14676	+ str r3, [sp, #8]
	14677	+ ldr r3, [r9, #4]
	14678	+ str r3, [sp, #4]
	14679	+ ldr r3, [r9]
	14680	+ str r3, [sp]
	14681	+ ldr r3, [r4, #-1272]
	14682	+ bl printk
	14683	+ sub r3, r8, #388
	14684	+ ldrsh r10, [r7, #4]
	14685	+ ldrh r5, [r3]
	14686	+.L2427:
	14687	+ sub r5, r5, #1
	14688	+ sxth r5, r5
	14689	+ b .L2423
	14690	+.L2425:
14288	14691	mvn r3, #0
14289	14692	str r3, [r4, #-1276]
14290		-.L2477:
	14693	+.L2424:
14291	14694	ldr r3, [r4, #-1276]
14292	14695	cmn r3, #1
14293		- beq .L2480
14294		- ldr r3, [r7, #-1476]
14295		- ldr r2, .L2502+24
	14696	+ beq .L2427
	14697	+ ldr r3, [r4, #-1472]
	14698	+ ldr r2, .L2449+16
14296	14699	ldr r3, [r3]
14297	14700	cmp r3, r2
14298		- bne .L2480
14299		- ldr r3, [r7, #-1444]
	14701	+ bne .L2427
	14702	+ ldr r3, [r4, #-1440]
14300	14703	ldrh r2, [r3]
14301	14704	movw r3, #61604
14302	14705	cmp r2, r3
14303		- bne .L2480
14304		-.L2484:
14305		- ldr r5, .L2502
	14706	+ bne .L2427
	14707	+.L2431:
14306	14708	mov r2, #48
14307	14709	ldr r1, [r4, #-1268]
14308		- add r0, r5, #816
14309		- sub r7, r5, #1728
	14710	+ ldr r0, .L2449+20
14310	14711	bl ftl_memcpy
14311		- ldrh r2, [r6]
	14712	+ ldrh r2, [r6, #-12]
14312	14713	ldr r1, [r4, #-1268]
14313		- ldr r0, [r4, #-1408]
	14714	+ ldr r0, [r4, #-1404]
	14715	+ lsl r2, r2, #1
14314	14716	add r1, r1, #48
14315		- mov r2, r2, asl #1
14316	14717	bl ftl_memcpy
14317		- ldrh r2, [r6]
14318		- ldr r1, [r4, #-1268]
14319		- ldr r0, [r4, #-1396]
14320		- mov r3, r2, asl #1
14321		- mov r2, r2, lsr #3
14322		- add r3, r3, #51
	14718	+ ldrh r1, [r6, #-12]
	14719	+ ldr r3, [r4, #-1268]
	14720	+ ldr r0, [fp, #32]
	14721	+ lsr r2, r1, #3
	14722	+ lsl r1, r1, #1
	14723	+ add r1, r1, #51
14323	14724	add r2, r2, #4
14324		- bic r3, r3, #3
14325		- add r1, r1, r3
	14725	+ bic r1, r1, #3
	14726	+ add r1, r3, r1
14326	14727	bl ftl_memcpy
14327		- sub r3, r5, #1616
14328		- ldrh r3, [r3, #-12]
14329		- cmp r3, #0
14330		- beq .L2482
14331		- ldrh r2, [r7]
14332		- ldr r1, [r5, #-1268]
14333		- ldr r0, [r5, #-1372]
14334		- mov r3, r2, lsr #3
14335		- add r3, r3, r2, asl #1
14336		- sub r2, r5, #1632
	14728	+ ldr r3, .L2449+24
	14729	+ ldrh r2, [r3, #-8]
	14730	+ cmp r2, #0
	14731	+ beq .L2429
	14732	+ ldrh r1, [r6, #-12]
	14733	+ ldrh r2, [r3, #-12]
	14734	+ ldr r0, [r4, #-1372]
	14735	+ lsr r3, r1, #3
	14736	+ lsl r2, r2, #2
	14737	+ add r3, r3, r1, lsl #1
	14738	+ ldr r1, [r4, #-1268]
14337	14739	add r3, r3, #52
14338		- ldrh r2, [r2]
14339	14740	ubfx r3, r3, #2, #14
14340		- add r1, r1, r3, asl #2
14341		- mov r2, r2, asl #2
	14741	+ add r1, r1, r3, lsl #2
14342	14742	bl ftl_memcpy
14343		- b .L2482
14344		-.L2480:
14345		- sub r5, r5, #1
14346		- uxth r5, r5
14347		- b .L2476
14348		-.L2482:
	14743	+.L2429:
14349	14744	ldr r2, [r4, #816]
14350		- ldr r3, .L2502+24
14351		- ldr r5, .L2502
	14745	+ ldr r3, .L2449+16
14352	14746	cmp r2, r3
14353		- bne .L2485
14354		- sub r2, r5, #1712
14355		- add r8, r5, #816
14356		- ldrb r1, [r5, #826] @ zero_extendqisi2
14357		- ldrh r2, [r2, #-2]
14358		- ldrh r3, [r8, #8]
14359		- cmp r1, r2
14360		- strh r3, [r9, #6] @ movhi
14361		- bne .L2485
14362		- sub r2, r5, #1664
14363		- sub r1, r5, #1648
14364		- ldr r7, .L2502+28
14365		- ldrh r2, [r2, #-4]
14366		- ldrh r1, [r1, #-14]
14367		- str r3, [r7, #1156]
14368		- mul r2, r3, r2
14369		- str r2, [r5, #-1284]
14370		- mul r2, r1, r2
14371		- ldrh r1, [r6, #-8]
14372		- mov r6, #0
14373		- str r2, [r5, #-2740]
14374		- ldr r2, .L2502+32
14375		- ldrh r0, [r2, #6]
14376		- ldr r2, [r5, #-1724]
14377		- rsb r0, r0, r2
14378		- rsb r0, r3, r0
14379		- bl __aeabi_uidiv
14380		- movw r3, #1160
14381		- ldrh r1, [r8, #14]
14382		- add r2, r5, #884
14383		- strb r6, [r7, #1170]
14384		- strb r6, [r7, #1172]
14385		- strh r1, [r2] @ movhi
14386		- str r6, [r5, #-1608]
14387		- strh r0, [r7, r3] @ movhi
14388		- ldrh r3, [r8, #16]
14389		- mov r0, r3, lsr #6
14390		- and r3, r3, #63
14391		- strb r3, [r5, #890]
14392		- ldrb r3, [r5, #827] @ zero_extendqisi2
14393		- strh r0, [r2, #2] @ movhi
14394		- mvn r2, #0
14395		- strb r3, [r5, #892]
14396		- movw r3, #1164
14397		- strh r2, [r7, r3] @ movhi
14398		- ldr r3, .L2502+36
14399		- ldrh r2, [r8, #18]
14400		- strh r6, [r3, #2] @ movhi
14401		- add r3, r5, #932
14402		- strh r2, [r3] @ movhi
14403		- ldrh r2, [r8, #20]
14404		- mov r0, r2, lsr #6
14405		- and r2, r2, #63
14406		- strb r2, [r5, #938]
14407		- ldrb r2, [r5, #828] @ zero_extendqisi2
14408		- strh r0, [r3, #2] @ movhi
14409		- ldrh r0, [r8, #22]
14410		- ldrh r8, [r8, #24]
14411		- strb r2, [r5, #940]
14412		- add r2, r5, #980
14413		- strh r0, [r2] @ movhi
14414		- mov r0, r8, lsr #6
14415		- strh r0, [r2, #2] @ movhi
14416		- and r8, r8, #63
14417		- ldrb r0, [r5, #829] @ zero_extendqisi2
14418		- mov r9, r2
14419		- strb r8, [r5, #986]
14420		- strb r0, [r5, #988]
14421		- str r6, [r5, #-1604]
14422		- ldr r0, [r5, #848]
14423		- ldr r2, [r4, #-1612]
14424		- ldr ip, [r5, #-1616]
14425		- str r0, [r5, #-1584]
14426		- ldr r0, [r5, #856]
14427		- str r6, [r5, #-1588]
14428		- str r6, [r5, #-1592]
14429		- cmp r0, ip
14430		- str r6, [r5, #-1580]
14431		- str r6, [r5, #-1572]
14432		- str r6, [r5, #-1596]
14433		- mov r6, r3
14434		- ldr r3, [r4, #852]
14435		- strhi r0, [r5, #-1616]
14436		- cmp r3, r2
14437		- ldrhi r2, .L2502
14438		- strhi r3, [r2, #-1612]
14439		- movw r3, #65535
	14747	+ bne .L2432
	14748	+ ldr r5, .L2449+20
	14749	+ ldrb r1, [r4, #826] @ zero_extendqisi2
	14750	+ sub r3, r5, #2512
	14751	+ ldrh r2, [r5, #8]
	14752	+ ldrh r3, [r3, #-14]
	14753	+ strh r2, [r7, #6] @ movhi
14440	14754	cmp r1, r3
14441		- beq .L2488
14442		- ldr r0, .L2502+40
	14755	+ bne .L2432
	14756	+ sub r1, r5, #2480
	14757	+ sub r0, r5, #2464
	14758	+ ldrh r3, [r1, #-2]
	14759	+ add r1, r1, #316
	14760	+ ldrh r0, [r0, #-12]
	14761	+ add r6, r5, #336
	14762	+ str r2, [r4, #1148]
	14763	+ mul r3, r2, r3
	14764	+ str r3, [r4, #-1284]
	14765	+ mul r3, r3, r0
	14766	+ ldr r0, [r4, #-1720]
	14767	+ str r3, [r4, #-2736]
	14768	+ ldrh r3, [r1, #6]
	14769	+ sub r0, r0, r3
	14770	+ sub r3, r5, #2544
	14771	+ ldrh r1, [r3, #-4]
	14772	+ sub r0, r0, r2
	14773	+ bl __aeabi_uidiv
	14774	+ ldrh r3, [r5, #16]
	14775	+ mov r2, r5
	14776	+ ldrh ip, [r5, #14]
	14777	+ strh r0, [r6] @ movhi
	14778	+ lsr r1, r3, #6
	14779	+ and r3, r3, #63
	14780	+ strb r3, [r4, #890]
	14781	+ ldrb r3, [r4, #827] @ zero_extendqisi2
	14782	+ strh ip, [r2, #68]! @ movhi
	14783	+ strh r1, [r2, #2] @ movhi
	14784	+ mvn r1, #0
	14785	+ strb r3, [r4, #892]
	14786	+ movw r3, #1156
	14787	+ strh r1, [r4, r3] @ movhi
	14788	+ add r2, r5, #340
	14789	+ ldrh r1, [r5, #18]
	14790	+ mov r3, #0
	14791	+ strh r3, [r2, #2] @ movhi
	14792	+ mov r2, r5
	14793	+ strb r3, [r4, #1162]
	14794	+ strh r1, [r2, #116]! @ movhi
	14795	+ ldrh r1, [r5, #20]
	14796	+ strb r3, [r4, #1164]
	14797	+ lsr r0, r1, #6
	14798	+ and r1, r1, #63
	14799	+ strb r1, [r4, #938]
	14800	+ ldrb r1, [r4, #828] @ zero_extendqisi2
	14801	+ strh r0, [r2, #2] @ movhi
	14802	+ ldrh r0, [r5, #22]
	14803	+ strb r1, [r4, #940]
	14804	+ mov r1, r5
	14805	+ strh r0, [r1, #164]! @ movhi
	14806	+ mov r6, r1
	14807	+ ldrh r0, [r5, #24]
	14808	+ mov r5, r2
	14809	+ lsr lr, r0, #6
	14810	+ and r0, r0, #63
	14811	+ strb r0, [r4, #986]
	14812	+ ldrb r0, [r4, #829] @ zero_extendqisi2
	14813	+ strh lr, [r1, #2] @ movhi
	14814	+ strb r0, [r4, #988]
	14815	+ str r3, [r4, #-1604]
	14816	+ ldr r0, [r4, #848]
	14817	+ str r3, [r4, #-1600]
	14818	+ str r3, [r4, #-1584]
	14819	+ str r3, [r4, #-1588]
	14820	+ str r0, [r4, #-1580]
	14821	+ str r3, [r4, #-1576]
	14822	+ ldr r0, [r4, #-1612]
	14823	+ str r3, [r4, #-1568]
	14824	+ str r3, [r4, #-1592]
	14825	+ ldr r3, [r4, #856]
	14826	+ ldr r2, [r4, #-1608]
	14827	+ cmp r3, r0
	14828	+ strhi r3, [r4, #-1612]
	14829	+ ldr r3, [r4, #852]
	14830	+ cmp r3, r2
	14831	+ strhi r3, [r4, #-1608]
	14832	+ movw r3, #65535
	14833	+ cmp ip, r3
	14834	+ beq .L2435
	14835	+ ldr r0, .L2449+28
14443	14836	bl make_superblock
14444		-.L2488:
	14837	+.L2435:
	14838	+ ldrh r2, [r5]
	14839	+ movw r3, #65535
	14840	+ cmp r2, r3
	14841	+ beq .L2436
	14842	+ ldr r0, .L2449+32
	14843	+ bl make_superblock
	14844	+.L2436:
14445	14845	ldrh r2, [r6]
14446	14846	movw r3, #65535
14447	14847	cmp r2, r3
14448		- beq .L2489
14449		- ldr r0, .L2502+44
	14848	+ beq .L2437
	14849	+ ldr r0, .L2449+36
14450	14850	bl make_superblock
14451		-.L2489:
14452		- ldrh r2, [r9]
	14851	+.L2437:
	14852	+ movw r3, #1156
	14853	+ ldrh r2, [r4, r3]
14453	14854	movw r3, #65535
14454	14855	cmp r2, r3
14455		- beq .L2490
14456		- ldr r0, .L2502+48
	14856	+ beq .L2438
	14857	+ ldr r0, .L2449+40
14457	14858	bl make_superblock
14458		-.L2490:
14459		- movw r3, #1164
14460		- ldrh r2, [r7, r3]
14461		- movw r3, #65535
14462		- cmp r2, r3
14463		- beq .L2491
14464		- ldr r0, .L2502+36
14465		- bl make_superblock
14466		-.L2491:
	14859	+.L2438:
14467	14860	mov r0, #0
14468		-.L2475:
14469		- add sp, sp, #44
14470		- @ sp needed
14471		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
14472		-.L2503:
	14861	+ b .L2420
	14862	+.L2450:
14473	14863	.align 2
14474		-.L2502:
	14864	+.L2449:
14475	14865	.word .LANCHOR2
14476	14866	.word .LANCHOR2+1128
14477		- .word .LANCHOR2-1276
14478	14867	.word .LANCHOR0
14479		- .word .LANCHOR2-1658
14480	14868	.word .LC64
14481	14869	.word 1179929683
14482		- .word .LANCHOR4
14483		- .word .LANCHOR2-1348
14484		- .word .LANCHOR4+1164
	14870	+ .word .LANCHOR2+816
	14871	+ .word .LANCHOR2-1616
14485	14872	.word .LANCHOR2+884
14486	14873	.word .LANCHOR2+932
14487	14874	.word .LANCHOR2+980
	14875	+ .word .LANCHOR2+1156
14488	14876	.fnend
14489	14877	.size FtlLoadSysInfo, .-FtlLoadSysInfo
14490	14878	.align 2
14491	14879	.global FtlDumpBlockInfo
	14880	+ .syntax unified
	14881	+ .arm
	14882	+ .fpu softvfp
14492	14883	.type FtlDumpBlockInfo, %function
14493	14884	FtlDumpBlockInfo:
14494	14885	.fnstart
14495	14886	@ args = 0, pretend = 0, frame = 72
14496	14887	@ frame_needed = 0, uses_anonymous_args = 0
14497		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	14888	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14498	14889	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14499	14890	ubfx r0, r0, #10, #16
	14891	+ ldr r7, .L2463
14500	14892	.pad #100
14501	14893	sub sp, sp, #100
14502		- mov r4, r1
	14894	+ mov r8, r1
14503	14895	bl P2V_block_in_plane
14504		- ldr r7, .L2518
14505		- ldr r1, .L2518+4
14506	14896	sub r5, r7, #1664
14507		- ldrh r9, [r5, #-4]
14508	14897	mov r6, r0
14509		- ldr r0, .L2518+8
	14898	+ ldr r1, .L2463+4
	14899	+ ldr r0, .L2463+8
	14900	+ ldrh r9, [r5, #-2]
14510	14901	bl printk
14511		- ldr r2, [r7, #-1408]
14512		- mov r3, r6, asl #1
	14902	+ ldr r2, [r7, #-1404]
	14903	+ lsl r3, r6, #1
14513	14904	mov r1, r6
14514		- ldr r0, .L2518+12
	14905	+ ldr r0, .L2463+12
14515	14906	ldrh r2, [r2, r3]
14516	14907	bl printk
14517	14908	add r0, sp, #96
14518	14909	strh r6, [r0, #-48]! @ movhi
14519	14910	bl make_superblock
14520		- ldrb r2, [r7, #-2744] @ zero_extendqisi2
14521		- clz r3, r4
14522		- cmp r2, #0
14523		- mov r3, r3, lsr #5
14524		- moveq r3, #0
	14911	+ ldrb r4, [r7, #-2740] @ zero_extendqisi2
	14912	+ str r7, [sp, #44]
	14913	+ adds r3, r4, #0
	14914	+ movne r3, #1
	14915	+ cmp r8, #0
	14916	+ movne r3, #0
14525	14917	cmp r3, #0
14526	14918	moveq r4, r3
14527		- str r7, [sp, #44]
14528		- beq .L2505
	14919	+ beq .L2452
14529	14920	mov r0, r6
14530	14921	bl ftl_get_blk_mode
14531	14922	cmp r0, #1
14532	14923	mov r4, r0
14533		- ldreqh r9, [r5, #-2]
14534		-.L2505:
14535		- ldr r0, .L2518+16
14536		- mov r1, r4
14537		- mov r2, r9
14538		- ldrh r3, [r5, #-4]
14539		- bl printk
14540		- ldr r8, .L2518
	14924	+ ldrheq r9, [r5]
	14925	+.L2452:
	14926	+ ldr r7, .L2463
14541	14927	mov r6, #0
14542		-.L2506:
14543		- ldr r3, .L2518+20
14544		- mov r2, #0
14545		- add r0, sp, #62
14546		- mov r5, r2
14547		- movw lr, #65535
14548	14928	mov r10, #36
14549		- ldrh r3, [r3]
14550		- mov r7, r3
14551		- ldr r3, [r8, #-1504]
14552		- str r3, [sp, #28]
14553		- ldr r3, [r8, #-1464]
14554		- str r3, [sp, #32]
14555		- ldr r3, .L2518+24
14556		- ldrh r3, [r3]
14557		- str r3, [sp, #36]
14558		- ldr r3, [r8, #-1436]
14559		- str r3, [sp, #40]
14560		- ldr r3, .L2518+28
14561		- ldrh ip, [r3]
14562		-.L2507:
14563		- uxth r3, r2
14564		- cmp r3, r7
14565		- bcs .L2516
14566		- ldrh r3, [r0, #2]!
14567		- cmp r3, lr
14568		- beq .L2508
14569		- ldr r1, [sp, #28]
14570		- orr r3, r6, r3, asl #10
14571		- mla r1, r10, r5, r1
14572		- str r3, [r1, #4]
14573		- ldr r3, [sp, #36]
14574		- mul r3, r3, r5
14575		- add fp, r3, #3
14576		- cmp r3, #0
14577		- movlt r3, fp
14578		- ldr fp, [sp, #32]
14579		- bic r3, r3, #3
14580		- add r3, fp, r3
14581		- str r3, [r1, #8]
14582		- mul r3, ip, r5
14583		- add r5, r5, #1
14584		- uxth r5, r5
14585		- add fp, r3, #3
14586		- cmp r3, #0
14587		- movlt r3, fp
14588		- ldr fp, [sp, #40]
14589		- bic r3, r3, #3
14590		- add r3, fp, r3
14591		- str r3, [r1, #12]
14592		-.L2508:
14593		- add r2, r2, #1
14594		- b .L2507
14595		-.L2516:
14596		- ldr r0, [r8, #-1504]
14597		- mov r1, r5
14598		- mov r2, r4
14599		- mov r10, #0
14600		- bl FlashReadPages
14601		- mov fp, #36
14602		-.L2510:
14603		- uxth r3, r10
14604		- cmp r3, r5
14605		- bcs .L2517
14606		- ldr r3, [sp, #44]
14607		- mul r2, fp, r10
14608		- ldrh r1, [sp, #48]
14609		- ldr lr, [r3, #-1504]
14610		- add r10, r10, #1
14611		- add ip, lr, r2
14612		- ldr r3, [ip, #12]
14613		- ldr r0, [ip, #8]
14614		- ldr r7, [r3]
14615		- str r7, [sp]
14616		- ldr r7, [r3, #4]
14617		- str r7, [sp, #4]
14618		- ldr r7, [r3, #8]
14619		- str r7, [sp, #8]
14620		- ldr r3, [r3, #12]
14621		- str r3, [sp, #12]
14622		- ldr r3, [r0]
14623		- str r3, [sp, #16]
14624		- ldr r3, [r0, #4]
14625		- ldr r0, .L2518+32
14626		- str r3, [sp, #20]
14627		- ldr r2, [lr, r2]
14628		- ldr r3, [ip, #4]
	14929	+ ldrh r3, [r5, #-2]
	14930	+ mov r2, r9
	14931	+ mov r1, r4
	14932	+ ldr r0, .L2463+16
14629	14933	bl printk
14630		- b .L2510
14631		-.L2517:
	14934	+.L2453:
	14935	+ ldr r3, .L2463+20
	14936	+ add ip, sp, #62
	14937	+ ldr r0, [r7, #-1500]
	14938	+ movw lr, #65535
	14939	+ ldrh r3, [r3, #-4]
	14940	+ str r3, [sp, #28]
	14941	+ ldr r3, [r7, #-1460]
	14942	+ str r3, [sp, #32]
	14943	+ ldr r3, .L2463+24
	14944	+ ldrh r2, [r3, #-8]
	14945	+ ldrh fp, [r3, #-6]
	14946	+ str r2, [sp, #36]
	14947	+ ldr r2, [r7, #-1432]
	14948	+ str r2, [sp, #40]
	14949	+ mov r2, #0
	14950	+ mov r5, r2
	14951	+.L2454:
	14952	+ ldr r1, [sp, #28]
	14953	+ uxth r3, r2
	14954	+ cmp r1, r3
	14955	+ bhi .L2456
	14956	+ mov r8, #0
	14957	+ mov r2, r4
	14958	+ mov r1, r5
	14959	+ bl FlashReadPages
	14960	+.L2457:
	14961	+ uxth r3, r8
	14962	+ cmp r5, r3
	14963	+ bhi .L2458
14632	14964	add r6, r6, #1
14633	14965	uxth r6, r6
14634		- cmp r6, r9
14635		- bne .L2506
14636		-.L2512:
	14966	+ cmp r9, r6
	14967	+ bne .L2453
	14968	+.L2459:
14637	14969	mov r0, #0
14638	14970	add sp, sp, #100
14639	14971	@ sp needed
14640		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
14641		-.L2519:
	14972	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	14973	+.L2456:
	14974	+ ldrh r3, [ip, #2]!
	14975	+ cmp r3, lr
	14976	+ beq .L2455
	14977	+ mla r1, r10, r5, r0
	14978	+ orr r3, r6, r3, lsl #10
	14979	+ str r3, [r1, #4]
	14980	+ ldr r3, [sp, #36]
	14981	+ mul r3, r3, r5
	14982	+ add r8, r3, #3
	14983	+ cmp r3, #0
	14984	+ movlt r3, r8
	14985	+ ldr r8, [sp, #32]
	14986	+ bic r3, r3, #3
	14987	+ add r3, r8, r3
	14988	+ str r3, [r1, #8]
	14989	+ mul r3, fp, r5
	14990	+ add r5, r5, #1
	14991	+ uxth r5, r5
	14992	+ add r8, r3, #3
	14993	+ cmp r3, #0
	14994	+ movlt r3, r8
	14995	+ ldr r8, [sp, #40]
	14996	+ bic r3, r3, #3
	14997	+ add r3, r8, r3
	14998	+ str r3, [r1, #12]
	14999	+.L2455:
	15000	+ add r2, r2, #1
	15001	+ b .L2454
	15002	+.L2458:
	15003	+ ldr r3, [sp, #44]
	15004	+ mul r0, r10, r8
	15005	+ ldrh r1, [sp, #48]
	15006	+ add r8, r8, #1
	15007	+ ldr ip, [r3, #-1500]
	15008	+ add r2, ip, r0
	15009	+ ldr lr, [r2, #8]
	15010	+ ldr r3, [r2, #12]
	15011	+ ldr fp, [lr, #4]
	15012	+ str fp, [sp, #20]
	15013	+ ldr lr, [lr]
	15014	+ str lr, [sp, #16]
	15015	+ ldr lr, [r3, #12]
	15016	+ str lr, [sp, #12]
	15017	+ ldr lr, [r3, #8]
	15018	+ str lr, [sp, #8]
	15019	+ ldr lr, [r3, #4]
	15020	+ str lr, [sp, #4]
	15021	+ ldr r3, [r3]
	15022	+ str r3, [sp]
	15023	+ ldr r3, [r2, #4]
	15024	+ ldr r2, [ip, r0]
	15025	+ ldr r0, .L2463+28
	15026	+ bl printk
	15027	+ b .L2457
	15028	+.L2464:
14642	15029	.align 2
14643		-.L2518:
	15030	+.L2463:
14644	15031	.word .LANCHOR2
14645		- .word .LANCHOR3+160
	15032	+ .word .LANCHOR3+153
14646	15033	.word .LC50
14647	15034	.word .LC65
14648	15035	.word .LC66
14649		- .word .LANCHOR2-1736
14650		- .word .LANCHOR2-1658
14651		- .word .LANCHOR2-1656
	15036	+ .word .LANCHOR2-1728
	15037	+ .word .LANCHOR2-1648
14652	15038	.word .LC60
14653	15039	.fnend
14654	15040	.size FtlDumpBlockInfo, .-FtlDumpBlockInfo
14655	15041	.align 2
14656	15042	.global FtlScanAllBlock
	15043	+ .syntax unified
	15044	+ .arm
	15045	+ .fpu softvfp
14657	15046	.type FtlScanAllBlock, %function
14658	15047	FtlScanAllBlock:
14659	15048	.fnstart
14660		- @ args = 0, pretend = 0, frame = 64
	15049	+ @ args = 0, pretend = 0, frame = 56
14661	15050	@ frame_needed = 0, uses_anonymous_args = 0
14662		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	15051	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14663	15052	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14664		- .pad #92
14665		- sub sp, sp, #92
14666		- ldr r0, .L2535
14667		- mov r7, #0
14668		- ldr r1, .L2535+4
	15053	+ mov r6, #0
	15054	+ ldr r5, .L2476
	15055	+ .pad #84
	15056	+ sub sp, sp, #84
	15057	+ ldr r1, .L2476+4
	15058	+ ldr r0, .L2476+8
14669	15059	bl printk
14670		- ldr r5, .L2535+8
14671		- mov r6, r5
14672		-.L2521:
14673		- ldr r3, .L2535+12
14674		- uxth r4, r7
14675		- ldrh r3, [r3]
14676		- cmp r3, r4
14677		- bls .L2531
14678		- add r8, sp, #88
14679		- mov r0, r4
	15060	+.L2466:
	15061	+ ldr r3, .L2476+12
	15062	+ uxth r0, r6
	15063	+ ldrh r3, [r3, #-10]
	15064	+ cmp r3, r0
	15065	+ bhi .L2474
	15066	+ mov r0, #0
	15067	+ add sp, sp, #84
	15068	+ @ sp needed
	15069	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	15070	+.L2474:
	15071	+ add r4, sp, #80
14680	15072	movw r9, #65535
	15073	+ strh r0, [r4, #-48]! @ movhi
14681	15074	mov r10, #36
14682		- strh r4, [r8, #-48]! @ movhi
14683	15075	bl ftl_get_blk_mode
14684		- ldr ip, [r5, #-1408]
14685		- mov r2, r4, asl #1
14686		- mov r1, r4
14687		- ldrh r2, [ip, r2]
	15076	+ uxth r1, r6
	15077	+ ldr ip, [r5, #-1404]
14688	15078	mov r3, r0
14689		- ldr r0, .L2535+16
	15079	+ ldr r0, .L2476+16
	15080	+ lsl r2, r1, #1
	15081	+ ldrh r2, [ip, r2]
14690	15082	bl printk
14691		- mov r0, r8
	15083	+ mov r0, r4
14692	15084	bl make_superblock
14693		- ldr r3, .L2535+20
14694		- ldr lr, [r5, #-1436]
14695		- ldrh r2, [r3]
14696		- ldrh ip, [r3, #78]
14697		- ldrh r8, [r3, #80]
	15085	+ ldr r3, .L2476+20
	15086	+ add ip, sp, #46
	15087	+ ldr r0, [r5, #-1500]
	15088	+ ldr r7, [r5, #-1432]
	15089	+ ldrh r2, [r3, #-4]
	15090	+ ldrh lr, [r3, #72]
	15091	+ ldrh r8, [r3, #74]
	15092	+ str r2, [sp, #24]
	15093	+ ldr r2, [r5, #-1460]
14698	15094	str r2, [sp, #28]
14699		- add r0, sp, #54
14700		- ldr r2, [r5, #-1504]
14701		- str r2, [sp, #32]
14702		- ldr r2, [r5, #-1464]
14703		- str r2, [sp, #36]
14704	15095	mov r2, #0
14705	15096	mov r4, r2
14706		-.L2522:
14707		- ldr r1, [sp, #28]
	15097	+.L2467:
	15098	+ ldr r1, [sp, #24]
14708	15099	uxth r3, r2
14709		- cmp r3, r1
14710		- bcs .L2532
14711		- ldrh r3, [r0, #2]!
	15100	+ cmp r1, r3
	15101	+ bhi .L2469
	15102	+ ldr r9, .L2476+24
	15103	+ mov r7, #0
	15104	+ mov r8, #36
	15105	+ mov r2, #0
	15106	+ mov r1, r4
	15107	+ bl FlashReadPages
	15108	+.L2470:
	15109	+ uxth r3, r7
	15110	+ cmp r4, r3
	15111	+ bhi .L2471
	15112	+ ldr r9, .L2476+28
	15113	+ mov r7, #0
	15114	+ mov r8, #36
	15115	+ mov r2, #1
	15116	+ mov r1, r4
	15117	+ ldr r0, [r5, #-1500]
	15118	+ bl FlashReadPages
	15119	+.L2472:
	15120	+ uxth r3, r7
	15121	+ cmp r4, r3
	15122	+ bhi .L2473
	15123	+ add r6, r6, #1
	15124	+ b .L2466
	15125	+.L2469:
	15126	+ ldrh r3, [ip, #2]!
14712	15127	cmp r3, r9
14713		- beq .L2523
14714		- ldr r1, [sp, #32]
14715		- mov r3, r3, asl #10
14716		- mla r1, r10, r4, r1
	15128	+ beq .L2468
	15129	+ mla r1, r10, r4, r0
	15130	+ lsl r3, r3, #10
14717	15131	str r3, [r1, #4]
14718		- mul r3, ip, r4
	15132	+ mul r3, lr, r4
14719	15133	add fp, r3, #3
14720	15134	cmp r3, #0
14721	15135	movlt r3, fp
14722		- ldr fp, [sp, #36]
	15136	+ ldr fp, [sp, #28]
14723	15137	bic r3, r3, #3
14724	15138	add r3, fp, r3
14725	15139	str r3, [r1, #8]
..	..	@@ -14730,340 +15144,311 @@
14730	15144	cmp r3, #0
14731	15145	movlt r3, fp
14732	15146	bic r3, r3, #3
14733		- add r3, lr, r3
	15147	+ add r3, r7, r3
14734	15148	str r3, [r1, #12]
14735		-.L2523:
	15149	+.L2468:
14736	15150	add r2, r2, #1
14737		- b .L2522
14738		-.L2532:
14739		- ldr r0, [r6, #-1504]
14740		- mov r1, r4
14741		- mov r2, #0
14742		- mov r8, #0
14743		- bl FlashReadPages
14744		- mov r9, #36
14745		-.L2525:
14746		- uxth r3, r8
14747		- cmp r3, r4
14748		- bcs .L2533
14749		- mul r2, r9, r8
14750		- ldr lr, [r6, #-1504]
14751		- ldrh r1, [sp, #40]
14752		- add r8, r8, #1
14753		- add ip, lr, r2
14754		- ldr r3, [ip, #12]
14755		- ldr r0, [ip, #8]
14756		- ldr r10, [r3]
14757		- str r10, [sp]
14758		- ldr r10, [r3, #4]
14759		- str r10, [sp, #4]
14760		- ldr r10, [r3, #8]
14761		- str r10, [sp, #8]
14762		- ldr r3, [r3, #12]
14763		- str r3, [sp, #12]
14764		- ldr r3, [r0]
14765		- str r3, [sp, #16]
14766		- ldr r3, [r0, #4]
14767		- ldr r0, .L2535+24
14768		- str r3, [sp, #20]
14769		- ldr r2, [lr, r2]
14770		- ldr r3, [ip, #4]
14771		- bl printk
14772		- b .L2525
14773		-.L2533:
14774		- ldr r0, [r6, #-1504]
14775		- mov r1, r4
14776		- mov r2, #1
14777		- mov r8, #0
14778		- bl FlashReadPages
14779		- mov r9, #36
14780		-.L2527:
14781		- uxth r3, r8
14782		- cmp r3, r4
14783		- bcs .L2534
14784		- mul r2, r9, r8
14785		- ldr lr, [r6, #-1504]
14786		- ldrh r1, [sp, #40]
14787		- add r8, r8, #1
14788		- add ip, lr, r2
14789		- ldr r3, [ip, #12]
14790		- ldr r0, [ip, #8]
14791		- ldr r10, [r3]
14792		- str r10, [sp]
14793		- ldr r10, [r3, #4]
14794		- str r10, [sp, #4]
14795		- ldr r10, [r3, #8]
14796		- str r10, [sp, #8]
14797		- ldr r3, [r3, #12]
14798		- str r3, [sp, #12]
14799		- ldr r3, [r0]
14800		- str r3, [sp, #16]
14801		- ldr r3, [r0, #4]
14802		- ldr r0, .L2535+28
14803		- str r3, [sp, #20]
14804		- ldr r2, [lr, r2]
14805		- ldr r3, [ip, #4]
14806		- bl printk
14807		- b .L2527
14808		-.L2534:
	15151	+ b .L2467
	15152	+.L2471:
	15153	+ mul r0, r8, r7
	15154	+ ldr ip, [r5, #-1500]
	15155	+ ldrh r1, [sp, #32]
14809	15156	add r7, r7, #1
14810		- b .L2521
14811		-.L2531:
14812		- mov r0, #0
14813		- add sp, sp, #92
14814		- @ sp needed
14815		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
14816		-.L2536:
	15157	+ add r2, ip, r0
	15158	+ ldr lr, [r2, #8]
	15159	+ ldr r3, [r2, #12]
	15160	+ ldr r10, [lr, #4]
	15161	+ str r10, [sp, #20]
	15162	+ ldr lr, [lr]
	15163	+ str lr, [sp, #16]
	15164	+ ldr lr, [r3, #12]
	15165	+ str lr, [sp, #12]
	15166	+ ldr lr, [r3, #8]
	15167	+ str lr, [sp, #8]
	15168	+ ldr lr, [r3, #4]
	15169	+ str lr, [sp, #4]
	15170	+ ldr r3, [r3]
	15171	+ str r3, [sp]
	15172	+ ldr r3, [r2, #4]
	15173	+ ldr r2, [ip, r0]
	15174	+ mov r0, r9
	15175	+ bl printk
	15176	+ b .L2470
	15177	+.L2473:
	15178	+ mul r0, r8, r7
	15179	+ ldr ip, [r5, #-1500]
	15180	+ ldrh r1, [sp, #32]
	15181	+ add r7, r7, #1
	15182	+ add r2, ip, r0
	15183	+ ldr lr, [r2, #8]
	15184	+ ldr r3, [r2, #12]
	15185	+ ldr r10, [lr, #4]
	15186	+ str r10, [sp, #20]
	15187	+ ldr lr, [lr]
	15188	+ str lr, [sp, #16]
	15189	+ ldr lr, [r3, #12]
	15190	+ str lr, [sp, #12]
	15191	+ ldr lr, [r3, #8]
	15192	+ str lr, [sp, #8]
	15193	+ ldr lr, [r3, #4]
	15194	+ str lr, [sp, #4]
	15195	+ ldr r3, [r3]
	15196	+ str r3, [sp]
	15197	+ ldr r3, [r2, #4]
	15198	+ ldr r2, [ip, r0]
	15199	+ mov r0, r9
	15200	+ bl printk
	15201	+ b .L2472
	15202	+.L2477:
14817	15203	.align 2
14818		-.L2535:
14819		- .word .LC50
14820		- .word .LANCHOR3+180
	15204	+.L2476:
14821	15205	.word .LANCHOR2
14822		- .word .LANCHOR2-1726
	15206	+ .word .LANCHOR3+170
	15207	+ .word .LC50
	15208	+ .word .LANCHOR2-1712
14823	15209	.word .LC67
14824		- .word .LANCHOR2-1736
	15210	+ .word .LANCHOR2-1728
14825	15211	.word .LC68
14826	15212	.word .LC69
14827	15213	.fnend
14828	15214	.size FtlScanAllBlock, .-FtlScanAllBlock
14829	15215	.align 2
14830	15216	.global SupperBlkListInit
	15217	+ .syntax unified
	15218	+ .arm
	15219	+ .fpu softvfp
14831	15220	.type SupperBlkListInit, %function
14832	15221	SupperBlkListInit:
14833	15222	.fnstart
14834		- @ args = 0, pretend = 0, frame = 24
	15223	+ @ args = 0, pretend = 0, frame = 16
14835	15224	@ frame_needed = 0, uses_anonymous_args = 0
14836		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	15225	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14837	15226	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
14838	15227	mov r2, #6
14839		- ldr r4, .L2549
	15228	+ ldr r4, .L2489
	15229	+ mov r5, #0
	15230	+ .pad #20
	15231	+ sub sp, sp, #20
14840	15232	mov r1, #0
14841		- .pad #28
14842		- sub sp, sp, #28
14843		- sub r3, r4, #1712
	15233	+ mov r8, r5
	15234	+ mov r9, r5
	15235	+ sub r6, r4, #1712
14844	15236	ldr r0, [r4, #-1356]
14845		- mov fp, r4
14846		- ldrh r3, [r3, #-14]
	15237	+ ldrh r3, [r6, #-10]
14847	15238	mul r2, r2, r3
14848	15239	bl ftl_memset
14849		- mov r3, #0
14850		- add r1, r4, #872
14851	15240	add r2, r4, #880
14852		- sub r0, r4, #1616
14853		- mov r5, r3
14854		- mov r8, r3
14855		- mov r9, r3
14856		- str r3, [r4, #876]
14857		- str r3, [r4, #864]
14858		- str r3, [r4, #868]
14859		- strh r3, [r1] @ movhi
14860		- strh r3, [r2] @ movhi
14861		- strh r3, [r0, #-10] @ movhi
14862		- str r1, [sp, #8]
14863		- str r2, [sp, #12]
14864		-.L2538:
14865		- ldr r3, .L2549+4
14866		- uxth r7, r5
14867		- sxth r10, r7
14868		- ldrh r2, [r3]
14869		- cmp r10, r2
14870		- bge .L2545
14871		- sub r3, r3, #8
14872		- ldr r2, .L2549+8
14873		- mov ip, r7
14874		- ldrh r3, [r3]
14875		- str r3, [sp]
14876		- ldrh r3, [r2]
14877		- mov r2, #0
14878		- mov r6, r2
	15241	+ add r3, r4, #872
	15242	+ strh r5, [r2] @ movhi
	15243	+ sub r2, r4, #1616
	15244	+ str r5, [r4, #876]
	15245	+ str r5, [r4, #864]
	15246	+ str r5, [r4, #868]
	15247	+ strh r5, [r3] @ movhi
	15248	+ strh r5, [r2, #-6] @ movhi
	15249	+ str r6, [sp]
14879	15250	str r3, [sp, #4]
14880		-.L2546:
	15251	+.L2479:
14881	15252	ldr r3, [sp]
14882		- sxth r1, r2
14883		- cmp r1, r3
14884		- bge .L2548
14885		- add r1, r4, r1
14886		- str r2, [sp, #20]
14887		- str ip, [sp, #16]
14888		- ldrb r0, [r1, #-1708] @ zero_extendqisi2
14889		- mov r1, ip
	15253	+ sxth r7, r5
	15254	+ ldrh r3, [r3, #-12]
	15255	+ cmp r7, r3
	15256	+ bge .L2486
	15257	+ ldr r3, .L2489+4
	15258	+ mov r10, #0
	15259	+ mov r6, r10
	15260	+ uxth fp, r5
	15261	+ ldrh r2, [r3]
	15262	+ add r3, r3, #4
	15263	+ ldrh r3, [r3, #62]
	15264	+ b .L2487
	15265	+.L2481:
	15266	+ add r0, r4, r1
	15267	+ mov r1, fp
	15268	+ ldrb r0, [r0, #-1706] @ zero_extendqisi2
	15269	+ add r10, r10, #1
	15270	+ str r3, [sp, #12]
	15271	+ str r2, [sp, #8]
14890	15272	bl V2P_block
14891	15273	bl FtlBbmIsBadBlock
	15274	+ ldr r3, [sp, #12]
14892	15275	cmp r0, #0
14893		- ldr r2, [sp, #20]
14894		- ldr ip, [sp, #16]
14895		- ldreq r3, [sp, #4]
14896		- add r2, r2, #1
	15276	+ ldr r2, [sp, #8]
14897	15277	addeq r6, r3, r6
14898		- uxtheq r6, r6
14899		- b .L2546
14900		-.L2548:
	15278	+ sxtheq r6, r6
	15279	+.L2487:
	15280	+ sxth r1, r10
	15281	+ cmp r1, r2
	15282	+ blt .L2481
14901	15283	cmp r6, #0
14902		- beq .L2541
14903		- sxth r1, r6
	15284	+ lsl r10, r7, #1
	15285	+ ldreq r3, [r4, #-1404]
	15286	+ mvneq r2, #0
	15287	+ strheq r2, [r3, r10] @ movhi
	15288	+ beq .L2483
	15289	+ mov r1, r6
14904	15290	mov r0, #32768
14905	15291	bl __aeabi_idiv
14906		- uxth r6, r0
14907		- b .L2542
14908		-.L2541:
14909		- sxth r7, r7
14910		- ldr r2, [r4, #-1408]
14911		- mvn r1, #0
14912		- mov r7, r7, asl #1
14913		- strh r1, [r2, r7] @ movhi
14914		-.L2542:
14915		- mov r1, r10, asl #1
	15292	+ sxth r6, r0
	15293	+.L2483:
14916	15294	ldr r2, [r4, #-1356]
14917		- add r0, r1, r10
14918		- add r2, r2, r0, asl #1
14919		- strh r6, [r2, #4] @ movhi
14920		- ldr r2, .L2549+12
14921		- ldrh r0, [r2]
14922		- cmp r10, r0
14923		- beq .L2543
14924		- ldrh r0, [r2, #48]
14925		- cmp r10, r0
14926		- beq .L2543
14927		- ldrh r2, [r2, #96]
14928		- cmp r10, r2
14929		- beq .L2543
14930		- ldr r3, [fp, #-1408]
	15295	+ add r3, r10, r7
	15296	+ add r3, r2, r3, lsl #1
	15297	+ strh r6, [r3, #4] @ movhi
	15298	+ ldr r3, .L2489+8
	15299	+ ldrh r3, [r3]
	15300	+ cmp r7, r3
	15301	+ beq .L2484
	15302	+ ldr r3, .L2489+12
	15303	+ ldrh r3, [r3]
	15304	+ cmp r7, r3
	15305	+ beq .L2484
	15306	+ ldr r3, .L2489+16
	15307	+ ldrh r3, [r3]
	15308	+ cmp r7, r3
	15309	+ beq .L2484
	15310	+ ldr r3, [r4, #-1404]
14931	15311	uxth r0, r5
14932		- ldrh r3, [r3, r1]
	15312	+ ldrh r3, [r3, r10]
14933	15313	cmp r3, #0
14934		- bne .L2544
	15314	+ bne .L2485
14935	15315	add r8, r8, #1
14936	15316	uxth r8, r8
14937	15317	bl INSERT_FREE_LIST
14938		- b .L2543
14939		-.L2544:
	15318	+.L2484:
	15319	+ add r5, r5, #1
	15320	+ b .L2479
	15321	+.L2485:
14940	15322	add r9, r9, #1
14941	15323	uxth r9, r9
14942	15324	bl INSERT_DATA_LIST
14943		-.L2543:
14944		- add r5, r5, #1
14945		- b .L2538
14946		-.L2545:
14947		- ldr r3, [sp, #8]
	15325	+ b .L2484
	15326	+.L2486:
	15327	+ ldr r3, [sp, #4]
14948	15328	mov r0, #0
14949	15329	strh r9, [r3] @ movhi
14950		- ldr r3, [sp, #12]
	15330	+ ldr r3, .L2489+20
14951	15331	strh r8, [r3] @ movhi
14952		- add sp, sp, #28
	15332	+ add sp, sp, #20
14953	15333	@ sp needed
14954		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
14955		-.L2550:
	15334	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	15335	+.L2490:
14956	15336	.align 2
14957		-.L2549:
	15337	+.L2489:
14958	15338	.word .LANCHOR2
14959		- .word .LANCHOR2-1728
14960		- .word .LANCHOR2-1668
	15339	+ .word .LANCHOR2-1732
14961	15340	.word .LANCHOR2+884
	15341	+ .word .LANCHOR2+932
	15342	+ .word .LANCHOR2+980
	15343	+ .word .LANCHOR2+880
14962	15344	.fnend
14963	15345	.size SupperBlkListInit, .-SupperBlkListInit
14964	15346	.align 2
14965	15347	.global Ftl_save_ext_data
	15348	+ .syntax unified
	15349	+ .arm
	15350	+ .fpu softvfp
14966	15351	.type Ftl_save_ext_data, %function
14967	15352	Ftl_save_ext_data:
14968	15353	.fnstart
14969	15354	@ args = 0, pretend = 0, frame = 0
14970	15355	@ frame_needed = 0, uses_anonymous_args = 0
14971	15356	@ link register save eliminated.
14972		- ldr r3, .L2553
14973		- ldr r2, .L2553+4
14974		- ldr r1, [r3, #1212]
	15357	+ ldr r3, .L2493
	15358	+ ldr r2, .L2493+4
	15359	+ ldr r1, [r3, #1204]
14975	15360	cmp r1, r2
14976	15361	bxne lr
14977		- ldr r2, .L2553+8
14978		- mov r0, #0
14979		- str r2, [r3, #1216]
14980		- ldr r2, [r3, #1724]
14981		- str r2, [r3, #1300]
14982		- ldr r2, [r3, #1728]
14983		- str r2, [r3, #1304]
14984		- ldr r2, .L2553+12
14985		- ldr r1, [r2, #-1608]
14986		- str r1, [r3, #1220]
14987		- ldr r1, [r2, #-1604]
14988		- str r1, [r3, #1224]
14989		- ldr r1, [r2, #-1588]
14990		- str r1, [r3, #1228]
14991		- ldr r1, [r2, #-1592]
14992		- str r1, [r3, #1232]
14993		- ldr r1, [r2, #-1580]
14994		- str r1, [r3, #1240]
14995		- ldr r1, [r2, #-1576]
14996		- str r1, [r3, #1244]
14997		- ldr r1, [r2, #-1600]
14998		- str r1, [r3, #1248]
14999		- ldr r1, [r2, #-1596]
15000		- str r1, [r3, #1252]
15001		- ldr r1, [r2, #-1572]
15002		- str r1, [r3, #1256]
15003		- ldr r1, [r2, #-1568]
15004		- str r1, [r3, #1260]
15005		- ldr r1, [r2, #-1620]
15006		- ldr r2, [r2, #-1624]
15007		- str r1, [r3, #1272]
	15362	+ ldr r2, .L2493+8
15008	15363	mov r1, #1
15009		- str r2, [r3, #1276]
15010		- ldr r2, .L2553+16
	15364	+ mov r0, #0
	15365	+ str r2, [r3, #1208]
	15366	+ ldr r2, [r3, #1716]
	15367	+ str r2, [r3, #1292]
	15368	+ ldr r2, [r3, #1720]
	15369	+ str r2, [r3, #1296]
	15370	+ ldr r2, [r3, #-1604]
	15371	+ str r2, [r3, #1212]
	15372	+ ldr r2, [r3, #-1600]
	15373	+ str r2, [r3, #1216]
	15374	+ ldr r2, [r3, #-1584]
	15375	+ str r2, [r3, #1220]
	15376	+ ldr r2, [r3, #-1588]
	15377	+ str r2, [r3, #1224]
	15378	+ ldr r2, [r3, #-1576]
	15379	+ str r2, [r3, #1232]
	15380	+ ldr r2, [r3, #-1572]
	15381	+ str r2, [r3, #1236]
	15382	+ ldr r2, [r3, #-1596]
	15383	+ str r2, [r3, #1240]
	15384	+ ldr r2, [r3, #-1592]
	15385	+ str r2, [r3, #1244]
	15386	+ ldr r2, [r3, #-1568]
	15387	+ str r2, [r3, #1248]
	15388	+ ldr r2, [r3, #-1564]
	15389	+ str r2, [r3, #1252]
	15390	+ ldr r2, [r3, #-1616]
	15391	+ str r2, [r3, #1264]
	15392	+ ldr r2, [r3, #-1620]
	15393	+ str r2, [r3, #1268]
	15394	+ ldr r2, .L2493+12
15011	15395	b FtlVendorPartWrite
15012		-.L2554:
	15396	+.L2494:
15013	15397	.align 2
15014		-.L2553:
15015		- .word .LANCHOR4
	15398	+.L2493:
	15399	+ .word .LANCHOR2
15016	15400	.word 1179929683
15017	15401	.word 1342177379
15018		- .word .LANCHOR2
15019		- .word .LANCHOR4+1212
	15402	+ .word .LANCHOR2+1204
15020	15403	.fnend
15021	15404	.size Ftl_save_ext_data, .-Ftl_save_ext_data
15022	15405	.align 2
15023	15406	.global FtlEctTblFlush
	15407	+ .syntax unified
	15408	+ .arm
	15409	+ .fpu softvfp
15024	15410	.type FtlEctTblFlush, %function
15025	15411	FtlEctTblFlush:
15026	15412	.fnstart
15027	15413	@ args = 0, pretend = 0, frame = 0
15028	15414	@ frame_needed = 0, uses_anonymous_args = 0
15029		- stmfd sp!, {r3, lr}
15030		- .save {r3, lr}
15031		- ldr r3, .L2563
15032		- ldr r2, [r3, #-1872]
	15415	+ ldr r3, .L2505
	15416	+ ldr r2, [r3, #-1868]
15033	15417	cmp r2, #0
15034	15418	moveq r2, #32
15035		- beq .L2556
15036		- ldr r2, [r3, #-1568]
	15419	+ beq .L2496
	15420	+ ldr r2, [r3, #-1564]
15037	15421	cmp r2, #39
15038	15422	movhi r2, #32
15039	15423	movls r2, #4
15040		-.L2556:
15041		- ldr lr, .L2563+4
15042		- movw ip, #1732
15043		- ldrh r1, [lr, ip]
	15424	+.L2496:
	15425	+ movw ip, #1724
	15426	+ ldrh r1, [r3, ip]
15044	15427	cmp r1, #31
15045	15428	addls r1, r1, #1
15046		- strlsh r1, [lr, ip] @ movhi
15047	15429	movls r2, #1
	15430	+ strhls r1, [r3, ip] @ movhi
15048	15431	cmp r0, #0
15049		- bne .L2558
15050		- ldr r1, [r3, #-1420]
	15432	+ bne .L2498
	15433	+ ldr r1, [r3, #-1416]
15051	15434	ldr r0, [r1, #20]
15052	15435	ldr r1, [r1, #16]
15053	15436	add r2, r2, r0
15054	15437	cmp r1, r2
15055		- bcc .L2559
15056		-.L2558:
15057		- ldr r2, [r3, #-1420]
	15438	+ bcc .L2503
	15439	+.L2498:
	15440	+ push {r4, lr}
	15441	+ .save {r4, lr}
15058	15442	mov r0, #64
	15443	+ ldr r2, [r3, #-1416]
15059	15444	ldr r1, [r2, #16]
15060	15445	str r1, [r2, #20]
15061		- ldr r1, .L2563+8
	15446	+ ldr r1, .L2505+4
15062	15447	str r1, [r2]
15063		- ldr r2, [r3, #-1420]
15064		- ldr r3, .L2563+12
15065		- ldrh r1, [r3, #-4]
15066		- mov r3, r1, asl #9
	15448	+ ldr r2, [r3, #-1416]
	15449	+ ldr r3, .L2505+8
	15450	+ ldrh r1, [r3]
	15451	+ lsl r3, r1, #9
15067	15452	str r3, [r2, #12]
15068	15453	ldr r3, [r2, #8]
15069	15454	add r3, r3, #1
..	..	@@ -15072,858 +15457,871 @@
15072	15457	str r3, [r2, #4]
15073	15458	bl FtlVendorPartWrite
15074	15459	bl Ftl_save_ext_data
15075		-.L2559:
15076	15460	mov r0, #0
15077		- ldmfd sp!, {r3, pc}
15078		-.L2564:
	15461	+ pop {r4, pc}
	15462	+.L2503:
	15463	+ mov r0, #0
	15464	+ bx lr
	15465	+.L2506:
15079	15466	.align 2
15080		-.L2563:
	15467	+.L2505:
15081	15468	.word .LANCHOR2
15082		- .word .LANCHOR4
15083	15469	.word 1112818501
15084	15470	.word .LANCHOR2-1424
15085	15471	.fnend
15086	15472	.size FtlEctTblFlush, .-FtlEctTblFlush
15087	15473	.align 2
15088	15474	.global Ftl_load_ext_data
	15475	+ .syntax unified
	15476	+ .arm
	15477	+ .fpu softvfp
15089	15478	.type Ftl_load_ext_data, %function
15090	15479	Ftl_load_ext_data:
15091	15480	.fnstart
15092	15481	@ args = 0, pretend = 0, frame = 0
15093	15482	@ frame_needed = 0, uses_anonymous_args = 0
15094		- stmfd sp!, {r3, r4, r5, lr}
15095		- .save {r3, r4, r5, lr}
15096		- mov r0, #0
15097		- ldr r5, .L2571
	15483	+ push {r4, r5, r6, lr}
	15484	+ .save {r4, r5, r6, lr}
15098	15485	mov r1, #1
15099		- ldr r2, .L2571+4
	15486	+ ldr r4, .L2513
	15487	+ mov r0, #0
	15488	+ ldr r2, .L2513+4
15100	15489	bl FtlVendorPartRead
15101		- ldr r4, .L2571+8
15102		- ldr r3, [r5, #1212]
15103		- cmp r3, r4
15104		- beq .L2566
15105		- ldr r0, .L2571+4
15106		- mov r1, #0
	15490	+ ldr r5, .L2513+8
	15491	+ ldr r3, [r4, #1204]
	15492	+ cmp r3, r5
	15493	+ beq .L2508
15107	15494	mov r2, #512
	15495	+ mov r1, #0
	15496	+ ldr r0, .L2513+4
15108	15497	bl ftl_memset
15109		- str r4, [r5, #1212]
15110		-.L2566:
15111		- ldr r2, [r5, #1212]
15112		- ldr r3, .L2571
15113		- cmp r2, r4
15114		- ldr r4, .L2571+12
15115		- bne .L2567
15116		- ldr r2, [r3, #1300]
15117		- str r2, [r3, #1724]
15118		- ldr r2, [r3, #1304]
15119		- str r2, [r3, #1728]
15120		- ldr r2, [r3, #1220]
15121		- str r2, [r4, #-1608]
15122		- ldr r2, [r3, #1224]
15123		- str r2, [r4, #-1604]
15124		- ldr r2, [r3, #1228]
15125		- str r2, [r4, #-1588]
15126		- ldr r2, [r3, #1232]
15127		- str r2, [r4, #-1592]
15128		- ldr r2, [r3, #1240]
15129		- str r2, [r4, #-1580]
15130		- ldr r2, [r3, #1244]
15131		- str r2, [r4, #-1576]
15132		- ldr r2, [r3, #1248]
15133		- str r2, [r4, #-1600]
15134		- ldr r2, [r3, #1252]
15135		- str r2, [r4, #-1596]
15136		- ldr r2, [r3, #1256]
15137		- str r2, [r4, #-1572]
15138		- ldr r2, [r3, #1260]
15139		- ldr r3, [r3, #1272]
15140		- str r2, [r4, #-1568]
	15498	+ str r5, [r4, #1204]
	15499	+.L2508:
	15500	+ ldr r3, [r4, #1204]
	15501	+ cmp r3, r5
	15502	+ bne .L2509
	15503	+ ldr r3, [r4, #1292]
	15504	+ str r3, [r4, #1716]
	15505	+ ldr r3, [r4, #1296]
	15506	+ str r3, [r4, #1720]
	15507	+ ldr r3, [r4, #1212]
	15508	+ str r3, [r4, #-1604]
	15509	+ ldr r3, [r4, #1216]
	15510	+ str r3, [r4, #-1600]
	15511	+ ldr r3, [r4, #1220]
	15512	+ str r3, [r4, #-1584]
	15513	+ ldr r3, [r4, #1224]
	15514	+ str r3, [r4, #-1588]
	15515	+ ldr r3, [r4, #1232]
	15516	+ str r3, [r4, #-1576]
	15517	+ ldr r3, [r4, #1236]
	15518	+ str r3, [r4, #-1572]
	15519	+ ldr r3, [r4, #1240]
	15520	+ str r3, [r4, #-1596]
	15521	+ ldr r3, [r4, #1244]
	15522	+ str r3, [r4, #-1592]
	15523	+ ldr r3, [r4, #1248]
	15524	+ str r3, [r4, #-1568]
	15525	+ ldr r3, [r4, #1252]
	15526	+ str r3, [r4, #-1564]
	15527	+ ldr r3, [r4, #1264]
	15528	+ str r3, [r4, #-1616]
	15529	+.L2509:
	15530	+ ldr r1, [r4, #1272]
	15531	+ mov r3, #0
	15532	+ ldr r2, .L2513+12
15141	15533	str r3, [r4, #-1620]
15142		-.L2567:
15143		- ldr r0, [r5, #1280]
15144		- mov r2, #0
15145		- ldr r1, .L2571+16
15146		- ldr r3, .L2571+12
15147		- cmp r0, r1
15148		- str r2, [r4, #-1624]
15149		- bne .L2568
15150		- ldrb r1, [r3, #-2744] @ zero_extendqisi2
15151	15534	cmp r1, r2
15152		- beq .L2569
15153		- ldr r3, .L2571
15154		- str r2, [r3, #1280]
	15535	+ bne .L2510
	15536	+ ldrb r2, [r4, #-2740] @ zero_extendqisi2
	15537	+ cmp r2, r3
	15538	+ beq .L2511
	15539	+ str r3, [r4, #1272]
15155	15540	bl Ftl_save_ext_data
15156		- b .L2568
15157		-.L2569:
15158		- ldr r0, .L2571+20
15159		- mov r2, #1
15160		- ldr r1, .L2571+24
15161		- str r2, [r3, #-1872]
15162		- bl printk
15163		-.L2568:
15164		- ldr r3, .L2571+28
15165		- ldr r2, [r4, #-1580]
15166		- ldr r0, [r4, #-1584]
15167		- ldrh r1, [r3, #-12]
15168		- mla r0, r0, r1, r2
15169		- ldrh r1, [r3, #-64]
	15541	+.L2510:
	15542	+ ldr r3, .L2513+16
	15543	+ ldr ip, [r4, #-1580]
	15544	+ ldr r2, [r4, #-1576]
	15545	+ ldrh r0, [r3, #-10]
	15546	+ ldrh r1, [r3, #-60]
	15547	+ mla r0, ip, r0, r2
15170	15548	bl __aeabi_uidiv
15171		- str r0, [r5, #1736]
15172		- ldmfd sp!, {r3, r4, r5, pc}
15173		-.L2572:
	15549	+ str r0, [r4, #1728]
	15550	+ pop {r4, r5, r6, pc}
	15551	+.L2511:
	15552	+ mov r3, #1
	15553	+ ldr r1, .L2513+20
	15554	+ ldr r0, .L2513+24
	15555	+ str r3, [r4, #-1868]
	15556	+ bl printk
	15557	+ b .L2510
	15558	+.L2514:
15174	15559	.align 2
15175		-.L2571:
15176		- .word .LANCHOR4
15177		- .word .LANCHOR4+1212
15178		- .word 1179929683
	15560	+.L2513:
15179	15561	.word .LANCHOR2
	15562	+ .word .LANCHOR2+1204
	15563	+ .word 1179929683
15180	15564	.word 305432421
15181		- .word .LC48
15182		- .word .LC70
15183	15565	.word .LANCHOR2-1664
	15566	+ .word .LC70
	15567	+ .word .LC49
15184	15568	.fnend
15185	15569	.size Ftl_load_ext_data, .-Ftl_load_ext_data
15186	15570	.align 2
15187	15571	.global ftl_scan_all_ppa
	15572	+ .syntax unified
	15573	+ .arm
	15574	+ .fpu softvfp
15188	15575	.type ftl_scan_all_ppa, %function
15189	15576	ftl_scan_all_ppa:
15190	15577	.fnstart
15191		- @ args = 0, pretend = 0, frame = 0
	15578	+ @ args = 0, pretend = 0, frame = 8
15192	15579	@ frame_needed = 0, uses_anonymous_args = 0
15193		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
15194		- .save {r4, r5, r6, r7, r8, r9, r10, lr}
15195		- .pad #24
15196		- sub sp, sp, #24
15197		- ldr r7, .L2592
15198		- ldr r9, .L2592+4
15199		- ldrh r4, [r7, #-6]
15200		- add r7, r7, #1664
	15580	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	15581	+ .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	15582	+ .pad #36
	15583	+ sub sp, sp, #36
	15584	+ ldr r6, .L2532
	15585	+ ldrh r4, [r6, #-4]
	15586	+ add r3, r6, #388
	15587	+ str r3, [sp, #28]
15201	15588	sub r4, r4, #16
15202		- mov r5, r7
15203		-.L2574:
15204		- ldrh r3, [r9]
	15589	+ lsl r10, r4, #10
	15590	+.L2516:
	15591	+ ldrh r3, [r6, #-4]
	15592	+ ldr r1, .L2532+4
15205	15593	cmp r4, r3
15206		- bge .L2590
15207		- uxth r10, r4
15208		- mov r0, r10
	15594	+ mov r5, r1
	15595	+ blt .L2524
	15596	+ ldr r1, .L2532+8
	15597	+ ldr r0, .L2532+12
	15598	+ add sp, sp, #36
	15599	+ @ sp needed
	15600	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	15601	+ b printk
	15602	+.L2524:
	15603	+ uxth r8, r4
	15604	+ mov r0, r8
15209	15605	bl ftl_get_blk_mode
15210		- ldrb r3, [r7, #-2744] @ zero_extendqisi2
	15606	+ ldrb r3, [r1, #-2740] @ zero_extendqisi2
15211	15607	cmp r3, #0
15212		- beq .L2575
15213		- ldr r3, .L2592+8
15214		- ldrh r2, [r3]
15215		- cmp r4, r2
15216		- bge .L2576
15217		- ldrh r3, [r3, #74]
	15608	+ beq .L2517
	15609	+ ldr r3, .L2532+16
	15610	+ ldrh r3, [r3]
15218	15611	cmp r4, r3
15219		- blt .L2576
15220		-.L2575:
	15612	+ bge .L2518
	15613	+ ldr r3, .L2532+20
	15614	+ ldrh r3, [r3]
	15615	+ cmp r4, r3
	15616	+ blt .L2518
	15617	+.L2517:
15221	15618	cmp r0, #1
15222		- bne .L2577
15223		-.L2576:
15224		- ldr r3, .L2592+12
15225		- mov r6, #-2147483648
15226		- ldrh r8, [r3]
15227		- b .L2578
15228		-.L2577:
15229		- ldr r3, .L2592+16
15230		- mov r6, #0
15231		- ldrh r8, [r3]
15232		-.L2578:
	15619	+ ldrhne r7, [r6, #-2]
	15620	+ movne r9, #0
	15621	+ bne .L2520
	15622	+.L2518:
	15623	+ ldrh r7, [r6]
	15624	+ mov r9, #-2147483648
	15625	+.L2520:
	15626	+ mov r3, r9
	15627	+ mov r2, r7
15233	15628	mov r1, r4
15234		- mov r2, r8
15235		- mov r3, r6
15236		- ldr r0, .L2592+20
	15629	+ ldr r0, .L2532+24
15237	15630	bl printk
15238		- mov r0, r10
	15631	+ mov r0, r8
15239	15632	bl FtlBbmIsBadBlock
15240	15633	cmp r0, #0
15241		- beq .L2579
15242		- ldr r0, .L2592+24
	15634	+ beq .L2521
	15635	+ mov r3, r9
	15636	+ mov r2, r7
15243	15637	mov r1, r4
15244		- mov r2, r8
15245		- mov r3, r6
	15638	+ ldr r0, .L2532+28
15246	15639	bl printk
15247		-.L2579:
15248		- add r6, r6, r4, asl #10
15249		- mov r10, #0
15250		-.L2580:
15251		- cmp r10, r8
15252		- beq .L2591
15253		- add r3, r6, r10
15254		- str r3, [r5, #-1272]
15255		- ldr r3, [r5, #-1476]
	15640	+.L2521:
	15641	+ ldr fp, .L2532+32
	15642	+ mov r8, #0
	15643	+.L2522:
	15644	+ cmp r8, r7
	15645	+ addeq r4, r4, #1
	15646	+ addeq r10, r10, #1024
	15647	+ beq .L2516
	15648	+.L2523:
	15649	+ add r3, r9, r10
15256	15650	mov r2, #0
	15651	+ add r3, r3, r8
15257	15652	mov r1, #1
15258		- ldr r0, .L2592+28
	15653	+ str r3, [r5, #-1272]
	15654	+ add r8, r8, #1
	15655	+ ldr r3, [r5, #-1472]
	15656	+ ldr r0, [sp, #28]
15259	15657	str r2, [r5, #-1276]
15260		- add r10, r10, #1
15261	15658	str r3, [r5, #-1268]
15262		- ldr r3, [r5, #-1444]
	15659	+ ldr r3, [r5, #-1440]
15263	15660	str r3, [r5, #-1264]
15264	15661	bl FlashReadPages
15265		- ldr r3, [r5, #-1264]
15266	15662	ldr r2, [r5, #-1268]
15267		- ldr r0, .L2592+32
15268		- ldr r1, [r3, #4]
15269		- str r1, [sp]
15270		- ldr r1, [r3, #8]
15271		- str r1, [sp, #4]
15272		- ldr r1, [r3, #12]
15273		- str r1, [sp, #8]
15274		- ldr r1, [r2]
15275		- str r1, [sp, #12]
15276		- ldr r2, [r2, #4]
15277		- str r2, [sp, #16]
15278		- ldr r1, [r5, #-1272]
15279		- ldr r2, [r5, #-1276]
	15663	+ mov r0, fp
	15664	+ ldr r3, [r5, #-1264]
	15665	+ ldr r1, [r2, #4]
	15666	+ str r1, [sp, #16]
	15667	+ ldr r2, [r2]
	15668	+ str r2, [sp, #12]
	15669	+ ldr r2, [r3, #12]
	15670	+ str r2, [sp, #8]
	15671	+ ldr r2, [r3, #8]
	15672	+ str r2, [sp, #4]
	15673	+ ldr r2, [r3, #4]
	15674	+ str r2, [sp]
15280	15675	ldr r3, [r3]
	15676	+ ldr r2, [r5, #-1276]
	15677	+ ldr r1, [r5, #-1272]
15281	15678	bl printk
15282		- b .L2580
15283		-.L2591:
15284		- add r4, r4, #1
15285		- b .L2574
15286		-.L2590:
15287		- ldr r0, .L2592+36
15288		- ldr r1, .L2592+40
15289		- add sp, sp, #24
15290		- @ sp needed
15291		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
15292		- b printk
15293		-.L2593:
	15679	+ b .L2522
	15680	+.L2533:
15294	15681	.align 2
15295		-.L2592:
	15682	+.L2532:
15296	15683	.word .LANCHOR2-1664
15297		- .word .LANCHOR2-1670
15298		- .word .LANCHOR2-1728
15299		- .word .LANCHOR2-1666
15300		- .word .LANCHOR2-1668
	15684	+ .word .LANCHOR2
	15685	+ .word .LANCHOR3+186
	15686	+ .word .LC74
	15687	+ .word .LANCHOR2-1724
	15688	+ .word .LANCHOR2-1652
15301	15689	.word .LC71
15302	15690	.word .LC72
15303		- .word .LANCHOR2-1276
15304	15691	.word .LC73
15305		- .word .LC74
15306		- .word .LANCHOR3+196
15307	15692	.fnend
15308	15693	.size ftl_scan_all_ppa, .-ftl_scan_all_ppa
15309	15694	.align 2
15310	15695	.global update_multiplier_value
	15696	+ .syntax unified
	15697	+ .arm
	15698	+ .fpu softvfp
15311	15699	.type update_multiplier_value, %function
15312	15700	update_multiplier_value:
15313	15701	.fnstart
15314	15702	@ args = 0, pretend = 0, frame = 0
15315	15703	@ frame_needed = 0, uses_anonymous_args = 0
15316		- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
15317		- .save {r3, r4, r5, r6, r7, r8, r9, lr}
	15704	+ ldr r3, .L2541
	15705	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
	15706	+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
15318	15707	mov r5, #0
15319		- ldr r3, .L2604
15320	15708	mov r7, r0
15321	15709	mov r4, r5
15322		- add r6, r3, #20
15323		- ldrh r8, [r3, #-8]
15324		- ldrh r9, [r3, #60]
15325		-.L2595:
	15710	+ add r6, r3, #22
	15711	+ ldrh r8, [r3, #-4]
	15712	+ ldrh r9, [r3, #62]
	15713	+.L2535:
15326	15714	uxth r3, r5
15327		- cmp r3, r8
15328		- bcs .L2603
15329		- ldrb r0, [r6, r5] @ zero_extendqisi2
15330		- mov r1, r7
15331		- bl V2P_block
15332		- add r5, r5, #1
15333		- bl FtlBbmIsBadBlock
15334		- cmp r0, #0
15335		- addeq r4, r4, r9
15336		- uxtheq r4, r4
15337		- b .L2595
15338		-.L2603:
	15715	+ cmp r8, r3
	15716	+ bhi .L2537
15339	15717	cmp r4, #0
15340		- beq .L2598
	15718	+ moveq r0, r4
	15719	+ beq .L2538
15341	15720	mov r1, r4
15342	15721	mov r0, #32768
15343	15722	bl __aeabi_idiv
15344		- uxth r4, r0
15345		-.L2598:
15346		- ldr r3, .L2604+4
	15723	+.L2538:
	15724	+ ldr r3, .L2541+4
15347	15725	mov r2, #6
15348		- mov r0, #0
15349	15726	ldr r3, [r3, #-1356]
15350	15727	mla r7, r2, r7, r3
15351		- strh r4, [r7, #4] @ movhi
15352		- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
15353		-.L2605:
	15728	+ strh r0, [r7, #4] @ movhi
	15729	+ mov r0, #0
	15730	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	15731	+.L2537:
	15732	+ mov r1, r7
	15733	+ ldrb r0, [r6, r5] @ zero_extendqisi2
	15734	+ bl V2P_block
	15735	+ bl FtlBbmIsBadBlock
	15736	+ cmp r0, #0
	15737	+ add r5, r5, #1
	15738	+ addeq r4, r4, r9
	15739	+ uxtheq r4, r4
	15740	+ b .L2535
	15741	+.L2542:
15354	15742	.align 2
15355		-.L2604:
	15743	+.L2541:
15356	15744	.word .LANCHOR2-1728
15357	15745	.word .LANCHOR2
15358	15746	.fnend
15359	15747	.size update_multiplier_value, .-update_multiplier_value
15360	15748	.align 2
15361	15749	.global GetFreeBlockMinEraseCount
	15750	+ .syntax unified
	15751	+ .arm
	15752	+ .fpu softvfp
15362	15753	.type GetFreeBlockMinEraseCount, %function
15363	15754	GetFreeBlockMinEraseCount:
15364	15755	.fnstart
15365	15756	@ args = 0, pretend = 0, frame = 0
15366	15757	@ frame_needed = 0, uses_anonymous_args = 0
15367	15758	@ link register save eliminated.
15368		- ldr r2, .L2609
	15759	+ ldr r2, .L2546
15369	15760	ldr r0, [r2, #876]
15370	15761	cmp r0, #0
15371	15762	bxeq lr
15372	15763	ldr r3, [r2, #-1356]
15373		- rsb r0, r3, r0
15374		- ldr r3, .L2609+4
15375		- mov r0, r0, asr #1
	15764	+ sub r0, r0, r3
	15765	+ ldr r3, .L2546+4
	15766	+ asr r0, r0, #1
15376	15767	mul r0, r3, r0
15377		- ldr r3, [r2, #-1416]
	15768	+ ldr r3, [r2, #-1412]
15378	15769	uxth r0, r0
15379		- mov r0, r0, asl #1
	15770	+ lsl r0, r0, #1
15380	15771	ldrh r0, [r3, r0]
15381	15772	bx lr
15382		-.L2610:
	15773	+.L2547:
15383	15774	.align 2
15384		-.L2609:
	15775	+.L2546:
15385	15776	.word .LANCHOR2
15386	15777	.word -1431655765
15387	15778	.fnend
15388	15779	.size GetFreeBlockMinEraseCount, .-GetFreeBlockMinEraseCount
15389	15780	.align 2
15390	15781	.global GetFreeBlockMaxEraseCount
	15782	+ .syntax unified
	15783	+ .arm
	15784	+ .fpu softvfp
15391	15785	.type GetFreeBlockMaxEraseCount, %function
15392	15786	GetFreeBlockMaxEraseCount:
15393	15787	.fnstart
15394	15788	@ args = 0, pretend = 0, frame = 0
15395	15789	@ frame_needed = 0, uses_anonymous_args = 0
15396		- ldr r1, .L2621
	15790	+ ldr r1, .L2560
15397	15791	ldr r3, [r1, #876]
15398	15792	cmp r3, #0
15399		- beq .L2617
	15793	+ beq .L2554
15400	15794	add r2, r1, #880
15401		- stmfd sp!, {r4, r5, lr}
	15795	+ push {r4, r5, lr}
15402	15796	.save {r4, r5, lr}
15403		- mov r4, #6
15404	15797	ldrh r2, [r2]
	15798	+ mov r4, #6
15405	15799	movw r5, #65535
15406	15800	ldr ip, [r1, #-1356]
15407		- rsb r2, r2, r2, asl #3
15408		- rsb r3, ip, r3
15409		- mov r2, r2, asr #3
15410		- mov r3, r3, asr #1
	15801	+ rsb r2, r2, r2, lsl #3
	15802	+ sub r3, r3, ip
	15803	+ asr r2, r2, #3
	15804	+ asr r3, r3, #1
15411	15805	cmp r0, r2
15412	15806	uxthgt r0, r2
15413		- ldr r2, .L2621+4
	15807	+ ldr r2, .L2560+4
15414	15808	mul r3, r2, r3
15415	15809	mov r2, #0
15416	15810	uxth r3, r3
15417		-.L2614:
	15811	+.L2551:
15418	15812	uxth lr, r2
15419		- cmp lr, r0
15420		- bcs .L2616
	15813	+ cmp r0, lr
	15814	+ bls .L2553
15421	15815	mul lr, r4, r3
15422	15816	add r2, r2, #1
15423	15817	ldrh lr, [ip, lr]
15424	15818	cmp lr, r5
15425		- bne .L2618
15426		-.L2616:
15427		- ldr r2, [r1, #-1416]
15428		- mov r3, r3, asl #1
	15819	+ bne .L2555
	15820	+.L2553:
	15821	+ ldr r2, [r1, #-1412]
	15822	+ lsl r3, r3, #1
15429	15823	ldrh r0, [r2, r3]
15430		- ldmfd sp!, {r4, r5, pc}
15431		-.L2618:
	15824	+ pop {r4, r5, pc}
	15825	+.L2555:
15432	15826	mov r3, lr
15433		- b .L2614
15434		-.L2617:
	15827	+ b .L2551
	15828	+.L2554:
15435	15829	mov r0, r3
15436	15830	bx lr
15437		-.L2622:
	15831	+.L2561:
15438	15832	.align 2
15439		-.L2621:
	15833	+.L2560:
15440	15834	.word .LANCHOR2
15441	15835	.word -1431655765
15442	15836	.fnend
15443	15837	.size GetFreeBlockMaxEraseCount, .-GetFreeBlockMaxEraseCount
15444	15838	.align 2
15445	15839	.global FtlPrintInfo2buf
	15840	+ .syntax unified
	15841	+ .arm
	15842	+ .fpu softvfp
15446	15843	.type FtlPrintInfo2buf, %function
15447	15844	FtlPrintInfo2buf:
15448	15845	.fnstart
15449	15846	@ args = 0, pretend = 0, frame = 16
15450	15847	@ frame_needed = 0, uses_anonymous_args = 0
15451		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
15452		- .save {r4, r5, r6, r7, r8, r9, r10, lr}
15453		- mov r7, r0
15454		- ldr r6, .L2634
15455		- add r5, r7, #12
15456		- ldr r1, .L2634+4
15457		- .pad #32
15458		- sub sp, sp, #32
	15848	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	15849	+ .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	15850	+ mov r8, r0
	15851	+ ldr r7, .L2575
	15852	+ add r5, r8, #12
	15853	+ .pad #36
	15854	+ sub sp, sp, #36
	15855	+ ldr r1, .L2575+4
15459	15856	bl strcpy
	15857	+ ldr r2, [r7, #-2768]
15460	15858	mov r0, r5
15461		- ldr r1, .L2634+8
15462		- ldr r2, [r6, #-2772]
	15859	+ ldr r1, .L2575+8
15463	15860	bl sprintf
15464		- ldr r1, .L2634+12
15465		- ldr r2, [r6, #-1652]
15466	15861	add r5, r5, r0
	15862	+ ldr r2, [r7, #-1648]
15467	15863	mov r0, r5
	15864	+ ldr r1, .L2575+12
15468	15865	bl sprintf
15469		- ldr r3, .L2634+16
15470		- ldr r3, [r3, #3444]
	15866	+ ldr r3, .L2575+16
	15867	+ add r5, r5, r0
	15868	+ ldr r3, [r3, #3440]
15471	15869	cmp r3, #1
15472		- add r4, r5, r0
15473		- bne .L2629
15474		- add r0, sp, #16
15475		- add r1, sp, #20
15476		- add r2, sp, #24
	15870	+ subne r0, r5, r8
	15871	+ bne .L2562
15477	15872	add r3, sp, #28
	15873	+ add r2, sp, #24
	15874	+ add r1, sp, #20
	15875	+ add r0, sp, #16
15478	15876	bl NandcGetTimeCfg
15479		- mov r0, r4
15480		- ldr r1, .L2634+20
15481		- add r10, r6, #880
15482		- ldr r8, .L2634+24
15483		- add r9, r6, #816
15484		- ldr r3, [sp, #24]
15485		- ldr r2, [sp, #16]
15486		- str r3, [sp]
15487	15877	ldr r3, [sp, #28]
	15878	+ mov r0, r5
	15879	+ ldr r2, [sp, #16]
	15880	+ sub r4, r7, #1344
	15881	+ ldr r1, .L2575+20
	15882	+ add r9, r7, #880
15488	15883	str r3, [sp, #4]
	15884	+ ldr r3, [sp, #24]
	15885	+ str r3, [sp]
15489	15886	ldr r3, [sp, #20]
15490	15887	bl sprintf
15491		- ldr r1, .L2634+28
15492		- add r4, r4, r0
15493		- add r5, r4, #10
15494		- mov r0, r4
15495		- sub r4, r6, #1344
	15888	+ add r6, r5, r0
	15889	+ ldr r1, .L2575+24
	15890	+ mov r0, r6
	15891	+ add r6, r6, #10
15496	15892	bl strcpy
15497		- mov r0, r5
15498		- ldr r1, .L2634+32
15499		- ldr r2, [r6, #-1284]
	15893	+ ldr r2, [r7, #-1284]
	15894	+ mov r0, r6
	15895	+ ldr r1, .L2575+28
	15896	+ add r5, r7, #816
15500	15897	bl sprintf
15501		- ldr r1, .L2634+36
15502		- ldr r2, [r6, #1124]
15503		- add r5, r5, r0
15504		- mov r0, r5
	15898	+ add r6, r6, r0
	15899	+ ldr r2, [r7, #1124]
	15900	+ ldr r1, .L2575+32
	15901	+ mov r0, r6
15505	15902	bl sprintf
15506		- ldr r1, .L2634+40
15507		- ldr r2, [r6, #-1588]
15508		- add r5, r5, r0
15509		- mov r0, r5
	15903	+ add r6, r6, r0
	15904	+ ldr r2, [r7, #-1584]
	15905	+ ldr r1, .L2575+36
	15906	+ mov r0, r6
15510	15907	bl sprintf
15511		- ldr r1, .L2634+44
15512		- ldr r2, [r6, #-1600]
15513		- add r5, r5, r0
15514		- mov r0, r5
	15908	+ add r6, r6, r0
	15909	+ ldr r2, [r7, #-1596]
	15910	+ ldr r1, .L2575+40
	15911	+ mov r0, r6
15515	15912	bl sprintf
15516		- ldr r1, .L2634+48
15517		- ldr r2, [r6, #-1604]
15518		- add r5, r5, r0
15519		- mov r0, r5
	15913	+ add r6, r6, r0
	15914	+ ldr r2, [r7, #-1600]
	15915	+ ldr r1, .L2575+44
	15916	+ mov r0, r6
15520	15917	bl sprintf
15521		- ldr r1, .L2634+52
15522		- ldr r2, [r6, #-1596]
15523		- add r5, r5, r0
15524		- mov r0, r5
	15918	+ add r6, r6, r0
	15919	+ ldr r2, [r7, #-1592]
	15920	+ ldr r1, .L2575+48
	15921	+ mov r0, r6
15525	15922	bl sprintf
15526		- ldr r1, .L2634+56
15527		- ldr r2, [r6, #-1592]
15528		- add r5, r5, r0
15529		- mov r0, r5
	15923	+ add r6, r6, r0
	15924	+ ldr r2, [r7, #-1588]
	15925	+ ldr r1, .L2575+52
	15926	+ mov r0, r6
15530	15927	bl sprintf
15531		- ldr r1, .L2634+60
15532		- ldr r2, [r6, #-1608]
15533		- add r5, r5, r0
15534		- mov r0, r5
	15928	+ add r6, r6, r0
	15929	+ ldr r2, [r7, #-1604]
	15930	+ ldr r1, .L2575+56
	15931	+ mov r0, r6
15535	15932	bl sprintf
15536		- ldr r2, [r8, #1724]
15537		- ldr r1, .L2634+64
15538		- mov r2, r2, lsr #11
15539		- add r5, r5, r0
15540		- mov r0, r5
	15933	+ ldr r2, [r7, #1716]
	15934	+ add r6, r6, r0
	15935	+ ldr r1, .L2575+60
	15936	+ mov r0, r6
	15937	+ lsr r2, r2, #11
15541	15938	bl sprintf
15542		- ldr r2, [r8, #1728]
15543		- ldr r1, .L2634+68
15544		- mov r2, r2, lsr #11
15545		- add r5, r5, r0
15546		- mov r0, r5
	15939	+ ldr r2, [r7, #1720]
	15940	+ add r6, r6, r0
	15941	+ ldr r1, .L2575+64
	15942	+ mov r0, r6
	15943	+ lsr r2, r2, #11
15547	15944	bl sprintf
15548		- ldr r1, .L2634+72
15549		- ldr r2, [r6, #-1616]
15550		- add r5, r5, r0
15551		- mov r0, r5
	15945	+ add r6, r6, r0
	15946	+ ldr r2, [r7, #-1612]
	15947	+ ldr r1, .L2575+68
	15948	+ mov r0, r6
15552	15949	bl sprintf
15553		- ldr r1, .L2634+76
15554		- ldr r2, [r6, #-1612]
15555		- add r5, r5, r0
15556		- mov r0, r5
	15950	+ add r6, r6, r0
	15951	+ ldr r2, [r7, #-1608]
	15952	+ ldr r1, .L2575+72
	15953	+ mov r0, r6
15557	15954	bl sprintf
15558		- add r5, r5, r0
	15955	+ add r6, r6, r0
15559	15956	bl FtlBbtCalcTotleCnt
15560	15957	ldrh r2, [r4, #2]
15561		- ldr r1, .L2634+80
15562	15958	mov r3, r0
15563		- mov r0, r5
	15959	+ ldr r1, .L2575+76
	15960	+ mov r0, r6
15564	15961	bl sprintf
15565		- ldr r1, .L2634+84
15566		- ldrh r2, [r10]
15567		- add r5, r5, r0
15568		- mov r0, r5
	15962	+ add r6, r6, r0
	15963	+ ldrh r2, [r9]
	15964	+ ldr r1, .L2575+80
	15965	+ mov r0, r6
15569	15966	bl sprintf
15570		- ldr r1, .L2634+88
15571		- ldr r2, [r6, #-1584]
15572		- add r5, r5, r0
15573		- mov r0, r5
	15967	+ add r6, r6, r0
	15968	+ ldr r2, [r7, #-1580]
	15969	+ ldr r1, .L2575+84
	15970	+ mov r0, r6
15574	15971	bl sprintf
15575		- ldr r1, .L2634+92
15576		- ldr r2, [r6, #-1580]
15577		- add r5, r5, r0
15578		- mov r0, r5
	15972	+ add r6, r6, r0
	15973	+ ldr r2, [r7, #-1576]
	15974	+ ldr r1, .L2575+88
	15975	+ mov r0, r6
15579	15976	bl sprintf
15580		- ldr r1, .L2634+96
15581		- ldr r2, [r8, #1736]
15582		- add r5, r5, r0
15583		- mov r0, r5
	15977	+ add r6, r6, r0
	15978	+ ldr r2, [r7, #1728]
	15979	+ ldr r1, .L2575+92
	15980	+ mov r0, r6
15584	15981	bl sprintf
15585		- ldr r1, .L2634+100
15586		- ldr r2, [r6, #-1576]
15587		- add r5, r5, r0
15588		- mov r0, r5
	15982	+ add r6, r6, r0
	15983	+ ldr r2, [r7, #-1572]
	15984	+ ldr r1, .L2575+96
	15985	+ mov r0, r6
15589	15986	bl sprintf
15590		- ldr r1, .L2634+104
15591		- ldr r2, [r6, #-1572]
15592		- add r5, r5, r0
15593		- mov r0, r5
	15987	+ add r6, r6, r0
	15988	+ ldr r2, [r7, #-1568]
	15989	+ ldr r1, .L2575+100
	15990	+ mov r0, r6
15594	15991	bl sprintf
15595		- ldr r1, .L2634+108
15596		- ldr r2, [r6, #-1568]
15597		- add r5, r5, r0
15598		- mov r0, r5
	15992	+ add r6, r6, r0
	15993	+ ldr r2, [r7, #-1564]
	15994	+ ldr r1, .L2575+104
	15995	+ mov r0, r6
15599	15996	bl sprintf
15600		- ldrh r2, [r9, #30]
15601		- ldr r1, .L2634+112
15602		- add r5, r5, r0
15603		- mov r0, r5
	15997	+ add r6, r6, r0
	15998	+ ldrh r2, [r5, #30]
	15999	+ ldr r1, .L2575+108
	16000	+ mov r0, r6
15604	16001	bl sprintf
15605		- ldrh r2, [r9, #28]
15606		- ldr r1, .L2634+116
15607		- movw r9, #1164
15608		- add r5, r5, r0
15609		- mov r0, r5
	16002	+ add r6, r6, r0
	16003	+ ldrh r2, [r5, #28]
	16004	+ ldr r1, .L2575+112
	16005	+ mov r0, r6
15610	16006	bl sprintf
15611		- ldr r1, .L2634+120
15612		- ldr r2, [r6, #-2740]
15613		- add r5, r5, r0
15614		- mov r0, r5
	16007	+ add r6, r6, r0
	16008	+ ldr r2, [r7, #-2736]
	16009	+ ldr r1, .L2575+116
	16010	+ mov r0, r6
15615	16011	bl sprintf
15616		- ldr r1, .L2634+124
15617		- ldr r2, [r6, #-1636]
15618		- add r5, r5, r0
15619		- mov r0, r5
	16012	+ add r6, r6, r0
	16013	+ ldr r2, [r7, #-1632]
	16014	+ ldr r1, .L2575+120
	16015	+ mov r0, r6
15620	16016	bl sprintf
15621		- ldr r1, .L2634+128
15622		- ldr r2, [r6, #-1740]
15623		- add r5, r5, r0
15624		- mov r0, r5
	16017	+ add r6, r6, r0
	16018	+ ldr r2, [r7, #-1736]
	16019	+ ldr r1, .L2575+124
	16020	+ mov r0, r6
15625	16021	bl sprintf
	16022	+ add r6, r6, r0
15626	16023	ldrh r2, [r4, #110]
15627		- ldr r1, .L2634+132
15628		- add r5, r5, r0
15629		- mov r0, r5
	16024	+ ldr r1, .L2575+128
	16025	+ mov r0, r6
15630	16026	bl sprintf
15631		- sub r3, r6, #1728
15632		- ldr r1, .L2634+136
	16027	+ sub r3, r7, #1712
	16028	+ add r6, r6, r0
	16029	+ ldrh r2, [r3, #-12]
	16030	+ mov r0, r6
	16031	+ ldr r1, .L2575+132
	16032	+ movw r5, #1156
	16033	+ bl sprintf
	16034	+ add r3, r7, #1152
	16035	+ add r6, r6, r0
15633	16036	ldrh r2, [r3]
15634		- add r5, r5, r0
15635		- mov r0, r5
	16037	+ mov r0, r6
	16038	+ ldr r1, .L2575+136
15636	16039	bl sprintf
15637		- movw r3, #1160
15638		- ldrh r2, [r8, r3]
15639		- ldr r1, .L2634+140
15640		- add r5, r5, r0
15641		- mov r0, r5
15642		- bl sprintf
15643		- ldr r1, .L2634+144
15644		- ldr r2, [r6, #-1724]
15645		- add r5, r5, r0
15646		- mov r0, r5
	16040	+ add r6, r6, r0
	16041	+ ldr r2, [r7, #-1720]
	16042	+ ldr r1, .L2575+140
	16043	+ mov r0, r6
15647	16044	bl sprintf
15648	16045	movw r3, #1128
15649		- ldrh r2, [r6, r3]
15650		- ldr r1, .L2634+148
15651		- add r5, r5, r0
15652		- mov r0, r5
	16046	+ add r6, r6, r0
	16047	+ ldrh r2, [r7, r3]
	16048	+ mov r0, r6
	16049	+ ldr r1, .L2575+144
15653	16050	bl sprintf
	16051	+ add r6, r6, r0
15654	16052	ldrh r2, [r4, #-4]
15655		- ldr r1, .L2634+152
15656		- add r4, r6, #884
15657		- add r5, r5, r0
15658		- mov r0, r5
	16053	+ ldr r1, .L2575+148
	16054	+ mov r0, r6
15659	16055	bl sprintf
	16056	+ add r4, r7, #884
	16057	+ add r6, r6, r0
15660	16058	ldrh r2, [r4, #2]
15661		- ldr r1, .L2634+156
15662		- add r5, r5, r0
15663		- mov r0, r5
	16059	+ mov r0, r6
	16060	+ ldr r1, .L2575+152
15664	16061	bl sprintf
15665		- ldr r1, .L2634+160
15666		- ldrb r2, [r6, #890] @ zero_extendqisi2
15667		- add r5, r5, r0
15668		- mov r0, r5
	16062	+ add r6, r6, r0
	16063	+ ldrb r2, [r7, #890] @ zero_extendqisi2
	16064	+ ldr r1, .L2575+156
	16065	+ mov r0, r6
15669	16066	bl sprintf
	16067	+ add r6, r6, r0
15670	16068	ldrh r2, [r4]
15671		- ldr r1, .L2634+164
15672		- add r5, r5, r0
15673		- mov r0, r5
	16069	+ ldr r1, .L2575+160
	16070	+ mov r0, r6
15674	16071	bl sprintf
15675		- ldr r1, .L2634+168
15676		- ldrb r2, [r6, #892] @ zero_extendqisi2
15677		- add r5, r5, r0
15678		- mov r0, r5
	16072	+ add r6, r6, r0
	16073	+ ldrb r2, [r7, #892] @ zero_extendqisi2
	16074	+ ldr r1, .L2575+164
	16075	+ mov r0, r6
15679	16076	bl sprintf
	16077	+ add r6, r6, r0
15680	16078	ldrh r2, [r4, #4]
15681		- ldr r1, .L2634+172
15682		- add r5, r5, r0
15683		- mov r0, r5
	16079	+ ldr r1, .L2575+168
	16080	+ mov r0, r6
15684	16081	bl sprintf
15685	16082	ldrh r3, [r4]
15686		- ldr r2, [r6, #-1408]
15687		- add r4, r6, #932
15688		- ldr r1, .L2634+176
15689		- mov r3, r3, asl #1
	16083	+ add r6, r6, r0
	16084	+ ldr r2, [r7, #-1404]
	16085	+ mov r0, r6
	16086	+ ldr r1, .L2575+172
	16087	+ add r4, r7, #932
	16088	+ lsl r3, r3, #1
15690	16089	ldrh r2, [r2, r3]
15691		- add r5, r5, r0
15692		- mov r0, r5
15693	16090	bl sprintf
	16091	+ add r6, r6, r0
15694	16092	ldrh r2, [r4, #2]
15695		- ldr r1, .L2634+180
15696		- add r5, r5, r0
15697		- mov r0, r5
	16093	+ ldr r1, .L2575+176
	16094	+ mov r0, r6
15698	16095	bl sprintf
15699		- ldr r1, .L2634+184
15700		- ldrb r2, [r6, #938] @ zero_extendqisi2
15701		- add r5, r5, r0
15702		- mov r0, r5
	16096	+ add r6, r6, r0
	16097	+ ldrb r2, [r7, #938] @ zero_extendqisi2
	16098	+ ldr r1, .L2575+180
	16099	+ mov r0, r6
15703	16100	bl sprintf
	16101	+ add r6, r6, r0
15704	16102	ldrh r2, [r4]
15705		- ldr r1, .L2634+188
15706		- add r5, r5, r0
15707		- mov r0, r5
	16103	+ ldr r1, .L2575+184
	16104	+ mov r0, r6
15708	16105	bl sprintf
15709		- ldr r1, .L2634+192
15710		- ldrb r2, [r6, #940] @ zero_extendqisi2
15711		- add r5, r5, r0
15712		- mov r0, r5
	16106	+ add r6, r6, r0
	16107	+ ldrb r2, [r7, #940] @ zero_extendqisi2
	16108	+ ldr r1, .L2575+188
	16109	+ mov r0, r6
15713	16110	bl sprintf
	16111	+ add r6, r6, r0
15714	16112	ldrh r2, [r4, #4]
15715		- ldr r1, .L2634+196
15716		- add r5, r5, r0
15717		- mov r0, r5
	16113	+ ldr r1, .L2575+192
	16114	+ mov r0, r6
15718	16115	bl sprintf
15719	16116	ldrh r3, [r4]
15720		- ldr r2, [r6, #-1408]
15721		- add r4, r6, #980
15722		- ldr r1, .L2634+200
15723		- mov r3, r3, asl #1
	16117	+ add r6, r6, r0
	16118	+ ldr r2, [r7, #-1404]
	16119	+ mov r0, r6
	16120	+ ldr r1, .L2575+196
	16121	+ add r4, r7, #980
	16122	+ lsl r3, r3, #1
15724	16123	ldrh r2, [r2, r3]
15725		- add r5, r5, r0
15726		- mov r0, r5
15727	16124	bl sprintf
	16125	+ add r6, r6, r0
15728	16126	ldrh r2, [r4, #2]
15729		- ldr r1, .L2634+204
15730		- add r5, r5, r0
15731		- mov r0, r5
	16127	+ ldr r1, .L2575+200
	16128	+ mov r0, r6
15732	16129	bl sprintf
15733		- ldr r1, .L2634+208
15734		- ldrb r2, [r6, #986] @ zero_extendqisi2
15735		- add r5, r5, r0
15736		- mov r0, r5
	16130	+ add r6, r6, r0
	16131	+ ldrb r2, [r7, #986] @ zero_extendqisi2
	16132	+ ldr r1, .L2575+204
	16133	+ mov r0, r6
15737	16134	bl sprintf
	16135	+ add r6, r6, r0
15738	16136	ldrh r2, [r4]
15739		- ldr r1, .L2634+212
15740		- add r5, r5, r0
15741		- mov r0, r5
	16137	+ ldr r1, .L2575+208
	16138	+ mov r0, r6
15742	16139	bl sprintf
15743		- ldr r1, .L2634+216
15744		- ldrb r2, [r6, #988] @ zero_extendqisi2
15745		- add r5, r5, r0
15746		- mov r0, r5
	16140	+ add r6, r6, r0
	16141	+ ldrb r2, [r7, #988] @ zero_extendqisi2
	16142	+ ldr r1, .L2575+212
	16143	+ mov r0, r6
15747	16144	bl sprintf
	16145	+ add r6, r6, r0
15748	16146	ldrh r2, [r4, #4]
15749		- ldr r1, .L2634+220
15750		- ldr r4, .L2634+224
15751		- add r5, r5, r0
15752		- mov r0, r5
	16147	+ ldr r1, .L2575+216
	16148	+ mov r0, r6
15753	16149	bl sprintf
15754		- ldrh r2, [r4, #2]
15755		- ldr r1, .L2634+228
15756		- add r5, r5, r0
15757		- mov r0, r5
	16150	+ add r6, r6, r0
	16151	+ ldrh r2, [r4, #178]
	16152	+ ldr r1, .L2575+220
	16153	+ mov r0, r6
15758	16154	bl sprintf
15759		- ldr r1, .L2634+232
15760		- ldrb r2, [r8, #1170] @ zero_extendqisi2
15761		- add r5, r5, r0
15762		- mov r0, r5
	16155	+ add r6, r6, r0
	16156	+ ldrb r2, [r7, #1162] @ zero_extendqisi2
	16157	+ ldr r1, .L2575+224
	16158	+ mov r0, r6
15763	16159	bl sprintf
15764		- ldr r1, .L2634+236
15765		- ldrh r2, [r8, r9]
15766		- add r5, r5, r0
15767		- mov r0, r5
	16160	+ add r6, r6, r0
	16161	+ ldrh r2, [r7, r5]
	16162	+ ldr r1, .L2575+228
	16163	+ mov r0, r6
15768	16164	bl sprintf
15769		- ldr r1, .L2634+240
15770		- ldrb r2, [r8, #1172] @ zero_extendqisi2
15771		- add r5, r5, r0
15772		- mov r0, r5
	16165	+ add r6, r6, r0
	16166	+ ldrb r2, [r7, #1164] @ zero_extendqisi2
	16167	+ ldr r1, .L2575+232
	16168	+ mov r0, r6
15773	16169	bl sprintf
15774		- ldrh r2, [r4, #4]
15775		- ldr r1, .L2634+244
15776		- add r5, r5, r0
15777		- mov r0, r5
	16170	+ add r6, r6, r0
	16171	+ ldrh r2, [r4, #180]
	16172	+ ldr r1, .L2575+236
	16173	+ mov r0, r6
15778	16174	bl sprintf
15779		- ldr r1, [r8, #1296]
15780		- ldr r2, [r6, #-1620]
15781		- ldr r3, [r6, #-1872]
15782		- orr r2, r3, r2, asl #8
15783		- str r1, [sp]
15784		- add r5, r5, r0
15785		- ldr r1, [r8, #1288]
15786		- mov r0, r5
15787		- str r1, [sp, #4]
15788		- ldr r1, .L2634+248
15789		- ldr r3, [r8, #1292]
	16175	+ ldr r3, [r7, #1280]
	16176	+ add r6, r6, r0
	16177	+ ldr r1, [r7, #-1616]
	16178	+ mov r0, r6
	16179	+ ldr r2, [r7, #-1868]
	16180	+ str r3, [sp, #4]
	16181	+ ldr r3, [r7, #1288]
	16182	+ orr r2, r2, r1, lsl #8
	16183	+ ldr r1, .L2575+240
	16184	+ str r3, [sp]
	16185	+ ldr r3, [r7, #1284]
15790	16186	bl sprintf
15791		- ldr r1, .L2634+252
15792		- ldr r2, [r8, #1284]
15793		- add r4, r5, r0
15794		- sub r5, r6, #1520
	16187	+ add r4, r6, r0
	16188	+ ldr r2, [r7, #1276]
	16189	+ ldr r1, .L2575+244
15795	16190	mov r0, r4
15796	16191	bl sprintf
15797		- ldr r1, .L2634+256
15798		- ldr r2, [r8, #1308]
15799	16192	add r4, r4, r0
	16193	+ ldr r2, [r7, #1300]
	16194	+ ldr r1, .L2575+248
15800	16195	mov r0, r4
15801	16196	bl sprintf
15802		- ldr r1, .L2634+260
15803		- ldrh r2, [r5, #-12]
	16197	+ sub r6, r7, #1520
15804	16198	add r4, r4, r0
	16199	+ ldrh r2, [r6, #-8]
	16200	+ mov r0, r4
	16201	+ ldr r1, .L2575+252
	16202	+ bl sprintf
	16203	+ add r4, r4, r0
	16204	+ ldrh r2, [r6, #-6]
	16205	+ ldr r1, .L2575+256
15805	16206	mov r0, r4
15806	16207	bl sprintf
15807		- ldr r1, .L2634+264
15808		- ldrh r2, [r5, #-10]
15809	16208	add r4, r4, r0
	16209	+ ldr r2, [r7, #-1544]
	16210	+ ldr r1, .L2575+260
15810	16211	mov r0, r4
15811	16212	bl sprintf
15812		- ldr r1, .L2634+268
15813		- ldr r2, [r6, #-1548]
15814	16213	add r4, r4, r0
15815		- mov r0, r4
15816		- bl sprintf
15817		- ldr r1, .L2634+272
15818		- ldrh r2, [r5, #-8]
15819		- add r4, r4, r0
	16214	+ ldrh r2, [r6, #-4]
	16215	+ ldr r1, .L2575+264
15820	16216	mov r0, r4
15821	16217	bl sprintf
15822	16218	add r4, r4, r0
15823	16219	bl GetFreeBlockMinEraseCount
15824		- ldr r1, .L2634+276
	16220	+ ldr r1, .L2575+268
15825	16221	mov r2, r0
15826	16222	mov r0, r4
15827	16223	bl sprintf
15828	16224	add r4, r4, r0
15829		- ldrh r0, [r10]
	16225	+ ldrh r0, [r9]
15830	16226	bl GetFreeBlockMaxEraseCount
15831		- ldr r1, .L2634+280
	16227	+ ldr r1, .L2575+272
15832	16228	mov r2, r0
15833	16229	mov r0, r4
15834	16230	bl sprintf
15835		- ldrh r3, [r8, r9]
	16231	+ ldrh r3, [r7, r5]
15836	16232	movw r2, #65535
15837		- cmp r3, r2
15838	16233	add r4, r4, r0
15839		- beq .L2626
15840		- ldr r2, [r6, #-1408]
15841		- mov r3, r3, asl #1
	16234	+ cmp r3, r2
	16235	+ beq .L2565
	16236	+ ldr r2, [r7, #-1404]
	16237	+ lsl r3, r3, #1
15842	16238	mov r0, r4
15843		- ldr r1, .L2634+284
	16239	+ ldr r1, .L2575+276
15844	16240	ldrh r2, [r2, r3]
15845	16241	bl sprintf
15846	16242	add r4, r4, r0
15847		-.L2626:
	16243	+.L2565:
15848	16244	mov r0, #0
15849		- mov r5, #0
	16245	+ ldr r9, .L2575+280
15850	16246	bl List_get_gc_head_node
15851		- movw r10, #65535
15852		- mov r9, #6
15853	16247	uxth r3, r0
15854		-.L2628:
15855		- cmp r3, r10
15856		- beq .L2627
15857		- ldr r2, [r6, #-1408]
15858		- mov r1, r3, asl #1
15859		- mul r8, r9, r3
	16248	+ mov r5, #0
	16249	+ movw fp, #65535
	16250	+ mov r10, #6
	16251	+.L2567:
	16252	+ cmp r3, fp
	16253	+ beq .L2566
	16254	+ ldr r2, [r7, #-1412]
	16255	+ lsl r1, r3, #1
	16256	+ mul r6, r10, r3
15860	16257	mov r0, r4
15861	16258	ldrh r2, [r2, r1]
15862		- str r2, [sp]
15863		- ldr r2, [r6, #-1356]
15864		- add r2, r2, r8
	16259	+ str r2, [sp, #8]
	16260	+ ldr r2, [r7, #-1356]
	16261	+ add r2, r2, r6
15865	16262	ldrh r2, [r2, #4]
15866	16263	str r2, [sp, #4]
15867		- ldr r2, [r6, #-1416]
	16264	+ ldr r2, [r7, #-1404]
15868	16265	ldrh r2, [r2, r1]
15869		- ldr r1, .L2634+288
15870		- str r2, [sp, #8]
	16266	+ mov r1, r9
	16267	+ str r2, [sp]
15871	16268	mov r2, r5
15872	16269	bl sprintf
15873	16270	add r5, r5, #1
15874		- ldr r3, [r6, #-1356]
	16271	+ ldr r3, [r7, #-1356]
15875	16272	cmp r5, #16
15876		- ldrh r3, [r3, r8]
15877	16273	add r4, r4, r0
15878		- bne .L2628
15879		-.L2627:
15880		- ldr r2, [r6, #-1356]
	16274	+ ldrh r3, [r3, r6]
	16275	+ bne .L2567
	16276	+.L2566:
	16277	+ ldr r2, [r7, #-1356]
15881	16278	mov r5, #0
15882		- ldr r3, [r6, #876]
15883		- movw r10, #65535
15884		- mov r9, #6
15885		- rsb r3, r2, r3
15886		- ldr r2, .L2634+292
15887		- mov r3, r3, asr #1
	16279	+ ldr r3, [r7, #876]
	16280	+ movw r9, #65535
	16281	+ ldr fp, .L2575+284
	16282	+ mov r10, #6
	16283	+ sub r3, r3, r2
	16284	+ ldr r2, .L2575+288
	16285	+ asr r3, r3, #1
15888	16286	mul r3, r2, r3
15889	16287	uxth r3, r3
15890		-.L2630:
15891		- cmp r3, r10
15892		- beq .L2629
15893		- mul r8, r9, r3
15894		- ldr r2, [r6, #-1356]
15895		- ldr r1, [r6, #-1416]
	16288	+.L2569:
	16289	+ cmp r3, r9
	16290	+ beq .L2568
	16291	+ ldr r1, [r7, #-1412]
	16292	+ lsl r2, r3, #1
	16293	+ mul r6, r10, r3
15896	16294	mov r0, r4
15897		- add r2, r2, r8
	16295	+ ldrh r2, [r1, r2]
	16296	+ mov r1, fp
	16297	+ str r2, [sp, #4]
	16298	+ ldr r2, [r7, #-1356]
	16299	+ add r2, r2, r6
15898	16300	ldrh r2, [r2, #4]
15899	16301	str r2, [sp]
15900		- mov r2, r3, asl #1
15901		- ldrh r2, [r1, r2]
15902		- ldr r1, .L2634+296
15903		- str r2, [sp, #4]
15904	16302	mov r2, r5
15905		- bl sprintf
15906	16303	add r5, r5, #1
15907		- ldr r3, [r6, #-1356]
	16304	+ bl sprintf
15908	16305	cmp r5, #4
15909		- ldrh r3, [r3, r8]
15910	16306	add r4, r4, r0
15911		- bne .L2630
15912		-.L2629:
15913		- rsb r0, r7, r4
15914		- add sp, sp, #32
	16307	+ ldrne r3, [r7, #-1356]
	16308	+ ldrhne r3, [r3, r6]
	16309	+ bne .L2569
	16310	+.L2568:
	16311	+ sub r0, r4, r8
	16312	+.L2562:
	16313	+ add sp, sp, #36
15915	16314	@ sp needed
15916		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
15917		-.L2635:
	16315	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	16316	+.L2576:
15918	16317	.align 2
15919		-.L2634:
	16318	+.L2575:
15920	16319	.word .LANCHOR2
15921	16320	.word .LC75
15922	16321	.word .LC76
15923	16322	.word .LC77
15924	16323	.word .LANCHOR1
15925	16324	.word .LC78
15926		- .word .LANCHOR4
15927	16325	.word .LC79
15928	16326	.word .LC80
15929	16327	.word .LC81
..	..	@@ -15973,7 +16371,6 @@
15973	16371	.word .LC125
15974	16372	.word .LC126
15975	16373	.word .LC127
15976		- .word .LANCHOR4+1164
15977	16374	.word .LC128
15978	16375	.word .LC129
15979	16376	.word .LC130
..	..	@@ -15990,236 +16387,239 @@
15990	16387	.word .LC141
15991	16388	.word .LC142
15992	16389	.word .LC143
15993		- .word -1431655765
15994	16390	.word .LC144
	16391	+ .word -1431655765
15995	16392	.fnend
15996	16393	.size FtlPrintInfo2buf, .-FtlPrintInfo2buf
15997	16394	.align 2
15998	16395	.global ftl_proc_ftl_read
	16396	+ .syntax unified
	16397	+ .arm
	16398	+ .fpu softvfp
15999	16399	.type ftl_proc_ftl_read, %function
16000	16400	ftl_proc_ftl_read:
16001	16401	.fnstart
16002	16402	@ args = 0, pretend = 0, frame = 0
16003	16403	@ frame_needed = 0, uses_anonymous_args = 0
16004		- stmfd sp!, {r3, r4, r5, lr}
16005		- .save {r3, r4, r5, lr}
	16404	+ push {r4, r5, r6, lr}
	16405	+ .save {r4, r5, r6, lr}
16006	16406	mov r5, r0
16007		- ldr r1, .L2638
16008		- ldr r2, .L2638+4
	16407	+ ldr r2, .L2579
	16408	+ ldr r1, .L2579+4
16009	16409	bl sprintf
16010	16410	add r4, r5, r0
16011	16411	mov r0, r4
16012	16412	bl FtlPrintInfo2buf
16013	16413	add r0, r4, r0
16014		- rsb r0, r5, r0
16015		- ldmfd sp!, {r3, r4, r5, pc}
16016		-.L2639:
	16414	+ sub r0, r0, r5
	16415	+ pop {r4, r5, r6, pc}
	16416	+.L2580:
16017	16417	.align 2
16018		-.L2638:
16019		- .word .LC48
	16418	+.L2579:
16020	16419	.word .LC145
	16420	+ .word .LC49
16021	16421	.fnend
16022	16422	.size ftl_proc_ftl_read, .-ftl_proc_ftl_read
16023	16423	.align 2
16024	16424	.global GetSwlReplaceBlock
	16425	+ .syntax unified
	16426	+ .arm
	16427	+ .fpu softvfp
16025	16428	.type GetSwlReplaceBlock, %function
16026	16429	GetSwlReplaceBlock:
16027	16430	.fnstart
16028	16431	@ args = 0, pretend = 0, frame = 8
16029	16432	@ frame_needed = 0, uses_anonymous_args = 0
16030		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	16433	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
16031	16434	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
16032	16435	.pad #28
16033	16436	sub sp, sp, #28
16034		- ldr r5, .L2670
16035		- ldr r4, .L2670+4
16036		- ldr r6, [r5, #1736]
16037		- ldr r3, [r4, #-1568]
16038		- cmp r6, r3
16039		- bcs .L2641
16040		- sub r3, r4, #1728
16041		- mov r6, #0
16042		- str r6, [r4, #-1584]
16043		- ldrh r1, [r3]
16044		- ldr r3, [r4, #-1416]
16045		- sub r3, r3, #2
16046		-.L2642:
16047		- cmp r6, r1
16048		- bcs .L2669
16049		- ldrh r2, [r3, #2]!
16050		- add r6, r6, #1
16051		- ldr r0, [r4, #-1584]
16052		- add r2, r2, r0
16053		- str r2, [r4, #-1584]
16054		- b .L2642
16055		-.L2669:
16056		- ldr r6, [r4, #-1584]
16057		- mov r0, r6
16058		- bl __aeabi_uidiv
16059		- ldr r3, .L2670+8
16060		- ldrh r1, [r3, #-12]
16061		- str r0, [r5, #1736]
16062		- ldr r0, [r4, #-1580]
16063		- rsb r0, r0, r6
16064		- bl __aeabi_uidiv
16065		- str r0, [r4, #-1584]
16066		- b .L2644
16067		-.L2641:
16068		- ldr r3, [r4, #-1572]
16069		- cmp r6, r3
16070		- bls .L2644
16071		- add r3, r3, #1
16072		- mov ip, r4
16073		- str r3, [r4, #-1572]
	16437	+ ldr r4, .L2609
	16438	+ ldr r2, [r4, #1728]
	16439	+ ldr r3, [r4, #-1564]
	16440	+ cmp r2, r3
	16441	+ bcs .L2582
	16442	+ sub r2, r4, #1712
16074	16443	mov r3, #0
16075		-.L2646:
16076		- ldr r2, .L2670+12
16077		- ldrh r2, [r2]
16078		- cmp r3, r2
16079		- bcs .L2644
16080		- ldr r0, [ip, #-1416]
16081		- mov r1, r3, asl #1
16082		- add r3, r3, #1
16083		- ldrh r2, [r0, r1]
16084		- add r2, r2, #1
16085		- strh r2, [r0, r1] @ movhi
16086		- b .L2646
16087		-.L2644:
16088		- ldr r6, [r4, #-1568]
16089		- ldr r8, [r5, #1736]
16090		- add r3, r6, #256
16091		- ldr r2, .L2670+4
16092		- cmp r3, r8
16093		- bls .L2649
16094		- ldr r1, [r2, #-1572]
16095		- add r3, r6, #768
	16444	+ ldrh r1, [r2, #-12]
	16445	+ ldr r2, [r4, #-1412]
	16446	+ str r3, [r4, #-1580]
	16447	+ sub r2, r2, #2
	16448	+.L2583:
16096	16449	cmp r3, r1
16097		- bls .L2649
16098		- cmp r6, #40
16099		- ldr r2, [r2, #-1872]
	16450	+ bcc .L2584
	16451	+ ldr r5, [r4, #-1580]
	16452	+ mov r0, r5
	16453	+ bl __aeabi_uidiv
	16454	+ ldr r3, .L2609+4
	16455	+ str r0, [r4, #1728]
	16456	+ ldr r0, [r4, #-1576]
	16457	+ ldrh r1, [r3, #-10]
	16458	+ sub r0, r5, r0
	16459	+ bl __aeabi_uidiv
	16460	+ str r0, [r4, #-1580]
	16461	+.L2585:
	16462	+ ldr r5, [r4, #-1564]
	16463	+ ldr r8, [r4, #1728]
	16464	+ add r3, r5, #256
	16465	+ cmp r3, r8
	16466	+ bls .L2590
	16467	+ ldr r2, [r4, #-1568]
	16468	+ add r3, r5, #768
	16469	+ cmp r3, r2
	16470	+ bls .L2590
	16471	+ ldr r2, [r4, #-1868]
	16472	+ cmp r5, #40
16100	16473	movls r3, #0
16101	16474	movhi r3, #1
16102	16475	cmp r2, #0
16103	16476	orreq r3, r3, #1
16104	16477	cmp r3, #0
16105		- beq .L2649
16106		-.L2651:
16107		- movw r0, #65535
16108		- b .L2650
16109		-.L2649:
16110		- ldr r10, .L2670+4
16111		- add r3, r10, #880
16112		- ldrh r0, [r3]
16113		- add r0, r0, r0, asl #1
16114		- ubfx r0, r0, #2, #16
16115		- bl GetFreeBlockMaxEraseCount
16116		- add r1, r6, #64
16117		- cmp r0, r1
16118		- mov r9, r0
16119		- movcs r1, #0
16120		- movcc r1, #1
16121		- cmp r6, #40
16122		- movls r1, #0
16123		- cmp r1, #0
16124		- bne .L2651
16125		- ldr r3, [r10, #864]
16126		- cmp r3, #0
16127		- beq .L2651
16128		- sub r2, r10, #1728
16129		- ldr r0, [r10, #-1356]
16130		- ldr ip, .L2670+16
16131		- movw r7, #65535
16132		- ldrh r2, [r2]
16133		- mov r5, r7
16134		- ldr r10, [r10, #-1416]
16135		- mov lr, #6
16136		- str r2, [sp, #20]
16137		-.L2652:
16138		- ldrh r2, [r3]
16139		- movw fp, #65535
16140		- cmp r2, fp
16141		- beq .L2654
16142		- add r1, r1, #1
16143		- ldr fp, [sp, #20]
16144		- uxth r1, r1
16145		- cmp r1, fp
16146		- bhi .L2651
16147		- ldrh fp, [r3, #4]
16148		- cmp fp, #0
16149		- beq .L2653
16150		- rsb r3, r0, r3
16151		- mov r3, r3, asr #1
16152		- mul r3, ip, r3
16153		- uxth r3, r3
16154		- mov fp, r3, asl #1
16155		- ldrh fp, [r10, fp]
16156		- cmp fp, r6
16157		- bls .L2658
16158		- cmp fp, r7
16159		- movcc r7, fp
16160		- movcc r5, r3
16161		-.L2653:
16162		- mla r3, lr, r2, r0
16163		- b .L2652
16164		-.L2658:
16165		- mov r5, r3
16166		-.L2654:
16167		- movw r3, #65535
16168		- cmp r5, r3
16169		- beq .L2651
16170		- mov r3, r5, asl #1
16171		- ldrh fp, [r10, r3]
16172		- cmp fp, r6
16173		- bls .L2656
16174		- str r3, [sp, #20]
16175		- bl GetFreeBlockMinEraseCount
16176		- ldr r3, [sp, #20]
16177		- cmp r0, r6
16178		- strhi r7, [r4, #-1568]
16179		-.L2656:
16180		- cmp fp, r8
16181		- bcs .L2651
16182		- add r2, fp, #128
16183		- cmp r9, r2
16184		- ble .L2651
16185		- add r2, fp, #256
16186		- cmp r2, r8
16187		- bcc .L2657
16188		- ldr r2, [r4, #-1572]
16189		- add fp, fp, #768
16190		- cmp fp, r2
16191		- bcs .L2651
16192		-.L2657:
16193		- ldr r2, [r4, #-1408]
16194		- mov r1, r5
16195		- ldr r0, .L2670+20
16196		- ldrh r2, [r2, r3]
16197		- str r2, [sp]
16198		- mov r2, r8
16199		- ldrh r3, [r10, r3]
16200		- stmib sp, {r3, r9}
16201		- ldr r3, [r4, #-1572]
16202		- bl printk
16203		- mov r0, r5
16204		- mov r3, #1
16205		- str r3, [r4, #-1560]
16206		-.L2650:
	16478	+ beq .L2590
	16479	+.L2592:
	16480	+ movw r6, #65535
	16481	+.L2591:
	16482	+ mov r0, r6
16207	16483	add sp, sp, #28
16208	16484	@ sp needed
16209		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
16210		-.L2671:
	16485	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	16486	+.L2584:
	16487	+ ldrh r0, [r2, #2]!
	16488	+ add r3, r3, #1
	16489	+ ldr ip, [r4, #-1580]
	16490	+ add r0, r0, ip
	16491	+ str r0, [r4, #-1580]
	16492	+ b .L2583
	16493	+.L2582:
	16494	+ ldr r3, [r4, #-1568]
	16495	+ cmp r2, r3
	16496	+ addhi r3, r3, #1
	16497	+ strhi r3, [r4, #-1568]
	16498	+ movhi r3, #0
	16499	+ bls .L2585
	16500	+.L2587:
	16501	+ ldr r2, .L2609+8
	16502	+ ldrh r2, [r2]
	16503	+ cmp r3, r2
	16504	+ bcs .L2585
	16505	+ ldr r0, [r4, #-1412]
	16506	+ lsl r1, r3, #1
	16507	+ add r3, r3, #1
	16508	+ ldrh r2, [r0, r1]
	16509	+ add r2, r2, #1
	16510	+ strh r2, [r0, r1] @ movhi
	16511	+ b .L2587
	16512	+.L2590:
	16513	+ ldr r6, .L2609+12
	16514	+ ldrh r0, [r6]
	16515	+ add r0, r0, r0, lsl #1
	16516	+ ubfx r0, r0, #2, #16
	16517	+ bl GetFreeBlockMaxEraseCount
	16518	+ add r1, r5, #64
	16519	+ mov r10, r0
	16520	+ cmp r0, r1
	16521	+ movcs r1, #0
	16522	+ movcc r1, #1
	16523	+ cmp r5, #40
	16524	+ movls r1, #0
	16525	+ cmp r1, #0
	16526	+ bne .L2592
	16527	+ ldr r3, [r4, #864]
	16528	+ cmp r3, #0
	16529	+ beq .L2592
	16530	+ sub r6, r6, #2592
	16531	+ ldr ip, [r4, #-1356]
	16532	+ ldrh r2, [r6, #-12]
	16533	+ movw r7, #65535
	16534	+ ldr r9, [r4, #-1412]
	16535	+ mov fp, #6
	16536	+ ldr lr, .L2609+16
	16537	+ str r2, [sp, #20]
	16538	+ mov r2, r7
	16539	+.L2593:
	16540	+ ldrh r0, [r3]
	16541	+ movw r6, #65535
	16542	+ cmp r0, r6
	16543	+ bne .L2596
	16544	+ mov r6, r2
	16545	+.L2595:
	16546	+ movw r3, #65535
	16547	+ cmp r6, r3
	16548	+ beq .L2592
	16549	+ lsl fp, r6, #1
	16550	+ ldrh r1, [r9, fp]
	16551	+ cmp r5, r1
	16552	+ bcs .L2597
	16553	+ bl GetFreeBlockMinEraseCount
	16554	+ cmp r5, r0
	16555	+ strcc r7, [r4, #-1564]
	16556	+.L2597:
	16557	+ cmp r8, r1
	16558	+ bls .L2592
	16559	+ add r3, r1, #128
	16560	+ cmp r10, r3
	16561	+ ble .L2592
	16562	+ add r3, r1, #256
	16563	+ cmp r8, r3
	16564	+ bhi .L2598
	16565	+ ldr r3, [r4, #-1568]
	16566	+ add r1, r1, #768
	16567	+ cmp r1, r3
	16568	+ bcs .L2592
	16569	+.L2598:
	16570	+ str r10, [sp, #8]
	16571	+ mov r2, r8
	16572	+ ldrh r3, [r9, fp]
	16573	+ mov r1, r6
	16574	+ ldr r0, .L2609+20
	16575	+ str r3, [sp, #4]
	16576	+ ldr r3, [r4, #-1404]
	16577	+ ldrh r3, [r3, fp]
	16578	+ str r3, [sp]
	16579	+ ldr r3, [r4, #-1568]
	16580	+ bl printk
	16581	+ mov r3, #1
	16582	+ str r3, [r4, #-1556]
	16583	+ b .L2591
	16584	+.L2596:
	16585	+ add r1, r1, #1
	16586	+ ldr r6, [sp, #20]
	16587	+ uxth r1, r1
	16588	+ cmp r1, r6
	16589	+ bhi .L2592
	16590	+ ldrh r6, [r3, #4]
	16591	+ cmp r6, #0
	16592	+ beq .L2594
	16593	+ sub r3, r3, ip
	16594	+ asr r3, r3, #1
	16595	+ mul r3, lr, r3
	16596	+ uxth r6, r3
	16597	+ lsl r3, r6, #1
	16598	+ ldrh r3, [r9, r3]
	16599	+ cmp r5, r3
	16600	+ bcs .L2595
	16601	+ cmp r7, r3
	16602	+ movhi r7, r3
	16603	+ movhi r2, r6
	16604	+.L2594:
	16605	+ mla r3, fp, r0, ip
	16606	+ b .L2593
	16607	+.L2610:
16211	16608	.align 2
16212		-.L2670:
16213		- .word .LANCHOR4
	16609	+.L2609:
16214	16610	.word .LANCHOR2
16215	16611	.word .LANCHOR2-1664
16216		- .word .LANCHOR2-1728
	16612	+ .word .LANCHOR2-1724
	16613	+ .word .LANCHOR2+880
16217	16614	.word -1431655765
16218	16615	.word .LC146
16219	16616	.fnend
16220	16617	.size GetSwlReplaceBlock, .-GetSwlReplaceBlock
16221	16618	.align 2
16222	16619	.global free_data_superblock
	16620	+ .syntax unified
	16621	+ .arm
	16622	+ .fpu softvfp
16223	16623	.type free_data_superblock, %function
16224	16624	free_data_superblock:
16225	16625	.fnstart
..	..	@@ -16227,1366 +16627,1361 @@
16227	16627	@ frame_needed = 0, uses_anonymous_args = 0
16228	16628	movw r2, #65535
16229	16629	cmp r0, r2
16230		- stmfd sp!, {r3, lr}
16231		- .save {r3, lr}
16232		- beq .L2673
16233		- ldr r2, .L2675
16234		- mov r3, r0, asl #1
	16630	+ beq .L2614
	16631	+ ldr r2, .L2617
	16632	+ lsl r3, r0, #1
	16633	+ push {r4, lr}
	16634	+ .save {r4, lr}
16235	16635	mov r1, #0
16236		- ldr r2, [r2, #-1408]
	16636	+ ldr r2, [r2, #-1404]
16237	16637	strh r1, [r2, r3] @ movhi
16238	16638	bl INSERT_FREE_LIST
16239		-.L2673:
16240	16639	mov r0, #0
16241		- ldmfd sp!, {r3, pc}
16242		-.L2676:
	16640	+ pop {r4, pc}
	16641	+.L2614:
	16642	+ mov r0, #0
	16643	+ bx lr
	16644	+.L2618:
16243	16645	.align 2
16244		-.L2675:
	16646	+.L2617:
16245	16647	.word .LANCHOR2
16246	16648	.fnend
16247	16649	.size free_data_superblock, .-free_data_superblock
16248	16650	.align 2
16249	16651	.global allocate_data_superblock
	16652	+ .syntax unified
	16653	+ .arm
	16654	+ .fpu softvfp
16250	16655	.type allocate_data_superblock, %function
16251	16656	allocate_data_superblock:
16252	16657	.fnstart
16253	16658	@ args = 0, pretend = 0, frame = 16
16254	16659	@ frame_needed = 0, uses_anonymous_args = 0
16255		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	16660	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
16256	16661	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
16257	16662	.pad #20
16258	16663	sub sp, sp, #20
16259		- ldr r4, .L2732
	16664	+ ldr r4, .L2669
16260	16665	ldr r3, [r4, #-1280]
16261	16666	cmp r3, #0
16262		- bne .L2678
16263		- sub r10, r4, #1728
	16667	+ bne .L2620
16264	16668	mov r5, r0
16265		- mov r6, r4
16266		-.L2679:
16267		- ldr r7, .L2732+4
	16669	+.L2621:
	16670	+ ldr r3, .L2669+4
16268	16671	ldrb r2, [r5, #8] @ zero_extendqisi2
16269		- cmp r5, r7
16270		- bne .L2680
16271		- ldrh r3, [r7, #-100]
16272		- ldr ip, [r6, #-1560]
16273		- mov r0, r3, lsr #1
	16672	+ cmp r5, r3
	16673	+ sub r7, r3, #100
	16674	+ sub r10, r7, #2592
	16675	+ bne .L2622
	16676	+ ldrh r3, [r7]
	16677	+ ldr ip, [r4, #-1556]
	16678	+ lsr r0, r3, #1
16274	16679	mul lr, ip, r3
16275	16680	add r1, r0, #1
16276	16681	add r1, r1, lr, lsr #2
16277		- ldr lr, [r6, #-1872]
16278		- cmp lr, #0
	16682	+ ldr lr, [r4, #-1868]
16279	16683	uxth r1, r1
16280		- beq .L2681
16281		- ldr lr, [r6, #-1568]
	16684	+ cmp lr, #0
	16685	+ beq .L2623
	16686	+ ldr lr, [r4, #-1564]
16282	16687	cmp lr, #39
16283		- bhi .L2681
	16688	+ bhi .L2623
16284	16689	cmp lr, #2
16285		- bls .L2706
	16690	+ bls .L2649
16286	16691	cmp ip, #0
16287	16692	movne r3, #0
16288	16693	andeq r3, r3, #1
16289	16694	cmp r3, #0
16290	16695	moveq r1, r0
16291		- beq .L2681
16292		- b .L2706
16293		-.L2680:
	16696	+ beq .L2623
	16697	+.L2649:
	16698	+ mov r1, #0
	16699	+ b .L2624
	16700	+.L2622:
16294	16701	cmp r2, #1
16295		- bne .L2706
16296		- ldr r3, .L2732+8
16297		- ldrh r3, [r3]
	16702	+ bne .L2649
	16703	+ ldrh r3, [r10]
16298	16704	cmp r3, #1
16299		- beq .L2706
16300		- ldrb r3, [r6, #-2744] @ zero_extendqisi2
	16705	+ beq .L2649
	16706	+ ldrb r3, [r4, #-2740] @ zero_extendqisi2
16301	16707	cmp r3, #0
16302		- bne .L2706
16303		- ldr r0, [r6, #-1872]
16304		- ldrh r3, [r7, #-100]
	16708	+ bne .L2649
	16709	+ ldr r0, [r4, #-1868]
	16710	+ ldrh r3, [r7]
16305	16711	cmp r0, #0
16306		- mov r1, r3, lsr #3
16307		- beq .L2681
16308		- ldr r0, [r6, #-1568]
	16712	+ lsr r1, r3, #3
	16713	+ beq .L2623
	16714	+ ldr r0, [r4, #-1564]
16309	16715	cmp r0, #1
16310		- rsbls r3, r3, r3, asl #3
	16716	+ rsbls r3, r3, r3, lsl #3
16311	16717	ubfxls r1, r3, #3, #16
16312		-.L2681:
	16718	+.L2623:
16313	16719	cmp r1, #0
16314	16720	subne r1, r1, #1
16315	16721	uxthne r1, r1
16316		- b .L2682
16317		-.L2706:
16318		- mov r1, #0
16319		-.L2682:
16320		- ldr r0, .L2732+12
	16722	+.L2624:
	16723	+ ldr r0, .L2669+8
16321	16724	bl List_pop_index_node
16322		- ldrh r3, [r7, #-100]
	16725	+ ldrh r3, [r7]
	16726	+ uxth r8, r0
16323	16727	sub r3, r3, #1
16324		- strh r3, [r7, #-100] @ movhi
16325		- ldrh r3, [r10]
16326		- uxth r9, r0
16327		- cmp r3, r9
16328		- bls .L2679
16329		- ldr r3, [r6, #-1408]
16330		- mov r8, r9, asl #1
16331		- ldrh r7, [r3, r8]
	16728	+ strh r3, [r7] @ movhi
	16729	+ ldrh r3, [r10, #-12]
	16730	+ cmp r3, r8
	16731	+ bls .L2621
	16732	+ ldr r3, [r4, #-1404]
	16733	+ lsl r6, r8, #1
	16734	+ ldrh r7, [r3, r6]
16332	16735	cmp r7, #0
16333		- bne .L2679
16334		- strh r9, [r5] @ movhi
	16736	+ bne .L2621
	16737	+ strh r8, [r5] @ movhi
16335	16738	mov r0, r5
16336	16739	bl make_superblock
16337	16740	ldrb r3, [r5, #7] @ zero_extendqisi2
16338	16741	cmp r3, #0
16339		- beq .L2684
16340		- ldr r2, .L2732+16
16341		- add ip, r5, #14
16342		- ldr r0, [r6, #-1492]
16343		- ldrh lr, [r2]
	16742	+ beq .L2666
	16743	+ ldr r2, .L2669+12
	16744	+ add r9, r5, #16
	16745	+ ldr r0, [r4, #-1488]
	16746	+ mov ip, r9
	16747	+ mov lr, r7
	16748	+ ldrh r1, [r2]
16344	16749	mov r2, #36
16345	16750	mov r3, r0
16346		- mla r1, r2, lr, r0
16347		- mov lr, r7
16348		- str r1, [sp]
16349		- b .L2685
16350		-.L2684:
16351		- ldr r3, [r6, #-1408]
16352		- b .L2727
16353		-.L2685:
16354		- ldr r1, [sp]
16355		- cmp r3, r1
16356		- beq .L2729
16357		- str lr, [r3, #8]
16358		- movw fp, #65535
16359		- str lr, [r3, #12]
16360		- add r3, r3, #36
16361		- ldrh r1, [ip, #2]!
16362		- cmp r1, fp
16363		- movne r1, r1, asl #10
16364		- mlane fp, r2, r7, r0
16365		- addne r7, r7, #1
16366		- uxthne r7, r7
16367		- strne r1, [fp, #4]
16368		- b .L2685
16369		-.L2729:
16370		- ldr r3, .L2732+20
16371		- ldr r2, [r4, #-1872]
16372		- rsb r3, r3, r5
16373		- clz r3, r3
16374		- cmp r2, #0
16375		- mov r3, r3, lsr #5
16376		- moveq r3, #0
	16751	+ mla r1, r2, r1, r0
	16752	+ str r1, [sp, #4]
	16753	+.L2627:
	16754	+ ldr r1, [sp, #4]
	16755	+ cmp r1, r3
	16756	+ bne .L2629
	16757	+ ldr r3, [r4, #-1868]
	16758	+ ldr r2, .L2669+16
	16759	+ adds r3, r3, #0
	16760	+ movne r3, #1
	16761	+ cmp r5, r2
	16762	+ movne r3, #0
16377	16763	cmp r3, #0
16378		- beq .L2688
16379		- ldr r3, [r6, #-1416]
16380		- ldrh r3, [r3, r8]
	16764	+ beq .L2630
	16765	+ ldr r3, [r4, #-1412]
	16766	+ ldrh r3, [r3, r6]
16381	16767	cmp r3, #40
16382	16768	movhi r3, #0
16383		- strhib r3, [r6, #892]
16384		-.L2688:
	16769	+ strbhi r3, [r4, #892]
	16770	+.L2630:
16385	16771	ldrb r3, [r5, #8] @ zero_extendqisi2
16386		- ldr r2, [r4, #-1416]
	16772	+ ldr r2, [r4, #-1412]
	16773	+ ldr fp, .L2669+20
16387	16774	cmp r3, #0
16388		- ldrh r3, [r2, r8]
16389		- bne .L2689
	16775	+ ldrh r3, [r2, r6]
	16776	+ bne .L2631
16390	16777	cmp r3, #0
16391		- mov r0, r9
16392		- ldrne r1, .L2732+24
	16778	+ mov r0, r8
	16779	+ ldrhne r1, [fp, #-10]
16393	16780	moveq r3, #2
16394		- ldrneh r1, [r1]
16395	16781	addne r3, r3, r1
16396	16782	mov r1, #0
16397		- uxthne r3, r3
16398		- strh r3, [r2, r8] @ movhi
16399		- ldr r3, [r4, #-1584]
16400		- add r3, r3, #1
16401		- str r3, [r4, #-1584]
16402		- bl ftl_set_blk_mode
16403		- b .L2691
16404		-.L2689:
16405		- add r3, r3, #1
16406		- strh r3, [r2, r8] @ movhi
16407		- ldr r1, [r4, #-1396]
16408		- mov r0, r9, lsr #5
	16783	+ strh r3, [r2, r6] @ movhi
16409	16784	ldr r3, [r4, #-1580]
16410		- mov ip, #1
16411	16785	add r3, r3, #1
16412	16786	str r3, [r4, #-1580]
16413		- ldr r2, [r1, r0, asl #2]
16414		- and r3, r9, #31
16415		- orr r3, r2, ip, asl r3
16416		- str r3, [r1, r0, asl #2]
16417		-.L2691:
16418		- ldr r3, [r4, #-1416]
16419		- ldr r2, [r4, #-1572]
16420		- ldr r0, [r4, #-1584]
16421		- ldrh r3, [r3, r8]
	16787	+ bl ftl_set_blk_mode
	16788	+.L2634:
	16789	+ ldr r3, [r4, #-1412]
	16790	+ ldr r2, [r4, #-1568]
	16791	+ ldr r0, [r4, #-1580]
	16792	+ ldrh r3, [r3, r6]
	16793	+ ldrh r1, [r10, #-12]
16422	16794	cmp r3, r2
16423		- strhi r3, [r6, #-1572]
16424		- ldr r3, .L2732+24
16425		- ldrh r2, [r3]
16426		- ldr r3, [r4, #-1580]
	16795	+ ldrh r2, [fp, #-10]
	16796	+ strhi r3, [r4, #-1568]
	16797	+ ldr r3, [r4, #-1576]
16427	16798	mla r0, r0, r2, r3
16428		- ldr r3, .L2732+28
16429		- ldrh r1, [r3]
16430	16799	bl __aeabi_uidiv
16431		- ldr r2, [r4, #-1420]
16432		- ldr r3, .L2732+32
16433		- str r0, [r3, #1736]
	16800	+ ldr r2, [r4, #-1416]
	16801	+ ldr r1, [r4, #-1488]
	16802	+ str r0, [r4, #1728]
16434	16803	ldr r3, [r2, #16]
16435	16804	add r3, r3, #1
16436	16805	str r3, [r2, #16]
16437		- ldr r2, [r4, #-1492]
16438		- mov r3, #36
16439		- add r1, r2, #4
16440		- mla r3, r3, r7, r2
16441		- add r3, r3, #40
16442		-.L2693:
16443		- add r1, r1, #36
16444		- cmp r1, r3
16445		- ldrne r2, [r1, #-36]
16446		- bicne r2, r2, #1020
16447		- bicne r2, r2, #3
16448		- strne r2, [r1, #-36]
16449		- bne .L2693
16450		-.L2730:
16451		- ldrb r3, [r4, #-2744] @ zero_extendqisi2
	16806	+ mov r2, #36
	16807	+ mla r2, r2, r7, r1
	16808	+ add r3, r1, #4
	16809	+ add r2, r2, #40
	16810	+.L2636:
	16811	+ add r3, r3, #36
	16812	+ cmp r2, r3
	16813	+ bne .L2637
	16814	+ ldrb r3, [r4, #-2740] @ zero_extendqisi2
16452	16815	cmp r3, #0
16453		- beq .L2695
	16816	+ beq .L2638
16454	16817	ldrb r3, [r5, #8] @ zero_extendqisi2
16455	16818	mov r2, r7
16456		- ldr r0, [r6, #-1492]
	16819	+ ldr r0, [r4, #-1488]
16457	16820	cmp r3, #1
16458	16821	moveq r1, #0
16459	16822	movne r1, #1
16460	16823	bl FlashEraseBlocks
16461		-.L2695:
	16824	+.L2638:
16462	16825	ldrb r1, [r5, #8] @ zero_extendqisi2
16463	16826	mov r2, r7
16464		- ldr r0, [r4, #-1492]
16465		- mov fp, #0
	16827	+ ldr r0, [r4, #-1488]
	16828	+ mov r10, #0
16466	16829	bl FlashEraseBlocks
16467		- add r1, r5, #16
16468		- mov r2, fp
16469		- mov ip, #36
16470		-.L2697:
16471		- uxth r3, fp
16472		- cmp r3, r7
16473		- bcs .L2731
16474		- mul r3, ip, fp
16475		- ldr lr, [r4, #-1492]
16476		- add r0, lr, r3
16477		- ldr r3, [lr, r3]
16478		- cmn r3, #1
16479		- bne .L2698
16480		- ldr r0, [r0, #4]
16481		- add r2, r2, #1
16482		- stmib sp, {r1, r3, ip}
16483		- ubfx r0, r0, #10, #16
16484		- str r2, [sp]
16485		- bl FtlBbmMapBadBlock
16486		- ldmib sp, {r1, r3}
16487		- ldr ip, [sp, #12]
16488		- ldr r2, [sp]
16489		- strh r3, [r1] @ movhi
16490		- ldrb r3, [r5, #7] @ zero_extendqisi2
16491		- sub r3, r3, #1
16492		- strb r3, [r5, #7]
16493		-.L2698:
16494		- add fp, fp, #1
16495		- add r1, r1, #2
16496		- b .L2697
16497		-.L2731:
16498		- cmp r2, #0
16499		- beq .L2700
16500		- mov r0, r9
	16830	+ mov r3, r10
	16831	+ mov r1, #36
	16832	+.L2640:
	16833	+ uxth r2, r10
	16834	+ cmp r7, r2
	16835	+ bhi .L2642
	16836	+ cmp r3, #0
	16837	+ ble .L2643
	16838	+ mov r0, r8
16501	16839	bl update_multiplier_value
16502	16840	bl FtlBbmTblFlush
16503		-.L2700:
16504		- ldrb r3, [r5, #7] @ zero_extendqisi2
16505		- cmp r3, #0
16506		- bne .L2701
16507		- ldr r3, [r4, #-1408]
16508		-.L2727:
	16841	+.L2643:
	16842	+ ldrb r2, [r5, #7] @ zero_extendqisi2
	16843	+ cmp r2, #0
	16844	+ bne .L2644
	16845	+.L2666:
	16846	+ ldr r3, [r4, #-1404]
16509	16847	mvn r2, #0
16510		- strh r2, [r3, r8] @ movhi
16511		- b .L2679
16512		-.L2701:
16513		- ldr r2, .L2732+36
16514		- ldrh r2, [r2, #-4]
16515		- strh r9, [r5] @ movhi
16516		- smulbb r3, r2, r3
	16848	+ strh r2, [r3, r6] @ movhi
	16849	+ b .L2621
	16850	+.L2629:
	16851	+ str lr, [r3, #8]
	16852	+ movw fp, #65535
	16853	+ str lr, [r3, #12]
	16854	+ add r3, r3, #36
	16855	+ ldrh r1, [ip], #2
	16856	+ cmp r1, fp
	16857	+ mlane fp, r2, r7, r0
	16858	+ lslne r1, r1, #10
	16859	+ addne r7, r7, #1
	16860	+ uxthne r7, r7
	16861	+ strne r1, [fp, #4]
	16862	+ b .L2627
	16863	+.L2631:
	16864	+ add r3, r3, #1
	16865	+ mov r0, r8
	16866	+ strh r3, [r2, r6] @ movhi
	16867	+ ldr r3, [r4, #-1576]
	16868	+ add r3, r3, #1
	16869	+ str r3, [r4, #-1576]
	16870	+ bl ftl_set_blk_mode.part.17
	16871	+ b .L2634
	16872	+.L2637:
	16873	+ ldr r1, [r3, #-36]
	16874	+ bic r1, r1, #1020
	16875	+ bic r1, r1, #3
	16876	+ str r1, [r3, #-36]
	16877	+ b .L2636
	16878	+.L2642:
	16879	+ mul r2, r1, r10
	16880	+ ldr r0, [r4, #-1488]
	16881	+ add ip, r0, r2
	16882	+ ldr r2, [r0, r2]
	16883	+ cmn r2, #1
	16884	+ bne .L2641
	16885	+ ldr r0, [ip, #4]
	16886	+ add r3, r3, #1
	16887	+ str r1, [sp, #12]
	16888	+ str r2, [sp, #8]
	16889	+ ubfx r0, r0, #10, #16
	16890	+ str r3, [sp, #4]
	16891	+ bl FtlBbmMapBadBlock
	16892	+ ldr r2, [sp, #8]
	16893	+ ldr r1, [sp, #12]
	16894	+ ldr r3, [sp, #4]
	16895	+ strh r2, [r9] @ movhi
	16896	+ ldrb r2, [r5, #7] @ zero_extendqisi2
	16897	+ sub r2, r2, #1
	16898	+ strb r2, [r5, #7]
	16899	+.L2641:
	16900	+ add r10, r10, #1
	16901	+ add r9, r9, #2
	16902	+ b .L2640
	16903	+.L2644:
	16904	+ ldrh r3, [fp, #-2]
	16905	+ strh r8, [r5] @ movhi
	16906	+ smulbb r3, r3, r2
16517	16907	mov r2, #0
16518	16908	strh r2, [r5, #2] @ movhi
16519	16909	strb r2, [r5, #6]
16520		- ldr r2, [r4, #-1616]
16521		- ldr r1, [r4, #-1408]
	16910	+ ldr r2, [r4, #-1612]
16522	16911	uxth r3, r3
	16912	+ ldr r1, [r4, #-1404]
16523	16913	strh r3, [r5, #4] @ movhi
16524	16914	str r2, [r5, #12]
16525	16915	add r2, r2, #1
16526		- str r2, [r4, #-1616]
	16916	+ str r2, [r4, #-1612]
16527	16917	ldrh r2, [r5]
16528		- mov r2, r2, asl #1
	16918	+ lsl r2, r2, #1
16529	16919	strh r3, [r1, r2] @ movhi
16530		-.L2678:
	16920	+.L2620:
16531	16921	mov r0, #0
16532	16922	add sp, sp, #20
16533	16923	@ sp needed
16534		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
16535		-.L2733:
	16924	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	16925	+.L2670:
16536	16926	.align 2
16537		-.L2732:
	16927	+.L2669:
16538	16928	.word .LANCHOR2
16539	16929	.word .LANCHOR2+980
16540		- .word .LANCHOR2-1716
16541	16930	.word .LANCHOR2+876
16542		- .word .LANCHOR2-1736
	16931	+ .word .LANCHOR2-1732
16543	16932	.word .LANCHOR2+884
16544		- .word .LANCHOR2-1676
16545		- .word .LANCHOR2-1728
16546		- .word .LANCHOR4
16547	16933	.word .LANCHOR2-1664
16548	16934	.fnend
16549	16935	.size allocate_data_superblock, .-allocate_data_superblock
16550	16936	.align 2
16551	16937	.global FtlGcBufInit
	16938	+ .syntax unified
	16939	+ .arm
	16940	+ .fpu softvfp
16552	16941	.type FtlGcBufInit, %function
16553	16942	FtlGcBufInit:
16554	16943	.fnstart
16555	16944	@ args = 0, pretend = 0, frame = 0
16556	16945	@ frame_needed = 0, uses_anonymous_args = 0
16557		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
16558		- .save {r4, r5, r6, r7, r8, r9, r10, lr}
16559		- mov r4, #12
16560		- ldr lr, .L2742
16561		- mov r5, #1
16562		- ldr r2, .L2742+4
16563		- mov r7, #36
16564		- ldr r1, .L2742+8
16565		- add r6, lr, #78
	16946	+ ldr r2, .L2677
	16947	+ mov ip, #12
	16948	+ push {r4, r5, r6, r7, r8, lr}
	16949	+ .save {r4, r5, r6, r7, r8, lr}
	16950	+ mov lr, #1
	16951	+ mov r4, #36
16566	16952	mov r3, #0
16567		- str r3, [r2, #1740]
16568		-.L2735:
16569		- ldrh r2, [lr]
16570		- add ip, r3, #1
16571		- uxth r3, r3
16572		- ldr r0, .L2742+8
16573		- cmp r3, r2
16574		- bcs .L2740
16575		- mul r0, r4, r3
16576		- ldr r8, [r1, #-1448]
16577		- add r2, r8, r0
16578		- str r5, [r2, #8]
16579		- ldrh r2, [r6]
16580		- mul r2, r2, r3
16581		- add r9, r2, #3
16582		- cmp r2, #0
16583		- movlt r2, r9
16584		- ldr r9, [r1, #-1464]
16585		- bic r2, r2, #3
16586		- add r2, r9, r2
16587		- str r2, [r8, r0]
16588		- ldr r2, .L2742+12
16589		- ldr r9, [r1, #-1448]
16590		- ldrh r2, [r2]
16591		- add r8, r9, r0
16592		- mul r2, r2, r3
16593		- add r10, r2, #3
16594		- cmp r2, #0
16595		- movlt r2, r10
16596		- ldr r10, [r1, #-1436]
16597		- bic r2, r2, #3
16598		- add r2, r10, r2
16599		- str r2, [r8, #4]
16600		- ldr r2, [r1, #-1488]
16601		- mla r3, r7, r3, r2
16602		- ldr r2, [r9, r0]
16603		- str r2, [r3, #8]
16604		- ldr r2, [r8, #4]
16605		- str r2, [r3, #12]
16606		- mov r3, ip
16607		- b .L2735
16608		-.L2740:
16609		- ldr r4, .L2742+16
16610		- mov r1, r0
	16953	+ str r3, [r2, #1732]
	16954	+.L2672:
	16955	+ ldr r8, .L2677+4
	16956	+ uxth r5, r3
	16957	+ add r0, r3, #1
	16958	+ ldrh r1, [r8]
	16959	+ cmp r5, r1
	16960	+ bcc .L2673
16611	16961	mov ip, #12
16612	16962	mov lr, #0
16613		-.L2737:
16614		- ldr r3, [r0, #-1480]
16615		- cmp r2, r3
16616		- bcs .L2741
16617		- mul r5, ip, r2
16618		- ldr r7, [r1, #-1448]
16619		- add r3, r7, r5
	16963	+.L2674:
	16964	+ ldr r3, [r2, #-1476]
	16965	+ cmp r1, r3
	16966	+ bcc .L2675
	16967	+ pop {r4, r5, r6, r7, r8, pc}
	16968	+.L2673:
	16969	+ uxth r3, r3
	16970	+ ldr r6, [r2, #-1444]
	16971	+ mul r5, ip, r3
	16972	+ add r1, r6, r5
	16973	+ str lr, [r1, #8]
	16974	+ ldrh r1, [r8, #76]
	16975	+ mul r1, r3, r1
	16976	+ add r7, r1, #3
	16977	+ cmp r1, #0
	16978	+ movlt r1, r7
	16979	+ ldr r7, [r2, #-1460]
	16980	+ bic r1, r1, #3
	16981	+ add r1, r7, r1
	16982	+ str r1, [r6, r5]
	16983	+ ldrh r1, [r8, #78]
	16984	+ ldr r7, [r2, #-1444]
	16985	+ mul r1, r3, r1
	16986	+ add r6, r7, r5
	16987	+ add r8, r1, #3
	16988	+ cmp r1, #0
	16989	+ movlt r1, r8
	16990	+ ldr r8, [r2, #-1432]
	16991	+ bic r1, r1, #3
	16992	+ add r1, r8, r1
	16993	+ str r1, [r6, #4]
	16994	+ ldr r1, [r2, #-1484]
	16995	+ mla r3, r4, r3, r1
	16996	+ ldr r1, [r7, r5]
	16997	+ str r1, [r3, #8]
	16998	+ ldr r1, [r6, #4]
	16999	+ str r1, [r3, #12]
	17000	+ mov r3, r0
	17001	+ b .L2672
	17002	+.L2675:
	17003	+ mul r4, ip, r1
	17004	+ ldr r6, [r2, #-1444]
	17005	+ ldr r5, .L2677+8
	17006	+ add r3, r6, r4
16620	17007	str lr, [r3, #8]
16621		- ldrh r3, [r4]
16622		- mul r3, r3, r2
16623		- add r6, r3, #3
	17008	+ ldrh r3, [r5]
	17009	+ mul r3, r1, r3
	17010	+ add r0, r3, #3
16624	17011	cmp r3, #0
16625		- movlt r3, r6
16626		- ldr r6, [r1, #-1464]
	17012	+ movlt r3, r0
	17013	+ ldr r0, [r2, #-1460]
16627	17014	bic r3, r3, #3
16628		- add r3, r6, r3
16629		- str r3, [r7, r5]
16630		- ldr r3, .L2742+12
16631		- ldr r6, [r1, #-1448]
16632		- ldrh r3, [r3]
16633		- add r5, r6, r5
16634		- mul r3, r3, r2
16635		- add r2, r2, #1
16636		- uxth r2, r2
16637		- add r6, r3, #3
	17015	+ add r3, r0, r3
	17016	+ str r3, [r6, r4]
	17017	+ ldrh r3, [r5, #2]
	17018	+ ldr r0, [r2, #-1444]
	17019	+ mul r3, r1, r3
	17020	+ add r0, r0, r4
	17021	+ add r1, r1, #1
	17022	+ uxth r1, r1
	17023	+ add r4, r3, #3
16638	17024	cmp r3, #0
16639		- movlt r3, r6
16640		- ldr r6, [r1, #-1436]
	17025	+ movlt r3, r4
	17026	+ ldr r4, [r2, #-1432]
16641	17027	bic r3, r3, #3
16642		- add r3, r6, r3
16643		- str r3, [r5, #4]
16644		- b .L2737
16645		-.L2741:
16646		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
16647		-.L2743:
	17028	+ add r3, r4, r3
	17029	+ str r3, [r0, #4]
	17030	+ b .L2674
	17031	+.L2678:
16648	17032	.align 2
16649		-.L2742:
16650		- .word .LANCHOR2-1736
16651		- .word .LANCHOR4
	17033	+.L2677:
16652	17034	.word .LANCHOR2
	17035	+ .word .LANCHOR2-1732
16653	17036	.word .LANCHOR2-1656
16654		- .word .LANCHOR2-1658
16655	17037	.fnend
16656	17038	.size FtlGcBufInit, .-FtlGcBufInit
16657	17039	.align 2
16658	17040	.global FtlVariablesInit
	17041	+ .syntax unified
	17042	+ .arm
	17043	+ .fpu softvfp
16659	17044	.type FtlVariablesInit, %function
16660	17045	FtlVariablesInit:
16661	17046	.fnstart
16662	17047	@ args = 0, pretend = 0, frame = 0
16663	17048	@ frame_needed = 0, uses_anonymous_args = 0
16664		- stmfd sp!, {r3, r4, r5, r6, r7, lr}
16665		- .save {r3, r4, r5, r6, r7, lr}
16666		- movw r2, #1748
16667		- ldr r6, .L2746
	17049	+ push {r4, r5, r6, lr}
	17050	+ .save {r4, r5, r6, lr}
16668	17051	mvn r3, #0
16669		- ldr r5, .L2746+4
16670		- mov r4, #0
16671		- mov r1, r4
16672		- strh r3, [r6, r2] @ movhi
16673		- sub r7, r5, #1712
16674		- str r3, [r6, #1760]
16675		- sub r3, r5, #1280
16676		- ldr r0, [r5, #-1392]
16677		- strh r4, [r3, #-8] @ movhi
16678		- sub r3, r5, #1648
16679		- str r4, [r6, #1744]
16680		- ldrh r2, [r3]
16681		- str r4, [r6, #1752]
16682		- str r4, [r6, #1756]
16683		- mov r2, r2, asl #1
16684		- str r4, [r5, #-1872]
	17052	+ ldr r4, .L2681
	17053	+ movw r2, #1740
	17054	+ mov r5, #0
	17055	+ mov r1, r5
	17056	+ strh r3, [r4, r2] @ movhi
	17057	+ sub r6, r4, #1712
	17058	+ str r3, [r4, #1752]
	17059	+ sub r3, r4, #1280
	17060	+ strh r5, [r3, #-8] @ movhi
	17061	+ sub r3, r4, #1632
	17062	+ ldrh r2, [r3, #-12]
	17063	+ ldr r0, [r4, #-1392]
	17064	+ str r5, [r4, #1736]
	17065	+ str r5, [r4, #1744]
	17066	+ lsl r2, r2, #1
	17067	+ str r5, [r4, #1748]
	17068	+ str r5, [r4, #-1868]
16685	17069	bl ftl_memset
16686		- ldrh r2, [r7, #-14]
16687		- mov r1, r4
16688		- ldr r0, [r5, #-1416]
16689		- mov r2, r2, asl #1
	17070	+ ldrh r2, [r6, #-10]
	17071	+ mov r1, r5
	17072	+ ldr r0, [r4, #-1412]
	17073	+ lsl r2, r2, #1
16690	17074	bl ftl_memset
16691		- ldrh r2, [r7, #-14]
16692		- mov r1, r4
16693		- ldr r0, [r5, #-1424]
16694		- mov r2, r2, asl #1
	17075	+ ldrh r2, [r6, #-10]
	17076	+ mov r1, r5
	17077	+ ldr r0, [r4, #-1420]
	17078	+ lsl r2, r2, #1
16695	17079	bl ftl_memset
16696		- mov r1, r4
16697		- add r0, r5, #816
	17080	+ mov r1, r5
16698	17081	mov r2, #48
	17082	+ add r0, r4, #816
16699	17083	bl ftl_memset
16700		- add r0, r6, #1200
16701		- mov r1, r4
	17084	+ add r0, r4, #1200
16702	17085	mov r2, #512
16703		- add r0, r0, #12
	17086	+ mov r1, r5
	17087	+ add r0, r0, #4
16704	17088	bl ftl_memset
16705	17089	bl FtlGcBufInit
16706	17090	bl FtlL2PDataInit
16707		- mov r0, r4
16708		- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
16709		-.L2747:
	17091	+ mov r0, r5
	17092	+ pop {r4, r5, r6, pc}
	17093	+.L2682:
16710	17094	.align 2
16711		-.L2746:
16712		- .word .LANCHOR4
	17095	+.L2681:
16713	17096	.word .LANCHOR2
16714	17097	.fnend
16715	17098	.size FtlVariablesInit, .-FtlVariablesInit
16716	17099	.align 2
16717	17100	.global FtlGcBufFree
	17101	+ .syntax unified
	17102	+ .arm
	17103	+ .fpu softvfp
16718	17104	.type FtlGcBufFree, %function
16719	17105	FtlGcBufFree:
16720	17106	.fnstart
16721	17107	@ args = 0, pretend = 0, frame = 0
16722	17108	@ frame_needed = 0, uses_anonymous_args = 0
16723		- ldr r3, .L2756
16724		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
	17109	+ ldr r3, .L2691
	17110	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
16725	17111	.save {r4, r5, r6, r7, r8, r9, r10, lr}
16726	17112	mov lr, #0
16727		- ldr r6, [r3, #-1480]
16728	17113	mov r5, #36
16729		- ldr r4, [r3, #-1448]
16730		- mov r7, lr
16731		- mov r8, #12
16732		-.L2749:
16733		- uxth ip, lr
16734		- cmp ip, r1
16735		- ldmcsfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
16736		- mla ip, r5, ip, r0
	17114	+ mov r7, #12
	17115	+ mov r8, lr
	17116	+ ldr r6, [r3, #-1476]
	17117	+ ldr r4, [r3, #-1444]
	17118	+.L2684:
	17119	+ uxth r3, lr
	17120	+ cmp r1, r3
	17121	+ popls {r4, r5, r6, r7, r8, r9, r10, pc}
	17122	+ mla ip, r5, r3, r0
16737	17123	mov r2, #0
16738		-.L2750:
	17124	+.L2685:
16739	17125	uxth r3, r2
16740		- cmp r3, r6
16741		- bcs .L2751
16742		- mul r3, r8, r3
	17126	+ cmp r6, r3
	17127	+ bls .L2686
	17128	+ mul r3, r7, r3
16743	17129	add r2, r2, #1
16744		- add r9, r4, r3
16745	17130	ldr r10, [r4, r3]
	17131	+ add r9, r4, r3
16746	17132	ldr r3, [ip, #8]
16747	17133	cmp r10, r3
16748		- bne .L2750
16749		- str r7, [r9, #8]
16750		-.L2751:
	17134	+ bne .L2685
	17135	+ str r8, [r9, #8]
	17136	+.L2686:
16751	17137	add lr, lr, #1
16752		- b .L2749
16753		-.L2757:
	17138	+ b .L2684
	17139	+.L2692:
16754	17140	.align 2
16755		-.L2756:
	17141	+.L2691:
16756	17142	.word .LANCHOR2
16757	17143	.fnend
16758	17144	.size FtlGcBufFree, .-FtlGcBufFree
16759	17145	.align 2
16760	17146	.global FtlGcBufAlloc
	17147	+ .syntax unified
	17148	+ .arm
	17149	+ .fpu softvfp
16761	17150	.type FtlGcBufAlloc, %function
16762	17151	FtlGcBufAlloc:
16763	17152	.fnstart
16764	17153	@ args = 0, pretend = 0, frame = 0
16765	17154	@ frame_needed = 0, uses_anonymous_args = 0
16766		- ldr r3, .L2767
	17155	+ ldr r3, .L2701
16767	17156	mov ip, #0
16768		- stmfd sp!, {r4, r5, r6, r7, r8, r9, lr}
	17157	+ push {r4, r5, r6, r7, r8, r9, lr}
16769	17158	.save {r4, r5, r6, r7, r8, r9, lr}
16770	17159	mov r6, #12
16771		- ldr r4, [r3, #-1480]
16772	17160	mov r7, #1
16773		- ldr r5, [r3, #-1448]
16774	17161	mov r8, #36
16775		-.L2759:
	17162	+ ldr r4, [r3, #-1476]
	17163	+ ldr r5, [r3, #-1444]
	17164	+.L2694:
16776	17165	uxth r2, ip
16777		- cmp r2, r1
16778		- bcs .L2766
	17166	+ cmp r1, r2
	17167	+ bhi .L2698
	17168	+ pop {r4, r5, r6, r7, r8, r9, pc}
	17169	+.L2698:
16779	17170	mov lr, #0
16780		-.L2760:
	17171	+.L2695:
16781	17172	uxth r3, lr
16782		- cmp r3, r4
16783		- bcs .L2761
	17173	+ cmp r4, r3
	17174	+ bls .L2696
16784	17175	mla r3, r6, r3, r5
16785	17176	add lr, lr, #1
16786	17177	ldr r9, [r3, #8]
16787	17178	cmp r9, #0
16788		- bne .L2760
	17179	+ bne .L2695
16789	17180	mla r2, r8, r2, r0
16790	17181	ldr lr, [r3]
16791	17182	str r7, [r3, #8]
16792	17183	str lr, [r2, #8]
16793	17184	ldr r3, [r3, #4]
16794	17185	str r3, [r2, #12]
16795		-.L2761:
	17186	+.L2696:
16796	17187	add ip, ip, #1
16797		- b .L2759
16798		-.L2766:
16799		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, pc}
16800		-.L2768:
	17188	+ b .L2694
	17189	+.L2702:
16801	17190	.align 2
16802		-.L2767:
	17191	+.L2701:
16803	17192	.word .LANCHOR2
16804	17193	.fnend
16805	17194	.size FtlGcBufAlloc, .-FtlGcBufAlloc
16806	17195	.align 2
16807	17196	.global IsBlkInGcList
	17197	+ .syntax unified
	17198	+ .arm
	17199	+ .fpu softvfp
16808	17200	.type IsBlkInGcList, %function
16809	17201	IsBlkInGcList:
16810	17202	.fnstart
16811	17203	@ args = 0, pretend = 0, frame = 0
16812	17204	@ frame_needed = 0, uses_anonymous_args = 0
16813	17205	@ link register save eliminated.
16814		- ldr r1, .L2775
16815		- movw r2, #1764
16816		- ldr r3, .L2775+4
16817		- ldrh r2, [r1, r2]
16818		- ldr r3, [r3, #-1512]
16819		- add r2, r3, r2, asl #1
16820		-.L2770:
	17206	+ ldr r2, .L2708
	17207	+ movw r1, #1756
	17208	+ ldr r3, [r2, #-1508]
	17209	+ ldrh r2, [r2, r1]
	17210	+ add r2, r3, r2, lsl #1
	17211	+.L2704:
16821	17212	cmp r3, r2
16822		- beq .L2774
16823		- ldrh r1, [r3], #2
16824		- cmp r1, r0
16825		- bne .L2770
16826		- mov r0, #1
16827		- bx lr
16828		-.L2774:
	17213	+ bne .L2706
16829	17214	mov r0, #0
16830	17215	bx lr
16831		-.L2776:
	17216	+.L2706:
	17217	+ ldrh r1, [r3], #2
	17218	+ cmp r1, r0
	17219	+ bne .L2704
	17220	+ mov r0, #1
	17221	+ bx lr
	17222	+.L2709:
16832	17223	.align 2
16833		-.L2775:
16834		- .word .LANCHOR4
	17224	+.L2708:
16835	17225	.word .LANCHOR2
16836	17226	.fnend
16837	17227	.size IsBlkInGcList, .-IsBlkInGcList
16838	17228	.align 2
16839	17229	.global FtlGcUpdatePage
	17230	+ .syntax unified
	17231	+ .arm
	17232	+ .fpu softvfp
16840	17233	.type FtlGcUpdatePage, %function
16841	17234	FtlGcUpdatePage:
16842	17235	.fnstart
16843	17236	@ args = 0, pretend = 0, frame = 0
16844	17237	@ frame_needed = 0, uses_anonymous_args = 0
16845		- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
16846		- .save {r3, r4, r5, r6, r7, r8, r9, lr}
	17238	+ push {r4, r5, r6, r7, r8, lr}
	17239	+ .save {r4, r5, r6, r7, r8, lr}
16847	17240	mov r4, r0
16848	17241	ubfx r0, r0, #10, #16
16849	17242	mov r5, r1
16850	17243	mov r6, r2
16851	17244	bl P2V_block_in_plane
16852		- ldr lr, .L2785
16853		- movw r2, #1764
16854		- ldr r3, .L2785+4
16855		- ldr r1, [lr, #-1512]
16856		- ldrh r7, [r3, r2]
16857		- mov r2, #0
16858		- sub r8, r1, #2
16859		-.L2778:
16860		- uxth ip, r2
16861		- cmp ip, r7
16862		- bcs .L2782
16863		- ldrh r9, [r8, #2]!
16864		- add r2, r2, #1
16865		- cmp r9, r0
16866		- bne .L2778
16867		-.L2782:
16868		- cmp ip, r7
16869		- bne .L2780
16870		- mov ip, ip, asl #1
16871		- movw r2, #1764
16872		- strh r0, [r1, ip] @ movhi
	17245	+ ldr r3, .L2715
	17246	+ movw r2, #1756
	17247	+ mov ip, #0
	17248	+ ldrh lr, [r3, r2]
	17249	+ ldr r2, [r3, #-1508]
	17250	+ sub r1, r2, #2
	17251	+.L2711:
	17252	+ uxth r7, ip
	17253	+ cmp r7, lr
	17254	+ bcc .L2713
	17255	+ bne .L2712
	17256	+ lsl ip, r7, #1
	17257	+ strh r0, [r2, ip] @ movhi
	17258	+ movw r2, #1756
16873	17259	ldrh r0, [r3, r2]
16874	17260	add r0, r0, #1
16875	17261	strh r0, [r3, r2] @ movhi
16876		-.L2780:
16877		- movw r0, #1766
16878		- mov ip, #12
16879		- ldrh r2, [r3, r0]
16880		- mul ip, ip, r2
16881		- ldr r2, [lr, #-1508]
16882		- add r1, r2, ip
	17262	+ b .L2712
	17263	+.L2713:
	17264	+ ldrh r7, [r1, #2]!
	17265	+ add ip, ip, #1
	17266	+ cmp r7, r0
	17267	+ bne .L2711
	17268	+.L2712:
	17269	+ movw ip, #1758
	17270	+ mov r0, #12
	17271	+ ldrh r2, [r3, ip]
	17272	+ mul r0, r0, r2
	17273	+ ldr r2, [r3, #-1504]
	17274	+ add r1, r2, r0
16883	17275	stmib r1, {r5, r6}
16884		- str r4, [r2, ip]
16885		- ldrh r2, [r3, r0]
	17276	+ str r4, [r2, r0]
	17277	+ ldrh r2, [r3, ip]
16886	17278	add r2, r2, #1
16887		- strh r2, [r3, r0] @ movhi
16888		- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
16889		-.L2786:
	17279	+ strh r2, [r3, ip] @ movhi
	17280	+ pop {r4, r5, r6, r7, r8, pc}
	17281	+.L2716:
16890	17282	.align 2
16891		-.L2785:
	17283	+.L2715:
16892	17284	.word .LANCHOR2
16893		- .word .LANCHOR4
16894	17285	.fnend
16895	17286	.size FtlGcUpdatePage, .-FtlGcUpdatePage
16896	17287	.align 2
16897	17288	.global FtlGcPageVarInit
	17289	+ .syntax unified
	17290	+ .arm
	17291	+ .fpu softvfp
16898	17292	.type FtlGcPageVarInit, %function
16899	17293	FtlGcPageVarInit:
16900	17294	.fnstart
16901	17295	@ args = 0, pretend = 0, frame = 0
16902	17296	@ frame_needed = 0, uses_anonymous_args = 0
16903		- stmfd sp!, {r3, r4, r5, lr}
16904		- .save {r3, r4, r5, lr}
16905		- movw r1, #1764
16906		- ldr r3, .L2789
16907		- mov r2, #0
16908		- ldr r4, .L2789+4
16909		- sub r5, r4, #1664
16910		- strh r2, [r3, r1] @ movhi
16911		- movw r1, #1766
16912		- ldr r0, [r4, #-1512]
16913		- strh r2, [r3, r1] @ movhi
	17297	+ push {r4, r5, r6, lr}
	17298	+ .save {r4, r5, r6, lr}
	17299	+ mov r3, #0
	17300	+ ldr r4, .L2719
	17301	+ movw r2, #1756
16914	17302	mov r1, #255
16915		- ldrh r2, [r5]
16916		- mov r2, r2, asl #1
16917		- bl ftl_memset
16918		- ldrh r3, [r5]
16919		- mov r2, #12
	17303	+ strh r3, [r4, r2] @ movhi
	17304	+ sub r5, r4, #1648
	17305	+ movw r2, #1758
16920	17306	ldr r0, [r4, #-1508]
	17307	+ strh r3, [r4, r2] @ movhi
	17308	+ ldrh r2, [r5, #-14]
	17309	+ lsl r2, r2, #1
	17310	+ bl ftl_memset
	17311	+ ldrh r3, [r5, #-14]
	17312	+ mov r2, #12
	17313	+ ldr r0, [r4, #-1504]
16921	17314	mov r1, #255
16922	17315	mul r2, r2, r3
16923	17316	bl ftl_memset
16924		- ldmfd sp!, {r3, r4, r5, lr}
	17317	+ pop {r4, r5, r6, lr}
16925	17318	b FtlGcBufInit
16926		-.L2790:
	17319	+.L2720:
16927	17320	.align 2
16928		-.L2789:
16929		- .word .LANCHOR4
	17321	+.L2719:
16930	17322	.word .LANCHOR2
16931	17323	.fnend
16932	17324	.size FtlGcPageVarInit, .-FtlGcPageVarInit
16933	17325	.align 2
16934	17326	.global FtlGcScanTempBlk
	17327	+ .syntax unified
	17328	+ .arm
	17329	+ .fpu softvfp
16935	17330	.type FtlGcScanTempBlk, %function
16936	17331	FtlGcScanTempBlk:
16937	17332	.fnstart
16938	17333	@ args = 0, pretend = 0, frame = 64
16939	17334	@ frame_needed = 0, uses_anonymous_args = 0
16940		- ldr r2, .L2844
16941		- movw r3, #3448
16942		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	17335	+ ldr r2, .L2770
	17336	+ movw r3, #3444
	17337	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
16943	17338	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
16944	17339	.pad #68
16945	17340	sub sp, sp, #68
16946		- ldrh r5, [r2, r3]
16947		- movw r3, #65535
16948		- mov r4, r0
	17341	+ mov r5, r0
16949	17342	str r1, [sp, #8]
16950		- cmp r5, r3
16951		- beq .L2825
16952		- cmp r5, #0
16953		- bne .L2792
16954		- b .L2793
16955		-.L2825:
16956		- mov r5, #0
16957		-.L2792:
16958		- ldr r3, .L2844+4
16959		- ldr r2, [sp, #8]
16960		- ldrh r3, [r3, #-4]
16961		- cmp r2, r3
16962		- bne .L2794
16963		-.L2793:
	17343	+ ldrh r6, [r2, r3]
	17344	+ movw r3, #65535
	17345	+ cmp r6, r3
	17346	+ beq .L2753
	17347	+ cmp r6, #0
	17348	+ bne .L2722
	17349	+.L2723:
16964	17350	bl FtlGcPageVarInit
16965		-.L2794:
16966		- ldr r6, .L2844+8
	17351	+ b .L2724
	17352	+.L2753:
	17353	+ mov r6, #0
	17354	+.L2722:
	17355	+ ldr r3, .L2770+4
	17356	+ ldr r2, [sp, #8]
	17357	+ ldrh r3, [r3, #-2]
	17358	+ cmp r3, r2
	17359	+ beq .L2723
	17360	+.L2724:
	17361	+ ldr r4, .L2770+8
16967	17362	mov r2, #0
16968	17363	mvn r3, #0
16969		- stmia sp, {r2, r3}
16970		-.L2795:
16971		- ldrh r1, [r4]
	17364	+ stm sp, {r2, r3}
	17365	+.L2725:
	17366	+ ldrh r1, [r5]
16972	17367	movw r3, #65535
16973	17368	mov r2, #0
16974		- strb r2, [r4, #8]
	17369	+ strb r2, [r5, #8]
16975	17370	cmp r1, r3
16976		- beq .L2796
16977		-.L2797:
16978		-.L2822:
16979		- ldr r3, .L2844+12
16980		- mov r7, #0
16981		- ldr r0, [r6, #-1436]
16982		- add r1, r4, #14
16983		- mov r8, r7
16984		- movw lr, #65535
16985		- ldrh r3, [r3]
	17371	+ beq .L2726
	17372	+.L2750:
	17373	+ ldr r3, .L2770+12
	17374	+ add ip, r5, #16
	17375	+ ldr r0, [r4, #-1500]
	17376	+ movw r8, #65535
	17377	+ ldr fp, [r4, #-1432]
16986	17378	mov r9, #36
16987		- str r3, [sp, #12]
16988		- ldr r3, [r6, #-1504]
16989		- str r3, [sp, #16]
16990		- ldr r3, [r6, #-1464]
16991		- str r3, [sp, #20]
16992		- ldr r3, .L2844+16
16993		- ldrh fp, [r3]
16994		- ldrh ip, [r3, #2]
16995		-.L2798:
16996		- ldr r2, [sp, #12]
16997		- uxth r3, r7
	17379	+ ldrh r2, [r3, #-4]
	17380	+ ldrh lr, [r3, #74]
	17381	+ str r2, [sp, #12]
	17382	+ ldr r2, [r4, #-1460]
	17383	+ str r2, [sp, #16]
	17384	+ ldrh r2, [r3, #72]
	17385	+ str r2, [sp, #20]
	17386	+ mov r2, #0
	17387	+ mov r7, r2
	17388	+.L2727:
	17389	+ ldr r1, [sp, #12]
	17390	+ uxth r3, r2
	17391	+ cmp r1, r3
	17392	+ bhi .L2729
	17393	+ mov r10, #0
	17394	+ mov r2, #0
	17395	+ mov r1, r7
	17396	+ bl FlashReadPages
	17397	+.L2730:
	17398	+ uxth r3, r10
	17399	+ cmp r7, r3
	17400	+ bhi .L2748
	17401	+ ldr r3, [sp]
	17402	+ add r6, r6, #1
	17403	+ uxth r6, r6
	17404	+ add r3, r3, #1
	17405	+ str r3, [sp]
	17406	+ ldr r2, [sp]
	17407	+ ldr r3, [sp, #8]
16998	17408	cmp r3, r2
16999		- bcs .L2842
17000		- ldrh r3, [r1, #2]!
17001		- cmp r3, lr
17002		- beq .L2799
17003		- ldr r2, [sp, #16]
17004		- orr r3, r5, r3, asl #10
17005		- mla r2, r9, r8, r2
17006		- str r3, [r2, #4]
17007		- mul r3, fp, r8
	17409	+ ldr r2, .L2770+4
	17410	+ bls .L2749
	17411	+.L2751:
	17412	+ ldrh r3, [r2, #-2]
	17413	+ cmp r3, r6
	17414	+ bhi .L2750
	17415	+ mov r2, #0
	17416	+ b .L2726
	17417	+.L2729:
	17418	+ ldrh r3, [ip], #2
	17419	+ cmp r3, r8
	17420	+ beq .L2728
	17421	+ mla r1, r9, r7, r0
	17422	+ orr r3, r6, r3, lsl #10
	17423	+ str r3, [r1, #4]
	17424	+ ldr r3, [sp, #20]
	17425	+ mul r3, r3, r7
17008	17426	add r10, r3, #3
17009	17427	cmp r3, #0
17010	17428	movlt r3, r10
17011		- ldr r10, [sp, #20]
	17429	+ ldr r10, [sp, #16]
17012	17430	bic r3, r3, #3
17013	17431	add r3, r10, r3
17014		- str r3, [r2, #8]
17015		- mul r3, ip, r8
17016		- add r8, r8, #1
17017		- uxth r8, r8
	17432	+ str r3, [r1, #8]
	17433	+ mul r3, lr, r7
	17434	+ add r7, r7, #1
	17435	+ uxth r7, r7
17018	17436	add r10, r3, #3
17019	17437	cmp r3, #0
17020	17438	movlt r3, r10
17021	17439	bic r3, r3, #3
17022		- add r3, r0, r3
17023		- str r3, [r2, #12]
17024		-.L2799:
17025		- add r7, r7, #1
17026		- b .L2798
17027		-.L2842:
17028		- ldr r0, [r6, #-1504]
17029		- mov r1, r8
17030		- mov r2, #0
17031		- mov r10, #0
17032		- bl FlashReadPages
17033		-.L2801:
17034		- uxth r3, r10
17035		- cmp r3, r8
17036		- bcs .L2843
17037		- ldr r3, .L2844+8
	17440	+ add r3, fp, r3
	17441	+ str r3, [r1, #12]
	17442	+.L2728:
	17443	+ add r2, r2, #1
	17444	+ b .L2727
	17445	+.L2748:
17038	17446	mov r9, #36
	17447	+ ldr r8, [r4, #-1500]
17039	17448	mul r9, r9, r10
17040		- ldr r7, [r3, #-1504]
17041		- add r3, r7, r9
17042		- str r3, [sp, #12]
	17449	+ add r3, r8, r9
17043	17450	ldr fp, [r3, #4]
	17451	+ str r3, [sp, #12]
17044	17452	ubfx r0, fp, #10, #16
17045	17453	bl P2V_plane
17046		- ldr r7, [r7, r9]
17047		- ldr ip, .L2844+8
17048		- cmp r7, #0
17049		- ldr r3, [sp, #12]
	17454	+ ldr r8, [r8, r9]
17050	17455	mov r2, r0
	17456	+ ldr r3, [sp, #12]
	17457	+ cmp r8, #0
17051	17458	ldr r3, [r3, #12]
17052		- bne .L2802
	17459	+ bne .L2731
17053	17460	ldrh r0, [r3]
17054	17461	movw r1, #65535
17055	17462	cmp r0, r1
17056		- bne .L2803
17057		-.L2806:
17058		- ldrb r1, [ip, #-2744] @ zero_extendqisi2
	17463	+ bne .L2732
	17464	+.L2735:
	17465	+ ldrb r1, [r4, #-2740] @ zero_extendqisi2
17059	17466	cmp r1, #0
17060		- beq .L2837
17061		- ldr r3, .L2844+20
17062		- mov r1, #1
17063		- str r1, [r3, #1756]
17064		- b .L2796
17065		-.L2803:
	17467	+ beq .L2765
	17468	+ mov r3, #1
	17469	+ str r3, [r4, #1748]
	17470	+.L2726:
	17471	+ ldr r1, .L2770
	17472	+ mvn r0, #0
	17473	+ movw r3, #3444
	17474	+ strh r6, [r5, #2] @ movhi
	17475	+ strb r2, [r5, #6]
	17476	+ strh r0, [r1, r3] @ movhi
	17477	+ mov r1, r6
	17478	+ mov r0, r5
	17479	+ bl ftl_sb_update_avl_pages
	17480	+ b .L2721
	17481	+.L2732:
17066	17482	ldr r0, [r3, #8]
17067		- ldr r1, [r6, #-1284]
	17483	+ ldr r1, [r4, #-1284]
17068	17484	cmp r0, r1
17069		- bls .L2838
17070		- b .L2806
17071		-.L2837:
17072		- ldrh r3, [r4]
17073		- ldr r2, [r6, #-1408]
17074		- mov r3, r3, asl #1
17075		- b .L2841
17076		-.L2838:
17077		- ldr r2, .L2844+24
17078		- ldrb r2, [r2] @ zero_extendqisi2
	17485	+ bhi .L2735
	17486	+ ldr r2, .L2770+16
	17487	+ ldrb r2, [r2, #36] @ zero_extendqisi2
17079	17488	cmp r2, #0
17080		- beq .L2810
	17489	+ bne .L2738
	17490	+.L2739:
	17491	+ ldr r2, [r3, #8]
	17492	+ mov r1, fp
	17493	+ ldr r0, [r3, #12]
	17494	+ add r10, r10, #1
	17495	+ bl FtlGcUpdatePage
	17496	+ b .L2730
	17497	+.L2765:
	17498	+ ldrh r3, [r5]
	17499	+ ldr r2, [r4, #-1404]
	17500	+ lsl r3, r3, #1
	17501	+.L2769:
	17502	+ strh r1, [r2, r3] @ movhi
	17503	+ ldrh r0, [r5]
	17504	+ bl INSERT_FREE_LIST
	17505	+ ldr r2, .L2770+20
	17506	+ mvn r3, #0
	17507	+ strh r3, [r5] @ movhi
	17508	+ strh r3, [r2] @ movhi
	17509	+.L2768:
	17510	+ bl FtlGcPageVarInit
	17511	+ mov r6, #0
	17512	+ b .L2725
	17513	+.L2738:
	17514	+ mov r2, r8
17081	17515	add r1, sp, #24
17082		- mov r2, r7
17083	17516	str r3, [sp, #12]
17084	17517	bl log2phys
17085	17518	ldr r3, [sp, #12]
17086	17519	ldr r1, [sp, #24]
17087	17520	ldr r2, [r3, #12]
17088	17521	cmn r1, #1
17089		- rsb r0, r2, r1
	17522	+ sub r0, r2, r1
17090	17523	clz r0, r0
17091		- mov r0, r0, lsr #5
	17524	+ lsr r0, r0, #5
17092	17525	moveq r0, #0
17093	17526	cmp r0, #0
17094		- beq .L2810
	17527	+ beq .L2739
17095	17528	str r2, [sp, #32]
17096	17529	mov r1, #1
17097		- ldr r2, [r6, #-1452]
	17530	+ ldr r2, [r4, #-1448]
17098	17531	add r0, sp, #28
17099	17532	str r2, [sp, #36]
17100		- ldr r2, [r6, #-1440]
	17533	+ ldr r2, [r4, #-1436]
17101	17534	str r2, [sp, #40]
17102		- mov r2, r7
	17535	+ mov r2, r8
17103	17536	bl FlashReadPages
17104		- ldr r2, .L2844+28
17105		- ldr r1, [r6, #-1504]
	17537	+ ldr r2, .L2770+24
	17538	+ ldr r1, [r4, #-1500]
	17539	+ ldr r3, [sp, #12]
17106	17540	ldrh r2, [r2]
17107	17541	add r9, r1, r9
17108		- mov r2, r2, asl #7
17109	17542	ldr r1, [sp, #36]
17110		- ldr r3, [sp, #12]
17111		- b .L2812
17112		-.L2813:
17113		- add r7, r7, #1
17114		-.L2812:
17115		- cmp r7, r2
17116		- beq .L2810
	17543	+ lsl r2, r2, #7
	17544	+.L2740:
	17545	+ cmp r8, r2
	17546	+ beq .L2739
17117	17547	ldr r0, [r9, #8]
17118		- ldr ip, [r0, r7, asl #2]
17119		- ldr r0, [r1, r7, asl #2]
	17548	+ ldr ip, [r0, r8, lsl #2]
	17549	+ ldr r0, [r1, r8, lsl #2]
17120	17550	cmp ip, r0
17121		- beq .L2813
17122		- ldrh r1, [r4]
	17551	+ beq .L2741
17123	17552	ldr r2, [sp, #32]
17124		- ldr r0, .L2844+32
	17553	+ ldrh r1, [r5]
	17554	+ ldr r0, .L2770+28
17125	17555	bl printk
17126		- ldrh r3, [r4]
17127		- ldr r2, [r6, #-1408]
	17556	+ ldrh r3, [r5]
17128	17557	mov r1, #0
17129		- mov r3, r3, asl #1
17130		-.L2841:
17131		- strh r1, [r2, r3] @ movhi
17132		- ldrh r0, [r4]
17133		- bl INSERT_FREE_LIST
17134		- ldr r2, .L2844+36
17135		- mvn r3, #0
17136		- strh r3, [r4] @ movhi
17137		- strh r3, [r2] @ movhi
17138		- b .L2840
17139		-.L2810:
17140		- ldr r0, [r3, #12]
17141		- mov r1, fp
17142		- ldr r2, [r3, #8]
17143		- add r10, r10, #1
17144		- bl FtlGcUpdatePage
17145		- b .L2801
17146		-.L2802:
17147		- ldr r0, .L2844+40
	17558	+ ldr r2, [r4, #-1404]
	17559	+ lsl r3, r3, #1
	17560	+ b .L2769
	17561	+.L2741:
	17562	+ add r8, r8, #1
	17563	+ b .L2740
	17564	+.L2731:
17148	17565	mov r2, fp
17149		- ldrh r1, [r4]
17150		- str ip, [sp, #12]
	17566	+ ldrh r1, [r5]
	17567	+ ldr r0, .L2770+32
17151	17568	bl printk
17152		- ldr r3, .L2844+8
17153		- ldrh r5, [r4]
17154		- ldr r3, [r3, #-1872]
	17569	+ ldr r3, [r4, #-1868]
17155	17570	cmp r3, #0
17156		- ldr ip, [sp, #12]
17157		- bne .L2816
17158		- ldr r3, .L2844+8
17159		- ldrb r3, [r3, #-2744] @ zero_extendqisi2
17160		- cmp r3, #0
17161		- beq .L2817
17162		-.L2816:
17163		- ldr r2, [ip, #-1416]
17164		- mov r3, r5, asl #1
17165		- ldrh r3, [r2, r3]
17166		- cmp r3, #159
17167		- bls .L2818
17168		-.L2817:
17169		- ldr r3, [ip, #-1504]
17170		- ldr r3, [r3, r9]
17171		- cmn r3, #1
17172		- bne .L2819
17173		-.L2818:
17174		- ldr r3, [ip, #-1504]
17175		- add r9, r3, r9
17176		- ldr r3, [r9, #4]
17177		- str r3, [sp, #4]
17178		-.L2819:
17179		- ldr r3, .L2844+8
17180		- mov r5, r5, asl #1
17181		- mov r2, #0
17182		- ldr r3, [r3, #-1408]
17183		- strh r2, [r3, r5] @ movhi
17184		- ldrh r0, [r4]
	17571	+ ldrh r3, [r5]
	17572	+ bne .L2744
	17573	+ ldrb r2, [r4, #-2740] @ zero_extendqisi2
	17574	+ cmp r2, #0
	17575	+ beq .L2745
	17576	+.L2744:
	17577	+ ldr r1, [r4, #-1412]
	17578	+ lsl r2, r3, #1
	17579	+ ldrh r2, [r1, r2]
	17580	+ cmp r2, #159
	17581	+ bls .L2746
	17582	+.L2745:
	17583	+ ldr r2, [r4, #-1500]
	17584	+ ldr r2, [r2, r9]
	17585	+ cmn r2, #1
	17586	+ bne .L2747
	17587	+.L2746:
	17588	+ ldr r2, [r4, #-1500]
	17589	+ add r9, r2, r9
	17590	+ ldr r2, [r9, #4]
	17591	+ str r2, [sp, #4]
	17592	+.L2747:
	17593	+ ldr r2, [r4, #-1404]
	17594	+ lsl r3, r3, #1
	17595	+ mov r1, #0
	17596	+ strh r1, [r2, r3] @ movhi
	17597	+ ldrh r0, [r5]
17185	17598	bl INSERT_FREE_LIST
17186	17599	mvn r3, #0
17187		- strh r3, [r4] @ movhi
17188		-.L2840:
17189		- bl FtlGcPageVarInit
17190		- mov r5, #0
17191		- b .L2795
17192		-.L2843:
17193		- ldr r3, [sp]
17194		- add r5, r5, #1
17195		- ldr r2, [sp, #8]
17196		- add r3, r3, #1
17197		- uxth r5, r5
17198		- cmp r3, r2
17199		- str r3, [sp]
17200		- ldr r2, .L2844+44
17201		- bcs .L2821
17202		-.L2823:
17203		- ldrh r3, [r2]
17204		- cmp r3, r5
17205		- bhi .L2822
17206		- mov r2, #0
17207		- b .L2796
17208		-.L2821:
17209		- ldr r1, .L2844+48
	17600	+ strh r3, [r5] @ movhi
	17601	+ b .L2768
	17602	+.L2749:
	17603	+ ldr r1, .L2770+36
17210	17604	movw r0, #65535
17211	17605	ldrh r3, [r1]
17212	17606	cmp r3, r0
17213		- beq .L2823
	17607	+ beq .L2751
17214	17608	ldr r0, [sp]
17215	17609	add r3, r3, r0
17216	17610	strh r3, [r1] @ movhi
17217		- ldrh r3, [r2]
17218		- cmp r3, r5
17219		- bls .L2823
17220		- b .L2824
17221		-.L2796:
17222		- ldr r1, .L2844
17223		- movw r3, #3448
17224		- mvn r0, #0
17225		- strh r5, [r4, #2] @ movhi
17226		- strb r2, [r4, #6]
17227		- strh r0, [r1, r3] @ movhi
17228		- mov r0, r4
17229		- mov r1, r5
17230		- bl ftl_sb_update_avl_pages
17231		-.L2824:
	17611	+ ldrh r3, [r2, #-2]
	17612	+ cmp r3, r6
	17613	+ bls .L2751
	17614	+.L2721:
17232	17615	ldr r0, [sp, #4]
17233	17616	add sp, sp, #68
17234	17617	@ sp needed
17235		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
17236		-.L2845:
	17618	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	17619	+.L2771:
17237	17620	.align 2
17238		-.L2844:
	17621	+.L2770:
17239	17622	.word .LANCHOR1
17240	17623	.word .LANCHOR2-1664
17241	17624	.word .LANCHOR2
17242		- .word .LANCHOR2-1736
17243		- .word .LANCHOR2-1658
17244		- .word .LANCHOR4
	17625	+ .word .LANCHOR2-1728
17245	17626	.word .LANCHOR0
17246		- .word .LANCHOR2-1662
	17627	+ .word .LANCHOR2+1156
	17628	+ .word .LANCHOR2-1660
17247	17629	.word .LC147
17248		- .word .LANCHOR4+1164
17249	17630	.word .LC148
17250		- .word .LANCHOR2-1668
17251		- .word .LANCHOR1+3448
	17631	+ .word .LANCHOR1+3444
17252	17632	.fnend
17253	17633	.size FtlGcScanTempBlk, .-FtlGcScanTempBlk
17254	17634	.align 2
17255	17635	.global FtlGcRefreshOpenBlock
	17636	+ .syntax unified
	17637	+ .arm
	17638	+ .fpu softvfp
17256	17639	.type FtlGcRefreshOpenBlock, %function
17257	17640	FtlGcRefreshOpenBlock:
17258	17641	.fnstart
17259	17642	@ args = 0, pretend = 0, frame = 0
17260	17643	@ frame_needed = 0, uses_anonymous_args = 0
17261		- stmfd sp!, {r4, r5, r6, lr}
	17644	+ push {r4, r5, r6, lr}
17262	17645	.save {r4, r5, r6, lr}
17263		- mov r5, r0
17264		- ldr r4, .L2854
17265		- ldrh r3, [r4, #-4]
	17646	+ ldr r6, .L2780
	17647	+ ldrh r3, [r6]
17266	17648	cmp r3, r0
17267		- beq .L2848
17268		- ldrh r3, [r4, #-2]
	17649	+ beq .L2774
	17650	+ add r5, r6, #16
	17651	+ ldrh r3, [r5, #-14]
17269	17652	cmp r3, r0
17270		- beq .L2848
17271		- ldrh r3, [r4]
	17653	+ beq .L2774
	17654	+ ldrh r3, [r5, #-12]
17272	17655	cmp r3, r0
17273		- beq .L2848
17274		- add r6, r4, #16
17275		- ldrh r3, [r6, #-14]
	17656	+ beq .L2774
	17657	+ ldrh r3, [r5, #-10]
17276	17658	cmp r3, r0
17277		- beq .L2848
17278		- ldr r0, .L2854+4
17279		- mov r1, r5
	17659	+ beq .L2774
	17660	+ mov r4, r0
	17661	+ mov r1, r0
	17662	+ ldr r0, .L2780+4
17280	17663	bl printk
17281		- ldrh r2, [r4, #-4]
	17664	+ ldrh r2, [r6]
17282	17665	movw r3, #65535
17283	17666	cmp r2, r3
17284		- streqh r5, [r4, #-4] @ movhi
17285		- beq .L2848
17286		- ldrh r2, [r4, #-2]
	17667	+ strheq r4, [r6] @ movhi
	17668	+ beq .L2774
	17669	+ ldrh r2, [r5, #-14]
17287	17670	cmp r2, r3
17288		- streqh r5, [r4, #-2] @ movhi
17289		- beq .L2848
17290		- ldrh r2, [r4]
	17671	+ strheq r4, [r5, #-14] @ movhi
	17672	+ beq .L2774
	17673	+ ldrh r2, [r5, #-12]
17291	17674	cmp r2, r3
17292		- streqh r5, [r4] @ movhi
17293		- beq .L2848
17294		- ldrh r2, [r6, #-14]
	17675	+ strheq r4, [r5, #-12] @ movhi
	17676	+ beq .L2774
	17677	+ ldrh r2, [r5, #-10]
17295	17678	cmp r2, r3
17296		- streqh r5, [r6, #-14] @ movhi
17297		-.L2848:
	17679	+ strheq r4, [r5, #-10] @ movhi
	17680	+.L2774:
17298	17681	mov r0, #0
17299		- ldmfd sp!, {r4, r5, r6, pc}
17300		-.L2855:
	17682	+ pop {r4, r5, r6, pc}
	17683	+.L2781:
17301	17684	.align 2
17302		-.L2854:
	17685	+.L2780:
17303	17686	.word .LANCHOR2-1536
17304	17687	.word .LC149
17305	17688	.fnend
17306	17689	.size FtlGcRefreshOpenBlock, .-FtlGcRefreshOpenBlock
17307	17690	.align 2
17308	17691	.global FtlGcRefreshBlock
	17692	+ .syntax unified
	17693	+ .arm
	17694	+ .fpu softvfp
17309	17695	.type FtlGcRefreshBlock, %function
17310	17696	FtlGcRefreshBlock:
17311	17697	.fnstart
17312	17698	@ args = 0, pretend = 0, frame = 0
17313	17699	@ frame_needed = 0, uses_anonymous_args = 0
17314		- stmfd sp!, {r4, r5, r6, lr}
	17700	+ push {r4, r5, r6, lr}
17315	17701	.save {r4, r5, r6, lr}
17316		- mov r5, r0
17317		- ldr r4, .L2867
17318		- ldrh r3, [r4, #-4]
	17702	+ ldr r6, .L2793
	17703	+ ldrh r3, [r6]
17319	17704	cmp r3, r0
17320		- beq .L2864
17321		- ldrh r3, [r4, #-2]
	17705	+ beq .L2790
	17706	+ add r5, r6, #16
	17707	+ ldrh r3, [r5, #-14]
17322	17708	cmp r3, r0
17323		- beq .L2864
17324		- ldrh r3, [r4]
	17709	+ beq .L2790
	17710	+ ldrh r3, [r5, #-12]
17325	17711	cmp r3, r0
17326		- beq .L2864
17327		- add r6, r4, #16
17328		- ldrh r3, [r6, #-14]
	17712	+ beq .L2790
	17713	+ ldrh r3, [r5, #-10]
17329	17714	cmp r3, r0
17330		- beq .L2864
17331		- ldr r0, .L2867+4
17332		- mov r1, r5
	17715	+ beq .L2790
	17716	+ mov r4, r0
	17717	+ mov r1, r0
	17718	+ ldr r0, .L2793+4
17333	17719	bl printk
17334		- ldrh r2, [r4, #-4]
	17720	+ ldrh r2, [r6]
17335	17721	movw r3, #65535
17336	17722	cmp r2, r3
17337		- streqh r5, [r4, #-4] @ movhi
17338		- beq .L2864
17339		- ldrh r2, [r4, #-2]
	17723	+ strheq r4, [r6] @ movhi
	17724	+ beq .L2790
	17725	+ ldrh r2, [r5, #-14]
17340	17726	cmp r2, r3
17341		- streqh r5, [r4, #-2] @ movhi
17342		- beq .L2864
17343		- ldrh r2, [r4]
	17727	+ strheq r4, [r5, #-14] @ movhi
	17728	+ beq .L2790
	17729	+ ldrh r2, [r5, #-12]
17344	17730	cmp r2, r3
17345		- streqh r5, [r4] @ movhi
17346		- beq .L2864
17347		- ldrh r2, [r6, #-14]
	17731	+ strheq r4, [r5, #-12] @ movhi
	17732	+ beq .L2790
	17733	+ ldrh r2, [r5, #-10]
17348	17734	cmp r2, r3
17349		- bne .L2865
17350		- strh r5, [r6, #-14] @ movhi
17351		-.L2864:
	17735	+ bne .L2791
	17736	+ strh r4, [r5, #-10] @ movhi
	17737	+.L2790:
17352	17738	mov r0, #0
17353		- ldmfd sp!, {r4, r5, r6, pc}
17354		-.L2865:
	17739	+ pop {r4, r5, r6, pc}
	17740	+.L2791:
17355	17741	mvn r0, #0
17356		- ldmfd sp!, {r4, r5, r6, pc}
17357		-.L2868:
	17742	+ pop {r4, r5, r6, pc}
	17743	+.L2794:
17358	17744	.align 2
17359		-.L2867:
	17745	+.L2793:
17360	17746	.word .LANCHOR2-1536
17361	17747	.word .LC149
17362	17748	.fnend
17363	17749	.size FtlGcRefreshBlock, .-FtlGcRefreshBlock
17364	17750	.align 2
17365	17751	.global FtlGcMarkBadPhyBlk
	17752	+ .syntax unified
	17753	+ .arm
	17754	+ .fpu softvfp
17366	17755	.type FtlGcMarkBadPhyBlk, %function
17367	17756	FtlGcMarkBadPhyBlk:
17368	17757	.fnstart
17369	17758	@ args = 0, pretend = 0, frame = 0
17370	17759	@ frame_needed = 0, uses_anonymous_args = 0
17371		- stmfd sp!, {r3, r4, r5, r6, r7, lr}
17372		- .save {r3, r4, r5, r6, r7, lr}
	17760	+ push {r4, r5, r6, r7, r8, lr}
	17761	+ .save {r4, r5, r6, r7, r8, lr}
17373	17762	mov r5, r0
	17763	+ ldr r6, .L2804
17374	17764	bl P2V_block_in_plane
17375		- ldr r6, .L2879
17376		- mov r2, r5
17377	17765	sub r7, r6, #1520
17378		- ldrh r1, [r7, #-6]
17379	17766	mov r4, r0
17380		- ldr r0, .L2879+4
	17767	+ mov r2, r5
	17768	+ ldrh r1, [r7, #-2]
	17769	+ ldr r0, .L2804+4
17381	17770	bl printk
17382	17771	mov r0, r4
17383	17772	bl FtlGcRefreshBlock
17384		- ldr r3, [r6, #-1872]
	17773	+ ldr r3, [r6, #-1868]
17385	17774	cmp r3, #0
17386		- beq .L2870
17387		- ldr r2, [r6, #-1416]
17388		- mov r4, r4, asl #1
	17775	+ beq .L2796
	17776	+ ldr r2, [r6, #-1412]
	17777	+ lsl r4, r4, #1
17389	17778	ldrh r3, [r2, r4]
17390	17779	cmp r3, #39
17391	17780	subhi r3, r3, #40
17392		- strhih r3, [r2, r4] @ movhi
17393		-.L2870:
17394		- ldrh r3, [r7, #-6]
	17781	+ strhhi r3, [r2, r4] @ movhi
	17782	+.L2796:
	17783	+ ldrh r3, [r7, #-2]
17395	17784	mov r2, #0
17396		- ldr r0, .L2879+8
17397		-.L2871:
	17785	+ ldr r0, .L2804+8
	17786	+.L2797:
17398	17787	uxth r1, r2
17399		- cmp r1, r3
17400		- bcs .L2878
17401		- add r2, r2, #1
17402		- add r1, r0, r2, asl #1
17403		- ldrh r1, [r1, #-2]
17404		- cmp r1, r5
17405		- bne .L2871
17406		- b .L2872
17407		-.L2878:
	17788	+ cmp r3, r1
	17789	+ bhi .L2799
17408	17790	cmp r3, #15
17409	17791	addls r2, r3, #1
17410		- strlsh r2, [r7, #-6] @ movhi
17411		- ldrls r2, .L2879+8
17412		- movls r3, r3, asl #1
17413		- strlsh r5, [r2, r3] @ movhi
17414		-.L2872:
	17792	+ lslls r3, r3, #1
	17793	+ strhls r2, [r7, #-2] @ movhi
	17794	+ ldrls r2, .L2804+8
	17795	+ strhls r5, [r2, r3] @ movhi
	17796	+ b .L2798
	17797	+.L2799:
	17798	+ add r2, r2, #1
	17799	+ add r1, r0, r2, lsl #1
	17800	+ ldrh r1, [r1, #-2]
	17801	+ cmp r1, r5
	17802	+ bne .L2797
	17803	+.L2798:
17415	17804	mov r0, #0
17416		- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
17417		-.L2880:
	17805	+ pop {r4, r5, r6, r7, r8, pc}
	17806	+.L2805:
17418	17807	.align 2
17419		-.L2879:
	17808	+.L2804:
17420	17809	.word .LANCHOR2
17421	17810	.word .LC150
17422		- .word .LANCHOR4+1768
	17811	+ .word .LANCHOR2+1760
17423	17812	.fnend
17424	17813	.size FtlGcMarkBadPhyBlk, .-FtlGcMarkBadPhyBlk
17425	17814	.align 2
17426	17815	.global FtlGcReFreshBadBlk
	17816	+ .syntax unified
	17817	+ .arm
	17818	+ .fpu softvfp
17427	17819	.type FtlGcReFreshBadBlk, %function
17428	17820	FtlGcReFreshBadBlk:
17429	17821	.fnstart
17430	17822	@ args = 0, pretend = 0, frame = 0
17431	17823	@ frame_needed = 0, uses_anonymous_args = 0
17432		- stmfd sp!, {r4, lr}
	17824	+ push {r4, lr}
17433	17825	.save {r4, lr}
17434		- ldr r4, .L2888
17435		- ldrh r3, [r4, #-6]
	17826	+ ldr r4, .L2813
	17827	+ ldrh r3, [r4, #-2]
17436	17828	cmp r3, #0
17437		- beq .L2882
17438		- ldrh r1, [r4, #-20]
	17829	+ beq .L2807
	17830	+ ldrh r1, [r4, #-16]
17439	17831	movw r2, #65535
17440	17832	cmp r1, r2
17441		- bne .L2882
17442		- ldrh r2, [r4, #-2]
	17833	+ bne .L2807
	17834	+ add r4, r4, #16
	17835	+ ldrh r2, [r4, #-14]
17443	17836	cmp r2, r3
17444		- ldr r2, .L2888+4
	17837	+ ldr r2, .L2813+4
17445	17838	movcs r3, #0
17446		- strcsh r3, [r4, #-2] @ movhi
17447		- ldrh r3, [r4, #-2]
17448		- mov r3, r3, asl #1
	17839	+ strhcs r3, [r4, #-14] @ movhi
	17840	+ ldrh r3, [r4, #-14]
	17841	+ lsl r3, r3, #1
17449	17842	ldrh r0, [r2, r3]
17450	17843	bl P2V_block_in_plane
17451	17844	bl FtlGcRefreshBlock
17452		- ldrh r3, [r4, #-2]
	17845	+ ldrh r3, [r4, #-14]
17453	17846	add r3, r3, #1
17454		- strh r3, [r4, #-2] @ movhi
17455		-.L2882:
	17847	+ strh r3, [r4, #-14] @ movhi
	17848	+.L2807:
17456	17849	mov r0, #0
17457		- ldmfd sp!, {r4, pc}
17458		-.L2889:
	17850	+ pop {r4, pc}
	17851	+.L2814:
17459	17852	.align 2
17460		-.L2888:
	17853	+.L2813:
17461	17854	.word .LANCHOR2-1520
17462		- .word .LANCHOR4+1768
	17855	+ .word .LANCHOR2+1760
17463	17856	.fnend
17464	17857	.size FtlGcReFreshBadBlk, .-FtlGcReFreshBadBlk
17465	17858	.align 2
17466	17859	.global FtlGcFreeBadSuperBlk
	17860	+ .syntax unified
	17861	+ .arm
	17862	+ .fpu softvfp
17467	17863	.type FtlGcFreeBadSuperBlk, %function
17468	17864	FtlGcFreeBadSuperBlk:
17469	17865	.fnstart
17470	17866	@ args = 0, pretend = 0, frame = 8
17471	17867	@ frame_needed = 0, uses_anonymous_args = 0
17472		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	17868	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
17473	17869	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
17474	17870	.pad #12
17475		- ldr r5, .L2904
17476		- ldrh r3, [r5, #-6]
	17871	+ ldr r4, .L2828
	17872	+ ldrh r3, [r4, #-2]
17477	17873	cmp r3, #0
17478		- beq .L2892
17479		- sub r5, r5, #6
17480		- mov r8, r0
	17874	+ beq .L2816
	17875	+ add r9, r4, #1520
17481	17876	mov r7, #0
17482		- mov r9, r5
17483		-.L2891:
17484		- ldr r3, .L2904+4
17485		- uxth r2, r7
17486		- ldrh r3, [r3]
17487		- cmp r3, r2
17488		- bls .L2901
17489		- ldr r3, .L2904+8
17490		- mov r1, r8
17491		- mov r10, #0
17492		- add r3, r3, r2
17493		- ldrb r0, [r3, #-1708] @ zero_extendqisi2
17494		- bl V2P_block
17495		- ldr ip, .L2904+12
17496		- mov fp, r0
17497		-.L2893:
17498		- ldrh r3, [r5]
17499		- uxth r4, r10
17500		- cmp r3, r4
17501		- bls .L2902
17502		- mov r3, r4, asl #1
17503		- add r6, ip, r3
17504		- ldrh r3, [ip, r3]
17505		- cmp r3, fp
17506		- bne .L2894
17507		- mov r1, fp
17508		- ldr r0, .L2904+16
17509		- str ip, [sp, #4]
17510		- bl printk
17511		- mov r0, fp
17512		- bl FtlBbmMapBadBlock
17513		- bl FtlBbmTblFlush
17514		- ldrh r2, [r5]
17515		- mov r3, r6
17516		- ldr ip, [sp, #4]
17517		-.L2895:
17518		- cmp r4, r2
17519		- ldrcch r1, [r3, #2]
17520		- addcc r4, r4, #1
17521		- uxthcc r4, r4
17522		- strcch r1, [r3], #2 @ movhi
17523		- bcc .L2895
17524		-.L2903:
17525		- sub r2, r2, #1
17526		- strh r2, [r9] @ movhi
17527		-.L2894:
17528		- add r10, r10, #1
17529		- b .L2893
17530		-.L2902:
17531		- add r7, r7, #1
17532		- b .L2891
17533		-.L2901:
	17877	+ add fp, r9, #1760
	17878	+ str r0, [sp]
	17879	+.L2817:
	17880	+ ldr r3, .L2828+4
	17881	+ ldrh r2, [r3, #-4]
	17882	+ uxth r3, r7
	17883	+ cmp r2, r3
	17884	+ bhi .L2823
17534	17885	bl FtlGcReFreshBadBlk
17535		-.L2892:
	17886	+.L2816:
17536	17887	mov r0, #0
17537	17888	add sp, sp, #12
17538	17889	@ sp needed
17539		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
17540		-.L2905:
	17890	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	17891	+.L2823:
	17892	+ uxtah r3, r9, r7
	17893	+ ldr r1, [sp]
	17894	+ mov r8, #0
	17895	+ ldrb r0, [r3, #-1706] @ zero_extendqisi2
	17896	+ bl V2P_block
	17897	+ ldr r2, .L2828+8
	17898	+ mov r10, r0
	17899	+.L2818:
	17900	+ ldrh r1, [r4, #-2]
	17901	+ uxth r5, r8
	17902	+ cmp r1, r5
	17903	+ addls r7, r7, #1
	17904	+ bls .L2817
	17905	+.L2822:
	17906	+ uxth r6, r8
	17907	+ lsl r1, r6, #1
	17908	+ ldrh r1, [fp, r1]
	17909	+ cmp r1, r10
	17910	+ bne .L2819
	17911	+ mov r1, r10
	17912	+ mov r0, r2
	17913	+ str r2, [sp, #4]
	17914	+ add r6, fp, r6, lsl #1
	17915	+ bl printk
	17916	+ mov r0, r10
	17917	+ bl FtlBbmMapBadBlock
	17918	+ bl FtlBbmTblFlush
	17919	+ ldrh r1, [r4, #-2]
	17920	+ ldr r2, [sp, #4]
	17921	+.L2820:
	17922	+ cmp r5, r1
	17923	+ bcc .L2821
	17924	+ sub r1, r1, #1
	17925	+ strh r1, [r4, #-2] @ movhi
	17926	+.L2819:
	17927	+ add r8, r8, #1
	17928	+ b .L2818
	17929	+.L2821:
	17930	+ ldrh r0, [r6, #2]!
	17931	+ add r5, r5, #1
	17932	+ uxth r5, r5
	17933	+ strh r0, [r6, #-2] @ movhi
	17934	+ b .L2820
	17935	+.L2829:
17541	17936	.align 2
17542		-.L2904:
	17937	+.L2828:
17543	17938	.word .LANCHOR2-1520
17544		- .word .LANCHOR2-1736
17545		- .word .LANCHOR2
17546		- .word .LANCHOR4+1768
	17939	+ .word .LANCHOR2-1728
17547	17940	.word .LC151
17548	17941	.fnend
17549	17942	.size FtlGcFreeBadSuperBlk, .-FtlGcFreeBadSuperBlk
17550	17943	.align 2
17551	17944	.global update_vpc_list
	17945	+ .syntax unified
	17946	+ .arm
	17947	+ .fpu softvfp
17552	17948	.type update_vpc_list, %function
17553	17949	update_vpc_list:
17554	17950	.fnstart
17555	17951	@ args = 0, pretend = 0, frame = 0
17556	17952	@ frame_needed = 0, uses_anonymous_args = 0
17557		- ldr r2, .L2916
17558		- mov r3, r0, asl #1
17559		- stmfd sp!, {r4, lr}
	17953	+ ldr r2, .L2839
	17954	+ lsl r3, r0, #1
	17955	+ push {r4, lr}
17560	17956	.save {r4, lr}
17561		- mov r4, r0
17562		- ldr r1, [r2, #-1408]
	17957	+ ldr r1, [r2, #-1404]
17563	17958	ldrh r3, [r1, r3]
17564	17959	cmp r3, #0
17565		- bne .L2907
17566		- ldr r0, .L2916+4
17567		- movw r1, #1164
17568		- ldrh ip, [r0, r1]
17569		- cmp ip, r4
	17960	+ bne .L2831
	17961	+ movw r1, #1156
	17962	+ mov r4, r0
	17963	+ ldrh r0, [r2, r1]
	17964	+ cmp r0, r4
17570	17965	mvneq r3, #0
17571		- streqh r3, [r0, r1] @ movhi
17572		- beq .L2909
	17966	+ strheq r3, [r2, r1] @ movhi
	17967	+ beq .L2833
17573	17968	add r1, r2, #884
17574	17969	ldrh r1, [r1]
17575	17970	cmp r1, r4
17576		- beq .L2915
	17971	+ beq .L2830
17577	17972	add r1, r2, #932
17578	17973	ldrh r1, [r1]
17579	17974	cmp r1, r4
17580		- beq .L2915
	17975	+ beq .L2830
17581	17976	add r2, r2, #980
17582	17977	ldrh r2, [r2]
17583	17978	cmp r2, r4
17584		- beq .L2915
17585		-.L2909:
	17979	+ beq .L2830
	17980	+.L2833:
17586	17981	mov r1, r4
17587		- ldr r0, .L2916+8
	17982	+ ldr r0, .L2839+4
17588	17983	bl List_remove_node
17589		- ldr r2, .L2916+12
	17984	+ ldr r2, .L2839+8
17590	17985	mov r0, r4
17591	17986	ldrh r3, [r2]
17592	17987	sub r3, r3, #1
..	..	@@ -17594,54 +17989,57 @@
17594	17989	bl free_data_superblock
17595	17990	mov r0, r4
17596	17991	bl FtlGcFreeBadSuperBlk
17597		- mov r0, #1
17598		- ldmfd sp!, {r4, pc}
17599		-.L2907:
	17992	+ mov r3, #1
	17993	+.L2830:
	17994	+ mov r0, r3
	17995	+ pop {r4, pc}
	17996	+.L2831:
17600	17997	bl List_update_data_list
17601		-.L2915:
17602		- mov r0, #0
17603		- ldmfd sp!, {r4, pc}
17604		-.L2917:
	17998	+ mov r3, #0
	17999	+ b .L2830
	18000	+.L2840:
17605	18001	.align 2
17606		-.L2916:
	18002	+.L2839:
17607	18003	.word .LANCHOR2
17608		- .word .LANCHOR4
17609	18004	.word .LANCHOR2+864
17610	18005	.word .LANCHOR2+872
17611	18006	.fnend
17612	18007	.size update_vpc_list, .-update_vpc_list
17613	18008	.align 2
17614	18009	.global decrement_vpc_count
	18010	+ .syntax unified
	18011	+ .arm
	18012	+ .fpu softvfp
17615	18013	.type decrement_vpc_count, %function
17616	18014	decrement_vpc_count:
17617	18015	.fnstart
17618	18016	@ args = 0, pretend = 0, frame = 0
17619	18017	@ frame_needed = 0, uses_anonymous_args = 0
17620	18018	movw r3, #65535
17621		- cmp r0, r3
17622		- stmfd sp!, {r4, r5, r6, lr}
	18019	+ push {r4, r5, r6, lr}
17623	18020	.save {r4, r5, r6, lr}
	18021	+ cmp r0, r3
17624	18022	mov r4, r0
17625		- beq .L2919
17626		- ldr r5, .L2929
17627		- mov r6, r0, asl #1
17628		- ldr r3, [r5, #-1408]
	18023	+ ldr r5, .L2852
	18024	+ beq .L2842
	18025	+ ldr r3, [r5, #-1404]
	18026	+ lsl r6, r0, #1
17629	18027	ldrh r2, [r3, r6]
17630	18028	cmp r2, #0
17631	18029	subne r2, r2, #1
17632		- strneh r2, [r3, r6] @ movhi
17633		- bne .L2919
17634		- mov r1, r4
17635		- ldr r0, .L2929+4
	18030	+ strhne r2, [r3, r6] @ movhi
	18031	+ bne .L2842
	18032	+ mov r1, r0
	18033	+ ldr r0, .L2852+4
17636	18034	bl printk
17637		- ldr r3, [r5, #-1408]
	18035	+ ldr r3, [r5, #-1404]
17638	18036	mov r2, #32
17639		- add r0, r5, #876
17640	18037	mov r1, r4
	18038	+ add r0, r5, #876
17641	18039	strh r2, [r3, r6] @ movhi
17642	18040	bl test_node_in_list
17643	18041	cmp r0, #0
17644		- beq .L2921
	18042	+ beq .L2844
17645	18043	mov r1, r4
17646	18044	add r0, r5, #876
17647	18045	bl List_remove_node
..	..	@@ -17651,842 +18049,794 @@
17651	18049	sub r3, r3, #1
17652	18050	strh r3, [r2] @ movhi
17653	18051	bl INSERT_DATA_LIST
17654		- ldr r3, [r5, #-1408]
17655		- ldr r0, .L2929+8
	18052	+ ldr r3, [r5, #-1404]
17656	18053	mov r1, r4
	18054	+ ldr r0, .L2852+8
17657	18055	ldrh r2, [r3, r6]
17658	18056	bl printk
17659		-.L2921:
	18057	+.L2844:
17660	18058	mov r0, r4
17661	18059	bl FtlGcRefreshBlock
17662		- b .L2924
17663		-.L2919:
17664		- ldr r6, .L2929+12
17665		- movw r5, #1748
17666		- movw r3, #65535
17667		- ldrh r0, [r6, r5]
17668		- cmp r0, r3
17669		- streqh r4, [r6, r5] @ movhi
17670		- beq .L2924
17671		- cmp r0, r4
17672		- beq .L2924
17673		- bl update_vpc_list
17674		- strh r4, [r6, r5] @ movhi
17675		- adds r0, r0, #0
17676		- movne r0, #1
17677		- ldmfd sp!, {r4, r5, r6, pc}
17678		-.L2924:
	18060	+.L2847:
17679	18061	mov r0, #0
17680		- ldmfd sp!, {r4, r5, r6, pc}
17681		-.L2930:
	18062	+ pop {r4, r5, r6, pc}
	18063	+.L2842:
	18064	+ movw r6, #1740
	18065	+ movw r3, #65535
	18066	+ ldrh r0, [r5, r6]
	18067	+ cmp r0, r3
	18068	+ strheq r4, [r5, r6] @ movhi
	18069	+ beq .L2847
	18070	+ cmp r4, r0
	18071	+ beq .L2847
	18072	+ bl update_vpc_list
	18073	+ adds r0, r0, #0
	18074	+ strh r4, [r5, r6] @ movhi
	18075	+ movne r0, #1
	18076	+ pop {r4, r5, r6, pc}
	18077	+.L2853:
17682	18078	.align 2
17683		-.L2929:
	18079	+.L2852:
17684	18080	.word .LANCHOR2
17685	18081	.word .LC152
17686	18082	.word .LC153
17687		- .word .LANCHOR4
17688	18083	.fnend
17689	18084	.size decrement_vpc_count, .-decrement_vpc_count
17690	18085	.align 2
17691	18086	.global FtlRecoverySuperblock
	18087	+ .syntax unified
	18088	+ .arm
	18089	+ .fpu softvfp
17692	18090	.type FtlRecoverySuperblock, %function
17693	18091	FtlRecoverySuperblock:
17694	18092	.fnstart
17695		- @ args = 0, pretend = 0, frame = 64
	18093	+ @ args = 0, pretend = 0, frame = 48
17696	18094	@ frame_needed = 0, uses_anonymous_args = 0
17697		- ldrh r3, [r0]
17698		- movw r2, #65535
17699		- mov r1, r0
17700		- cmp r3, r2
17701		- beq .L3075
17702		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	18095	+ ldrh r2, [r0]
	18096	+ movw r1, #65535
	18097	+ cmp r2, r1
	18098	+ beq .L2999
	18099	+ ldr r2, .L3011
	18100	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
17703	18101	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
17704		- .pad #68
17705		- sub sp, sp, #68
	18102	+ .pad #52
	18103	+ sub sp, sp, #52
17706	18104	ldrh r3, [r0, #2]
	18105	+ mov fp, r0
	18106	+ ldrh r2, [r2, #-2]
17707	18107	str r3, [sp, #8]
17708		- ldrb r3, [r0, #6] @ zero_extendqisi2
17709		- ldr r0, [sp, #8]
17710		- str r3, [sp]
17711		- ldr r3, .L3090
17712		- ldrh r3, [r3, #-4]
17713		- cmp r3, r0
17714		- mov r3, #0
17715		- streqh r3, [r1, #4] @ movhi
17716		- streqb r3, [r1, #6]
17717		- ldrneh r0, [r1, #16]
17718		- beq .L3072
17719		-.L2935:
17720		- cmp r0, r2
17721		- add r3, r3, #1
17722		- uxtheq r0, r3
17723		- addeq r0, r1, r0, asl #1
17724		- ldreqh r0, [r0, #16]
17725		- beq .L2935
17726		-.L3085:
17727		- mov r9, r1
17728		- ldrb r1, [r1, #8] @ zero_extendqisi2
17729		- cmp r1, #1
17730		- bne .L2937
17731		- bl FtlGetLastWrittenPage
17732		- cmn r0, #1
17733		- mov r4, r0
17734		- beq .L2938
17735		- ldr r3, .L3090+4
17736		- ldrb r3, [r3, #-2744] @ zero_extendqisi2
17737		- cmp r3, #0
17738		- bne .L3076
17739		- ldr r3, .L3090+8
17740		- add r3, r3, r0, asl #1
17741		- ldrh r6, [r3, #80]
17742		- b .L3009
17743		-.L2937:
17744		- mov r1, #0
17745		- bl FtlGetLastWrittenPage
17746		- cmn r0, #1
17747		- mov r4, r0
17748		- beq .L2938
17749		-.L3076:
17750		- mov r6, r4
17751		-.L3009:
17752		- ldr r3, .L3090+4
17753		- movw r8, #65535
17754		- sub r2, r3, #1728
17755		- sub r3, r3, #1648
17756		- ldr ip, [r3, #144]
17757		- ldr lr, [r3, #212]
17758		- ldrh r2, [r2, #-8]
17759		- ldrh r7, [r3, #-8]
17760		- add r3, r9, #14
17761		- str r3, [sp, #20]
17762		- str r2, [sp, #4]
	18108	+ cmp r2, r3
17763	18109	mov r2, #0
17764		- mov r0, r3
17765		- mov r5, r2
17766		- mov r10, r2
17767		- b .L2940
17768		-.L2938:
17769		- mov r3, #0
17770		- strh r3, [r9, #2] @ movhi
17771		- strb r3, [r9, #6]
17772		- b .L3072
17773		-.L2942:
17774		- ldrh r3, [r0, #2]!
17775		- cmp r3, r8
17776		- beq .L2941
17777		- mov r1, #36
17778		- orr r3, r6, r3, asl #10
17779		- mla r1, r1, r5, ip
17780		- stmib r1, {r3, r10}
17781		- mul r3, r7, r5
17782		- add r5, r5, #1
17783		- uxth r5, r5
17784		- add fp, r3, #3
17785		- cmp r3, #0
17786		- movlt r3, fp
17787		- bic r3, r3, #3
17788		- add r3, lr, r3
17789		- str r3, [r1, #12]
17790		-.L2941:
	18110	+ strheq r2, [r0, #4] @ movhi
	18111	+ strbeq r2, [r0, #6]
	18112	+ ldrhne r0, [r0, #16]
	18113	+ bne .L2858
	18114	+.L2997:
	18115	+ mov r0, #0
	18116	+ add sp, sp, #52
	18117	+ @ sp needed
	18118	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	18119	+.L2859:
	18120	+ uxth r0, r2
	18121	+ add r0, fp, r0, lsl #1
	18122	+ ldrh r0, [r0, #16]
	18123	+.L2858:
	18124	+ cmp r0, r1
17791	18125	add r2, r2, #1
17792		-.L2940:
17793		- ldr r1, [sp, #4]
	18126	+ beq .L2859
	18127	+ ldrb r1, [fp, #8] @ zero_extendqisi2
	18128	+ ldrb r3, [fp, #6] @ zero_extendqisi2
	18129	+ cmp r1, #1
	18130	+ str r3, [sp, #12]
	18131	+ bne .L2860
	18132	+ bl FtlGetLastWrittenPage
	18133	+ cmn r0, #1
	18134	+ mov r4, r0
	18135	+ beq .L2861
	18136	+ ldr r3, .L3011+4
	18137	+ ldrb r3, [r3, #-2740] @ zero_extendqisi2
	18138	+ cmp r3, #0
	18139	+ bne .L2932
	18140	+ ldr r3, .L3011+8
	18141	+ add r3, r3, r0, lsl #1
	18142	+ ldrh r5, [r3, #84]
	18143	+.L2862:
	18144	+ ldr r3, .L3011+4
	18145	+ mov r9, #36
	18146	+ sub r2, r3, #1728
	18147	+ ldr r0, [r3, #-1500]
	18148	+ ldrh r2, [r2, #-4]
	18149	+ sub r3, r3, #1648
	18150	+ ldr lr, [r3, #216]
	18151	+ ldrh r7, [r3, #-6]
	18152	+ add r3, fp, #16
	18153	+ str r2, [sp]
	18154	+ mov r2, #0
	18155	+ mov ip, r3
	18156	+ mov r6, r2
	18157	+ mov r10, r2
	18158	+ str r3, [sp, #20]
	18159	+.L2863:
	18160	+ ldr r1, [sp]
17794	18161	uxth r3, r2
17795		- cmp r3, r1
17796		- bcc .L2942
17797		- ldrb r3, [r9, #8] @ zero_extendqisi2
17798		- ldr fp, .L3090+4
	18162	+ cmp r1, r3
	18163	+ bhi .L2865
	18164	+ ldrb r3, [fp, #8] @ zero_extendqisi2
	18165	+ ldr r8, .L3011+4
17799	18166	cmp r3, #1
17800	18167	movne r3, #0
17801		- bne .L3077
17802		- ldrb lr, [fp, #-2744] @ zero_extendqisi2
17803		- adds r3, lr, #0
	18168	+ bne .L3002
	18169	+ ldrb r3, [r8, #-2740] @ zero_extendqisi2
	18170	+ adds r3, r3, #0
17804	18171	movne r3, #1
17805		-.L3077:
	18172	+.L3002:
17806	18173	str r3, [sp, #24]
17807		- mov r1, r5
	18174	+ mov r1, r6
17808	18175	ldr r2, [sp, #24]
17809		- mov r10, #0
17810		- ldr r0, [fp, #-1504]
	18176	+ mov r7, #0
	18177	+ ldr r10, .L3011+4
	18178	+ movw r9, #65535
17811	18179	bl FlashReadPages
17812		- ldr r3, [fp, #-1612]
17813		- ldr r2, .L3090+4
17814		- str r3, [sp, #28]
17815		- movw r3, #65535
	18180	+ ldr r3, [r8, #-1608]
17816	18181	str r3, [sp, #16]
17817		-.L2944:
17818		- uxth r7, r10
17819		- cmp r7, r5
17820		- bcs .L2951
17821		- mov r1, #36
17822		- ldr r0, [r2, #-1504]
17823		- mul r1, r1, r10
17824		- add ip, r0, r1
17825		- ldr r1, [r0, r1]
17826		- cmp r1, #0
17827		- bne .L2945
17828		- ldr ip, [ip, #12]
17829		- ldr r8, [ip, #4]
17830		- cmn r8, #1
17831		- beq .L2946
17832		- ldr r1, [r2, #-1612]
17833		- mov r0, r8
17834		- str ip, [sp, #12]
17835		- str r2, [sp, #4]
17836		- bl ftl_cmp_data_ver
17837		- ldr r2, [sp, #4]
17838		- cmp r0, #0
17839		- ldr ip, [sp, #12]
17840		- addne r8, r8, #1
17841		- strne r8, [r2, #-1612]
17842		-.L2946:
17843		- ldr r1, [ip]
17844		- cmn r1, #1
17845		- bne .L2947
17846		-.L2951:
17847		- cmp r7, r5
17848		- ldr r5, .L3090+4
17849		- bne .L3073
17850		- add fp, r4, #1
17851		- uxth r3, fp
17852		- str r3, [sp, #4]
17853		- ldr r3, [r5, #-1504]
17854		- ldr r0, [r3, #4]
17855		- b .L3078
17856		-.L2945:
17857		- ldr r1, [ip, #4]
17858		- ldr r0, .L3090+12
17859		- str r2, [sp, #4]
17860		- bl printk
17861		- uxth r3, r6
17862		- ldrh r1, [r9]
17863		- str r3, [sp, #16]
17864		- ldr r2, [sp, #4]
17865		- ldr r3, .L3090+16
17866		- strh r1, [r3] @ movhi
17867		-.L2947:
17868		- add r10, r10, #1
17869		- b .L2944
17870		-.L3073:
	18182	+.L2867:
	18183	+ uxth r3, r7
	18184	+ cmp r6, r3
	18185	+ bhi .L2872
	18186	+ bne .L2870
	18187	+ add r4, r4, #1
17871	18188	uxth r3, r4
17872		- str r3, [sp, #4]
17873		- ldr r3, [fp, #-1504]
17874		- mov r2, #36
17875		- mla r7, r2, r7, r3
17876		- ldr r0, [r7, #4]
17877		-.L3078:
	18189	+ str r3, [sp]
	18190	+ ldr r3, [r8, #-1500]
	18191	+ ldr r0, [r3, #4]
	18192	+.L3003:
17878	18193	ubfx r0, r0, #10, #16
17879	18194	bl P2V_plane
17880		- ldrb r3, [r9, #8] @ zero_extendqisi2
	18195	+ ldrb r3, [fp, #8] @ zero_extendqisi2
	18196	+ str r0, [sp, #4]
17881	18197	cmp r3, #1
17882		- str r0, [sp, #12]
17883		- bne .L2953
17884		- ldrb r2, [r5, #-2744] @ zero_extendqisi2
	18198	+ bne .L2874
	18199	+ ldrb r2, [r8, #-2740] @ zero_extendqisi2
17885	18200	cmp r2, #0
17886		- ldreq r1, [sp, #4]
17887		- ldreq r2, .L3090+8
17888		- addeq r2, r2, r1, asl #1
17889		- ldreqh r2, [r2, #80]
17890		- streq r2, [sp, #4]
17891		-.L2953:
17892		- ldr r2, .L3090
17893		- ldr r1, [sp, #4]
17894		- ldr r0, [sp, #12]
17895		- ldrh r2, [r2, #-4]
	18201	+ ldreq r2, [sp]
	18202	+ ldreq r4, .L3011+8
	18203	+ addeq r4, r4, r2, lsl #1
	18204	+ ldrheq r2, [r4, #84]
	18205	+ streq r2, [sp]
	18206	+.L2874:
	18207	+ ldr r2, .L3011
	18208	+ ldr r1, [sp]
	18209	+ ldrh r2, [r2, #-2]
17896	18210	cmp r2, r1
17897		- ldr r1, [sp, #8]
17898		- ldreqh r2, [sp, #4]
17899		- streqh r2, [r9, #2] @ movhi
	18211	+ ldmib sp, {r0, r1}
	18212	+ ldrheq r2, [sp]
	18213	+ strheq r2, [fp, #2] @ movhi
17900	18214	moveq r2, #0
17901		- streqb r2, [r9, #6]
17902		- streqh r2, [r9, #4] @ movhi
17903		- ldrh r2, [sp]
17904		- str r2, [sp, #32]
17905		- ldr ip, [sp, #32]
17906		- ldr r2, [sp, #4]
	18215	+ strbeq r2, [fp, #6]
	18216	+ strheq r2, [fp, #4] @ movhi
	18217	+ ldrh r2, [sp, #12]
	18218	+ str r2, [sp, #28]
	18219	+ ldr ip, [sp, #28]
	18220	+ ldr r2, [sp]
17907	18221	cmp r2, r1
17908	18222	cmpeq r0, ip
17909		- moveq r0, r9
17910		- moveq r1, r2
17911		- beq .L3083
17912		- clz r3, r3
17913		- ldr r2, [sp, #28]
17914		- ldr r1, [sp, #16]
17915		- mov r3, r3, lsr #5
17916		- sub r2, r2, #1
17917		- str r2, [sp]
	18223	+ moveq r2, r0
	18224	+ beq .L3010
	18225	+ ldr r2, [sp, #16]
	18226	+ sub r10, r2, #1
17918	18227	movw r2, #65535
17919		- cmp r1, r2
17920		- orrne r3, r3, #1
	18228	+ subs r9, r9, r2
	18229	+ movne r9, #1
17921	18230	cmp r3, #0
17922		- beq .L2957
17923		- ldr r3, .L3090+20
17924		- uxth fp, r6
17925		- ldr r8, .L3090+4
17926		- mvn r7, #0
17927		- mov r6, r7
17928		- ldr r2, [r3, #1760]
17929		- cmn r2, #1
17930		- ldreq r2, [sp]
17931		- streq r2, [r3, #1760]
17932		- ldr r10, [r3, #1760]
	18231	+ orreq r9, r9, #1
	18232	+ cmp r9, #0
	18233	+ beq .L2878
	18234	+ ldr r3, [r8, #1752]
	18235	+ uxth r9, r5
	18236	+ uxth r5, r5
	18237	+ ldr r6, .L3011+4
	18238	+ cmn r3, #1
	18239	+ streq r10, [r8, #1752]
	18240	+ ldr r3, [r8, #1752]
	18241	+ mvn r8, #0
	18242	+ mov r7, r8
	18243	+ str r3, [sp, #12]
17933	18244	ldr r3, [sp, #8]
17934	18245	add r3, r3, #7
17935		- cmp fp, r3
17936		- subgt r4, fp, #7
	18246	+ cmp r5, r3
	18247	+ subgt r4, r9, #7
17937	18248	ldrle r4, [sp, #8]
17938	18249	uxthgt r4, r4
17939		-.L2960:
17940		- cmp r4, fp
17941		- bhi .L2973
17942		- ldr r3, .L3090+24
17943		- mov r0, #36
17944		- ldr lr, [r8, #-1504]
	18250	+.L2881:
	18251	+ cmp r4, r9
	18252	+ bhi .L2894
	18253	+ ldr r3, .L3011+12
	18254	+ mov ip, #36
	18255	+ ldr r0, [r6, #-1500]
17945	18256	ldr r1, [sp, #20]
17946	18257	ldrh r3, [r3]
17947	18258	str r3, [sp, #16]
17948	18259	mov r3, #0
17949	18260	mov r5, r3
17950		-.L2974:
17951		- ldr ip, [sp, #16]
17952		- uxth r2, r3
17953		- cmp r2, ip
17954		- bcs .L3086
17955		- ldrh r2, [r1, #2]!
17956		- movw ip, #65535
	18261	+ b .L2895
	18262	+.L2860:
	18263	+ mov r1, #0
	18264	+ bl FtlGetLastWrittenPage
	18265	+ cmn r0, #1
	18266	+ mov r4, r0
	18267	+ beq .L2861
	18268	+.L2932:
	18269	+ mov r5, r4
	18270	+ b .L2862
	18271	+.L2861:
	18272	+ mov r3, #0
	18273	+ strh r3, [fp, #2] @ movhi
	18274	+.L3009:
	18275	+ strb r3, [fp, #6]
	18276	+ b .L2997
	18277	+.L2865:
	18278	+ ldrh r3, [ip], #2
	18279	+ movw r1, #65535
	18280	+ cmp r3, r1
	18281	+ beq .L2864
	18282	+ mla r1, r9, r6, r0
	18283	+ orr r3, r5, r3, lsl #10
	18284	+ stmib r1, {r3, r10}
	18285	+ mul r3, r7, r6
	18286	+ add r6, r6, #1
	18287	+ uxth r6, r6
	18288	+ add r8, r3, #3
	18289	+ cmp r3, #0
	18290	+ movlt r3, r8
	18291	+ bic r3, r3, #3
	18292	+ add r3, lr, r3
	18293	+ str r3, [r1, #12]
	18294	+.L2864:
	18295	+ add r2, r2, #1
	18296	+ b .L2863
	18297	+.L2872:
	18298	+ mov r3, #36
	18299	+ ldr r1, [r10, #-1500]
	18300	+ mul r3, r3, r7
	18301	+ add r2, r1, r3
	18302	+ ldr r3, [r1, r3]
	18303	+ cmp r3, #0
	18304	+ bne .L2868
	18305	+ ldr r2, [r2, #12]
	18306	+ ldr r3, [r2, #4]
	18307	+ cmn r3, #1
	18308	+ beq .L2869
	18309	+ ldr r1, [r10, #-1608]
	18310	+ mov r0, r3
	18311	+ bl ftl_cmp_data_ver
	18312	+ cmp r0, #0
	18313	+ addne r3, r3, #1
	18314	+ strne r3, [r10, #-1608]
	18315	+.L2869:
	18316	+ ldr r3, [r2]
	18317	+ cmn r3, #1
	18318	+ bne .L2871
	18319	+.L2870:
	18320	+ uxth r3, r4
	18321	+ uxth r7, r7
	18322	+ str r3, [sp]
	18323	+ mov r2, #36
	18324	+ ldr r3, [r8, #-1500]
	18325	+ mla r7, r2, r7, r3
	18326	+ ldr r0, [r7, #4]
	18327	+ b .L3003
	18328	+.L2868:
	18329	+ ldr r1, [r2, #4]
	18330	+ uxth r9, r5
	18331	+ ldr r0, .L3011+16
	18332	+ bl printk
	18333	+ ldrh r3, [fp]
	18334	+ ldr r2, .L3011+20
	18335	+ strh r3, [r2] @ movhi
	18336	+.L2871:
	18337	+ add r7, r7, #1
	18338	+ b .L2867
	18339	+.L2883:
	18340	+ ldrh r2, [r1], #2
	18341	+ movw lr, #65535
17957	18342	add r3, r3, #1
17958		- cmp r2, ip
17959		- orrne r2, r4, r2, asl #10
17960		- mlane ip, r0, r5, lr
	18343	+ cmp r2, lr
	18344	+ mlane lr, ip, r5, r0
17961	18345	addne r5, r5, #1
	18346	+ orrne r2, r4, r2, lsl #10
17962	18347	uxthne r5, r5
17963		- strne r2, [ip, #4]
17964		- b .L2974
17965		-.L3086:
	18348	+ strne r2, [lr, #4]
	18349	+.L2895:
	18350	+ ldr lr, [sp, #16]
	18351	+ uxth r2, r3
	18352	+ cmp r2, lr
	18353	+ bcc .L2883
17966	18354	mov r1, r5
17967	18355	ldr r2, [sp, #24]
17968		- ldr r0, [r8, #-1504]
17969	18356	bl FlashReadPages
17970		- ldr r3, [r8, #-1504]
	18357	+ ldr r3, [r6, #-1500]
17971	18358	mov r2, #36
17972		- ldrb ip, [r8, #-2744] @ zero_extendqisi2
	18359	+ ldrb ip, [r6, #-2740] @ zero_extendqisi2
17973	18360	movw r1, #65535
17974	18361	mla r5, r2, r5, r3
17975		- ldr r2, .L3090+28
17976		- add r2, r2, r4, asl #1
17977		-.L2963:
17978		- cmp r3, r5
17979		- beq .L3087
	18362	+ ldr r2, .L3011+24
	18363	+ add r2, r2, r4, lsl #1
	18364	+.L2884:
	18365	+ cmp r5, r3
	18366	+ addeq r4, r4, #1
	18367	+ uxtheq r4, r4
	18368	+ beq .L2881
	18369	+.L2893:
17980	18370	ldr r0, [r3]
17981	18371	cmp r0, #0
17982		- bne .L2964
	18372	+ bne .L2885
17983	18373	ldr r0, [r3, #12]
17984	18374	ldrh lr, [r0]
17985	18375	cmp lr, r1
17986		- beq .L2965
	18376	+ beq .L2886
17987	18377	ldr r0, [r0, #4]
17988	18378	cmn r0, #1
17989		- beq .L2965
17990		- ldr lr, .L3090+20
17991		- cmn r7, #1
17992		- ldr r6, [lr, #1760]
17993		- str r0, [lr, #1760]
17994		- bne .L2965
	18379	+ beq .L2886
	18380	+ cmn r8, #1
	18381	+ ldr r7, [r6, #1752]
	18382	+ str r0, [r6, #1752]
	18383	+ bne .L2886
17995	18384	ldrh r0, [r2]
17996	18385	cmp r0, r1
17997		- bne .L2966
	18386	+ bne .L2887
17998	18387	cmp ip, #0
17999		- beq .L2965
18000		-.L2966:
18001		- ldr r0, [sp]
18002		- cmp r6, r0
18003		- mvneq r7, #0
18004		- movne r7, r6
18005		- b .L2965
18006		-.L2964:
18007		- ldrh r1, [r9]
18008		- movw r2, #1802
18009		- ldr r3, .L3090+20
	18388	+ beq .L2886
	18389	+.L2887:
	18390	+ cmp r10, r7
	18391	+ movne r8, r7
	18392	+.L2886:
	18393	+ add r3, r3, #36
	18394	+ b .L2884
	18395	+.L2885:
	18396	+ ldrh r1, [fp]
	18397	+ movw r2, #1794
	18398	+ ldr r3, .L3011+4
18010	18399	strh r1, [r3, r2] @ movhi
18011		- ldrb r2, [r9, #8] @ zero_extendqisi2
	18400	+ ldrb r2, [fp, #8] @ zero_extendqisi2
18012	18401	cmp r2, #0
18013		- bne .L2957
18014		- ldr r2, .L3090+28
18015		- mov r4, r4, asl #1
	18402	+ bne .L2878
	18403	+ ldr r2, .L3011+24
	18404	+ lsl r4, r4, #1
18016	18405	ldrh r1, [r2, r4]
18017	18406	movw r2, #65535
18018	18407	cmp r1, r2
18019		- bne .L2968
18020		- cmn r7, #1
18021		- strne r7, [r3, #1760]
18022		- bne .L2957
18023		- ldr r2, [sp]
	18408	+ bne .L2889
	18409	+ cmn r8, #1
	18410	+ strne r8, [r3, #1752]
	18411	+ bne .L2878
	18412	+ ldr r2, [sp, #12]
18024	18413	cmp r10, r2
18025		- strne r10, [r3, #1760]
18026		- ldreq r2, [r3, #1760]
18027		- bne .L2957
18028		- b .L3084
18029		-.L2968:
18030		- ldr r2, [sp]
18031		- cmp r6, r2
18032		- beq .L2971
18033		- cmn r6, #1
18034		- strne r6, [r3, #1760]
18035		- b .L2957
18036		-.L2971:
18037		- ldr r2, [r3, #1760]
18038		- ldr r1, [sp]
18039		- cmp r2, r1
18040		- beq .L2957
18041		-.L3084:
	18414	+ beq .L2891
	18415	+.L3005:
	18416	+ str r2, [r3, #1752]
	18417	+ b .L2878
	18418	+.L2891:
	18419	+ ldr r2, [r3, #1752]
	18420	+.L3004:
18042	18421	sub r2, r2, #1
18043		- b .L3079
18044		-.L2965:
18045		- add r3, r3, #36
18046		- b .L2963
18047		-.L3087:
18048		- add r4, r4, #1
18049		- uxth r4, r4
18050		- b .L2960
18051		-.L2973:
18052		- ldr r3, .L3090+20
18053		- mvn r2, #0
18054		-.L3079:
18055		- str r2, [r3, #1760]
18056		-.L2957:
18057		- ldr fp, .L3090+20
18058		- movw r3, #1804
18059		- ldr r10, [sp, #8]
	18422	+ b .L3005
	18423	+.L2889:
	18424	+ cmp r7, r10
	18425	+ beq .L2892
	18426	+ cmn r7, #1
	18427	+ strne r7, [r3, #1752]
	18428	+.L2878:
	18429	+ ldr r9, [sp, #8]
18060	18430	mov r2, #1
18061		- strh r2, [fp, r3] @ movhi
18062		-.L2975:
18063		- ldr r3, .L3090+4
18064		- movw lr, #65535
18065		- ldr r2, .L3090+24
18066		- mov r1, #36
18067		- ldr r5, [sp, #20]
18068		- mov r4, #0
18069		- ldr r7, [r3, #-1504]
18070		- ldrh r6, [r2]
18071		- ldrb r8, [r3, #-2744] @ zero_extendqisi2
18072		- str r4, [sp, #16]
18073		-.L2976:
18074		- uxth r3, r4
18075		- cmp r3, r6
18076		- bcs .L3088
18077		- ldrh r3, [r5, #2]!
18078		- cmp r3, lr
18079		- beq .L2977
18080		- ldr r2, [sp, #16]
18081		- orr r3, r10, r3, asl #10
18082		- mla r2, r1, r2, r7
18083		- str r3, [r2, #4]
18084		- ldrb r0, [r9, #8] @ zero_extendqisi2
18085		- cmp r0, #1
18086		- bne .L2978
18087		- cmp r8, #0
18088		- orrne r3, r3, #-2147483648
18089		- strne r3, [r2, #4]
18090		-.L2978:
18091		- ldr r3, [sp, #16]
18092		- add ip, r3, #1
18093		- uxth r3, ip
18094		- str r3, [sp, #16]
18095		-.L2977:
18096		- add r4, r4, #1
18097		- b .L2976
18098		-.L3088:
18099		- ldr r4, .L3090+4
18100		- ldr r1, [sp, #16]
	18431	+ ldr r4, .L3011+4
	18432	+ movw r3, #1796
	18433	+ strh r2, [r4, r3] @ movhi
	18434	+.L2896:
	18435	+ ldr r3, .L3011+28
	18436	+ movw r6, #65535
	18437	+ ldr r0, [r4, #-1500]
	18438	+ mov r7, #36
	18439	+ ldrb r5, [r4, #-2740] @ zero_extendqisi2
	18440	+ mov r2, #0
	18441	+ ldrh lr, [r3, #-4]
	18442	+ ldr r1, [sp, #20]
	18443	+ str r2, [sp, #12]
	18444	+.L2897:
	18445	+ uxth r3, r2
	18446	+ cmp lr, r3
	18447	+ bhi .L2900
18101	18448	ldr r2, [sp, #24]
18102		- ldr r0, [r4, #-1504]
	18449	+ ldr r1, [sp, #12]
18103	18450	bl FlashReadPages
18104	18451	mov r3, #0
18105		-.L3082:
18106		- str r3, [sp, #28]
18107		- ldr r2, [sp, #16]
18108		- ldrh r3, [sp, #28]
18109		- cmp r3, r2
18110		- bcs .L3089
18111		- ldr r3, [sp, #28]
18112		- mov r5, #36
18113		- ldr r8, [r4, #-1504]
18114		- mul r5, r5, r3
18115		- add r7, r8, r5
18116		- ldr r6, [r7, #4]
18117		- ubfx r0, r6, #10, #16
18118		- str r6, [sp, #60]
	18452	+.L3008:
	18453	+ str r3, [sp, #16]
	18454	+ ldr r2, [sp, #12]
	18455	+ ldrh r3, [sp, #16]
	18456	+ cmp r2, r3
	18457	+ bhi .L2926
	18458	+ ldrb r3, [fp, #8] @ zero_extendqisi2
	18459	+ add r9, r9, #1
	18460	+ uxth r9, r9
	18461	+ cmp r3, #1
	18462	+ ldr r3, .L3011
	18463	+ bne .L2927
	18464	+ ldrb r2, [r4, #-2740] @ zero_extendqisi2
	18465	+ cmp r2, #0
	18466	+ beq .L2927
	18467	+ ldrh r2, [r3]
	18468	+ ldr r1, [sp]
	18469	+ cmp r2, r9
	18470	+ cmpeq r1, r9
	18471	+ beq .L2903
	18472	+.L2927:
	18473	+ ldrh r3, [r3, #-2]
	18474	+ cmp r3, r9
	18475	+ bne .L2896
	18476	+ ldr r2, .L3011+28
	18477	+ movw r0, #65535
	18478	+ mov r3, #0
	18479	+ strh r9, [fp, #2] @ movhi
	18480	+ strh r3, [fp, #4] @ movhi
	18481	+ ldrh r2, [r2, #-4]
	18482	+.L2928:
	18483	+ uxth r1, r3
	18484	+ cmp r1, r2
	18485	+ bcs .L2997
	18486	+ ldr r1, [sp, #20]
	18487	+ ldrh ip, [r1], #2
	18488	+ cmp ip, r0
	18489	+ str r1, [sp, #20]
	18490	+ add r1, r3, #1
	18491	+ bne .L3009
	18492	+ mov r3, r1
	18493	+ b .L2928
	18494	+.L2892:
	18495	+ ldr r2, [r3, #1752]
	18496	+ cmp r10, r2
	18497	+ bne .L3004
	18498	+ b .L2878
	18499	+.L2894:
	18500	+ mvn r3, #0
	18501	+ str r3, [r6, #1752]
	18502	+ b .L2878
	18503	+.L2900:
	18504	+ ldrh r3, [r1], #2
	18505	+ cmp r3, r6
	18506	+ beq .L2898
	18507	+ ldr ip, [sp, #12]
	18508	+ orr r3, r9, r3, lsl #10
	18509	+ mla ip, r7, ip, r0
	18510	+ str r3, [ip, #4]
	18511	+ ldrb r8, [fp, #8] @ zero_extendqisi2
	18512	+ cmp r8, #1
	18513	+ bne .L2899
	18514	+ cmp r5, #0
	18515	+ orrne r3, r3, #-2147483648
	18516	+ strne r3, [ip, #4]
	18517	+.L2899:
	18518	+ ldr r3, [sp, #12]
	18519	+ add r3, r3, #1
	18520	+ uxth r3, r3
	18521	+ str r3, [sp, #12]
	18522	+.L2898:
	18523	+ add r2, r2, #1
	18524	+ b .L2897
	18525	+.L2926:
	18526	+ ldr r3, [sp, #16]
	18527	+ mov r6, #36
	18528	+ ldr r8, [r4, #-1500]
	18529	+ mul r6, r6, r3
	18530	+ add r7, r8, r6
	18531	+ ldr r5, [r7, #4]
	18532	+ ubfx r0, r5, #10, #16
	18533	+ str r5, [sp, #44]
18119	18534	bl P2V_plane
18120	18535	ldr r3, [sp, #8]
18121		- cmp r10, r3
18122		- bcc .L2981
18123		- ldr r3, [sp, #32]
18124		- ldr r2, [sp, #8]
18125		- cmp r0, r3
18126		- movcs r3, #0
18127		- movcc r3, #1
18128		- cmp r10, r2
	18536	+ cmp r9, r3
	18537	+ bcc .L2902
	18538	+ ldr r2, [sp, #28]
	18539	+ moveq r3, #1
18129	18540	movne r3, #0
18130		- cmp r3, #0
18131		- bne .L2981
18132		- ldr r3, [sp, #12]
18133		- ldr r2, [sp, #4]
18134		- cmp r0, r3
18135		- cmpeq r10, r2
18136		- beq .L2982
18137		- ldr r3, [r8, r5]
18138		- cmn r3, #1
18139		- beq .L2983
18140		- ldr r7, [r7, #12]
18141		- movw r3, #61589
18142		- ldrh r2, [r7]
18143		- cmp r2, r3
18144		- ldrneh r0, [r9]
18145		- bne .L3080
18146		- ldr r3, [r7, #4]
18147		- cmn r3, #1
18148		- str r3, [sp]
18149		- beq .L2985
18150		- mov r0, r3
18151		- ldr r1, [r4, #-1612]
18152		- bl ftl_cmp_data_ver
18153		- cmp r0, #0
18154		- ldrne r3, [sp]
18155		- addne r3, r3, #1
18156		- strne r3, [r4, #-1612]
18157		-.L2985:
18158		- ldr r6, [r7, #8]
18159		- add r1, sp, #56
18160		- ldr r3, [r7, #12]
18161		- mov r2, #0
18162		- mov r0, r6
18163		- str r3, [sp, #52]
18164		- bl log2phys
18165		- ldr r1, [fp, #1760]
18166		- cmn r1, #1
18167		- beq .L2986
18168		- ldr r0, [sp]
18169		- bl ftl_cmp_data_ver
18170		- cmp r0, #0
18171		- beq .L2986
18172		- ldr r3, [sp, #52]
18173		- cmn r3, #1
18174		- beq .L2987
18175		- ldr r0, [r4, #-1504]
18176		- mov r2, #0
18177		- mov r1, #1
18178		- add r0, r0, r5
18179		- str r3, [r0, #4]
18180		- ldr r8, [r0, #12]
18181		- bl FlashReadPages
18182		- ldr r2, [r4, #-1504]
18183		- ldr r3, [r8, #4]
18184		- add ip, r2, r5
18185		- str r3, [sp, #36]
18186		- ldr r3, [r2, r5]
18187		- cmn r3, #1
18188		- bne .L2988
18189		- b .L2989
18190		-.L2987:
18191		- ldr r3, [sp, #60]
18192		- ldr r2, [sp, #56]
18193		- cmp r2, r3
18194		- bne .L2981
18195		- mov r0, r6
18196		- add r1, sp, #52
18197		- mov r2, #1
18198		- bl log2phys
18199		- b .L2981
18200		-.L2988:
18201		- ldr r7, [r8, #8]
18202		- cmp r7, r6
18203		- bne .L2989
18204		- ldr r0, [fp, #1760]
18205		- ldr r1, [sp, #36]
18206		- str r2, [sp, #44]
18207		- str ip, [sp, #40]
18208		- bl ftl_cmp_data_ver
18209		- cmp r0, #0
18210		- ldr ip, [sp, #40]
18211		- ldr r2, [sp, #44]
18212		- beq .L2989
18213		- ldr r3, [sp, #56]
18214		- ldr r1, [sp, #60]
18215		- cmp r3, r1
18216		- beq .L2994
18217		- ldr r1, [sp, #52]
18218		- cmp r3, r1
18219		- beq .L2989
18220		- cmn r3, #1
18221		- streq r3, [r2, r5]
18222		- beq .L2993
18223		- str r3, [ip, #4]
18224		- mov r0, ip
18225		- mov r1, #1
18226		- mov r2, #0
18227		- ldr r8, [ip, #12]
18228		- bl FlashReadPages
18229		-.L2993:
18230		- ldr r3, [r4, #-1504]
18231		- ldr r3, [r3, r5]
18232		- cmn r3, #1
18233		- beq .L2994
18234		- ldr r5, [r8, #4]
18235		- ldr r0, [fp, #1760]
18236		- mov r1, r5
18237		- bl ftl_cmp_data_ver
18238		- cmp r0, #0
18239		- beq .L2994
18240		- ldr r0, [sp, #36]
18241		- mov r1, r5
18242		- bl ftl_cmp_data_ver
18243		- cmp r0, #0
18244		- beq .L2989
18245		-.L2994:
18246		- mov r0, r7
18247		- ldr r1, [sp, #52]
18248		- bl FtlReUsePrevPpa
18249		-.L2989:
18250		- mvn r3, #0
18251		- str r3, [sp, #52]
18252		- b .L2996
18253		-.L2986:
18254		- ldr r3, [sp, #60]
18255		- ldr r2, [sp, #56]
18256		- cmp r2, r3
18257		- beq .L2996
18258		- ldr r3, [sp, #52]
18259		- cmn r3, #1
18260		- beq .L2998
18261		- ldr r2, [r4, #-1720]
18262		- ubfx r3, r3, #10, #21
18263		- cmp r3, r2
18264		- bcs .L2981
18265		-.L2998:
18266		- mov r0, r6
18267		- add r1, sp, #60
18268		- mov r2, #1
18269		- bl log2phys
18270		- ldr r8, [sp, #56]
18271		- cmn r8, #1
18272		- beq .L2996
18273		- ldr r3, [sp, #52]
18274		- cmp r8, r3
18275		- beq .L2996
18276		- ubfx r0, r8, #10, #16
18277		- ldr r5, .L3090+32
18278		- bl P2V_block_in_plane
18279		- ldrh r3, [r5]
18280		- cmp r3, r0
18281		- beq .L3000
18282		- add r2, r5, #48
18283		- ldrh r2, [r2]
18284	18541	cmp r2, r0
18285		- beq .L3000
18286		- add r3, r5, #96
18287		- ldrh r3, [r3]
18288		- cmp r3, r0
18289		- bne .L2996
18290		-.L3000:
18291		- ldr r0, [r5, #-2388]
18292		- mov r1, #1
	18542	+ movls r3, #0
	18543	+ andhi r3, r3, #1
	18544	+ cmp r3, #0
	18545	+ bne .L2902
	18546	+ ldr r3, [sp]
	18547	+ ldr r2, [sp, #4]
	18548	+ cmp r9, r3
	18549	+ cmpeq r2, r0
	18550	+ beq .L2903
	18551	+ ldr r3, [r8, r6]
	18552	+ cmn r3, #1
	18553	+ beq .L2904
	18554	+ ldr r3, [r7, #12]
	18555	+ movw r2, #61589
	18556	+ ldrh r1, [r3]
	18557	+ cmp r1, r2
	18558	+ ldrhne r0, [fp]
	18559	+ bne .L3006
	18560	+ ldr r10, [r3, #4]
	18561	+ cmn r10, #1
	18562	+ beq .L2906
	18563	+ ldr r1, [r4, #-1608]
	18564	+ mov r0, r10
	18565	+ bl ftl_cmp_data_ver
	18566	+ cmp r0, #0
	18567	+ addne r2, r10, #1
	18568	+ strne r2, [r4, #-1608]
	18569	+.L2906:
	18570	+ ldr r5, [r3, #8]
	18571	+ add r1, sp, #40
	18572	+ ldr r3, [r3, #12]
18293	18573	mov r2, #0
18294		- str r8, [r0, #4]
	18574	+ mov r0, r5
	18575	+ str r3, [sp, #36]
	18576	+ bl log2phys
	18577	+ ldr r1, [r4, #1752]
	18578	+ cmn r1, #1
	18579	+ beq .L2907
	18580	+ mov r0, r10
	18581	+ bl ftl_cmp_data_ver
	18582	+ cmp r0, #0
	18583	+ beq .L2907
	18584	+ ldr r3, [sp, #36]
	18585	+ cmn r3, #1
	18586	+ beq .L2908
	18587	+ ldr r0, [r4, #-1500]
	18588	+ mov r2, #0
	18589	+ mov r1, #1
	18590	+ add r0, r0, r6
	18591	+ str r3, [r0, #4]
18295	18592	ldr r7, [r0, #12]
18296	18593	bl FlashReadPages
18297		- ldr r3, [r5, #-2388]
18298		- ldr r1, [r7, #4]
18299		- ldr r3, [r3]
18300		- cmn r3, #1
18301		- beq .L2996
18302		- ldr r0, [sp]
18303		- bl ftl_cmp_data_ver
18304		- cmp r0, #0
18305		- bne .L2996
18306		- mov r0, r6
18307		- add r1, sp, #56
18308		- mov r2, #1
18309		- bl log2phys
18310		-.L2996:
18311		- ldr r0, [sp, #52]
18312		- cmn r0, #1
18313		- beq .L2981
18314		- ubfx r0, r0, #10, #16
	18594	+ ldr r2, [r4, #-1500]
	18595	+ ldr r1, [r2, r6]
	18596	+ add r3, r2, r6
	18597	+ cmn r1, #1
	18598	+ bne .L2909
	18599	+.L2910:
	18600	+ mvn r3, #0
	18601	+ str r3, [sp, #36]
	18602	+.L2917:
	18603	+ ldr r8, [sp, #36]
	18604	+ cmn r8, #1
	18605	+ beq .L2902
	18606	+.L2931:
	18607	+ ubfx r0, r8, #10, #16
18315	18608	bl P2V_block_in_plane
18316		- ldr r2, [r4, #-1408]
18317		- mov r3, r0, asl #1
	18609	+ ldr r2, [r4, #-1404]
	18610	+ lsl r3, r0, #1
18318	18611	mov r1, r0
18319	18612	ldrh r3, [r2, r3]
18320	18613	cmp r3, #0
18321		- beq .L3001
18322		-.L3080:
18323		- bl decrement_vpc_count
18324		- b .L2981
18325		-.L3001:
18326		- ldr r0, .L3090+36
18327		- bl printk
18328		- b .L2981
18329		-.L2983:
18330		- ldrh r2, [r9]
18331		- mov r1, r6
18332		- ldr r3, .L3090+16
18333		- ldr r0, .L3090+40
18334		- strh r2, [r3] @ movhi
18335		- ldr r2, [sp]
18336		- bl printk
18337		- ldr r3, [fp, #1808]
18338		- cmp r3, #31
18339		- addls r2, fp, r3, asl #2
18340		- addls r3, r3, #1
18341		- strls r3, [fp, #1808]
18342		- ldrls r1, [sp, #60]
18343		- strls r1, [r2, #1812]
18344		- ldrh r0, [r9]
18345		- bl decrement_vpc_count
18346		- ldr r3, .L3090+20
18347		- ldr r3, [r3, #1760]
18348		- cmn r3, #1
18349		- ldreq r3, [sp]
18350		- beq .L3081
18351		- ldr r2, [sp]
18352		- cmp r3, r2
18353		- bls .L2981
18354		- mov r3, r2
18355		-.L3081:
18356		- str r3, [fp, #1760]
18357		-.L2981:
18358		- ldr r3, [sp, #28]
18359		- add r3, r3, #1
18360		- b .L3082
18361		-.L3089:
18362		- ldrb r3, [r9, #8] @ zero_extendqisi2
18363		- add r10, r10, #1
18364		- cmp r3, #1
18365		- uxth r10, r10
18366		- bne .L3005
18367		- ldr r3, .L3090+4
18368		- ldrb r3, [r3, #-2744] @ zero_extendqisi2
18369		- cmp r3, #0
18370		- beq .L3005
18371		- ldr r3, .L3090+44
18372		- ldr r2, [sp, #4]
18373		- ldrh r3, [r3]
18374		- cmp r2, r10
18375		- cmpeq r3, r10
18376		- beq .L2982
18377		-.L3005:
18378		- ldr r2, .L3090+48
18379		- ldrh r3, [r2]
18380		- cmp r10, r3
18381		- bne .L2975
18382		- ldrh r1, [r2, #-68]
18383		- movw r0, #65535
18384		- mov r3, #0
18385		- strh r10, [r9, #2] @ movhi
18386		- strh r3, [r9, #4] @ movhi
	18614	+ beq .L2923
18387	18615	.L3006:
18388		- uxth r2, r3
18389		- cmp r2, r1
18390		- bcs .L3072
18391		- ldr lr, [sp, #20]
	18616	+ bl decrement_vpc_count
	18617	+ b .L2902
	18618	+.L2908:
	18619	+ ldr r3, [sp, #44]
	18620	+ ldr r2, [sp, #40]
	18621	+ cmp r2, r3
	18622	+ bne .L2902
	18623	+ mov r2, #1
	18624	+ add r1, sp, #36
	18625	+ mov r0, r5
	18626	+ bl log2phys
	18627	+.L2902:
	18628	+ ldr r3, [sp, #16]
18392	18629	add r3, r3, #1
18393		- ldrh ip, [lr, #2]!
18394		- cmp ip, r0
18395		- str lr, [sp, #20]
18396		- beq .L3006
18397		- strb r2, [r9, #6]
18398		- b .L3072
18399		-.L2982:
18400		- ldrb r3, [sp, #12] @ zero_extendqisi2
18401		- mov r0, r9
18402		- ldr r1, [sp, #4]
18403		- strb r3, [r9, #6]
18404		- ldrh r3, [sp, #4]
18405		- strh r3, [r9, #2] @ movhi
18406		-.L3083:
18407		- ldr r2, [sp, #12]
	18630	+ b .L3008
	18631	+.L2909:
	18632	+ ldr r1, [r7, #8]
	18633	+ cmp r5, r1
	18634	+ bne .L2910
	18635	+ ldr r8, [r7, #4]
	18636	+ ldr r0, [r4, #1752]
	18637	+ mov r1, r8
	18638	+ bl ftl_cmp_data_ver
	18639	+ cmp r0, #0
	18640	+ beq .L2910
	18641	+ ldr r1, [sp, #40]
	18642	+ ldr r0, [sp, #44]
	18643	+ cmp r1, r0
	18644	+ bne .L2912
	18645	+.L2915:
	18646	+ ldr r1, [sp, #36]
	18647	+ mov r0, r5
	18648	+ bl FtlReUsePrevPpa
	18649	+ b .L2910
	18650	+.L2912:
	18651	+ ldr r0, [sp, #36]
	18652	+ cmp r1, r0
	18653	+ beq .L2910
	18654	+ cmn r1, #1
	18655	+ streq r1, [r2, r6]
	18656	+ beq .L2914
	18657	+ str r1, [r3, #4]
	18658	+ mov r2, #0
	18659	+ mov r1, #1
	18660	+ mov r0, r3
	18661	+ ldr r7, [r3, #12]
	18662	+ bl FlashReadPages
	18663	+.L2914:
	18664	+ ldr r3, [r4, #-1500]
	18665	+ ldr r3, [r3, r6]
	18666	+ cmn r3, #1
	18667	+ beq .L2915
	18668	+ ldr r3, [r7, #4]
	18669	+ ldr r0, [r4, #1752]
	18670	+ mov r1, r3
	18671	+ bl ftl_cmp_data_ver
	18672	+ cmp r0, #0
	18673	+ beq .L2915
	18674	+ mov r1, r3
	18675	+ mov r0, r8
	18676	+ bl ftl_cmp_data_ver
	18677	+ cmp r0, #0
	18678	+ beq .L2910
	18679	+ b .L2915
	18680	+.L2907:
	18681	+ ldr r3, [sp, #44]
	18682	+ ldr r2, [sp, #40]
	18683	+ cmp r2, r3
	18684	+ beq .L2917
	18685	+ ldr r3, [sp, #36]
	18686	+ cmn r3, #1
	18687	+ beq .L2919
	18688	+ ldr r2, [r4, #-1716]
	18689	+ ubfx r3, r3, #10, #21
	18690	+ cmp r3, r2
	18691	+ bcs .L2902
	18692	+.L2919:
	18693	+ mov r2, #1
	18694	+ add r1, sp, #44
	18695	+ mov r0, r5
	18696	+ bl log2phys
	18697	+ ldr r8, [sp, #40]
	18698	+ cmn r8, #1
	18699	+ beq .L2917
	18700	+ ldr r3, [sp, #36]
	18701	+ cmp r8, r3
	18702	+ beq .L2931
	18703	+ ldr r6, .L3011+32
	18704	+ ubfx r0, r8, #10, #16
	18705	+ bl P2V_block_in_plane
	18706	+ ldrh r3, [r6]
	18707	+ sub r6, r6, #884
	18708	+ cmp r3, r0
	18709	+ beq .L2922
	18710	+ add r3, r6, #932
	18711	+ ldrh r3, [r3]
	18712	+ cmp r3, r0
	18713	+ beq .L2922
	18714	+ add r3, r6, #980
	18715	+ ldrh r3, [r3]
	18716	+ cmp r3, r0
	18717	+ bne .L2917
	18718	+.L2922:
	18719	+ ldr r0, [r6, #-1500]
	18720	+ mov r2, #0
	18721	+ mov r1, #1
	18722	+ str r8, [r0, #4]
	18723	+ ldr r7, [r0, #12]
	18724	+ bl FlashReadPages
	18725	+ ldr r3, [r6, #-1500]
	18726	+ ldr r3, [r3]
	18727	+ cmn r3, #1
	18728	+ beq .L2917
	18729	+ ldr r1, [r7, #4]
	18730	+ mov r0, r10
	18731	+ bl ftl_cmp_data_ver
	18732	+ cmp r0, #0
	18733	+ bne .L2917
	18734	+ mov r2, #1
	18735	+ add r1, sp, #40
	18736	+ mov r0, r5
	18737	+ bl log2phys
	18738	+ b .L2917
	18739	+.L2923:
	18740	+ ldr r0, .L3011+36
	18741	+ bl printk
	18742	+ b .L2902
	18743	+.L2904:
	18744	+ ldrh r3, [fp]
	18745	+ mov r1, r5
	18746	+ ldr r2, .L3011+20
	18747	+ ldr r0, .L3011+40
	18748	+ strh r3, [r2] @ movhi
	18749	+ mov r2, r10
	18750	+ bl printk
	18751	+ ldr r3, [r4, #1800]
	18752	+ cmp r3, #31
	18753	+ ldrls r1, [sp, #44]
	18754	+ addls r2, r4, r3, lsl #2
	18755	+ addls r3, r3, #1
	18756	+ strls r3, [r4, #1800]
	18757	+ strls r1, [r2, #1804]
	18758	+ ldrh r0, [fp]
	18759	+ bl decrement_vpc_count
	18760	+ ldr r3, [r4, #1752]
	18761	+ cmn r3, #1
	18762	+ bne .L2925
	18763	+.L3007:
	18764	+ str r10, [r4, #1752]
	18765	+ b .L2902
	18766	+.L2925:
	18767	+ cmp r10, r3
	18768	+ bcs .L2902
	18769	+ b .L3007
	18770	+.L2903:
	18771	+ ldrb r3, [sp, #4] @ zero_extendqisi2
	18772	+ ldr r2, [sp, #4]
	18773	+ strb r3, [fp, #6]
	18774	+ ldrh r3, [sp]
	18775	+ strh r3, [fp, #2] @ movhi
	18776	+.L3010:
	18777	+ ldr r1, [sp]
	18778	+ mov r0, fp
18408	18779	bl ftl_sb_update_avl_pages
18409		-.L3072:
18410		- mov r0, #0
18411		- add sp, sp, #68
18412		- @ sp needed
18413		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
18414		-.L3075:
	18780	+ b .L2997
	18781	+.L2999:
18415	18782	mov r0, #0
18416	18783	bx lr
18417		-.L3091:
	18784	+.L3012:
18418	18785	.align 2
18419		-.L3090:
	18786	+.L3011:
18420	18787	.word .LANCHOR2-1664
18421	18788	.word .LANCHOR2
18422	18789	.word .LANCHOR0
	18790	+ .word .LANCHOR2-1732
18423	18791	.word .LC154
18424		- .word .LANCHOR4+1802
18425		- .word .LANCHOR4
18426		- .word .LANCHOR2-1736
18427		- .word .LANCHOR0+1104
	18792	+ .word .LANCHOR2+1794
	18793	+ .word .LANCHOR0+1108
	18794	+ .word .LANCHOR2-1728
18428	18795	.word .LANCHOR2+884
18429	18796	.word .LC155
18430	18797	.word .LC156
18431		- .word .LANCHOR2-1666
18432		- .word .LANCHOR2-1668
18433	18798	.fnend
18434	18799	.size FtlRecoverySuperblock, .-FtlRecoverySuperblock
18435	18800	.align 2
18436	18801	.global FtlSlcSuperblockCheck
	18802	+ .syntax unified
	18803	+ .arm
	18804	+ .fpu softvfp
18437	18805	.type FtlSlcSuperblockCheck, %function
18438	18806	FtlSlcSuperblockCheck:
18439	18807	.fnstart
18440	18808	@ args = 0, pretend = 0, frame = 0
18441	18809	@ frame_needed = 0, uses_anonymous_args = 0
18442		- stmfd sp!, {r3, r4, r5, r6, r7, lr}
18443		- .save {r3, r4, r5, r6, r7, lr}
18444	18810	ldrh r3, [r0, #4]
18445	18811	cmp r3, #0
18446		- ldmeqfd sp!, {r3, r4, r5, r6, r7, pc}
	18812	+ bxeq lr
18447	18813	ldrh r2, [r0]
18448	18814	movw r3, #65535
18449	18815	cmp r2, r3
18450		- ldmeqfd sp!, {r3, r4, r5, r6, r7, pc}
18451		- ldrb r3, [r0, #6] @ zero_extendqisi2
	18816	+ bxeq lr
	18817	+ push {r4, r5, r6, lr}
	18818	+ .save {r4, r5, r6, lr}
18452	18819	mov r4, r0
18453		- ldr r5, .L3105
18454		- ldr r6, .L3105+4
18455		- add r3, r0, r3, asl #1
18456		- ldr r7, .L3105+8
	18820	+ ldrb r3, [r0, #6] @ zero_extendqisi2
	18821	+ ldr r5, .L3028
	18822	+ ldr r6, .L3028+4
	18823	+ add r3, r0, r3, lsl #1
18457	18824	ldrh r3, [r3, #16]
18458		-.L3096:
18459		- movw r2, #65535
18460		- cmp r3, r2
18461		- bne .L3104
18462		-.L3098:
18463		- ldrb r3, [r4, #6] @ zero_extendqisi2
18464		- ldrh r2, [r7]
18465		- add r3, r3, #1
18466		- uxtb r3, r3
18467		- strb r3, [r4, #6]
18468		- cmp r2, r3
18469		- ldreqh r3, [r4, #2]
18470		- addeq r3, r3, #1
18471		- streqh r3, [r4, #2] @ movhi
18472		- moveq r3, #0
18473		- streqb r3, [r4, #6]
18474		- ldrb r3, [r4, #6] @ zero_extendqisi2
18475		- add r3, r4, r3, asl #1
18476		- ldrh r3, [r3, #16]
18477		- b .L3096
18478		-.L3104:
18479		- ldrb r1, [r4, #8] @ zero_extendqisi2
18480		- cmp r1, #1
18481		- bne .L3099
18482		- ldrb r3, [r5, #-2744] @ zero_extendqisi2
	18825	+.L3017:
	18826	+ movw r1, #65535
	18827	+ cmp r3, r1
	18828	+ beq .L3019
	18829	+ ldrb r2, [r4, #8] @ zero_extendqisi2
	18830	+ cmp r2, #1
	18831	+ bne .L3020
	18832	+ ldrb r3, [r5, #-2740] @ zero_extendqisi2
18483	18833	cmp r3, #0
18484		- bne .L3099
	18834	+ bne .L3020
18485	18835	ldrh r3, [r4, #2]
18486		- mov r3, r3, asl #1
	18836	+ lsl r3, r3, #1
18487	18837	ldrh r3, [r6, r3]
18488		- cmp r3, r2
18489		- bne .L3099
	18838	+ cmp r3, r1
	18839	+ bne .L3020
18490	18840	ldrh r3, [r4, #4]
18491	18841	ldrh r0, [r4]
18492	18842	sub r3, r3, #1
..	..	@@ -18494,426 +18844,448 @@
18494	18844	bl decrement_vpc_count
18495	18845	ldrh r2, [r4, #4]
18496	18846	cmp r2, #0
18497		- bne .L3098
	18847	+ bne .L3019
18498	18848	ldrh r3, [r4, #2]
18499	18849	strb r2, [r4, #6]
18500	18850	add r3, r3, #1
18501	18851	strh r3, [r4, #2] @ movhi
18502		- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
18503		-.L3099:
18504		- ldr r2, .L3105
18505		- ldrb r3, [r2, #-2744] @ zero_extendqisi2
	18852	+ pop {r4, r5, r6, pc}
	18853	+.L3019:
	18854	+ ldrb r3, [r4, #6] @ zero_extendqisi2
	18855	+ ldr r2, .L3028+8
	18856	+ add r3, r3, #1
	18857	+ ldrh r2, [r2]
	18858	+ uxtb r3, r3
	18859	+ strb r3, [r4, #6]
	18860	+ cmp r2, r3
	18861	+ ldrheq r3, [r4, #2]
	18862	+ addeq r3, r3, #1
	18863	+ strheq r3, [r4, #2] @ movhi
	18864	+ moveq r3, #0
	18865	+ strbeq r3, [r4, #6]
	18866	+ ldrb r3, [r4, #6] @ zero_extendqisi2
	18867	+ add r3, r4, r3, lsl #1
	18868	+ ldrh r3, [r3, #16]
	18869	+ b .L3017
	18870	+.L3020:
	18871	+ ldrb r3, [r5, #-2740] @ zero_extendqisi2
	18872	+ adds r3, r3, #0
	18873	+ movne r3, #1
	18874	+ cmp r2, #1
	18875	+ movne r3, #0
18506	18876	cmp r3, #0
18507		- ldmeqfd sp!, {r3, r4, r5, r6, r7, pc}
18508		- cmp r1, #1
18509		- ldmnefd sp!, {r3, r4, r5, r6, r7, pc}
18510		- sub r1, r2, #1664
18511		- ldrh r0, [r4, #2]
18512		- ldrh r3, [r1, #-2]
18513		- cmp r0, r3
18514		- ldmccfd sp!, {r3, r4, r5, r6, r7, pc}
	18877	+ popeq {r4, r5, r6, pc}
	18878	+ ldr r1, .L3028+12
	18879	+ ldrh r2, [r4, #2]
	18880	+ ldrh r3, [r1]
	18881	+ cmp r2, r3
	18882	+ popcc {r4, r5, r6, pc}
18515	18883	ldrh r3, [r4]
18516		- ldr r0, [r2, #-1408]
	18884	+ ldr r0, [r5, #-1404]
18517	18885	ldrh ip, [r4, #4]
18518		- mov r3, r3, asl #1
	18886	+ lsl r3, r3, #1
18519	18887	ldrh r2, [r0, r3]
18520		- rsb r2, ip, r2
	18888	+ sub r2, r2, ip
18521	18889	strh r2, [r0, r3] @ movhi
18522		- ldrh r2, [r1, #-4]
18523	18890	mov r3, #0
	18891	+ ldrh r2, [r1, #-2]
18524	18892	strh r3, [r4, #4] @ movhi
18525	18893	strb r3, [r4, #6]
18526	18894	strh r2, [r4, #2] @ movhi
18527		- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
18528		-.L3106:
	18895	+ pop {r4, r5, r6, pc}
	18896	+.L3029:
18529	18897	.align 2
18530		-.L3105:
	18898	+.L3028:
18531	18899	.word .LANCHOR2
18532		- .word .LANCHOR0+1104
18533		- .word .LANCHOR2-1736
	18900	+ .word .LANCHOR0+1108
	18901	+ .word .LANCHOR2-1732
	18902	+ .word .LANCHOR2-1664
18534	18903	.fnend
18535	18904	.size FtlSlcSuperblockCheck, .-FtlSlcSuperblockCheck
18536	18905	.align 2
18537	18906	.global get_new_active_ppa
	18907	+ .syntax unified
	18908	+ .arm
	18909	+ .fpu softvfp
18538	18910	.type get_new_active_ppa, %function
18539	18911	get_new_active_ppa:
18540	18912	.fnstart
18541	18913	@ args = 0, pretend = 0, frame = 0
18542	18914	@ frame_needed = 0, uses_anonymous_args = 0
18543		- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
18544		- .save {r3, r4, r5, r6, r7, r8, r9, lr}
18545	18915	mov r3, #0
	18916	+ push {r4, r5, r6, r7, r8, lr}
	18917	+ .save {r4, r5, r6, r7, r8, lr}
18546	18918	strb r3, [r0, #10]
18547	18919	mov r4, r0
18548	18920	ldrb r3, [r0, #6] @ zero_extendqisi2
18549		- ldr r7, .L3125
18550		- ldr r8, .L3125+4
18551		- add r3, r0, r3, asl #1
18552		- ldr r9, .L3125+8
	18921	+ ldr r6, .L3046
	18922	+ ldr r8, .L3046+4
	18923	+ add r3, r0, r3, lsl #1
	18924	+ add r7, r6, #1728
18553	18925	ldrh r2, [r3, #16]
18554		-.L3108:
	18926	+.L3031:
18555	18927	movw r1, #65535
18556	18928	cmp r2, r1
18557		- ldr r6, .L3125
18558		- bne .L3124
18559		-.L3109:
18560		- ldrb r3, [r4, #6] @ zero_extendqisi2
18561		- ldrh r2, [r7]
18562		- add r3, r3, #1
18563		- uxtb r3, r3
18564		- strb r3, [r4, #6]
18565		- cmp r2, r3
18566		- ldreqh r3, [r4, #2]
18567		- addeq r3, r3, #1
18568		- streqh r3, [r4, #2] @ movhi
18569		- moveq r3, #0
18570		- streqb r3, [r4, #6]
18571		- ldrb r3, [r4, #6] @ zero_extendqisi2
18572		- add r3, r4, r3, asl #1
18573		- ldrh r2, [r3, #16]
18574		- b .L3108
18575		-.L3124:
	18929	+ beq .L3032
18576	18930	ldrb r3, [r4, #8] @ zero_extendqisi2
18577	18931	ldrh r5, [r4, #2]
18578	18932	cmp r3, #1
18579	18933	ldrh r3, [r4, #4]
18580		- bne .L3111
18581		- ldrb r0, [r8, #-2744] @ zero_extendqisi2
	18934	+ bne .L3034
	18935	+ ldrb r0, [r7, #-2740] @ zero_extendqisi2
18582	18936	cmp r0, #0
18583		- bne .L3111
18584		- mov r0, r5, asl #1
18585		- ldrh r0, [r9, r0]
	18937	+ bne .L3034
	18938	+ lsl r0, r5, #1
	18939	+ ldrh r0, [r8, r0]
18586	18940	cmp r0, r1
18587		- bne .L3111
	18941	+ bne .L3034
18588	18942	sub r3, r3, #1
18589	18943	ldrh r0, [r4]
18590	18944	strh r3, [r4, #4] @ movhi
18591	18945	bl decrement_vpc_count
18592		- b .L3109
18593		-.L3111:
18594		- ldr r7, .L3125+4
18595		- orr r5, r5, r2, asl #10
	18946	+.L3032:
	18947	+ ldrb r3, [r4, #6] @ zero_extendqisi2
	18948	+ ldrh r2, [r6, #-4]
	18949	+ add r3, r3, #1
	18950	+ uxtb r3, r3
	18951	+ cmp r2, r3
	18952	+ strb r3, [r4, #6]
	18953	+ ldrheq r3, [r4, #2]
	18954	+ addeq r3, r3, #1
	18955	+ strheq r3, [r4, #2] @ movhi
	18956	+ moveq r3, #0
	18957	+ strbeq r3, [r4, #6]
	18958	+ ldrb r3, [r4, #6] @ zero_extendqisi2
	18959	+ add r3, r4, r3, lsl #1
	18960	+ ldrh r2, [r3, #16]
	18961	+ b .L3031
	18962	+.L3034:
	18963	+ ldr r7, .L3046+8
	18964	+ orr r5, r5, r2, lsl #10
	18965	+ ldr r8, .L3046+4
18596	18966	sub r3, r3, #1
18597	18967	strh r3, [r4, #4] @ movhi
18598		-.L3112:
	18968	+.L3035:
18599	18969	ldrb r3, [r4, #6] @ zero_extendqisi2
18600	18970	movw r2, #65535
18601		- ldrh r0, [r6]
18602		-.L3114:
	18971	+ ldrh r0, [r6, #-4]
	18972	+.L3037:
18603	18973	add r3, r3, #1
18604	18974	uxtb r3, r3
18605	18975	cmp r3, r0
18606		- ldreqh r3, [r4, #2]
	18976	+ ldrheq r3, [r4, #2]
18607	18977	addeq r3, r3, #1
18608		- streqh r3, [r4, #2] @ movhi
	18978	+ strheq r3, [r4, #2] @ movhi
18609	18979	moveq r3, #0
18610		- add r1, r4, r3, asl #1
	18980	+ add r1, r4, r3, lsl #1
18611	18981	ldrh r1, [r1, #16]
18612	18982	cmp r1, r2
18613		- beq .L3114
	18983	+ beq .L3037
18614	18984	strb r3, [r4, #6]
18615	18985	ldrb r3, [r4, #8] @ zero_extendqisi2
18616	18986	cmp r3, #1
18617		- bne .L3119
18618		- ldrb r3, [r7, #-2744] @ zero_extendqisi2
	18987	+ bne .L3030
	18988	+ ldrb r3, [r7, #-2740] @ zero_extendqisi2
18619	18989	cmp r3, #0
18620		- bne .L3116
18621	18990	ldrh r3, [r4, #2]
18622		- ldr r2, .L3125+8
18623		- mov r3, r3, asl #1
18624		- ldrh r2, [r2, r3]
18625		- movw r3, #65535
18626		- cmp r2, r3
18627		- bne .L3116
	18991	+ bne .L3039
	18992	+ lsl r3, r3, #1
	18993	+ ldrh r3, [r8, r3]
	18994	+ cmp r3, r2
	18995	+ bne .L3030
18628	18996	ldrh r3, [r4, #4]
18629	18997	cmp r3, #0
18630		- beq .L3116
	18998	+ beq .L3030
18631	18999	sub r3, r3, #1
18632	19000	ldrh r0, [r4]
18633	19001	strh r3, [r4, #4] @ movhi
18634	19002	bl decrement_vpc_count
18635		- b .L3112
18636		-.L3116:
18637		- ldr r2, .L3125+4
18638		- ldrb r3, [r2, #-2744] @ zero_extendqisi2
18639		- cmp r3, #0
18640		- beq .L3119
18641		- sub r1, r2, #1664
18642		- ldrh r0, [r4, #2]
18643		- ldrh r3, [r1, #-2]
18644		- cmp r0, r3
18645		- bcc .L3119
	19003	+ b .L3035
	19004	+.L3039:
	19005	+ ldr r1, .L3046+12
	19006	+ ldrh r2, [r1]
	19007	+ cmp r3, r2
	19008	+ bcc .L3030
18646	19009	ldrh r3, [r4]
18647		- ldr r0, [r2, #-1408]
	19010	+ ldr r0, [r7, #-1404]
18648	19011	ldrh ip, [r4, #4]
18649		- mov r3, r3, asl #1
	19012	+ lsl r3, r3, #1
18650	19013	ldrh r2, [r0, r3]
18651		- rsb r2, ip, r2
	19014	+ sub r2, r2, ip
18652	19015	strh r2, [r0, r3] @ movhi
18653		- ldrh r2, [r1, #-4]
18654	19016	mov r3, #0
	19017	+ ldrh r2, [r1, #-2]
18655	19018	strh r3, [r4, #4] @ movhi
18656	19019	strb r3, [r4, #6]
18657	19020	strh r2, [r4, #2] @ movhi
18658		-.L3119:
	19021	+.L3030:
18659	19022	mov r0, r5
18660		- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
18661		-.L3126:
	19023	+ pop {r4, r5, r6, r7, r8, pc}
	19024	+.L3047:
18662	19025	.align 2
18663		-.L3125:
18664		- .word .LANCHOR2-1736
	19026	+.L3046:
	19027	+ .word .LANCHOR2-1728
	19028	+ .word .LANCHOR0+1108
18665	19029	.word .LANCHOR2
18666		- .word .LANCHOR0+1104
	19030	+ .word .LANCHOR2-1664
18667	19031	.fnend
18668	19032	.size get_new_active_ppa, .-get_new_active_ppa
18669	19033	.align 2
18670	19034	.global FtlWriteDumpData
	19035	+ .syntax unified
	19036	+ .arm
	19037	+ .fpu softvfp
18671	19038	.type FtlWriteDumpData, %function
18672	19039	FtlWriteDumpData:
18673	19040	.fnstart
18674	19041	@ args = 0, pretend = 0, frame = 40
18675	19042	@ frame_needed = 0, uses_anonymous_args = 0
18676		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	19043	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
18677	19044	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
18678	19045	.pad #44
18679	19046	sub sp, sp, #44
18680		- ldr r4, .L3146
	19047	+ ldr r4, .L3067
18681	19048	ldr r3, [r4, #-1280]
18682	19049	cmp r3, #0
18683		- bne .L3127
18684		- add r7, r4, #884
18685		- ldrh r5, [r7, #4]
18686		- cmp r5, #0
18687		- beq .L3129
	19050	+ bne .L3048
	19051	+ add r6, r4, #884
	19052	+ ldrh r2, [r6, #4]
	19053	+ cmp r2, #0
	19054	+ beq .L3050
18688	19055	ldrb r3, [r4, #892] @ zero_extendqisi2
18689	19056	cmp r3, #0
18690		- bne .L3129
	19057	+ bne .L3050
18691	19058	sub r3, r4, #1664
18692		- ldrb r2, [r4, #891] @ zero_extendqisi2
18693		- ldrh r3, [r3, #-4]
18694		- mul r3, r3, r2
18695		- cmp r5, r3
18696		- beq .L3129
	19059	+ ldrb r1, [r4, #891] @ zero_extendqisi2
	19060	+ ldrh r3, [r3, #-2]
	19061	+ mul r3, r3, r1
	19062	+ cmp r2, r3
	19063	+ beq .L3050
18697	19064	ldrb r8, [r4, #894] @ zero_extendqisi2
18698		- sub r3, r4, #1728
18699		- ldr r6, [r4, #-1284]
18700	19065	cmp r8, #0
18701		- ldrh r9, [r3, #-8]
18702		- bne .L3127
18703		- sub r6, r6, #1
18704		- mov r1, sp
	19066	+ bne .L3048
	19067	+ ldr r7, [r4, #-1284]
	19068	+ sub r3, r4, #1728
18705	19069	mov r2, r8
18706		- mov r0, r6
	19070	+ mov r1, sp
	19071	+ ldrh r9, [r3, #-4]
	19072	+ sub r7, r7, #1
	19073	+ mov r0, r7
18707	19074	bl log2phys
18708		- ldr r5, [r4, #-1444]
18709		- ldr r0, [r4, #-1476]
18710	19075	ldr r3, [sp]
18711		- str r6, [sp, #20]
	19076	+ ldr r5, [r4, #-1440]
	19077	+ ldr r0, [r4, #-1472]
18712	19078	cmn r3, #1
18713		- str r0, [sp, #12]
18714	19079	str r3, [sp, #8]
	19080	+ str r7, [sp, #20]
	19081	+ str r0, [sp, #12]
18715	19082	str r5, [sp, #16]
18716	19083	str r8, [r5, #4]
18717		- beq .L3131
18718		- mov r1, #1
	19084	+ beq .L3052
18719	19085	mov r2, r8
	19086	+ mov r1, #1
18720	19087	add r0, sp, #4
18721	19088	bl FlashReadPages
18722		- b .L3132
18723		-.L3131:
	19089	+.L3053:
	19090	+ ldr r10, .L3067+4
	19091	+ mov r8, #0
	19092	+ ldr r3, .L3067+8
	19093	+ lsl r9, r9, #2
	19094	+ mov fp, r8
	19095	+ strh r3, [r5] @ movhi
	19096	+.L3054:
	19097	+ cmp r9, r8
	19098	+ bne .L3058
	19099	+.L3055:
	19100	+ mov r3, #1
	19101	+.L3066:
	19102	+ strb r3, [r4, #894]
	19103	+.L3048:
	19104	+ add sp, sp, #44
	19105	+ @ sp needed
	19106	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	19107	+.L3052:
18724	19108	sub r3, r4, #1648
18725	19109	mov r1, #255
18726		- ldrh r2, [r3, #-10]
	19110	+ ldrh r2, [r3, #-8]
18727	19111	bl ftl_memset
18728		-.L3132:
18729		- ldr r3, .L3146+4
18730		- mov r8, #0
18731		- ldr fp, .L3146
18732		- mov r9, r9, asl #2
18733		- mov r10, r8
18734		- strh r3, [r5] @ movhi
18735		-.L3133:
18736		- cmp r8, r9
18737		- beq .L3134
18738		- ldrh r3, [r7, #4]
18739		- ldr r0, .L3146+8
	19112	+ b .L3053
	19113	+.L3058:
	19114	+ ldrh r3, [r6, #4]
18740	19115	cmp r3, #0
18741		- beq .L3134
	19116	+ beq .L3055
18742	19117	ldr r3, [sp, #8]
	19118	+ mov r0, r10
	19119	+ str r7, [r5, #8]
18743	19120	add r8, r8, #1
18744		- str r6, [r5, #8]
18745	19121	str r3, [r5, #12]
18746		- ldrh r3, [r0]
	19122	+ ldrh r3, [r6]
18747	19123	strh r3, [r5, #2] @ movhi
18748	19124	bl get_new_active_ppa
18749		- ldr r3, [fp, #-1612]
18750		- mov r2, #0
	19125	+ ldr r3, [r4, #-1608]
18751	19126	mov r1, #1
18752	19127	str r0, [sp, #8]
18753	19128	add r0, sp, #4
18754	19129	str r3, [r5, #4]
18755	19130	add r3, r3, #1
18756	19131	cmn r3, #1
18757		- moveq r3, r10
18758		- str r3, [fp, #-1612]
18759		- mov r3, r2
18760		- bl FlashProgPages
18761		- ldrh r0, [r7]
18762		- bl decrement_vpc_count
18763		- b .L3133
18764		-.L3134:
18765		- mov r3, #1
18766		- b .L3145
18767		-.L3129:
	19132	+ moveq r3, fp
	19133	+ str r3, [r4, #-1608]
18768	19134	mov r3, #0
18769		-.L3145:
18770		- strb r3, [r4, #894]
18771		-.L3127:
18772		- add sp, sp, #44
18773		- @ sp needed
18774		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
18775		-.L3147:
	19135	+ mov r2, r3
	19136	+ bl FlashProgPages
	19137	+ ldrh r0, [r6]
	19138	+ bl decrement_vpc_count
	19139	+ b .L3054
	19140	+.L3050:
	19141	+ mov r3, #0
	19142	+ b .L3066
	19143	+.L3068:
18776	19144	.align 2
18777		-.L3146:
	19145	+.L3067:
18778	19146	.word .LANCHOR2
18779		- .word -3947
18780	19147	.word .LANCHOR2+884
	19148	+ .word -3947
18781	19149	.fnend
18782	19150	.size FtlWriteDumpData, .-FtlWriteDumpData
18783	19151	.align 2
18784	19152	.global l2p_flush
	19153	+ .syntax unified
	19154	+ .arm
	19155	+ .fpu softvfp
18785	19156	.type l2p_flush, %function
18786	19157	l2p_flush:
18787	19158	.fnstart
18788	19159	@ args = 0, pretend = 0, frame = 0
18789	19160	@ frame_needed = 0, uses_anonymous_args = 0
18790		- stmfd sp!, {r3, r4, r5, r6, r7, lr}
18791		- .save {r3, r4, r5, r6, r7, lr}
18792		- bl FtlWriteDumpData
	19161	+ push {r4, r5, r6, r7, r8, lr}
	19162	+ .save {r4, r5, r6, r7, r8, lr}
18793	19163	mov r4, #0
18794		- ldr r6, .L3154
	19164	+ ldr r5, .L3074
18795	19165	mov r7, #12
18796		- ldr r5, .L3154+4
18797		-.L3149:
18798		- ldrh r3, [r5]
	19166	+ bl FtlWriteDumpData
	19167	+ sub r6, r5, #1616
	19168	+.L3070:
	19169	+ ldrh r3, [r6, #-10]
18799	19170	uxth r0, r4
18800	19171	cmp r3, r0
18801		- bls .L3153
18802		- ldr r3, [r6, #-1364]
18803		- mla r3, r7, r0, r3
	19172	+ bhi .L3072
	19173	+ mov r0, #0
	19174	+ pop {r4, r5, r6, r7, r8, pc}
	19175	+.L3072:
	19176	+ ldr r2, [r5, #-1364]
	19177	+ uxth r3, r4
	19178	+ mla r3, r7, r3, r2
18804	19179	ldr r3, [r3, #4]
18805	19180	cmp r3, #0
18806		- bge .L3150
	19181	+ bge .L3071
18807	19182	bl flush_l2p_region
18808		-.L3150:
	19183	+.L3071:
18809	19184	add r4, r4, #1
18810		- b .L3149
18811		-.L3153:
18812		- mov r0, #0
18813		- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
18814		-.L3155:
	19185	+ b .L3070
	19186	+.L3075:
18815	19187	.align 2
18816		-.L3154:
	19188	+.L3074:
18817	19189	.word .LANCHOR2
18818		- .word .LANCHOR2-1630
18819	19190	.fnend
18820	19191	.size l2p_flush, .-l2p_flush
18821	19192	.align 2
18822	19193	.global FtlSuperblockPowerLostFix
	19194	+ .syntax unified
	19195	+ .arm
	19196	+ .fpu softvfp
18823	19197	.type FtlSuperblockPowerLostFix, %function
18824	19198	FtlSuperblockPowerLostFix:
18825	19199	.fnstart
18826	19200	@ args = 0, pretend = 0, frame = 40
18827	19201	@ frame_needed = 0, uses_anonymous_args = 0
18828		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
18829		- .save {r4, r5, r6, r7, r8, r9, r10, lr}
18830		- .pad #40
18831		- sub sp, sp, #40
18832		- ldr r5, .L3173
18833		- ldr r3, [r5, #-1280]
	19202	+ push {r4, r5, r6, r7, r8, r9, lr}
	19203	+ .save {r4, r5, r6, r7, r8, r9, lr}
	19204	+ .pad #44
	19205	+ sub sp, sp, #44
	19206	+ ldr r5, .L3092
	19207	+ ldr r9, [r5, #-1280]
	19208	+ cmp r9, #0
	19209	+ bne .L3076
	19210	+ ldrb r3, [r5, #-2740] @ zero_extendqisi2
18834	19211	cmp r3, #0
18835		- bne .L3156
18836		- ldrb r6, [r5, #-2744] @ zero_extendqisi2
18837		- cmp r6, #0
18838		- beq .L3172
18839		- ldrb r6, [r0, #8] @ zero_extendqisi2
18840		- cmp r6, #1
18841		- ldreqh r10, [r0, #4]
18842		- beq .L3158
18843		- mov r6, r3
18844		-.L3172:
18845		- mov r10, #12
18846		-.L3158:
18847		- ldr r7, [r5, #-1444]
	19212	+ beq .L3087
	19213	+ ldrb r3, [r0, #8] @ zero_extendqisi2
	19214	+ cmp r3, #1
	19215	+ ldrheq r7, [r0, #4]
	19216	+ moveq r9, r3
	19217	+ beq .L3078
	19218	+.L3087:
	19219	+ mov r7, #12
	19220	+.L3078:
18848	19221	mvn r3, #0
	19222	+ ldr r6, [r5, #-1440]
18849	19223	str r3, [sp, #20]
18850	19224	mov r8, #0
18851		- ldr r3, [r5, #-1476]
	19225	+ ldr r3, [r5, #-1472]
18852	19226	movw r2, #61589
18853		- str r7, [sp, #16]
	19227	+ str r6, [sp, #16]
18854	19228	mov r4, r0
18855		- ldr r9, .L3173
18856	19229	str r3, [sp, #12]
18857	19230	mvn r3, #2
18858		- str r3, [r7, #8]
	19231	+ str r3, [r6, #8]
18859	19232	mvn r3, #1
18860		- str r3, [r7, #12]
	19233	+ str r3, [r6, #12]
18861	19234	ldrh r3, [r0]
18862		- strh r8, [r7] @ movhi
18863		- strh r3, [r7, #2] @ movhi
18864		- ldr r3, [r5, #-1476]
	19235	+ strh r8, [r6] @ movhi
	19236	+ strh r3, [r6, #2] @ movhi
	19237	+ ldr r3, [r5, #-1472]
18865	19238	str r2, [r3]
18866		- ldr r2, .L3173+4
18867		- ldr r3, [r5, #-1476]
	19239	+ ldr r2, .L3092+4
	19240	+ ldr r3, [r5, #-1472]
18868	19241	str r2, [r3, #4]
18869		-.L3159:
18870		- subs r10, r10, #1
18871		- bcc .L3162
	19242	+.L3079:
	19243	+ subs r7, r7, #1
	19244	+ bcc .L3082
18872	19245	ldrh r3, [r4, #4]
18873	19246	cmp r3, #0
18874		- bne .L3160
18875		-.L3162:
	19247	+ bne .L3080
	19248	+.L3082:
18876	19249	ldrh r3, [r4]
18877		- ldr r1, [r5, #-1408]
	19250	+ ldr r1, [r5, #-1404]
18878	19251	ldrh r0, [r4, #4]
18879		- mov r3, r3, asl #1
	19252	+ lsl r3, r3, #1
18880	19253	ldrh r2, [r1, r3]
18881		- rsb r2, r0, r2
	19254	+ sub r2, r2, r0
18882	19255	strh r2, [r1, r3] @ movhi
18883		- ldr r3, .L3173+8
18884		- ldrh r3, [r3, #-4]
	19256	+ ldr r3, .L3092+8
	19257	+ ldrh r3, [r3, #-2]
18885	19258	strh r3, [r4, #2] @ movhi
18886	19259	mov r3, #0
18887	19260	strb r3, [r4, #6]
18888	19261	strh r3, [r4, #4] @ movhi
18889		- b .L3156
18890		-.L3160:
	19262	+.L3076:
	19263	+ add sp, sp, #44
	19264	+ @ sp needed
	19265	+ pop {r4, r5, r6, r7, r8, r9, pc}
	19266	+.L3080:
18891	19267	mov r0, r4
18892	19268	bl get_new_active_ppa
18893	19269	cmn r0, #1
18894	19270	str r0, [sp, #8]
18895		- beq .L3162
18896		- ldr r3, [r5, #-1612]
	19271	+ beq .L3082
	19272	+ ldr r3, [r5, #-1608]
	19273	+ mov r2, r9
18897	19274	mov r1, #1
18898		- mov r2, r6
18899	19275	add r0, sp, #4
18900		- str r3, [r7, #4]
	19276	+ str r3, [r6, #4]
18901	19277	add r3, r3, #1
18902	19278	cmn r3, #1
18903	19279	moveq r3, r8
18904		- str r3, [r9, #-1612]
	19280	+ str r3, [r5, #-1608]
18905	19281	mov r3, #0
18906	19282	bl FlashProgPages
18907	19283	ldrh r0, [r4]
18908	19284	bl decrement_vpc_count
18909		- b .L3159
18910		-.L3156:
18911		- add sp, sp, #40
18912		- @ sp needed
18913		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
18914		-.L3174:
	19285	+ b .L3079
	19286	+.L3093:
18915	19287	.align 2
18916		-.L3173:
	19288	+.L3092:
18917	19289	.word .LANCHOR2
18918	19290	.word 305419896
18919	19291	.word .LANCHOR2-1664
..	..	@@ -18921,254 +19293,264 @@
18921	19293	.size FtlSuperblockPowerLostFix, .-FtlSuperblockPowerLostFix
18922	19294	.align 2
18923	19295	.global FtlVpcCheckAndModify
	19296	+ .syntax unified
	19297	+ .arm
	19298	+ .fpu softvfp
18924	19299	.type FtlVpcCheckAndModify, %function
18925	19300	FtlVpcCheckAndModify:
18926	19301	.fnstart
18927	19302	@ args = 0, pretend = 0, frame = 8
18928	19303	@ frame_needed = 0, uses_anonymous_args = 0
18929		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
18930		- .save {r4, r5, r6, r7, r8, r9, lr}
	19304	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	19305	+ .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
18931	19306	.pad #12
18932	19307	mov r5, #0
18933		- ldr r4, .L3192
18934		- ldr r1, .L3192+4
18935		- ldr r0, .L3192+8
	19308	+ ldr r4, .L3109
	19309	+ ldr r1, .L3109+4
	19310	+ ldr r0, .L3109+8
	19311	+ sub r7, r4, #1712
18936	19312	bl printk
18937		- sub r3, r4, #1712
18938		- ldr r0, [r4, #-1412]
	19313	+ ldrh r2, [r7, #-10]
18939	19314	mov r1, #0
18940		- ldrh r2, [r3, #-14]
18941		- mov r6, r4
18942		- mov r2, r2, asl #1
	19315	+ ldr r0, [r4, #-1408]
	19316	+ lsl r2, r2, #1
18943	19317	bl ftl_memset
18944		-.L3176:
	19318	+.L3095:
18945	19319	ldr r3, [r4, #-1284]
18946	19320	cmp r5, r3
18947		- bcs .L3190
18948		- mov r0, r5
18949		- add r1, sp, #4
18950		- mov r2, #0
18951		- bl log2phys
18952		- ldr r0, [sp, #4]
18953		- cmn r0, #1
18954		- beq .L3177
18955		- ubfx r0, r0, #10, #16
18956		- bl P2V_block_in_plane
18957		- ldr r2, [r6, #-1412]
18958		- mov r0, r0, asl #1
18959		- ldrh r3, [r2, r0]
18960		- add r3, r3, #1
18961		- strh r3, [r2, r0] @ movhi
18962		-.L3177:
18963		- add r5, r5, #1
18964		- b .L3176
18965		-.L3190:
18966		- ldr r5, .L3192
18967		- mov r7, #0
18968		- add r8, r5, #884
18969		- add r9, r5, #980
18970		-.L3179:
18971		- ldr r3, .L3192+12
18972		- uxth r4, r7
18973		- ldrh r3, [r3]
18974		- cmp r3, r4
18975		- bls .L3191
18976		- ldr r3, [r5, #-1408]
18977		- mov r6, r4, asl #1
18978		- movw r1, #65535
18979		- ldrh r2, [r3, r6]
18980		- ldr r3, [r5, #-1412]
18981		- ldrh r3, [r3, r6]
18982		- cmp r2, r1
18983		- cmpne r2, r3
18984		- beq .L3180
18985		- ldrh r1, [r8]
18986		- cmp r1, r4
18987		- beq .L3180
18988		- ldrh r1, [r9]
18989		- cmp r1, r4
18990		- beq .L3180
18991		- ldr r1, .L3192+16
18992		- ldrh r1, [r1]
18993		- cmp r1, r4
18994		- beq .L3180
18995		- ldr r0, .L3192+20
18996		- mov r1, r4
18997		- bl printk
18998		- ldr r3, [r5, #-1408]
18999		- ldrh r2, [r3, r6]
19000		- cmp r2, #0
19001		- ldr r2, [r5, #-1412]
19002		- ldrh r2, [r2, r6]
19003		- strh r2, [r3, r6] @ movhi
19004		- beq .L3180
19005		- mov r0, r4
19006		- bl update_vpc_list
19007		-.L3180:
19008		- add r7, r7, #1
19009		- b .L3179
19010		-.L3191:
	19321	+ bcc .L3097
	19322	+ ldr r9, .L3109+12
	19323	+ mov r8, #0
	19324	+ add r10, r9, #96
	19325	+ add fp, r9, #48
	19326	+.L3098:
	19327	+ ldrh r3, [r7, #-12]
	19328	+ uxth r6, r8
	19329	+ cmp r3, r6
	19330	+ bhi .L3101
19011	19331	bl l2p_flush
19012	19332	bl FtlVpcTblFlush
19013	19333	add sp, sp, #12
19014	19334	@ sp needed
19015		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, pc}
19016		-.L3193:
	19335	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	19336	+.L3097:
	19337	+ mov r2, #0
	19338	+ add r1, sp, #4
	19339	+ mov r0, r5
	19340	+ bl log2phys
	19341	+ ldr r0, [sp, #4]
	19342	+ cmn r0, #1
	19343	+ beq .L3096
	19344	+ ubfx r0, r0, #10, #16
	19345	+ bl P2V_block_in_plane
	19346	+ ldr r2, [r4, #-1408]
	19347	+ lsl r0, r0, #1
	19348	+ ldrh r3, [r2, r0]
	19349	+ add r3, r3, #1
	19350	+ strh r3, [r2, r0] @ movhi
	19351	+.L3096:
	19352	+ add r5, r5, #1
	19353	+ b .L3095
	19354	+.L3101:
	19355	+ uxth r1, r8
	19356	+ ldr r3, [r4, #-1404]
	19357	+ movw r0, #65535
	19358	+ lsl r5, r1, #1
	19359	+ ldrh r2, [r3, r5]
	19360	+ ldr r3, [r4, #-1408]
	19361	+ ldrh r3, [r3, r5]
	19362	+ cmp r2, r0
	19363	+ cmpne r2, r3
	19364	+ beq .L3099
	19365	+ ldrh r0, [r9]
	19366	+ cmp r0, r6
	19367	+ beq .L3099
	19368	+ ldrh r0, [r10]
	19369	+ cmp r0, r6
	19370	+ beq .L3099
	19371	+ ldrh r0, [fp]
	19372	+ cmp r0, r6
	19373	+ beq .L3099
	19374	+ ldr r0, .L3109+16
	19375	+ bl printk
	19376	+ ldr r3, [r4, #-1404]
	19377	+ ldrh r2, [r3, r5]
	19378	+ cmp r2, #0
	19379	+ ldr r2, [r4, #-1408]
	19380	+ ldrh r2, [r2, r5]
	19381	+ strh r2, [r3, r5] @ movhi
	19382	+ bne .L3100
	19383	+.L3099:
	19384	+ add r8, r8, #1
	19385	+ b .L3098
	19386	+.L3100:
	19387	+ mov r0, r6
	19388	+ bl update_vpc_list
	19389	+ b .L3099
	19390	+.L3110:
19017	19391	.align 2
19018		-.L3192:
	19392	+.L3109:
19019	19393	.word .LANCHOR2
19020		- .word .LANCHOR3+216
	19394	+ .word .LANCHOR3+203
19021	19395	.word .LC50
19022		- .word .LANCHOR2-1728
19023		- .word .LANCHOR2+932
	19396	+ .word .LANCHOR2+884
19024	19397	.word .LC157
19025	19398	.fnend
19026	19399	.size FtlVpcCheckAndModify, .-FtlVpcCheckAndModify
19027	19400	.align 2
19028	19401	.global allocate_new_data_superblock
	19402	+ .syntax unified
	19403	+ .arm
	19404	+ .fpu softvfp
19029	19405	.type allocate_new_data_superblock, %function
19030	19406	allocate_new_data_superblock:
19031	19407	.fnstart
19032	19408	@ args = 0, pretend = 0, frame = 0
19033	19409	@ frame_needed = 0, uses_anonymous_args = 0
19034		- stmfd sp!, {r3, r4, r5, r6, r7, lr}
19035		- .save {r3, r4, r5, r6, r7, lr}
19036		- ldr r5, .L3221
19037		- ldrh r7, [r0]
19038		- ldr r3, [r5, #-1280]
	19410	+ push {r4, r5, r6, lr}
	19411	+ .save {r4, r5, r6, lr}
	19412	+ ldr r4, .L3138
	19413	+ ldr r3, [r4, #-1280]
19039	19414	cmp r3, #0
19040		- bne .L3195
	19415	+ bne .L3112
	19416	+ ldrh r6, [r0]
19041	19417	movw r3, #65535
19042		- cmp r7, r3
19043		- mov r4, r0
19044		- beq .L3196
19045		- ldr r2, [r5, #-1408]
19046		- mov r3, r7, asl #1
19047		- mov r0, r7
	19418	+ mov r5, r0
	19419	+ cmp r6, r3
	19420	+ beq .L3113
	19421	+ ldr r2, [r4, #-1404]
	19422	+ lsl r3, r6, #1
	19423	+ mov r0, r6
19048	19424	ldrh r3, [r2, r3]
19049	19425	cmp r3, #0
19050		- beq .L3197
	19426	+ beq .L3114
19051	19427	bl INSERT_DATA_LIST
19052		- b .L3196
19053		-.L3197:
19054		- bl INSERT_FREE_LIST
19055		-.L3196:
	19428	+.L3113:
19056	19429	mov r3, #0
19057		- strb r3, [r4, #8]
19058		- ldr r3, .L3221
19059		- add r2, r3, #932
19060		- cmp r4, r2
19061		- beq .L3198
19062		- sub r2, r3, #1712
19063		- ldrh r2, [r2, #-4]
	19430	+ strb r3, [r5, #8]
	19431	+ ldr r3, .L3138+4
	19432	+ cmp r5, r3
	19433	+ beq .L3115
	19434	+ ldr r2, .L3138+8
	19435	+ ldrh r2, [r2]
19064	19436	cmp r2, #1
19065		- beq .L3198
19066		- ldrb r1, [r3, #-2744] @ zero_extendqisi2
	19437	+ beq .L3115
	19438	+ ldrb r1, [r4, #-2740] @ zero_extendqisi2
19067	19439	cmp r1, #0
19068		- beq .L3199
19069		-.L3198:
	19440	+ beq .L3116
	19441	+.L3115:
19070	19442	mov r3, #1
19071		- strb r3, [r4, #8]
19072		- b .L3200
19073		-.L3199:
19074		- add r1, r3, #884
19075		- cmp r4, r1
19076		- bne .L3200
19077		- cmp r2, #3
19078		- beq .L3202
19079		- ldr r3, [r3, #-1620]
19080		- cmp r3, #1
19081		- bne .L3203
19082		-.L3202:
19083		- mov r3, #1
19084		- strb r3, [r5, #892]
19085		-.L3203:
19086		- ldr r2, [r5, #-1872]
19087		- ldr r3, .L3221
19088		- cmp r2, #0
19089		- beq .L3200
19090		- ldr r2, [r3, #-1568]
19091		- cmp r2, #39
19092		- movls r2, #1
19093		- strlsb r2, [r3, #892]
19094		-.L3200:
19095		- ldr r3, .L3221+4
19096		- movw r2, #1748
19097		- ldrh r0, [r3, r2]
19098		- movw r2, #65535
19099		- mov r6, r3
19100		- cmp r0, r2
19101		- beq .L3205
19102		- cmp r7, r0
19103		- bne .L3206
19104		- ldr r2, [r5, #-1408]
19105		- mov r3, r0, asl #1
	19443	+ strb r3, [r5, #8]
	19444	+.L3117:
	19445	+ movw r3, #1740
	19446	+ ldrh r0, [r4, r3]
	19447	+ movw r3, #65535
	19448	+ cmp r0, r3
	19449	+ beq .L3122
	19450	+ cmp r6, r0
	19451	+ bne .L3123
	19452	+ ldr r2, [r4, #-1404]
	19453	+ lsl r3, r0, #1
19106	19454	ldrh r3, [r2, r3]
19107	19455	cmp r3, #0
19108		- beq .L3207
19109		-.L3206:
	19456	+ beq .L3124
	19457	+.L3123:
19110	19458	bl update_vpc_list
19111		-.L3207:
19112		- movw r3, #1748
	19459	+.L3124:
19113	19460	mvn r2, #0
19114		- strh r2, [r6, r3] @ movhi
19115		-.L3205:
19116		- mov r0, r4
	19461	+ movw r3, #1740
	19462	+ strh r2, [r4, r3] @ movhi
	19463	+.L3122:
	19464	+ mov r0, r5
19117	19465	bl allocate_data_superblock
19118	19466	bl l2p_flush
19119	19467	mov r0, #0
19120	19468	bl FtlEctTblFlush
19121	19469	bl FtlVpcTblFlush
19122		-.L3195:
	19470	+.L3112:
19123	19471	mov r0, #0
19124		- ldmfd sp!, {r3, r4, r5, r6, r7, pc}
19125		-.L3222:
	19472	+ pop {r4, r5, r6, pc}
	19473	+.L3114:
	19474	+ bl INSERT_FREE_LIST
	19475	+ b .L3113
	19476	+.L3116:
	19477	+ sub r3, r3, #48
	19478	+ cmp r5, r3
	19479	+ bne .L3117
	19480	+ cmp r2, #3
	19481	+ beq .L3119
	19482	+ ldr r3, [r4, #-1616]
	19483	+ cmp r3, #1
	19484	+ bne .L3120
	19485	+.L3119:
	19486	+ mov r3, #1
	19487	+ strb r3, [r4, #892]
	19488	+.L3120:
	19489	+ ldr r3, [r4, #-1868]
	19490	+ cmp r3, #0
	19491	+ beq .L3117
	19492	+ ldr r3, [r4, #-1564]
	19493	+ cmp r3, #39
	19494	+ movls r3, #1
	19495	+ strbls r3, [r4, #892]
	19496	+ b .L3117
	19497	+.L3139:
19126	19498	.align 2
19127		-.L3221:
	19499	+.L3138:
19128	19500	.word .LANCHOR2
19129		- .word .LANCHOR4
	19501	+ .word .LANCHOR2+932
	19502	+ .word .LANCHOR2-1712
19130	19503	.fnend
19131	19504	.size allocate_new_data_superblock, .-allocate_new_data_superblock
19132	19505	.align 2
19133	19506	.global FtlReadRefresh
	19507	+ .syntax unified
	19508	+ .arm
	19509	+ .fpu softvfp
19134	19510	.type FtlReadRefresh, %function
19135	19511	FtlReadRefresh:
19136	19512	.fnstart
19137	19513	@ args = 0, pretend = 0, frame = 40
19138	19514	@ frame_needed = 0, uses_anonymous_args = 0
19139		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, lr}
	19515	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
19140	19516	.save {r4, r5, r6, r7, r8, r9, r10, lr}
19141	19517	.pad #40
19142	19518	sub sp, sp, #40
19143		- ldr r7, .L3240
19144		- ldr r5, .L3240+4
19145		- ldr r10, [r7, #1292]
19146		- mov r6, r7
19147		- cmp r10, #0
19148		- beq .L3224
19149		- ldr r2, [r7, #1296]
	19519	+ ldr r5, .L3157
	19520	+ ldr r9, [r5, #1284]
	19521	+ mov r6, r5
	19522	+ cmp r9, #0
	19523	+ beq .L3141
	19524	+ ldr r2, [r5, #1288]
19150	19525	ldr r3, [r5, #-1284]
19151	19526	cmp r2, r3
19152		- bcs .L3225
	19527	+ bcs .L3142
19153	19528	mov r4, #2048
19154		-.L3230:
19155		- ldr r0, [r6, #1296]
19156		- ldr r3, [r5, #-1284]
	19529	+.L3147:
	19530	+ ldr r0, [r6, #1288]
	19531	+ ldr r3, [r6, #-1284]
19157	19532	cmp r0, r3
19158		- bcs .L3229
	19533	+ bcc .L3143
	19534	+.L3146:
	19535	+ mvn r0, #0
	19536	+.L3140:
	19537	+ add sp, sp, #40
	19538	+ @ sp needed
	19539	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	19540	+.L3143:
19159	19541	mov r2, #0
19160	19542	mov r1, sp
19161	19543	bl log2phys
19162		- ldr r3, [r7, #1296]
19163		- add r3, r3, #1
19164		- str r3, [r7, #1296]
19165	19544	ldr r2, [sp]
	19545	+ ldr r3, [r6, #1288]
19166	19546	cmn r2, #1
19167		- beq .L3228
19168		- add r0, sp, #40
	19547	+ add r3, r3, #1
	19548	+ str r3, [r6, #1288]
	19549	+ beq .L3145
19169	19550	str r2, [sp, #8]
19170		- mov r1, #1
	19551	+ add r0, sp, #40
19171	19552	mov r2, #0
	19553	+ mov r1, #1
19172	19554	str r2, [r0, #-36]!
19173	19555	str r3, [sp, #20]
19174	19556	str r2, [sp, #12]
..	..	@@ -19176,1342 +19558,1318 @@
19176	19558	bl FlashReadPages
19177	19559	ldr r3, [sp, #4]
19178	19560	cmp r3, #256
19179		- bne .L3229
	19561	+ bne .L3146
19180	19562	ldr r0, [sp]
19181	19563	ubfx r0, r0, #10, #16
19182	19564	bl P2V_block_in_plane
19183	19565	bl FtlGcRefreshBlock
19184		-.L3229:
19185		- mvn r0, #0
19186		- b .L3232
19187		-.L3228:
	19566	+ b .L3146
	19567	+.L3145:
19188	19568	subs r4, r4, #1
19189		- bne .L3230
19190		- b .L3229
19191		-.L3225:
19192		- ldr r3, [r5, #-1588]
	19569	+ bne .L3147
	19570	+ b .L3146
	19571	+.L3142:
	19572	+ ldr r3, [r5, #-1584]
19193	19573	mov r0, #0
19194		- str r0, [r7, #1292]
19195		- str r0, [r7, #1296]
19196		- str r3, [r7, #1288]
19197		- b .L3232
19198		-.L3224:
19199		- ldr r1, [r5, #-1572]
	19574	+ str r0, [r5, #1284]
	19575	+ str r0, [r5, #1288]
	19576	+ str r3, [r5, #1280]
	19577	+ b .L3140
	19578	+.L3141:
	19579	+ ldr r1, [r5, #-1568]
19200	19580	movw r4, #10000
19201		- ldr r9, [r5, #-1588]
19202		- add r5, r5, #816
	19581	+ ldr r8, [r5, #-1584]
	19582	+ add r10, r5, #816
	19583	+ ldr r7, [r5, #1280]
19203	19584	cmp r1, r4
19204		- ldr r8, [r7, #1288]
19205		- add r2, r9, #1048576
19206		- ldr r3, [r5, #-2100]
	19585	+ add r3, r8, #1048576
19207	19586	movhi r4, #31
19208	19587	movls r4, #63
19209		- cmp r8, r2
19210		- bhi .L3234
19211		- mov r1, r1, lsr #10
	19588	+ cmp r7, r3
	19589	+ bhi .L3151
	19590	+ ldr r3, [r5, #-1284]
	19591	+ lsr r1, r1, #10
19212	19592	mov r0, #1000
19213		- mul r0, r0, r3
19214	19593	add r1, r1, #1
	19594	+ mul r0, r0, r3
19215	19595	bl __aeabi_uidiv
19216		- add r0, r0, r8
19217		- cmp r0, r9
19218		- bcc .L3234
19219		- ldrh r3, [r5, #28]
	19596	+ add r0, r0, r7
	19597	+ cmp r8, r0
	19598	+ bhi .L3151
	19599	+ ldrh r3, [r10, #28]
19220	19600	ands r0, r4, r3
19221		- movne r0, r10
19222		- bne .L3232
19223		- ldr r2, [r7, #1312]
19224		- cmp r2, r3
19225		- beq .L3232
19226		-.L3234:
19227		- ldrh r3, [r5, #28]
	19601	+ movne r0, r9
	19602	+ bne .L3140
	19603	+ ldr r2, [r5, #1304]
	19604	+ cmp r3, r2
	19605	+ beq .L3140
	19606	+.L3151:
	19607	+ ldrh r3, [r10, #28]
19228	19608	mov r0, #0
19229		- str r9, [r6, #1288]
19230		- str r0, [r6, #1296]
19231		- str r3, [r6, #1312]
	19609	+ str r0, [r6, #1288]
	19610	+ str r8, [r6, #1280]
	19611	+ str r3, [r6, #1304]
19232	19612	mov r3, #1
19233		- str r3, [r6, #1292]
19234		-.L3232:
19235		- add sp, sp, #40
19236		- @ sp needed
19237		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, pc}
19238		-.L3241:
	19613	+ str r3, [r6, #1284]
	19614	+ b .L3140
	19615	+.L3158:
19239	19616	.align 2
19240		-.L3240:
19241		- .word .LANCHOR4
	19617	+.L3157:
19242	19618	.word .LANCHOR2
19243	19619	.fnend
19244	19620	.size FtlReadRefresh, .-FtlReadRefresh
19245	19621	.align 2
19246	19622	.global ftl_do_gc
	19623	+ .syntax unified
	19624	+ .arm
	19625	+ .fpu softvfp
19247	19626	.type ftl_do_gc, %function
19248	19627	ftl_do_gc:
19249	19628	.fnstart
19250	19629	@ args = 0, pretend = 0, frame = 32
19251	19630	@ frame_needed = 0, uses_anonymous_args = 0
19252		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	19631	+ ldr r3, .L3323
	19632	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
19253	19633	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	19634	+ mov lr, r0
19254	19635	.pad #44
19255	19636	sub sp, sp, #44
19256		- ldr r5, .L3406
19257		- ldr r8, [r5, #-1280]
19258		- cmp r8, #0
19259		- movne r0, #0
19260		- bne .L3395
19261		- ldr r2, .L3406+4
19262		- ldr r6, [r2, #3444]
19263		- cmp r6, #1
19264		- bne .L3338
19265		- ldr r3, [r5, #-1564]
19266		- cmp r3, #0
19267		- bne .L3338
19268		- mov r4, r0
19269		- add r0, r5, #872
	19637	+ ldr r0, [r3, #-1280]
	19638	+ cmp r0, #0
	19639	+ bne .L3255
	19640	+ ldr ip, .L3323+4
	19641	+ ldr r4, [ip, #3440]
	19642	+ cmp r4, #1
	19643	+ bne .L3159
	19644	+ ldr r2, [r3, #-1560]
	19645	+ cmp r2, #0
	19646	+ bne .L3159
	19647	+ add r0, r3, #872
19270	19648	ldrh r0, [r0]
19271	19649	cmp r0, #47
19272		- movls r0, r3
19273		- bls .L3395
19274		- movw r3, #3448
19275		- mov r7, r5
19276		- ldrh r2, [r2, r3]
19277		- movw r3, #65535
19278		- mov r9, r1
19279		- str r4, [sp, #20]
19280		- cmp r2, r3
19281		- bne .L3244
19282		-.L3247:
19283		- ldr r8, .L3406+8
19284		- movw r5, #65535
19285		- ldrh r4, [r8, #-2]
19286		- cmp r4, r5
19287		- bne .L3245
19288		- b .L3246
19289		-.L3244:
19290		- add r5, r5, #980
19291		- ldrh r2, [r5]
19292		- cmp r2, r3
19293		- beq .L3247
19294		- mov r0, r6
19295		- bl FtlGcFreeTempBlock
19296		- cmp r0, #0
19297		- beq .L3247
19298		- mov r0, r6
19299		- b .L3395
19300		-.L3245:
19301		- ldrh r3, [r8, #-4]
19302		- cmp r3, r5
19303		- bne .L3246
19304		- ldrh r0, [r8]
19305		- cmp r0, r3
19306		- beq .L3246
19307		- ldrh r1, [r8, #2]
19308		- cmp r1, r3
19309		- strneh r4, [r8, #-4] @ movhi
19310		- strneh r0, [r8, #-2] @ movhi
19311		- mvnne r3, #0
19312		- strneh r1, [r8] @ movhi
19313		- strneh r3, [r8, #2] @ movhi
19314		-.L3246:
19315		- ldr r1, [sp, #20]
19316		- ldr r3, [r7, #-1548]
19317		- cmp r1, #1
19318		- ldr r2, .L3406
19319		- add r3, r3, #1
19320		- ldr r6, .L3406+12
19321		- add r3, r3, r1, asl #7
19322		- str r3, [r7, #-1548]
19323		- bne .L3258
19324		- ldr r1, [r2, #-1872]
19325		- cmp r1, #0
19326		- bne .L3249
19327		- ldrb r2, [r2, #-2744] @ zero_extendqisi2
19328		- cmp r2, #0
19329		- beq .L3258
19330		-.L3249:
19331		- ldr r2, [r7, #-1568]
19332		- ldr r4, .L3406
19333		- cmp r2, #39
19334		- bhi .L3258
19335		- movw r2, #1940
19336		- ldrh r2, [r6, r2]
19337		- add r3, r3, r2
19338		- str r3, [r4, #-1548]
19339		- bl FtlGcReFreshBadBlk
19340		- movw r3, #1164
19341		- ldrh r3, [r6, r3]
	19650	+ bls .L3255
	19651	+ movw r2, #3444
	19652	+ mov r8, r1
	19653	+ ldrh r1, [ip, r2]
19342	19654	movw r2, #65535
19343		- cmp r3, r2
19344		- bne .L3258
19345		- ldrh r2, [r8, #-4]
19346		- cmp r2, r3
19347		- bne .L3258
19348		- ldr r3, [r4, #-1548]
19349		- add r4, r4, #880
19350		- cmp r3, #1024
19351		- bhi .L3250
19352		- ldrh r3, [r4]
19353		- cmp r3, #63
19354		- bhi .L3258
19355		-.L3250:
19356		- ldr ip, .L3406
19357		- movw r3, #1940
19358		- ldrh r0, [r4]
	19655	+ mov r5, r3
	19656	+ str lr, [sp, #24]
	19657	+ cmp r1, r2
	19658	+ bne .L3161
	19659	+.L3164:
	19660	+ ldr r6, .L3323+8
	19661	+ movw r1, #65535
	19662	+ ldrh ip, [r6, #-14]
	19663	+ cmp ip, r1
	19664	+ bne .L3162
	19665	+.L3163:
	19666	+ ldr r3, [r5, #-1544]
	19667	+ ldr r2, [sp, #24]
	19668	+ add r3, r3, #1
	19669	+ cmp r2, #1
	19670	+ add r3, r3, r2, lsl #7
	19671	+ str r3, [r5, #-1544]
	19672	+ bne .L3165
	19673	+ ldr r2, [r5, #-1868]
	19674	+ cmp r2, #0
	19675	+ bne .L3166
	19676	+ ldrb r2, [r5, #-2740] @ zero_extendqisi2
	19677	+ cmp r2, #0
	19678	+ beq .L3165
	19679	+.L3166:
	19680	+ ldr r2, [r5, #-1564]
	19681	+ cmp r2, #39
	19682	+ bhi .L3165
	19683	+ movw r2, #1932
	19684	+ movw r4, #65535
	19685	+ ldrh r2, [r5, r2]
	19686	+ add r3, r2, r3
	19687	+ str r3, [r5, #-1544]
	19688	+ bl FtlGcReFreshBadBlk
	19689	+ movw r3, #1156
	19690	+ ldrh r2, [r5, r3]
	19691	+ cmp r2, r4
	19692	+ bne .L3167
	19693	+ ldr r3, .L3323+12
	19694	+ ldrh r1, [r3]
	19695	+ cmp r1, r2
	19696	+ bne .L3254
	19697	+ ldr r2, [r5, #-1544]
	19698	+ add r3, r3, #2416
	19699	+ cmp r2, #1024
	19700	+ bhi .L3169
	19701	+ ldrh r2, [r3]
	19702	+ cmp r2, #63
	19703	+ bhi .L3254
	19704	+.L3169:
	19705	+ ldrh r0, [r3]
	19706	+ movw r2, #1932
	19707	+ ldrh r3, [r6, #-6]
19359	19708	mov r1, #0
19360		- sub r4, ip, #1520
19361		- ldr r2, .L3406+12
19362		- strh r1, [r6, r3] @ movhi
19363		- ldrh r10, [r4, #-10]
19364		- add r5, r10, #64
19365		- cmp r0, r5
19366		- bgt .L3258
19367		- str r1, [ip, #-1548]
19368		- ldr r1, [ip, #-1568]
19369		- cmp r1, #0
19370		- moveq r1, #6
19371		- beq .L3397
19372		- cmp r1, #5
19373		- bhi .L3252
19374		- mov r1, #18
19375		-.L3397:
19376		- strh r1, [r2, r3] @ movhi
19377		-.L3252:
	19709	+ strh r1, [r5, r2] @ movhi
	19710	+ add r3, r3, #64
	19711	+ cmp r0, r3
	19712	+ bgt .L3254
	19713	+ ldr r3, [r5, #-1564]
	19714	+ str r1, [r5, #-1544]
	19715	+ cmp r3, r1
	19716	+ moveq r3, #6
	19717	+ beq .L3315
	19718	+ cmp r3, #5
	19719	+ bhi .L3171
	19720	+ mov r3, #18
	19721	+.L3315:
	19722	+ strh r3, [r5, r2] @ movhi
	19723	+.L3171:
19378	19724	mov r0, #32
	19725	+ movw r10, #65535
19379	19726	bl List_get_gc_head_node
19380		- movw ip, #65535
19381		- uxth r2, r0
19382		- cmp r2, ip
19383		- beq .L3257
19384		- ldrh r0, [r4, #-8]
19385		- ldr r5, .L3406
	19727	+ uxth r3, r0
	19728	+ cmp r3, r10
	19729	+ beq .L3175
	19730	+ ldrh r0, [r6, #-4]
19386	19731	cmp r0, #0
19387		- sub r10, r5, #1520
19388		- beq .L3254
19389		- sub r1, r5, #1664
19390		- ldr r3, [r5, #-1408]
19391		- mov r2, r2, asl #1
19392		- ldrh r4, [r1, #-2]
19393		- sub r1, r5, #1728
19394		- ldrh lr, [r3, r2]
19395		- ldrh r1, [r1, #-8]
19396		- mul r1, r1, r4
19397		- add r1, r1, #1
19398		- cmp lr, r1
19399		- bgt .L3257
19400		- add r1, r0, #1
19401		- str r2, [sp, #28]
19402		- str ip, [sp, #24]
19403		- mov fp, #0
19404		- uxth r1, r1
19405		- str r3, [sp, #16]
19406		- strh r1, [r10, #-8] @ movhi
	19732	+ beq .L3173
	19733	+ ldr r2, .L3323+16
	19734	+ lsl r7, r3, #1
	19735	+ ldr r1, [r5, #-1404]
	19736	+ ldrh lr, [r2], #-64
	19737	+ ldrh ip, [r1, r7]
19407	19738	str r1, [sp, #12]
19408		- str fp, [r5, #-1560]
	19739	+ ldrh r3, [r2, #-4]
	19740	+ mul r3, r3, lr
	19741	+ add r3, r3, #1
	19742	+ cmp ip, r3
	19743	+ bgt .L3175
	19744	+ add fp, r0, #1
	19745	+ mov r9, #0
	19746	+ uxth fp, fp
	19747	+ str r9, [r5, #-1556]
	19748	+ strh fp, [r6, #-4] @ movhi
19409	19749	bl List_get_gc_head_node
19410		- ldr ip, [sp, #24]
19411	19750	uxth r4, r0
19412	19751	ldr r1, [sp, #12]
19413		- cmp r4, ip
19414		- ldr r3, [sp, #16]
19415		- ldr r2, [sp, #28]
19416		- beq .L3257
19417		- mov ip, r4, asl #1
19418		- ldr r0, .L3406+16
19419		- str ip, [sp, #12]
19420		- ldrh lr, [r3, ip]
19421		- ldrh r3, [r3, r2]
	19752	+ cmp r4, r10
	19753	+ beq .L3175
	19754	+ lsl r10, r4, #1
19422	19755	mov r2, r4
19423		- str r3, [sp]
19424		- mov r3, lr
	19756	+ ldr r0, .L3323+20
	19757	+ ldrh r3, [r1, r10]
	19758	+ ldrh r1, [r1, r7]
	19759	+ str r1, [sp]
	19760	+ mov r1, fp
19425	19761	bl printk
19426		- ldrh r3, [r10, #-8]
	19762	+ ldrh r3, [r6, #-4]
19427	19763	cmp r3, #40
19428		- ldr ip, [sp, #12]
19429		- bls .L3255
19430		- ldr r3, [r5, #-1408]
19431		- ldrh r3, [r3, ip]
	19764	+ bls .L3174
	19765	+ ldr r3, [r5, #-1404]
	19766	+ ldrh r3, [r3, r10]
19432	19767	cmp r3, #32
19433		- strhih fp, [r10, #-8] @ movhi
19434		-.L3255:
19435		- movw r3, #1940
	19768	+ strhhi r9, [r6, #-4] @ movhi
	19769	+.L3174:
19436	19770	mov r2, #6
19437		- strh r2, [r6, r3] @ movhi
19438		- b .L3259
19439		-.L3254:
19440		- mov r3, #1
19441		- strh r3, [r10, #-8] @ movhi
19442		-.L3257:
19443		- bl GetSwlReplaceBlock
19444		- movw r3, #65535
19445		- cmp r0, r3
19446		- mov r4, r0
19447		- bne .L3259
19448		- movw r3, #1940
19449		- mov r2, #0
19450		- strh r2, [r6, r3] @ movhi
19451		-.L3258:
19452		- movw r3, #1164
19453		- movw r4, #65535
19454		- ldrh r3, [r6, r3]
19455		- cmp r3, r4
19456		- bne .L3259
19457		- ldr r5, .L3406
19458		- add r2, r5, #980
19459		- ldrh r4, [r2]
19460		- cmp r4, r3
19461		- movne r4, r3
19462		- beq .L3402
19463		-.L3259:
	19771	+ movw r3, #1932
	19772	+ strh r2, [r5, r3] @ movhi
	19773	+.L3167:
19464	19774	movw r0, #65535
19465		- rsb r3, r0, r4
19466		- clz r3, r3
19467		- ldr r2, [sp, #20]
19468		- mov r3, r3, lsr #5
19469		- cmp r2, #0
	19775	+ ldr r3, [sp, #24]
	19776	+ sub r2, r4, r0
	19777	+ clz r2, r2
	19778	+ lsr r2, r2, #5
	19779	+ cmp r3, #0
19470	19780	movne r1, #0
19471		- andeq r1, r3, #1
	19781	+ andeq r1, r2, #1
19472	19782	cmp r1, #0
19473		- beq .L3272
19474		- ldr r3, .L3406+20
19475		- ldrh r0, [r3]
19476		- cmp r0, #24
19477		- movhi r5, #1
19478		- bhi .L3273
	19783	+ beq .L3189
	19784	+ ldr r3, .L3323+24
	19785	+ ldrh r2, [r3]
	19786	+ cmp r2, #24
	19787	+ movhi r9, #1
	19788	+ bhi .L3190
	19789	+ cmp r2, #16
19479	19790	sub r3, r3, #2544
19480		- cmp r0, #16
19481		- ldrh r5, [r3, #-4]
19482		- movhi r5, r5, lsr #5
19483		- bhi .L3273
19484		- cmp r0, #12
19485		- movhi r5, r5, lsr #4
19486		- bhi .L3273
19487		- cmp r0, #8
19488		- movhi r5, r5, lsr #2
19489		-.L3273:
19490		- ldr r1, .L3406
19491		- sub r2, r1, #1520
19492		- ldrh r3, [r2, #-12]
19493		- cmp r3, r0
19494		- bcs .L3277
19495		- add r3, r1, #980
19496		- movw r0, #65535
19497		- ldrh r3, [r3]
19498		- cmp r3, r0
19499		- bne .L3278
19500		- ldrh r0, [r8, #-4]
19501		- cmp r0, r3
19502		- bne .L3278
19503		- movw r3, #1940
19504		- ldrh r0, [r6, r3]
19505		- cmp r0, #0
19506		- bne .L3279
19507		- ldr r3, [r1, #-1284]
19508		- ldr r1, [r1, #1124]
19509		- add r3, r3, r3, asl #1
19510		- cmp r1, r3, lsr #2
19511		- movcs r3, #18
19512		- bcs .L3280
19513		-.L3279:
19514		- movw r3, #1160
19515		- ldrh r3, [r6, r3]
19516		- add r3, r3, r3, asl #1
19517		- ubfx r3, r3, #2, #16
19518		-.L3280:
19519		- strh r3, [r2, #-12] @ movhi
19520		- mov r3, #0
19521		- str r3, [r7, #-1560]
19522		- b .L3395
19523		-.L3278:
19524		- movw r3, #1160
19525		- ldrh r3, [r6, r3]
19526		- add r3, r3, r3, asl #1
19527		- mov r3, r3, asr #2
19528		- strh r3, [r2, #-12] @ movhi
19529		-.L3277:
19530		- cmp r9, #2
19531		- ldr r3, [r7, #-1872]
19532		- movw r4, #65535
19533		- movhi r9, #0
19534		- movls r9, #1
19535		- cmp r3, #0
19536		- moveq r9, #0
19537		- cmp r9, #0
19538		- addne r5, r5, #1
19539		- uxthne r5, r5
19540		- b .L3282
19541		-.L3272:
19542		- ldr r5, .L3406
19543		- add r2, r5, #980
19544		- ldrh r2, [r2]
19545		- cmp r2, r0
19546		- bne .L3283
19547		- ldrh r0, [r8, #-4]
19548		- cmp r0, r2
19549		- movne r3, #0
19550		- andeq r3, r3, #1
19551		- cmp r3, #0
19552		- beq .L3283
19553		- movw r3, #1164
19554		- ldrh r3, [r6, r3]
	19791	+ ldrhhi r3, [r3, #-2]
	19792	+ lsrhi r9, r3, #5
	19793	+ bhi .L3190
	19794	+ cmp r2, #12
	19795	+ ldrhhi r3, [r3, #-2]
	19796	+ lsrhi r9, r3, #4
	19797	+ bhi .L3190
	19798	+ cmp r2, #8
	19799	+ ldrhhi r3, [r3, #-2]
	19800	+ ldrhls r9, [r3, #-2]
	19801	+ lsrhi r9, r3, #2
	19802	+.L3190:
	19803	+ ldrh r3, [r6, #-8]
19555	19804	cmp r3, r2
19556		- beq .L3284
19557		-.L3288:
19558		- movw r4, #65535
19559		- b .L3283
19560		-.L3284:
19561		- add r4, r5, #880
19562		- sub r10, r5, #1520
19563		- str r1, [r5, #-1560]
19564		- ldrh r2, [r4]
19565		- ldrh r3, [r10, #-12]
	19805	+ bcs .L3194
	19806	+ ldr r3, .L3323+28
	19807	+ movw r2, #65535
	19808	+ ldrh r3, [r3]
	19809	+ cmp r3, r2
	19810	+ bne .L3195
	19811	+ ldr r2, .L3323+12
	19812	+ ldrh r2, [r2]
19566	19813	cmp r2, r3
19567		- bls .L3285
19568		- ldr r2, .L3406+12
19569		- movw r3, #1940
19570		- ldrh r3, [r2, r3]
19571		- cmp r3, #0
19572		- bne .L3286
	19814	+ bne .L3195
	19815	+ movw r3, #1932
	19816	+ ldrh r0, [r5, r3]
	19817	+ cmp r0, #0
	19818	+ bne .L3196
19573	19819	ldr r3, [r5, #-1284]
19574	19820	ldr r2, [r5, #1124]
19575		- add r3, r3, r3, asl #1
	19821	+ add r3, r3, r3, lsl #1
19576	19822	cmp r2, r3, lsr #2
19577	19823	movcs r3, #18
19578		- bcs .L3287
19579		-.L3286:
19580		- movw r3, #1160
19581		- ldrh r3, [r6, r3]
19582		- add r3, r3, r3, asl #1
19583		- ubfx r3, r3, #2, #16
19584		-.L3287:
19585		- strh r3, [r10, #-12] @ movhi
	19824	+ bcs .L3319
	19825	+.L3196:
	19826	+ ldr r3, .L3323+32
	19827	+ ldrh r3, [r3]
	19828	+ add r3, r3, r3, lsl #1
	19829	+ asr r3, r3, #2
	19830	+.L3319:
	19831	+ strh r3, [r6, #-8] @ movhi
	19832	+ mov r3, #0
	19833	+ str r3, [r5, #-1556]
	19834	+.L3159:
	19835	+ add sp, sp, #44
	19836	+ @ sp needed
	19837	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	19838	+.L3161:
	19839	+ add r3, r3, #980
	19840	+ ldrh r3, [r3]
	19841	+ cmp r3, r2
	19842	+ beq .L3164
	19843	+ mov r0, r4
	19844	+ bl FtlGcFreeTempBlock
	19845	+ cmp r0, #0
	19846	+ beq .L3164
	19847	+ mov r0, r4
	19848	+ b .L3159
	19849	+.L3162:
	19850	+ mov r3, r6
	19851	+ ldrh r2, [r3, #-16]!
	19852	+ cmp r2, r1
	19853	+ bne .L3163
	19854	+ ldrh r0, [r6, #-12]
	19855	+ cmp r0, r2
	19856	+ beq .L3163
	19857	+ ldrh r1, [r6, #-10]
	19858	+ cmp r1, r2
	19859	+ strhne ip, [r3] @ movhi
	19860	+ mvnne r3, #0
	19861	+ strhne r0, [r6, #-14] @ movhi
	19862	+ strhne r1, [r6, #-12] @ movhi
	19863	+ strhne r3, [r6, #-10] @ movhi
	19864	+ b .L3163
	19865	+.L3173:
	19866	+ mov r3, #1
	19867	+ strh r3, [r6, #-4] @ movhi
	19868	+.L3175:
	19869	+ bl GetSwlReplaceBlock
	19870	+ movw r3, #65535
	19871	+ mov r4, r0
	19872	+ cmp r0, r3
	19873	+ bne .L3167
	19874	+ mov r2, #0
	19875	+ movw r3, #1932
	19876	+ strh r2, [r5, r3] @ movhi
	19877	+.L3165:
	19878	+ movw r3, #1156
	19879	+ movw r4, #65535
	19880	+ ldrh r3, [r5, r3]
	19881	+ cmp r3, r4
	19882	+ bne .L3167
	19883	+.L3254:
	19884	+ ldr r7, .L3323+28
	19885	+ movw r3, #65535
	19886	+ ldrh r4, [r7]
	19887	+ cmp r4, r3
	19888	+ movne r4, r3
	19889	+ bne .L3167
	19890	+ ldr r3, .L3323+12
	19891	+ ldrh r9, [r3]
	19892	+ cmp r9, r4
	19893	+ bne .L3167
	19894	+ ldrh r3, [r7, #-100]!
	19895	+ ldr r2, [r5, #-1544]
	19896	+ cmp r3, #24
	19897	+ movcc r3, #5120
	19898	+ movcs r3, #1024
	19899	+ cmp r2, r3
	19900	+ bls .L3167
	19901	+ mov r3, #0
	19902	+ movw r2, #1932
	19903	+ str r3, [r5, #-1544]
	19904	+ strh r3, [r5, r2] @ movhi
	19905	+ bl GetSwlReplaceBlock
	19906	+ cmp r0, r9
	19907	+ mov r4, r0
	19908	+ movne r9, r0
	19909	+ bne .L3177
	19910	+ ldrh r2, [r7]
	19911	+ ldrh r3, [r6, #-6]
	19912	+ cmp r2, r3
	19913	+ bcs .L3178
	19914	+ mov r0, #64
	19915	+ bl List_get_gc_head_node
	19916	+ uxth r3, r0
	19917	+ cmp r3, r4
	19918	+ beq .L3180
	19919	+ ldr r3, [r5, #-1620]
	19920	+ ldr r1, .L3323+36
	19921	+ cmp r3, #0
	19922	+ uxth r3, r0
	19923	+ bne .L3181
	19924	+ ldrh r2, [r1]
	19925	+ cmp r2, #3
	19926	+ beq .L3181
	19927	+ ldr r2, [r5, #-1616]
	19928	+ cmp r2, #0
	19929	+ bne .L3181
	19930	+ ldr r2, [r5, #-1868]
	19931	+ cmp r2, #0
	19932	+ bne .L3181
	19933	+ ldrb r0, [r5, #-2740] @ zero_extendqisi2
	19934	+ cmp r0, #0
	19935	+ beq .L3182
	19936	+.L3181:
	19937	+ ldr r2, [r5, #-1404]
	19938	+ lsl r3, r3, #1
	19939	+ ldrh r1, [r1]
	19940	+ ldrh r0, [r2, r3]
	19941	+ ldr r2, .L3323+16
	19942	+ cmp r1, #3
	19943	+ ldrh r3, [r2], #-64
	19944	+ ldrh r2, [r2, #-4]
	19945	+ mul r2, r3, r2
	19946	+ lsreq r3, r3, #1
	19947	+ movne r3, #0
	19948	+ add r3, r3, r2
	19949	+ cmp r0, r3
	19950	+ bgt .L3184
	19951	+ mov r0, #0
	19952	+ bl List_get_gc_head_node
	19953	+ ldr r3, [r5, #-1284]
	19954	+ uxth r9, r0
	19955	+ ldr r2, [r5, #1124]
	19956	+ add r3, r3, r3, lsl #1
	19957	+ cmp r2, r3, lsr #2
	19958	+ movls r3, #160
	19959	+ bls .L3316
	19960	+.L3317:
	19961	+ mov r3, #128
	19962	+.L3316:
	19963	+ strh r3, [r6, #-6] @ movhi
	19964	+ movw r3, #65535
	19965	+ cmp r9, r3
	19966	+ beq .L3180
	19967	+.L3177:
	19968	+ ldr r3, [r5, #-1404]
	19969	+ lsl r1, r9, #1
	19970	+ ldrh r0, [r6, #-8]
	19971	+ mov r4, r9
	19972	+ ldrh r2, [r7]
	19973	+ ldrh r3, [r3, r1]
	19974	+ str r0, [sp, #4]
	19975	+ ldr r0, [r5, #-1412]
	19976	+ ldrh r1, [r0, r1]
	19977	+ ldr r0, .L3323+40
	19978	+ str r1, [sp]
	19979	+ mov r1, r9
	19980	+ bl printk
	19981	+ b .L3180
	19982	+.L3184:
	19983	+ mov r3, #128
	19984	+.L3318:
	19985	+ strh r3, [r6, #-6] @ movhi
	19986	+.L3180:
	19987	+ bl FtlGcReFreshBadBlk
	19988	+ b .L3167
	19989	+.L3182:
	19990	+ ldr r2, [r5, #-1404]
	19991	+ lsl r3, r3, #1
	19992	+ ldrh r3, [r2, r3]
	19993	+ cmp r3, #7
	19994	+ bhi .L3187
	19995	+ bl List_get_gc_head_node
	19996	+ uxth r9, r0
	19997	+ b .L3317
	19998	+.L3187:
	19999	+ mov r3, #64
	20000	+ b .L3318
	20001	+.L3178:
	20002	+ mov r3, #80
	20003	+ b .L3318
	20004	+.L3195:
	20005	+ ldr r3, .L3323+32
	20006	+ ldrh r3, [r3]
	20007	+ add r3, r3, r3, lsl #1
	20008	+ asr r3, r3, #2
	20009	+ strh r3, [r6, #-8] @ movhi
	20010	+.L3194:
	20011	+ ldr r3, [r5, #-1868]
	20012	+ movw r4, #65535
	20013	+ adds r3, r3, #0
	20014	+ movne r3, #1
	20015	+ cmp r8, #2
	20016	+ movhi r3, #0
	20017	+ cmp r3, #0
	20018	+ addne r3, r9, #1
	20019	+ uxthne r9, r3
	20020	+.L3200:
	20021	+ movw r3, #1156
	20022	+ ldrh r2, [r5, r3]
	20023	+ movw r1, #65535
	20024	+ cmp r2, r1
	20025	+ bne .L3210
	20026	+ cmp r4, r2
	20027	+ strhne r4, [r5, r3] @ movhi
	20028	+ bne .L3212
	20029	+ ldr r3, .L3323+12
	20030	+ ldrh r2, [r3]
	20031	+ cmp r2, r4
	20032	+ beq .L3212
	20033	+ ldr r1, [r5, #-1404]
	20034	+ lsl r2, r2, #1
	20035	+ ldrh r2, [r1, r2]
	20036	+ cmp r2, #0
	20037	+ mvneq r2, #0
	20038	+ strheq r2, [r3] @ movhi
	20039	+ movw r2, #1156
	20040	+ ldrh r1, [r3]
	20041	+ strh r1, [r5, r2] @ movhi
	20042	+ mvn r2, #0
	20043	+ strh r2, [r3] @ movhi
	20044	+.L3212:
	20045	+ movw r6, #1156
	20046	+ mov r3, #0
	20047	+ ldrh r0, [r5, r6]
	20048	+ strb r3, [r5, #1164]
	20049	+ movw r3, #65535
	20050	+ cmp r0, r3
	20051	+ beq .L3210
	20052	+ bl IsBlkInGcList
	20053	+ cmp r0, #0
	20054	+ mvnne r3, #0
	20055	+ strhne r3, [r5, r6] @ movhi
	20056	+ ldrb r3, [r5, #-2740] @ zero_extendqisi2
	20057	+ cmp r3, #0
	20058	+ beq .L3216
	20059	+ movw r3, #1156
	20060	+ ldrh r0, [r5, r3]
	20061	+ bl ftl_get_blk_mode
	20062	+ strb r0, [r5, #1164]
	20063	+.L3216:
	20064	+ movw r7, #1156
	20065	+ movw r3, #65535
	20066	+ ldrh r2, [r5, r7]
	20067	+ ldr r6, .L3323+44
	20068	+ cmp r2, r3
	20069	+ beq .L3210
	20070	+ mov r0, r6
	20071	+ bl make_superblock
	20072	+ mov r3, #0
	20073	+ movw r2, #1934
	20074	+ strh r3, [r6, #2] @ movhi
	20075	+ add r6, r6, #780
	20076	+ strh r3, [r5, r2] @ movhi
	20077	+ strb r3, [r5, #1162]
	20078	+ ldrh r3, [r5, r7]
	20079	+ ldr r2, [r5, #-1404]
	20080	+ lsl r3, r3, #1
	20081	+ ldrh r3, [r2, r3]
	20082	+ strh r3, [r6] @ movhi
	20083	+.L3210:
	20084	+ ldr r2, .L3323+48
	20085	+ movw r3, #1156
	20086	+ ldrh r3, [r5, r3]
	20087	+ ldrh r1, [r2]
	20088	+ cmp r1, r3
	20089	+ beq .L3217
	20090	+ ldrh r1, [r2, #48]
	20091	+ cmp r1, r3
	20092	+ beq .L3217
	20093	+ ldrh r2, [r2, #96]
	20094	+ cmp r2, r3
	20095	+ bne .L3218
	20096	+.L3217:
	20097	+ mvn r2, #0
	20098	+ movw r3, #1156
	20099	+ strh r2, [r5, r3] @ movhi
	20100	+.L3218:
	20101	+ ldr r5, .L3323
	20102	+ mov r10, r5
	20103	+.L3251:
	20104	+ ldr r8, .L3323+44
	20105	+ movw r3, #65535
	20106	+ ldrh r2, [r8]
	20107	+ cmp r2, r3
	20108	+ bne .L3219
	20109	+ ldr fp, .L3323+8
	20110	+ mov r3, #0
	20111	+ str r3, [r5, #-1556]
	20112	+.L3220:
	20113	+ ldr r6, .L3323+52
	20114	+ ldrh r7, [r6]
	20115	+ mov r0, r7
	20116	+ bl List_get_gc_head_node
	20117	+ ldr r1, .L3323+44
	20118	+ uxth r2, r0
	20119	+ strh r2, [r1] @ movhi
	20120	+ movw r1, #65535
	20121	+ cmp r2, r1
	20122	+ bne .L3221
	20123	+ mov r3, #0
	20124	+ mov r0, #8
	20125	+ strh r3, [r6] @ movhi
	20126	+ b .L3159
	20127	+.L3189:
	20128	+ ldr r3, .L3323+28
	20129	+ ldrh r8, [r3]
	20130	+ cmp r8, r0
	20131	+ bne .L3201
	20132	+ ldr r0, .L3323+12
	20133	+ ldrh r0, [r0]
	20134	+ cmp r0, r8
	20135	+ movne r2, #0
	20136	+ andeq r2, r2, #1
	20137	+ cmp r2, #0
	20138	+ beq .L3201
	20139	+ movw r2, #1156
	20140	+ ldrh r2, [r5, r2]
	20141	+ cmp r2, r8
	20142	+ beq .L3202
	20143	+.L3207:
	20144	+ mov r4, r8
	20145	+.L3201:
	20146	+ ldr r3, [r5, #-1868]
	20147	+ cmp r3, #0
	20148	+ moveq r9, #1
	20149	+ movne r9, #2
	20150	+ b .L3200
	20151	+.L3202:
	20152	+ mov r4, r3
	20153	+ ldrh r3, [r6, #-8]
	20154	+ ldrh r2, [r4, #-100]!
	20155	+ str r1, [r5, #-1556]
	20156	+ cmp r2, r3
	20157	+ bls .L3203
	20158	+ movw r3, #1932
	20159	+ ldrh r3, [r5, r3]
	20160	+ cmp r3, #0
	20161	+ bne .L3204
	20162	+ ldr r3, [r5, #-1284]
	20163	+ ldr r2, [r5, #1124]
	20164	+ add r3, r3, r3, lsl #1
	20165	+ cmp r2, r3, lsr #2
	20166	+ movcs r3, #18
	20167	+ bcs .L3320
	20168	+.L3204:
	20169	+ ldr r3, .L3323+32
	20170	+ ldrh r3, [r3]
	20171	+ add r3, r3, r3, lsl #1
	20172	+ asr r3, r3, #2
	20173	+.L3320:
	20174	+ strh r3, [r6, #-8] @ movhi
19586	20175	bl FtlReadRefresh
19587	20176	mov r0, #0
19588	20177	bl List_get_gc_head_node
19589		- ldr r3, [r7, #-1408]
19590	20178	uxth r0, r0
19591		- mov r0, r0, asl #1
	20179	+ ldr r3, [r5, #-1404]
	20180	+ lsl r0, r0, #1
19592	20181	ldrh r3, [r3, r0]
19593	20182	cmp r3, #4
19594		- movwhi r3, #1940
19595		- ldrhih r0, [r6, r3]
19596		- bhi .L3395
19597		-.L3285:
19598		- movw r5, #1940
19599		- ldr r9, .L3406+12
19600		- ldrh r0, [r6, r5]
	20183	+ bls .L3203
	20184	+.L3322:
	20185	+ movw r3, #1932
	20186	+ ldrh r0, [r5, r3]
	20187	+ b .L3159
	20188	+.L3203:
	20189	+ movw r7, #1932
	20190	+ ldrh r0, [r5, r7]
19601	20191	cmp r0, #0
19602		- bne .L3288
19603		- movw r3, #1160
19604		- ldrh fp, [r9, r3]
19605		- add r3, fp, fp, asl #1
19606		- mov r3, r3, asr #2
19607		- strh r3, [r10, #-12] @ movhi
	20192	+ bne .L3207
	20193	+ ldr r10, .L3323+32
	20194	+ ldrh r9, [r10]
	20195	+ add r3, r9, r9, lsl #1
	20196	+ asr r3, r3, #2
	20197	+ strh r3, [r6, #-8] @ movhi
19608	20198	bl List_get_gc_head_node
19609		- ldr r3, [r7, #-1408]
19610	20199	uxth r0, r0
19611		- mov r0, r0, asl #1
19612		- ldrh r1, [r3, r0]
19613		- ldr r3, .L3406+24
19614		- ldrh r2, [r3, #-2]
19615		- ldrh r3, [r3, #-72]
19616		- mul r3, r3, r2
	20200	+ ldr r3, [r5, #-1404]
	20201	+ lsl r0, r0, #1
	20202	+ ldrh r2, [r3, r0]
	20203	+ sub r3, r10, #2816
	20204	+ sub r10, r10, #2880
	20205	+ ldrh r1, [r3]
	20206	+ ldrh r3, [r10, #-4]
	20207	+ mul r3, r3, r1
19617	20208	add r3, r3, r3, lsr #31
19618		- cmp r1, r3, asr #1
19619		- ble .L3289
	20209	+ cmp r2, r3, asr #1
	20210	+ ble .L3208
19620	20211	ldrh r3, [r4]
19621		- sub r2, fp, #1
19622		- cmp r3, r2
19623		- blt .L3289
	20212	+ sub r9, r9, #1
	20213	+ cmp r3, r9
	20214	+ blt .L3208
19624	20215	bl FtlReadRefresh
19625		- ldrh r0, [r9, r5]
19626		- b .L3395
19627		-.L3289:
19628		- cmp r1, #0
19629		- bne .L3288
	20216	+ ldrh r0, [r5, r7]
	20217	+ b .L3159
	20218	+.L3208:
	20219	+ cmp r2, #0
	20220	+ bne .L3207
19630	20221	movw r0, #65535
19631	20222	bl decrement_vpc_count
19632	20223	ldrh r0, [r4]
19633	20224	add r0, r0, #1
19634		- b .L3395
19635		-.L3283:
19636		- ldr r3, [r7, #-1872]
19637		- cmp r3, #0
19638		- moveq r5, #1
19639		- movne r5, #2
19640		-.L3282:
19641		- movw r3, #1164
19642		- movw r1, #65535
19643		- ldrh r2, [r6, r3]
19644		- cmp r2, r1
19645		- bne .L3291
19646		- cmp r4, r2
19647		- ldrne r2, .L3406+12
19648		- strneh r4, [r2, r3] @ movhi
19649		- bne .L3293
19650		- ldrh r3, [r8, #-4]
19651		- ldr r2, .L3406
19652		- cmp r3, r4
19653		- sub r1, r2, #1536
19654		- beq .L3293
19655		- ldr r2, [r2, #-1408]
19656		- mov r3, r3, asl #1
19657		- ldrh r3, [r2, r3]
19658		- cmp r3, #0
19659		- mvneq r3, #0
19660		- streqh r3, [r1, #-4] @ movhi
19661		- ldrh r2, [r8, #-4]
19662		- movw r3, #1164
19663		- strh r2, [r6, r3] @ movhi
19664		- mvn r3, #0
19665		- strh r3, [r8, #-4] @ movhi
19666		-.L3293:
19667		- movw r8, #1164
19668		- mov r3, #0
19669		- ldrh r0, [r6, r8]
19670		- strb r3, [r6, #1172]
19671		- movw r3, #65535
19672		- cmp r0, r3
19673		- beq .L3291
	20225	+ b .L3159
	20226	+.L3221:
	20227	+ str r0, [sp, #16]
	20228	+ mov r0, r2
	20229	+ str r2, [sp, #12]
	20230	+ add r7, r7, #1
19674	20231	bl IsBlkInGcList
19675	20232	cmp r0, #0
19676		- ldrne r3, .L3406+12
19677		- mvnne r2, #0
19678		- strneh r2, [r3, r8] @ movhi
19679		- ldrb r3, [r7, #-2744] @ zero_extendqisi2
19680		- cmp r3, #0
19681		- beq .L3297
19682		- movw r3, #1164
19683		- ldrh r0, [r6, r3]
19684		- bl ftl_get_blk_mode
19685		- strb r0, [r6, #1172]
19686		-.L3297:
19687		- movw r9, #1164
19688		- movw r3, #65535
19689		- ldrh r2, [r6, r9]
19690		- ldr r8, .L3406+12
19691		- cmp r2, r3
19692		- ldr r10, .L3406+28
19693		- beq .L3291
19694		- mov r0, r10
19695		- bl make_superblock
19696		- movw r2, #1942
19697		- mov r3, #0
19698		- strh r3, [r8, r2] @ movhi
19699		- strh r3, [r10, #2] @ movhi
19700		- strb r3, [r8, #1170]
19701		- ldrh r3, [r8, r9]
19702		- ldr r2, [r7, #-1408]
19703		- mov r3, r3, asl #1
19704		- ldrh r2, [r2, r3]
19705		- movw r3, #1944
19706		- strh r2, [r8, r3] @ movhi
19707		-.L3291:
19708		- ldr r2, .L3406+32
19709		- movw r3, #1164
19710		- ldrh r3, [r6, r3]
19711		- ldrh r1, [r2]
19712		- cmp r1, r3
19713		- beq .L3298
19714		- ldrh r1, [r2, #48]
19715		- cmp r1, r3
19716		- beq .L3298
19717		- ldrh r2, [r2, #96]
19718		- cmp r2, r3
19719		- bne .L3332
19720		-.L3298:
19721		- movw r3, #1164
19722		- mvn r2, #0
19723		- strh r2, [r6, r3] @ movhi
19724		-.L3332:
19725		- ldr r8, .L3406+28
19726		- movw r3, #65535
19727		- ldr r7, .L3406
19728		- ldrh r2, [r8]
19729		- cmp r2, r3
19730		- bne .L3300
19731		- mov fp, r7
19732		- mov r3, #0
19733		- str r3, [r7, #-1560]
19734		-.L3301:
19735		- ldr r10, .L3406+36
19736		- ldr r9, .L3406+12
19737		- ldrh r6, [r10]
19738		- mov r0, r6
19739		- bl List_get_gc_head_node
19740		- ldr r2, .L3406+28
19741		- uxth r3, r0
19742		- strh r3, [r2] @ movhi
19743		- movw r2, #65535
19744		- cmp r3, r2
19745		- moveq r3, #0
19746		- moveq r0, #8
19747		- streqh r3, [r10] @ movhi
19748		- beq .L3395
19749		-.L3302:
19750		- mov r0, r3
19751		- str r3, [sp, #12]
19752		- bl IsBlkInGcList
19753		- add r6, r6, #1
19754		- cmp r0, #0
19755		- ldr r3, [sp, #12]
19756		- ldrne r3, .L3406+36
19757		- strneh r6, [r3] @ movhi
19758		- bne .L3301
19759		- ldr r2, .L3406+36
19760		- uxth r6, r6
19761		- ldrh r1, [r10, #-208]
19762		- mov r0, r3, asl #1
19763		- ldr ip, [fp, #-1408]
19764		- strh r6, [r2] @ movhi
19765		- ldrh r2, [r10, #-140]
19766		- ldrh lr, [ip, r0]
19767		- mul r2, r1, r2
19768		- add r1, r2, r2, lsr #31
19769		- cmp lr, r1, asr #1
19770		- bgt .L3305
19771		- cmp lr, #8
19772		- cmphi r6, #48
19773		- bls .L3306
19774		- ldr r1, .L3406+40
19775		- ldrh r1, [r1]
19776		- cmp r1, #35
19777		- bhi .L3306
19778		-.L3305:
19779		- ldr lr, .L3406+36
19780		- mov r1, #0
19781		- strh r1, [lr] @ movhi
19782		-.L3306:
19783		- ldrh r1, [ip, r0]
	20233	+ ldr r2, [sp, #12]
	20234	+ ldr r3, [sp, #16]
	20235	+ strhne r7, [r6] @ movhi
	20236	+ bne .L3220
	20237	+ ldr lr, .L3323+16
	20238	+ uxth r3, r3
	20239	+ ldr r0, [r10, #-1404]
	20240	+ uxth r7, r7
	20241	+ lsl r1, r3, #1
	20242	+ ldrh r3, [r6, #-142]
	20243	+ ldrh lr, [lr, #-68]
	20244	+ strh r7, [r6] @ movhi
	20245	+ ldrh ip, [r0, r1]
	20246	+ mul r3, lr, r3
	20247	+ add lr, r3, r3, lsr #31
	20248	+ cmp ip, lr, asr #1
	20249	+ bgt .L3224
	20250	+ cmp r7, #48
	20251	+ cmphi ip, #8
	20252	+ bls .L3225
	20253	+ add r6, r6, #3280
	20254	+ ldrh ip, [r6]
	20255	+ cmp ip, #35
	20256	+ bhi .L3225
	20257	+.L3224:
	20258	+ mov ip, #0
	20259	+ strh ip, [fp, #-4] @ movhi
	20260	+.L3225:
	20261	+ ldrh r1, [r0, r1]
19784	20262	movw r0, #65535
19785		- cmp r1, r2
19786		- cmpge r4, r0
19787		- bne .L3307
19788		- ldr r2, .L3406+36
19789		- ldrh r2, [r2]
19790		- cmp r2, #3
19791		- bhi .L3307
19792		- movw r3, #1164
19793		- mvn r2, #0
19794		- strh r2, [r9, r3] @ movhi
	20263	+ cmp r3, r1
	20264	+ cmple r4, r0
	20265	+ bne .L3226
	20266	+ ldrh r0, [fp, #-4]
	20267	+ cmp r0, #3
	20268	+ bhi .L3226
	20269	+ movw r2, #1156
	20270	+ mvn r1, #0
	20271	+ strh r1, [r10, r2] @ movhi
	20272	+ movw r3, #1932
19795	20273	mov r2, #0
19796		- ldr r3, .L3406+36
19797		- strh r2, [r3] @ movhi
19798		- b .L3400
19799		-.L3307:
	20274	+ ldrh r0, [r10, r3]
	20275	+ strh r2, [fp, #-4] @ movhi
	20276	+ b .L3159
	20277	+.L3226:
19800	20278	cmp r1, #0
19801		- bne .L3308
	20279	+ bne .L3227
19802	20280	movw r0, #65535
19803	20281	bl decrement_vpc_count
19804		- ldr r3, .L3406+36
19805		- ldr r2, .L3406+36
19806		- ldrh r3, [r3]
	20282	+ ldrh r3, [fp, #-4]
19807	20283	add r3, r3, #1
19808		- strh r3, [r2] @ movhi
19809		- b .L3301
19810		-.L3308:
19811		- mov r2, #0
19812		- strb r2, [r9, #1172]
19813		- ldrb r2, [r7, #-2744] @ zero_extendqisi2
19814		- cmp r2, #0
19815		- beq .L3309
19816		- mov r0, r3
	20284	+ strh r3, [fp, #-4] @ movhi
	20285	+ b .L3220
	20286	+.L3227:
	20287	+ mov r3, #0
	20288	+ strb r3, [r10, #1164]
	20289	+ ldrb r3, [r10, #-2740] @ zero_extendqisi2
	20290	+ cmp r3, #0
	20291	+ beq .L3228
	20292	+ mov r0, r2
19817	20293	bl ftl_get_blk_mode
19818		- ldr r3, .L3406+12
19819		- strb r0, [r3, #1172]
19820		-.L3309:
19821		- ldr r0, .L3406+28
	20294	+ strb r0, [r10, #1164]
	20295	+.L3228:
	20296	+ ldr r0, .L3323+44
19822	20297	bl make_superblock
19823	20298	ldrh r2, [r8]
19824		- ldr r1, .L3406+44
19825	20299	mov r3, #0
19826		- ldr r0, [r7, #-1408]
19827		- mov r2, r2, asl #1
	20300	+ ldr r1, .L3323+56
	20301	+ ldr r0, [r10, #-1404]
	20302	+ lsl r2, r2, #1
19828	20303	strh r3, [r1] @ movhi
19829	20304	ldrh r2, [r0, r2]
19830	20305	strh r3, [r8, #2] @ movhi
19831		- strb r3, [r9, #1170]
	20306	+ strb r3, [r10, #1162]
19832	20307	strh r2, [r1, #2] @ movhi
19833		-.L3300:
19834		- ldr r3, [sp, #20]
	20308	+.L3219:
	20309	+ ldr r3, [sp, #24]
19835	20310	cmp r3, #1
19836		- bne .L3310
	20311	+ bne .L3229
19837	20312	bl FtlReadRefresh
19838		-.L3310:
	20313	+.L3229:
19839	20314	mov r3, #1
19840		- str r3, [r7, #-1564]
19841		- ldr r3, .L3406+48
19842		- ldrh r2, [r3]
	20315	+ str r3, [r10, #-1560]
	20316	+ ldr r3, .L3323+16
	20317	+ ldrh r2, [r3, #-2]
19843	20318	str r2, [sp, #12]
19844		- ldrb r2, [r7, #-2744] @ zero_extendqisi2
	20319	+ ldrb r2, [r10, #-2740] @ zero_extendqisi2
19845	20320	cmp r2, #0
19846		- beq .L3311
19847		- ldr r2, .L3406+12
19848		- ldrb r2, [r2, #1172] @ zero_extendqisi2
	20321	+ beq .L3230
	20322	+ ldrb r2, [r10, #1164] @ zero_extendqisi2
19849	20323	cmp r2, #1
19850		- ldreqh r3, [r3, #2]
	20324	+ ldrheq r3, [r3]
19851	20325	streq r3, [sp, #12]
19852		-.L3311:
	20326	+.L3230:
19853	20327	ldrh r3, [r8, #2]
19854	20328	ldr r1, [sp, #12]
19855		- add r2, r3, r5
19856		- ldr r8, .L3406+12
	20329	+ ldr r6, .L3323+44
	20330	+ add r2, r3, r9
19857	20331	cmp r2, r1
19858	20332	movgt r2, r1
19859		- rsbgt r3, r3, r2
19860		- uxthgt r5, r3
	20333	+ subgt r3, r2, r3
	20334	+ uxthgt r9, r3
19861	20335	mov r3, #0
19862		- str r3, [sp, #16]
19863		- b .L3313
19864		-.L3405:
19865		- ldr r0, [r7, #-1488]
19866		- mov r1, r6
19867		- ldrb r2, [r8, #1172] @ zero_extendqisi2
19868		- mov r10, #0
19869		- bl FlashReadPages
19870		- ldr r7, .L3406
19871		-.L3316:
19872		- uxth r3, r10
19873		- cmp r3, r6
19874		- bcs .L3403
19875		- mov r3, #36
19876		- ldr r2, [r7, #-1488]
19877		- mul r9, r3, r10
19878		- add r1, r2, r9
19879		- ldr r2, [r2, r9]
19880		- ldr fp, [r1, #12]
19881		- cmn r2, #1
19882		- beq .L3352
19883		- ldrh r1, [fp]
19884		- movw r2, #61589
19885		- cmp r1, r2
19886		- bne .L3352
19887		- add r1, sp, #32
19888		- mov r2, #0
19889		- ldr r0, [fp, #8]
19890		- str r3, [sp, #24]
19891		- bl log2phys
19892		- ldr r1, [r7, #-1488]
19893		- add r1, r1, r9
19894		- ldr r0, [r1, #4]
19895		- ldr r2, [sp, #32]
19896		- ldr r3, [sp, #24]
19897		- bic r2, r2, #-2147483648
19898		- cmp r2, r0
19899		- bne .L3352
19900		- ldr r0, .L3406+44
19901		- ldr r1, [r1, #16]
19902		- str r3, [sp, #28]
19903		- ldrh r2, [r0]
19904		- add r2, r2, #1
19905		- strh r2, [r0] @ movhi
19906		- ldr r0, [r8, #1740]
19907		- ldr r2, [r7, #-1500]
19908		- mla r2, r3, r0, r2
19909		- str r1, [r2, #16]
19910		- str r2, [sp, #24]
19911		- bl Ftl_get_new_temp_ppa
19912		- ldr r1, [r8, #1740]
19913		- ldr r2, [sp, #24]
19914		- ldr r3, [sp, #28]
19915		- str r0, [r2, #4]
19916		- ldr r2, [r7, #-1500]
19917		- mla r3, r3, r1, r2
19918		- ldr r2, [r7, #-1488]
19919		- add r2, r2, r9
19920		- ldr r1, [r2, #8]
19921		- str r1, [r3, #8]
19922		- mov r1, #1
19923		- ldr r2, [r2, #12]
19924		- str r2, [r3, #12]
19925		- ldr r3, [sp, #32]
19926		- str r3, [fp, #12]
19927		- ldr r3, .L3406+52
19928		- ldrh r2, [r3]
19929		- str r3, [sp, #24]
19930		- strh r2, [fp, #2] @ movhi
19931		- ldr r2, [r7, #-1612]
19932		- ldr r0, [r7, #-1488]
19933		- str r2, [fp, #4]
19934		- add r0, r0, r9
19935		- ldr r2, [r8, #1740]
19936		- ldr r9, .L3406+12
19937		- add r2, r2, #1
19938		- str r2, [r8, #1740]
19939		- bl FtlGcBufAlloc
19940		- ldrb r2, [r7, #-2744] @ zero_extendqisi2
19941		- cmp r2, #0
19942		- beq .L3404
19943		-.L3318:
19944		- bl Ftl_gc_temp_data_write_back
19945		- cmp r0, #0
19946		- beq .L3352
19947		- ldr r2, .L3406
	20336	+ str r3, [sp, #20]
	20337	+.L3232:
	20338	+ ldrh r3, [sp, #20]
	20339	+ cmp r9, r3
	20340	+ bls .L3239
	20341	+ ldr r3, .L3323+60
	20342	+ add ip, r6, #14
	20343	+ ldrh r1, [r6, #2]
	20344	+ mov lr, #36
	20345	+ ldr r0, [r5, #-1484]
	20346	+ ldrh r8, [r3]
	20347	+ ldr r3, [sp, #20]
	20348	+ add r1, r1, r3
19948	20349	mov r3, #0
19949		- mvn r1, #0
19950		- str r3, [r2, #-1564]
19951		- movw r2, #1164
19952		- strh r1, [r9, r2] @ movhi
19953		- ldr r2, .L3406+28
19954		- strh r3, [r2, #2] @ movhi
19955		-.L3400:
19956		- movw r3, #1940
19957		- ldrh r0, [r9, r3]
19958		- b .L3395
19959		-.L3403:
19960		- ldr r3, [sp, #16]
	20350	+ mov fp, r3
	20351	+ b .L3240
	20352	+.L3234:
	20353	+ ldrh r2, [ip, #2]!
	20354	+ movw r7, #65535
19961	20355	add r3, r3, #1
19962		- str r3, [sp, #16]
19963		-.L3313:
19964		- ldrh r3, [sp, #16]
19965		- ldr r7, .L3406
19966		- cmp r3, r5
19967		- ldr r6, .L3406+28
19968		- bcs .L3320
19969		- ldr r3, .L3406+56
19970		- mov r2, #0
19971		- ldrh r0, [r6, #2]
19972		- movw lr, #65535
19973		- ldr r9, [r7, #-1488]
19974		- mov ip, #36
19975		- ldrh r10, [r3]
19976		- ldr r3, [sp, #16]
19977		- add r0, r0, r3
19978		- add r3, r6, #14
19979		- mov r6, r2
	20356	+ cmp r2, r7
	20357	+ mlane r7, lr, fp, r0
	20358	+ addne fp, fp, #1
	20359	+ orrne r2, r1, r2, lsl #10
	20360	+ uxthne fp, fp
	20361	+ strne r2, [r7, #4]
	20362	+.L3240:
	20363	+ uxth r2, r3
	20364	+ cmp r8, r2
	20365	+ bhi .L3234
	20366	+ ldrb r2, [r5, #1164] @ zero_extendqisi2
	20367	+ mov r1, fp
	20368	+ bl FlashReadPages
	20369	+ mov r3, #0
19980	20370	.L3321:
19981		- uxth r1, r2
19982		- cmp r1, r10
19983		- bcs .L3405
19984		- ldrh r1, [r3, #2]!
19985		- add r2, r2, #1
19986		- cmp r1, lr
19987		- orrne r1, r0, r1, asl #10
19988		- mlane fp, ip, r6, r9
19989		- addne r6, r6, #1
19990		- uxthne r6, r6
19991		- strne r1, [fp, #4]
19992		- b .L3321
19993		-.L3404:
19994		- ldrb r2, [r7, #987] @ zero_extendqisi2
19995		- ldr r1, [r8, #1740]
19996		- cmp r1, r2
19997		- beq .L3318
19998		- ldr r3, [sp, #24]
	20371	+ str r3, [sp, #16]
	20372	+ ldrh r3, [sp, #16]
	20373	+ cmp fp, r3
	20374	+ ldrls r3, [sp, #20]
	20375	+ addls r3, r3, #1
	20376	+ strls r3, [sp, #20]
	20377	+ bls .L3232
	20378	+.L3238:
	20379	+ ldr r2, [sp, #16]
	20380	+ mov r3, #36
	20381	+ mul r7, r3, r2
	20382	+ ldr r3, [r5, #-1484]
	20383	+ add r2, r3, r7
	20384	+ ldr r3, [r3, r7]
	20385	+ cmn r3, #1
	20386	+ beq .L3236
	20387	+ ldr r8, [r2, #12]
	20388	+ movw r3, #61589
	20389	+ ldrh r2, [r8]
	20390	+ cmp r2, r3
	20391	+ bne .L3236
	20392	+ mov r2, #0
	20393	+ add r1, sp, #32
	20394	+ ldr r0, [r8, #8]
	20395	+ bl log2phys
	20396	+ ldr r2, [r5, #-1484]
	20397	+ ldr r3, [sp, #32]
	20398	+ add r2, r2, r7
	20399	+ ldr r1, [r2, #4]
	20400	+ bic r3, r3, #-2147483648
	20401	+ cmp r3, r1
	20402	+ bne .L3236
	20403	+ ldr r3, .L3323+56
	20404	+ mov r0, #36
	20405	+ ldr r1, .L3323+56
	20406	+ ldr r2, [r2, #16]
	20407	+ ldrh r3, [r3]
	20408	+ add r3, r3, #1
	20409	+ strh r3, [r1] @ movhi
	20410	+ ldr r1, [r5, #1732]
	20411	+ ldr r3, [r5, #-1496]
	20412	+ mla r3, r0, r1, r3
	20413	+ str r2, [r3, #16]
	20414	+ str r3, [sp, #28]
	20415	+ bl Ftl_get_new_temp_ppa
	20416	+ ldr r3, [sp, #28]
	20417	+ mov r1, #36
	20418	+ ldr r2, [r5, #-1496]
	20419	+ str r0, [r3, #4]
	20420	+ ldr r3, [r5, #1732]
	20421	+ mla r2, r1, r3, r2
	20422	+ ldr r3, [r5, #-1484]
	20423	+ add r3, r3, r7
	20424	+ ldr r1, [r3, #8]
	20425	+ str r1, [r2, #8]
	20426	+ mov r1, #1
	20427	+ ldr r3, [r3, #12]
	20428	+ str r3, [r2, #12]
	20429	+ ldr r3, [sp, #32]
	20430	+ str r3, [r8, #12]
	20431	+ ldr r3, .L3323+28
	20432	+ ldrh r3, [r3]
	20433	+ strh r3, [r8, #2] @ movhi
	20434	+ ldr r3, [r5, #-1608]
	20435	+ ldr r0, [r5, #-1484]
	20436	+ str r3, [r8, #4]
	20437	+ ldr r3, [r5, #1732]
	20438	+ add r0, r0, r7
	20439	+ add r3, r3, #1
	20440	+ str r3, [r5, #1732]
	20441	+ bl FtlGcBufAlloc
	20442	+ ldrb r3, [r5, #-2740] @ zero_extendqisi2
	20443	+ cmp r3, #0
	20444	+ bne .L3237
	20445	+ ldrb r2, [r5, #987] @ zero_extendqisi2
	20446	+ ldr r3, [r5, #1732]
	20447	+ cmp r2, r3
	20448	+ beq .L3237
	20449	+ ldr r3, .L3323+28
19999	20450	ldrh r3, [r3, #4]
20000	20451	cmp r3, #0
20001		- beq .L3318
20002		-.L3352:
20003		- add r10, r10, #1
20004		- b .L3316
20005		-.L3320:
	20452	+ bne .L3236
	20453	+.L3237:
	20454	+ bl Ftl_gc_temp_data_write_back
	20455	+ cmp r0, #0
	20456	+ beq .L3236
	20457	+ ldr r3, .L3323
	20458	+ mvn r0, #0
	20459	+ movw r1, #1156
	20460	+ mov r2, #0
	20461	+ strh r0, [r3, r1] @ movhi
	20462	+ ldr r1, .L3323+44
	20463	+ str r2, [r3, #-1560]
	20464	+ strh r2, [r1, #2] @ movhi
	20465	+ movw r2, #1932
	20466	+ ldrh r0, [r3, r2]
	20467	+ b .L3159
	20468	+.L3236:
	20469	+ ldr r3, [sp, #16]
	20470	+ add r3, r3, #1
	20471	+ b .L3321
	20472	+.L3239:
20006	20473	ldrh r3, [r6, #2]
20007		- ldr r8, .L3406+12
20008		- add r5, r5, r3
20009		- ldr r3, [sp, #12]
20010		- uxth r5, r5
20011		- mov r9, r8
20012		- cmp r5, r3
20013		- strh r5, [r6, #2] @ movhi
20014		- bcc .L3322
20015		- ldr r3, [r8, #1740]
	20474	+ ldr r2, [sp, #12]
	20475	+ add r3, r9, r3
	20476	+ uxth r3, r3
	20477	+ cmp r2, r3
	20478	+ strh r3, [r6, #2] @ movhi
	20479	+ bhi .L3241
	20480	+ ldr r3, [r5, #1732]
20016	20481	cmp r3, #0
20017		- beq .L3323
	20482	+ beq .L3242
20018	20483	bl Ftl_gc_temp_data_write_back
20019	20484	cmp r0, #0
20020	20485	movne r3, #0
20021		- strne r3, [r7, #-1564]
20022		- movwne r3, #1940
20023		- ldrneh r0, [r8, r3]
20024		- bne .L3395
20025		-.L3323:
20026		- ldr r3, .L3406+44
20027		- ldrh r5, [r3]
20028		- cmp r5, #0
20029		- bne .L3324
	20486	+ strne r3, [r5, #-1560]
	20487	+ bne .L3322
	20488	+.L3242:
	20489	+ ldr r3, .L3323+56
	20490	+ ldrh r7, [r3]
	20491	+ cmp r7, #0
	20492	+ bne .L3243
20030	20493	ldrh r3, [r6]
20031		- ldr r2, [r7, #-1408]
20032		- mov r3, r3, asl #1
	20494	+ ldr r2, [r5, #-1404]
	20495	+ lsl r3, r3, #1
20033	20496	ldrh r3, [r2, r3]
20034	20497	cmp r3, #0
20035		- beq .L3324
20036		-.L3325:
20037		- ldr r3, [r7, #-1284]
20038		- cmp r5, r3
20039		- bcs .L3330
20040		- mov r0, r5
20041		- add r1, sp, #36
	20498	+ beq .L3243
	20499	+.L3244:
	20500	+ ldr r3, [r5, #-1284]
	20501	+ cmp r7, r3
	20502	+ bcs .L3249
20042	20503	mov r2, #0
	20504	+ add r1, sp, #36
	20505	+ mov r0, r7
20043	20506	bl log2phys
20044	20507	ldr r0, [sp, #36]
20045	20508	cmn r0, #1
20046		- beq .L3326
	20509	+ beq .L3245
20047	20510	ubfx r0, r0, #10, #16
20048	20511	bl P2V_block_in_plane
20049	20512	ldrh r3, [r6]
20050	20513	cmp r3, r0
20051		- bne .L3326
20052		-.L3330:
20053		- ldr r3, [r7, #-1284]
20054		- cmp r5, r3
20055		- bcc .L3324
20056		- ldr r2, .L3406
20057		- mov r1, #0
	20514	+ bne .L3245
	20515	+.L3249:
	20516	+ ldr r3, [r5, #-1284]
	20517	+ cmp r7, r3
	20518	+ bcc .L3243
20058	20519	ldrh r3, [r6]
20059		- ldr r2, [r2, #-1408]
20060		- mov r3, r3, asl #1
	20520	+ mov r1, #0
	20521	+ ldr r2, [r5, #-1404]
	20522	+ lsl r3, r3, #1
20061	20523	strh r1, [r2, r3] @ movhi
20062	20524	ldrh r0, [r6]
20063	20525	bl update_vpc_list
20064	20526	bl FtlCacheWriteBack
20065	20527	bl l2p_flush
20066	20528	bl FtlVpcTblFlush
20067		- b .L3324
20068		-.L3326:
20069		- add r5, r5, #1
20070		- b .L3325
20071		-.L3324:
	20529	+.L3243:
20072	20530	mvn r3, #0
20073	20531	strh r3, [r6] @ movhi
20074		-.L3322:
20075		- ldr r2, .L3406
20076		- add r3, r2, #880
	20532	+.L3241:
	20533	+ ldr r3, .L3323+24
20077	20534	ldrh r3, [r3]
20078	20535	cmp r3, #2
20079		- ldrls r3, .L3406+48
20080		- ldrlsh r5, [r3]
20081		- bls .L3332
20082		-.L3331:
20083		- mov r1, #0
20084		- str r1, [r2, #-1564]
20085		- movw r2, #1940
20086		- ldrh r0, [r9, r2]
20087		- cmp r0, r1
20088		- addeq r0, r3, #1
20089		- b .L3395
20090		-.L3338:
20091		- mov r0, r8
20092		- b .L3395
20093		-.L3402:
20094		- ldrh fp, [r8, #-4]
20095		- cmp fp, r4
20096		- bne .L3259
20097		- add r10, r5, #880
20098		- ldr r2, [r5, #-1548]
20099		- ldrh r3, [r10]
20100		- cmp r3, #24
20101		- movcc r3, #5120
20102		- movcs r3, #1024
20103		- cmp r2, r3
20104		- movls r4, fp
20105		- bls .L3259
20106		- movw r2, #1940
20107		- mov r3, #0
20108		- str r3, [r7, #-1548]
20109		- strh r3, [r6, r2] @ movhi
20110		- bl GetSwlReplaceBlock
20111		- cmp r0, fp
20112		- mov r4, r0
20113		- sub fp, r5, #1520
20114		- bne .L3261
20115		- ldrh r2, [r10]
20116		- ldrh r3, [fp, #-10]
20117		- cmp r2, r3
20118		- bcs .L3262
20119		- mov r0, #64
20120		- bl List_get_gc_head_node
20121		- uxth r3, r0
20122		- cmp r3, r4
20123		- beq .L3271
20124		- ldr r2, [r5, #-1624]
20125		- sub r1, r5, #1712
20126		- cmp r2, #0
20127		- bne .L3264
20128		- ldrh r2, [r1, #-4]
20129		- cmp r2, #3
20130		- beq .L3264
20131		- ldr r2, [r5, #-1620]
20132		- cmp r2, #0
20133		- bne .L3264
20134		- ldr r2, [r5, #-1872]
20135		- cmp r2, #0
20136		- bne .L3264
20137		- ldrb r0, [r5, #-2744] @ zero_extendqisi2
	20536	+ bhi .L3250
	20537	+ ldr r3, .L3323+64
	20538	+ ldrh r9, [r3]
	20539	+ b .L3251
	20540	+.L3245:
	20541	+ add r7, r7, #1
	20542	+ b .L3244
	20543	+.L3250:
	20544	+ mov r2, #0
	20545	+ str r2, [r5, #-1560]
	20546	+ movw r2, #1932
	20547	+ ldrh r0, [r5, r2]
20138	20548	cmp r0, #0
20139		- beq .L3265
20140		-.L3264:
20141		- ldr r2, [r7, #-1408]
20142		- mov r3, r3, asl #1
20143		- ldrh r1, [r1, #-4]
20144		- ldrh r0, [r2, r3]
20145		- cmp r1, #3
20146		- ldr r2, .L3406+24
20147		- ldrh r3, [r2, #-2]
20148		- ldrh r2, [r2, #-72]
20149		- mul r2, r2, r3
20150		- moveq r3, r3, lsr #1
20151		- movne r3, #0
20152		- add r3, r2, r3
20153		- cmp r0, r3
20154		- bgt .L3267
	20549	+ addeq r0, r3, #1
	20550	+ b .L3159
	20551	+.L3255:
20155	20552	mov r0, #0
20156		- bl List_get_gc_head_node
20157		- ldr r3, [r7, #-1284]
20158		- ldr r2, [r7, #1124]
20159		- add r3, r3, r3, asl #1
20160		- cmp r2, r3, lsr #2
20161		- movls r3, #160
20162		- uxth r4, r0
20163		- bls .L3398
20164		- b .L3401
20165		-.L3265:
20166		- ldr r2, [r5, #-1408]
20167		- mov r3, r3, asl #1
20168		- ldrh r3, [r2, r3]
20169		- cmp r3, #7
20170		- bhi .L3270
20171		- bl List_get_gc_head_node
20172		- uxth r4, r0
20173		-.L3401:
20174		- mov r3, #128
20175		-.L3398:
20176		- strh r3, [fp, #-10] @ movhi
20177		- movw r3, #65535
20178		- cmp r4, r3
20179		- beq .L3271
20180		- b .L3261
20181		-.L3267:
20182		- mov r3, #128
20183		- b .L3399
20184		-.L3270:
20185		- mov r3, #64
20186		- b .L3399
20187		-.L3262:
20188		- mov r3, #80
20189		-.L3399:
20190		- strh r3, [fp, #-10] @ movhi
20191		- b .L3271
20192		-.L3261:
20193		- ldr r0, [r7, #-1416]
20194		- mov r1, r4, asl #1
20195		- ldr r3, [r7, #-1408]
20196		- ldrh r2, [r10]
20197		- ldrh r3, [r3, r1]
20198		- ldrh r1, [r0, r1]
20199		- ldr r0, .L3406+60
20200		- str r1, [sp]
20201		- ldrh r1, [fp, #-12]
20202		- str r1, [sp, #4]
20203		- mov r1, r4
20204		- bl printk
20205		-.L3271:
20206		- bl FtlGcReFreshBadBlk
20207		- b .L3259
20208		-.L3395:
20209		- add sp, sp, #44
20210		- @ sp needed
20211		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
20212		-.L3407:
	20553	+ b .L3159
	20554	+.L3324:
20213	20555	.align 2
20214		-.L3406:
	20556	+.L3323:
20215	20557	.word .LANCHOR2
20216	20558	.word .LANCHOR1
	20559	+ .word .LANCHOR2-1520
20217	20560	.word .LANCHOR2-1536
20218		- .word .LANCHOR4
	20561	+ .word .LANCHOR2-1664
20219	20562	.word .LC158
20220	20563	.word .LANCHOR2+880
20221		- .word .LANCHOR2-1664
20222		- .word .LANCHOR4+1164
20223		- .word .LANCHOR2+884
20224		- .word .LANCHOR2-1528
20225		- .word .LANCHOR4+1764
20226		- .word .LANCHOR4+1942
20227		- .word .LANCHOR2-1668
20228	20564	.word .LANCHOR2+980
20229		- .word .LANCHOR2-1736
	20565	+ .word .LANCHOR2+1152
	20566	+ .word .LANCHOR2-1712
20230	20567	.word .LC159
	20568	+ .word .LANCHOR2+1156
	20569	+ .word .LANCHOR2+884
	20570	+ .word .LANCHOR2-1524
	20571	+ .word .LANCHOR2+1934
	20572	+ .word .LANCHOR2-1732
	20573	+ .word .LANCHOR2-1666
20231	20574	.fnend
20232	20575	.size ftl_do_gc, .-ftl_do_gc
20233	20576	.align 2
20234	20577	.global FtlCacheWriteBack
	20578	+ .syntax unified
	20579	+ .arm
	20580	+ .fpu softvfp
20235	20581	.type FtlCacheWriteBack, %function
20236	20582	FtlCacheWriteBack:
20237	20583	.fnstart
20238	20584	@ args = 0, pretend = 0, frame = 8
20239	20585	@ frame_needed = 0, uses_anonymous_args = 0
20240		- stmfd sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
	20586	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
20241	20587	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
20242	20588	.pad #12
20243		- ldr r4, .L3452
20244		- ldr r8, .L3452+4
20245		- ldr r3, [r4, #-1280]
20246		- ldr r5, [r8, #1948]
20247		- cmp r3, #0
20248		- bne .L3410
20249		- ldr r1, [r4, #-1516]
	20589	+ ldr r4, .L3368
	20590	+ ldr r8, [r4, #-1280]
	20591	+ cmp r8, #0
	20592	+ bne .L3327
	20593	+ ldr r1, [r4, #-1512]
20250	20594	cmp r1, #0
20251		- beq .L3410
20252		- ldrb r6, [r4, #-2744] @ zero_extendqisi2
20253		- mov r7, #0
20254		- ldr r0, [r4, #-1484]
20255		- mov r10, #36
20256		- cmp r6, #0
	20595	+ beq .L3327
	20596	+ ldrb r3, [r4, #-2740] @ zero_extendqisi2
	20597	+ mov r6, #0
	20598	+ ldr r5, [r4, #1940]
	20599	+ mov r9, #36
	20600	+ ldr r10, .L3368+4
	20601	+ cmp r3, #0
	20602	+ ldr r0, [r4, #-1480]
	20603	+ ldrbne r7, [r5, #8] @ zero_extendqisi2
	20604	+ moveq r7, r8
20257	20605	ldrb r3, [r5, #9] @ zero_extendqisi2
20258		- ldr r9, .L3452
20259		- ldrneb r6, [r5, #8] @ zero_extendqisi2
20260		- subne r6, r6, #1
20261		- clzne r6, r6
20262		- movne r6, r6, lsr #5
20263		- mov r2, r6
	20606	+ subne r7, r7, #1
	20607	+ clzne r7, r7
	20608	+ lsrne r7, r7, #5
	20609	+ mov r2, r7
20264	20610	bl FlashProgPages
20265		-.L3413:
20266		- ldr r3, [r4, #-1516]
20267		- cmp r7, r3
20268		- bcs .L3431
20269		- mul fp, r10, r7
20270		- ldr r3, [r9, #-1484]
20271		- add r2, r3, fp
	20611	+.L3330:
	20612	+ ldr r3, [r4, #-1512]
	20613	+ cmp r6, r3
	20614	+ bcc .L3337
	20615	+.L3349:
	20616	+ mov r3, #0
	20617	+ str r3, [r4, #-1512]
	20618	+.L3327:
	20619	+ mov r0, #0
	20620	+ add sp, sp, #12
	20621	+ @ sp needed
	20622	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	20623	+.L3337:
	20624	+ mul fp, r9, r6
	20625	+ ldr r3, [r4, #-1480]
	20626	+ add r0, r3, fp
20272	20627	ldr r3, [r3, fp]
20273	20628	cmn r3, #1
20274		- beq .L3434
20275		- ldr r3, [r2, #4]
20276		- cmp r6, #0
20277		- ldr r0, [r2, #16]
20278		- add r1, sp, #4
	20629	+ bne .L3331
	20630	+ ldr r10, .L3368+4
	20631	+.L3332:
	20632	+ ldr r3, [r4, #-1512]
	20633	+ cmp r8, r3
	20634	+ bcc .L3347
	20635	+ movw r5, #16386
	20636	+.L3350:
	20637	+ ldr r3, .L3368+8
	20638	+ ldrh r3, [r3]
	20639	+ cmp r3, #0
	20640	+ beq .L3349
	20641	+ mov r1, #1
	20642	+ mov r0, r1
	20643	+ bl ftl_do_gc
	20644	+ subs r5, r5, #1
	20645	+ bne .L3350
	20646	+ b .L3349
	20647	+.L3331:
	20648	+ ldr r3, [r0, #4]
	20649	+ cmp r7, #0
20279	20650	mov r2, #1
	20651	+ add r1, sp, #4
	20652	+ ldr r0, [r0, #16]
20280	20653	orrne r3, r3, #-2147483648
20281	20654	str r3, [sp, #4]
20282	20655	bl log2phys
20283		- ldr r3, [r4, #-1484]
20284		- add r3, r3, fp
20285		- ldr r3, [r3, #12]
	20656	+ ldr r3, [r4, #-1480]
	20657	+ add fp, r3, fp
	20658	+ ldr r3, [fp, #12]
20286	20659	ldr r0, [r3, #12]
20287	20660	cmn r0, #1
20288		- beq .L3417
	20661	+ beq .L3335
20289	20662	ubfx r0, r0, #10, #16
20290	20663	bl P2V_block_in_plane
20291		- ldr r2, [r9, #-1408]
20292		- mov r3, r0, asl #1
	20664	+ ldr r2, [r4, #-1404]
	20665	+ lsl r3, r0, #1
20293	20666	mov fp, r0
20294	20667	ldrh r2, [r2, r3]
20295	20668	cmp r2, #0
20296		- bne .L3418
20297		- ldr r0, .L3452+8
20298		- mov r1, fp
	20669	+ bne .L3336
	20670	+ mov r1, r0
	20671	+ mov r0, r10
20299	20672	bl printk
20300		-.L3418:
	20673	+.L3336:
20301	20674	mov r0, fp
20302	20675	bl decrement_vpc_count
20303		-.L3417:
20304		- add r7, r7, #1
20305		- b .L3413
20306		-.L3450:
20307		- ldr r6, .L3452+12
20308		- movw r5, #16386
20309		-.L3430:
20310		- ldrh r3, [r6]
20311		- cmp r3, #0
20312		- beq .L3431
20313		- mov r0, #1
20314		- mov r1, r0
20315		- bl ftl_do_gc
20316		- subs r5, r5, #1
20317		- bne .L3430
20318		-.L3431:
20319		- mov r3, #0
20320		- str r3, [r4, #-1516]
20321		- b .L3410
20322		-.L3434:
20323		- ldr r10, .L3452
	20676	+.L3335:
	20677	+ add r6, r6, #1
	20678	+ b .L3330
	20679	+.L3347:
	20680	+ mov r6, #36
	20681	+ ldr r3, [r4, #-1480]
	20682	+ mul r6, r6, r8
20324	20683	mov r9, #0
20325		-.L3414:
20326		- ldr r3, [r4, #-1516]
20327		- cmp r9, r3
20328		- bcs .L3450
20329		- mov r7, #36
20330		- ldr r3, [r10, #-1484]
20331		- mul r7, r7, r9
20332		- mov fp, #0
	20684	+ mov fp, #1
20333	20685	mvn r2, #0
20334		- str r2, [r3, r7]
20335		-.L3420:
20336		- ldr r3, [r4, #-1484]
20337		- add r2, r3, r7
20338		- ldr r3, [r3, r7]
20339		- cmn r3, #1
20340		- bne .L3451
20341		- ldr r0, [r2, #4]
	20686	+ str r2, [r3, r6]
	20687	+.L3338:
	20688	+ ldr r2, [r4, #-1480]
	20689	+ add r3, r2, r6
	20690	+ ldr r2, [r2, r6]
	20691	+ ldr r0, [r3, #4]
	20692	+ cmn r2, #1
	20693	+ beq .L3342
	20694	+ cmp r7, #0
	20695	+ mov r2, #1
	20696	+ orrne r0, r0, #-2147483648
	20697	+ add r1, sp, #4
	20698	+ str r0, [sp, #4]
	20699	+ ldr r0, [r3, #16]
	20700	+ bl log2phys
	20701	+ ldr r3, [r4, #-1480]
	20702	+ add r6, r3, r6
	20703	+ ldr r3, [r6, #12]
	20704	+ ldr r0, [r3, #12]
	20705	+ cmn r0, #1
	20706	+ beq .L3345
	20707	+ ubfx r0, r0, #10, #16
	20708	+ bl P2V_block_in_plane
	20709	+ ldr r2, [r4, #-1404]
	20710	+ lsl r3, r0, #1
	20711	+ mov r6, r0
	20712	+ ldrh r2, [r2, r3]
	20713	+ cmp r2, #0
	20714	+ bne .L3346
	20715	+ mov r1, r0
	20716	+ mov r0, r10
	20717	+ bl printk
	20718	+.L3346:
	20719	+ mov r0, r6
	20720	+ bl decrement_vpc_count
	20721	+.L3345:
	20722	+ add r8, r8, #1
	20723	+ b .L3332
	20724	+.L3342:
20342	20725	ubfx r0, r0, #10, #16
20343	20726	bl P2V_block_in_plane
20344	20727	ldrh r3, [r5]
20345	20728	cmp r3, r0
20346		- bne .L3421
20347		- ldr r1, [r10, #-1408]
20348		- mov r3, r3, asl #1
	20729	+ bne .L3339
	20730	+ ldr r1, [r4, #-1404]
	20731	+ lsl r3, r3, #1
20349	20732	ldrh r0, [r5, #4]
20350	20733	ldrh r2, [r1, r3]
20351		- rsb r2, r0, r2
	20734	+ sub r2, r2, r0
20352	20735	strh r2, [r1, r3] @ movhi
20353		- ldr r3, .L3452+16
20354		- strb fp, [r5, #6]
20355		- strh fp, [r5, #4] @ movhi
	20736	+ ldr r3, .L3368+12
	20737	+ strb r9, [r5, #6]
	20738	+ strh r9, [r5, #4] @ movhi
20356	20739	ldrh r3, [r3]
20357	20740	strh r3, [r5, #2] @ movhi
20358		-.L3421:
	20741	+.L3339:
20359	20742	ldrh r3, [r5, #4]
20360	20743	cmp r3, #0
20361		- bne .L3422
	20744	+ bne .L3340
20362	20745	mov r0, r5
20363	20746	bl allocate_new_data_superblock
20364		-.L3422:
20365		- ldr r3, [r8, #1308]
	20747	+.L3340:
	20748	+ ldr r3, [r4, #1300]
20366	20749	add r3, r3, #1
20367		- str r3, [r8, #1308]
20368		- ldr r3, [r4, #-1484]
20369		- add r3, r3, r7
	20750	+ str r3, [r4, #1300]
	20751	+ ldr r3, [r4, #-1480]
	20752	+ add r3, r3, r6
20370	20753	ldr r0, [r3, #4]
20371	20754	ubfx r0, r0, #10, #16
20372	20755	bl FtlGcMarkBadPhyBlk
20373	20756	mov r0, r5
20374	20757	bl get_new_active_ppa
20375		- ldr r3, [r4, #-1484]
20376		- mov r1, #1
20377		- mov r2, r6
20378		- add r3, r3, r7
	20758	+ ldr r3, [r4, #-1480]
	20759	+ mov r2, r0
20379	20760	str r0, [sp, #4]
20380		- str r0, [r3, #4]
20381		- mov r0, r3
	20761	+ mov r1, #1
	20762	+ add r0, r3, r6
	20763	+ str r2, [r0, #4]
	20764	+ mov r2, r7
20382	20765	ldrb r3, [r5, #9] @ zero_extendqisi2
20383	20766	bl FlashProgPages
20384		- ldr r3, [r4, #-1484]
20385		- ldr r3, [r3, r7]
	20767	+ ldr r3, [r4, #-1480]
	20768	+ ldr r3, [r3, r6]
20386	20769	cmn r3, #1
20387		- moveq r3, #1
20388		- streq r3, [r10, #-1280]
	20770	+ streq fp, [r4, #-1280]
20389	20771	ldr r3, [r4, #-1280]
20390	20772	cmp r3, #0
20391		- beq .L3420
20392		- b .L3410
20393		-.L3451:
20394		- ldr r3, [r2, #4]
20395		- cmp r6, #0
20396		- ldr r0, [r2, #16]
20397		- add r1, sp, #4
20398		- mov r2, #1
20399		- orrne r3, r3, #-2147483648
20400		- str r3, [sp, #4]
20401		- bl log2phys
20402		- ldr r3, [r4, #-1484]
20403		- add r7, r3, r7
20404		- ldr r3, [r7, #12]
20405		- ldr r0, [r3, #12]
20406		- cmn r0, #1
20407		- beq .L3427
20408		- ubfx r0, r0, #10, #16
20409		- bl P2V_block_in_plane
20410		- ldr r2, [r10, #-1408]
20411		- mov r3, r0, asl #1
20412		- mov r7, r0
20413		- ldrh r2, [r2, r3]
20414		- cmp r2, #0
20415		- bne .L3428
20416		- ldr r0, .L3452+8
20417		- mov r1, r7
20418		- bl printk
20419		-.L3428:
20420		- mov r0, r7
20421		- bl decrement_vpc_count
20422		-.L3427:
20423		- add r9, r9, #1
20424		- b .L3414
20425		-.L3410:
20426		- mov r0, #0
20427		- add sp, sp, #12
20428		- @ sp needed
20429		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
20430		-.L3453:
	20773	+ beq .L3338
	20774	+ b .L3327
	20775	+.L3369:
20431	20776	.align 2
20432		-.L3452:
	20777	+.L3368:
20433	20778	.word .LANCHOR2
20434		- .word .LANCHOR4
20435	20779	.word .LC160
20436		- .word .LANCHOR2-1526
20437		- .word .LANCHOR2-1668
	20780	+ .word .LANCHOR2-1522
	20781	+ .word .LANCHOR2-1666
20438	20782	.fnend
20439	20783	.size FtlCacheWriteBack, .-FtlCacheWriteBack
20440	20784	.align 2
20441	20785	.global FtlSysFlush
	20786	+ .syntax unified
	20787	+ .arm
	20788	+ .fpu softvfp
20442	20789	.type FtlSysFlush, %function
20443	20790	FtlSysFlush:
20444	20791	.fnstart
20445	20792	@ args = 0, pretend = 0, frame = 0
20446	20793	@ frame_needed = 0, uses_anonymous_args = 0
20447		- ldr r3, .L3458
	20794	+ ldr r3, .L3376
20448	20795	ldr r3, [r3, #-1280]
20449	20796	cmp r3, #0
20450		- bne .L3457
20451		- ldr r3, .L3458+4
20452		- stmfd sp!, {r4, lr}
	20797	+ bne .L3373
	20798	+ ldr r3, .L3376+4
	20799	+ push {r4, lr}
20453	20800	.save {r4, lr}
20454		- ldr r4, [r3, #3444]
	20801	+ ldr r4, [r3, #3440]
20455	20802	cmp r4, #1
20456		- bne .L3455
	20803	+ bne .L3371
20457	20804	bl FtlCacheWriteBack
20458	20805	bl l2p_flush
20459	20806	mov r0, r4
20460	20807	bl FtlEctTblFlush
20461	20808	bl FtlVpcTblFlush
20462		-.L3455:
	20809	+.L3371:
20463	20810	mov r0, #0
20464		- ldmfd sp!, {r4, pc}
20465		-.L3457:
	20811	+ pop {r4, pc}
	20812	+.L3373:
20466	20813	mov r0, #0
20467	20814	bx lr
20468		-.L3459:
	20815	+.L3377:
20469	20816	.align 2
20470		-.L3458:
	20817	+.L3376:
20471	20818	.word .LANCHOR2
20472	20819	.word .LANCHOR1
20473	20820	.fnend
20474	20821	.size FtlSysFlush, .-FtlSysFlush
20475	20822	.align 2
20476	20823	.global FtlDeInit
	20824	+ .syntax unified
	20825	+ .arm
	20826	+ .fpu softvfp
20477	20827	.type FtlDeInit, %function
20478	20828	FtlDeInit:
20479	20829	.fnstart
20480	20830	@ args = 0, pretend = 0, frame = 0
20481	20831	@ frame_needed = 0, uses_anonymous_args = 0
20482		- stmfd sp!, {r3, lr}
20483		- .save {r3, lr}
20484		- ldr r3, .L3463
20485		- ldr r3, [r3, #3444]
	20832	+ ldr r3, .L3384
	20833	+ ldr r3, [r3, #3440]
20486	20834	cmp r3, #1
20487		- bne .L3461
	20835	+ bne .L3381
	20836	+ push {r4, lr}
	20837	+ .save {r4, lr}
20488	20838	bl FtlSysFlush
20489		-.L3461:
20490	20839	mov r0, #0
20491		- ldmfd sp!, {r3, pc}
20492		-.L3464:
	20840	+ pop {r4, pc}
	20841	+.L3381:
	20842	+ mov r0, #0
	20843	+ bx lr
	20844	+.L3385:
20493	20845	.align 2
20494		-.L3463:
	20846	+.L3384:
20495	20847	.word .LANCHOR1
20496	20848	.fnend
20497	20849	.size FtlDeInit, .-FtlDeInit
20498	20850	.align 2
20499	20851	.global ftl_deinit
	20852	+ .syntax unified
	20853	+ .arm
	20854	+ .fpu softvfp
20500	20855	.type ftl_deinit, %function
20501	20856	ftl_deinit:
20502	20857	.fnstart
20503	20858	@ args = 0, pretend = 0, frame = 0
20504	20859	@ frame_needed = 0, uses_anonymous_args = 0
20505		- stmfd sp!, {r3, lr}
20506		- .save {r3, lr}
	20860	+ push {r4, lr}
	20861	+ .save {r4, lr}
20507	20862	bl ftl_flash_de_init
20508	20863	bl FtlDeInit
20509		- ldmfd sp!, {r3, lr}
	20864	+ pop {r4, lr}
20510	20865	b ftl_flash_de_init
20511	20866	.fnend
20512	20867	.size ftl_deinit, .-ftl_deinit
20513	20868	.align 2
20514	20869	.global ftl_cache_flush
	20870	+ .syntax unified
	20871	+ .arm
	20872	+ .fpu softvfp
20515	20873	.type ftl_cache_flush, %function
20516	20874	ftl_cache_flush:
20517	20875	.fnstart
..	..	@@ -20523,393 +20881,387 @@
20523	20881	.size ftl_cache_flush, .-ftl_cache_flush
20524	20882	.align 2
20525	20883	.global ftl_discard
	20884	+ .syntax unified
	20885	+ .arm
	20886	+ .fpu softvfp
20526	20887	.type ftl_discard, %function
20527	20888	ftl_discard:
20528	20889	.fnstart
20529	20890	@ args = 0, pretend = 0, frame = 8
20530	20891	@ frame_needed = 0, uses_anonymous_args = 0
20531		- stmfd sp!, {r0, r1, r4, r5, r6, r7, r8, lr}
20532		- .save {r4, r5, r6, r7, r8, lr}
20533		- .pad #8
20534		- mov r6, r0
20535		- ldr r5, .L3486
20536		- mov r4, r1
20537		- ldr r3, [r5, #-2740]
20538		- cmp r1, r3
20539		- cmpls r0, r3
20540		- bcs .L3477
	20892	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
	20893	+ .save {r4, r5, r6, r7, r8, r9, lr}
	20894	+ .pad #12
	20895	+ ldr r4, .L3406
	20896	+ ldr r3, [r4, #-2736]
	20897	+ cmp r3, r1
	20898	+ cmpcs r3, r0
	20899	+ bls .L3398
20541	20900	add r2, r0, r1
20542		- cmp r2, r3
20543		- bhi .L3477
20544		- cmp r1, #31
20545		- bhi .L3470
20546		-.L3471:
20547		- mov r0, #0
20548		- b .L3469
20549		-.L3470:
20550		- ldr r3, [r5, #-1280]
20551		- cmp r3, #0
20552		- bne .L3471
20553		- sub r5, r5, #1648
20554		- bl FtlCacheWriteBack
20555		- mov r0, r6
20556		- ldrh r5, [r5, #-14]
20557		- mov r1, r5
20558		- bl __aeabi_uidiv
20559		- smulbb r3, r0, r5
20560	20901	mov r7, r0
20561		- rsb r6, r3, r6
20562		- uxth r6, r6
20563		- cmp r6, #0
20564		- beq .L3472
20565		- rsb r5, r6, r5
20566		- add r7, r0, #1
20567		- cmp r5, r4
20568		- movcs r5, r4
20569		- uxth r5, r5
20570		- rsb r4, r5, r4
20571		-.L3472:
20572		- ldr r5, .L3486+4
20573		- mvn r3, #0
20574		- ldr r8, .L3486
20575		- str r3, [sp, #4]
20576		- mov r6, r5
20577		-.L3473:
20578		- ldrh r3, [r5]
20579		- cmp r4, r3
20580		- bcc .L3485
	20902	+ cmp r3, r2
	20903	+ mov r5, r1
	20904	+ bcc .L3398
	20905	+ cmp r1, #31
	20906	+ bhi .L3391
	20907	+.L3392:
	20908	+ mov r0, #0
	20909	+.L3389:
	20910	+ add sp, sp, #12
	20911	+ @ sp needed
	20912	+ pop {r4, r5, r6, r7, r8, r9, pc}
	20913	+.L3391:
	20914	+ ldr r3, [r4, #-1280]
	20915	+ cmp r3, #0
	20916	+ bne .L3392
	20917	+ sub r9, r4, #1648
	20918	+ bl FtlCacheWriteBack
	20919	+ ldrh r6, [r9, #-12]
20581	20920	mov r0, r7
20582		- mov r1, sp
	20921	+ mov r1, r6
	20922	+ bl __aeabi_uidiv
	20923	+ smulbb r3, r0, r6
	20924	+ mov r8, r0
	20925	+ sub r7, r7, r3
	20926	+ uxth r7, r7
	20927	+ cmp r7, #0
	20928	+ beq .L3393
	20929	+ sub r6, r6, r7
	20930	+ add r8, r0, #1
	20931	+ cmp r6, r5
	20932	+ movcs r6, r5
	20933	+ uxth r6, r6
	20934	+ sub r5, r5, r6
	20935	+.L3393:
	20936	+ mvn r3, #0
	20937	+ str r3, [sp, #4]
	20938	+.L3394:
	20939	+ ldrh r3, [r9, #-12]
	20940	+ cmp r5, r3
	20941	+ bcs .L3396
	20942	+ ldr r3, [r4, #1944]
	20943	+ cmp r3, #32
	20944	+ bls .L3392
	20945	+ mov r5, #0
	20946	+ str r5, [r4, #1944]
	20947	+ bl l2p_flush
	20948	+ bl FtlVpcTblFlush
	20949	+ b .L3392
	20950	+.L3396:
20583	20951	mov r2, #0
	20952	+ mov r1, sp
	20953	+ mov r0, r8
20584	20954	bl log2phys
20585	20955	ldr r3, [sp]
20586	20956	cmn r3, #1
20587		- beq .L3474
20588		- ldr r2, .L3486+8
20589		- add r1, sp, #4
20590		- mov r0, r7
20591		- ldr r3, [r2, #1952]
20592		- add r3, r3, #1
20593		- str r3, [r2, #1952]
20594		- ldr r3, [r8, #-1600]
	20957	+ beq .L3395
	20958	+ ldr r3, [r4, #1944]
20595	20959	mov r2, #1
	20960	+ add r1, sp, #4
	20961	+ mov r0, r8
20596	20962	add r3, r3, #1
20597		- str r3, [r8, #-1600]
	20963	+ str r3, [r4, #1944]
	20964	+ ldr r3, [r4, #-1596]
	20965	+ add r3, r3, #1
	20966	+ str r3, [r4, #-1596]
20598	20967	bl log2phys
20599	20968	ldr r0, [sp]
20600	20969	ubfx r0, r0, #10, #16
20601	20970	bl P2V_block_in_plane
20602	20971	bl decrement_vpc_count
20603		-.L3474:
20604		- ldrh r3, [r6]
20605		- add r7, r7, #1
20606		- rsb r4, r3, r4
20607		- b .L3473
20608		-.L3485:
20609		- ldr r3, .L3486+8
20610		- ldr r2, [r3, #1952]
20611		- cmp r2, #32
20612		- bls .L3471
20613		- mov r4, #0
20614		- str r4, [r3, #1952]
20615		- bl l2p_flush
20616		- bl FtlVpcTblFlush
20617		- b .L3471
20618		-.L3477:
	20972	+.L3395:
	20973	+ ldrh r3, [r9, #-12]
	20974	+ add r8, r8, #1
	20975	+ sub r5, r5, r3
	20976	+ b .L3394
	20977	+.L3398:
20619	20978	mvn r0, #0
20620		-.L3469:
20621		- add sp, sp, #8
20622		- @ sp needed
20623		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
20624		-.L3487:
	20979	+ b .L3389
	20980	+.L3407:
20625	20981	.align 2
20626		-.L3486:
	20982	+.L3406:
20627	20983	.word .LANCHOR2
20628		- .word .LANCHOR2-1662
20629		- .word .LANCHOR4
20630	20984	.fnend
20631	20985	.size ftl_discard, .-ftl_discard
20632	20986	.align 2
20633	20987	.global FtlGcFreeTempBlock
	20988	+ .syntax unified
	20989	+ .arm
	20990	+ .fpu softvfp
20634	20991	.type FtlGcFreeTempBlock, %function
20635	20992	FtlGcFreeTempBlock:
20636	20993	.fnstart
20637		- @ args = 0, pretend = 0, frame = 16
	20994	+ @ args = 0, pretend = 0, frame = 8
20638	20995	@ frame_needed = 0, uses_anonymous_args = 0
20639		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	20996	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
20640	20997	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
20641		- .pad #20
20642		- sub sp, sp, #20
20643		- ldr r6, .L3527
20644		- sub r9, r6, #1664
20645		- ldr r8, [r6, #-1280]
20646		- ldrh r1, [r9, #-4]
20647		- cmp r8, #0
20648		- bne .L3525
20649		- add r4, r6, #980
20650		- mov r5, r6
20651		- movw ip, #65535
20652		- ldrh r6, [r4]
20653		- cmp r6, ip
20654		- bne .L3491
20655		-.L3500:
20656		- ldrh r2, [r4]
	20998	+ .pad #12
	20999	+ ldr r4, .L3447
	21000	+ ldr ip, [r4, #-1280]
	21001	+ sub r7, r4, #1664
	21002	+ ldrh r1, [r7, #-2]
	21003	+ cmp ip, #0
	21004	+ beq .L3409
	21005	+.L3445:
	21006	+ mov r0, #0
	21007	+.L3408:
	21008	+ add sp, sp, #12
	21009	+ @ sp needed
	21010	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	21011	+.L3409:
	21012	+ add r5, r4, #980
	21013	+ movw lr, #65535
	21014	+ ldrh r6, [r5]
	21015	+ cmp r6, lr
	21016	+ bne .L3411
	21017	+.L3420:
	21018	+ ldrh r2, [r5]
20657	21019	movw r3, #65535
20658		- ldr r6, .L3527+4
20659		- mov r7, #0
20660		- ldr r8, .L3527
	21020	+ mov r6, #0
	21021	+ str r6, [r4, #1748]
20661	21022	cmp r2, r3
20662		- str r7, [r6, #1756]
20663		- add r10, r8, #980
20664		- beq .L3525
	21023	+ beq .L3445
20665	21024	bl FtlCacheWriteBack
20666		- ldrh r2, [r9, #-4]
20667		- ldrb r0, [r8, #987] @ zero_extendqisi2
20668		- ldrh r3, [r10]
	21025	+ ldrb r2, [r4, #987] @ zero_extendqisi2
20669	21026	mov r10, #12
20670		- ldr r1, [r8, #-1408]
20671		- smulbb r2, r0, r2
20672		- mov r3, r3, asl #1
20673		- ldr r9, .L3527+8
	21027	+ ldrh r0, [r7, #-2]
	21028	+ ldrh r3, [r5]
	21029	+ ldr r1, [r4, #-1404]
	21030	+ ldr r9, .L3447+4
	21031	+ smulbb r2, r2, r0
	21032	+ lsl r3, r3, #1
20674	21033	strh r2, [r1, r3] @ movhi
20675		- movw r3, #1766
20676		- ldr r2, [r8, #-1608]
20677		- ldrh r3, [r6, r3]
	21034	+ movw r3, #1758
	21035	+ ldr r2, [r4, #-1604]
	21036	+ ldrh r3, [r4, r3]
20678	21037	add r3, r3, r2
20679		- str r3, [r8, #-1608]
20680		- b .L3501
20681		-.L3491:
	21038	+ str r3, [r4, #-1604]
	21039	+.L3421:
	21040	+ ldrh r2, [r9]
	21041	+ uxth r3, r6
	21042	+ cmp r2, r3
	21043	+ bhi .L3425
	21044	+ movw r0, #65535
	21045	+ bl decrement_vpc_count
	21046	+ ldrb r3, [r4, #-2740] @ zero_extendqisi2
	21047	+ cmp r3, #0
	21048	+ beq .L3426
	21049	+ ldrh r1, [r5]
	21050	+ ldr r0, .L3447+8
	21051	+ bl printk
	21052	+.L3426:
	21053	+ ldrh r0, [r5]
	21054	+ ldr r2, [r4, #-1404]
	21055	+ lsl r3, r0, #1
	21056	+ ldrh r3, [r2, r3]
	21057	+ cmp r3, #0
	21058	+ beq .L3427
	21059	+ bl INSERT_DATA_LIST
	21060	+.L3428:
	21061	+ mvn r6, #0
	21062	+ movw r3, #1758
	21063	+ strh r6, [r5] @ movhi
	21064	+ mov r5, #0
	21065	+ strh r5, [r4, r3] @ movhi
	21066	+ movw r3, #1756
	21067	+ strh r5, [r4, r3] @ movhi
	21068	+ bl l2p_flush
	21069	+ bl FtlVpcTblFlush
	21070	+ movw r3, #1156
	21071	+ strh r6, [r4, r3] @ movhi
	21072	+ ldr r3, [r4, #-1868]
	21073	+ cmp r3, r5
	21074	+ ldr r3, .L3447+12
	21075	+ add r2, r3, #272
	21076	+ ldrh r2, [r2]
	21077	+ beq .L3429
	21078	+ ldr r1, [r4, #-1564]
	21079	+ cmp r1, #39
	21080	+ bhi .L3429
	21081	+ ldrh r1, [r3]
	21082	+ cmp r1, r2
	21083	+ subcc r3, r3, #2400
	21084	+ lslcc r2, r2, #1
	21085	+ bcs .L3445
	21086	+.L3446:
	21087	+ strh r2, [r3, #-8] @ movhi
	21088	+ b .L3445
	21089	+.L3411:
20682	21090	cmp r0, #0
20683		- beq .L3494
20684		- ldr r2, .L3527+12
20685		- movw r3, #3448
	21091	+ beq .L3414
	21092	+ ldr r2, .L3447+16
	21093	+ movw r3, #3444
20686	21094	ldrh r0, [r2, r3]
20687		- cmp r0, ip
20688		- beq .L3495
20689		-.L3496:
	21095	+ cmp r0, lr
	21096	+ beq .L3415
	21097	+.L3416:
20690	21098	mov r1, #2
20691		- b .L3494
20692		-.L3495:
20693		- strh r8, [r2, r3] @ movhi
20694		- add r3, r5, #880
20695		- ldrh r3, [r3]
20696		- cmp r3, #17
20697		- bhi .L3496
20698		-.L3494:
20699		- ldr r7, .L3527
20700		- add r0, r7, #980
	21099	+.L3414:
	21100	+ ldr r0, .L3447+20
20701	21101	bl FtlGcScanTempBlk
20702	21102	cmn r0, #1
20703		- str r0, [sp, #12]
20704		- beq .L3497
20705		- ldr r2, [r7, #-1416]
20706		- mov r6, r6, asl #1
	21103	+ str r0, [sp, #4]
	21104	+ beq .L3417
	21105	+ ldr r2, [r4, #-1412]
	21106	+ lsl r6, r6, #1
20707	21107	ldrh r3, [r2, r6]
20708	21108	cmp r3, #4
20709		- bls .L3498
	21109	+ bls .L3418
20710	21110	sub r3, r3, #5
20711	21111	mov r0, #1
20712	21112	strh r3, [r2, r6] @ movhi
20713	21113	bl FtlEctTblFlush
20714		-.L3498:
20715		- ldr r4, .L3527+4
20716		- ldr r3, [r4, #1756]
	21114	+.L3418:
	21115	+ ldr r3, [r4, #1748]
20717	21116	cmp r3, #0
20718		- bne .L3499
20719		- ldr r0, [sp, #12]
20720		- ldr r3, [r4, #1308]
20721		- ubfx r0, r0, #10, #16
	21117	+ bne .L3419
	21118	+ ldr r3, [r4, #1300]
	21119	+ ldr r0, [sp, #4]
20722	21120	add r3, r3, #1
20723		- str r3, [r4, #1308]
	21121	+ ubfx r0, r0, #10, #16
	21122	+ str r3, [r4, #1300]
20724	21123	bl FtlBbmMapBadBlock
20725	21124	bl FtlBbmTblFlush
20726		-.L3499:
	21125	+.L3419:
20727	21126	mov r3, #0
20728		- str r3, [r4, #1756]
20729		- b .L3511
20730		-.L3497:
20731		- ldr r2, .L3527+12
20732		- movw r3, #3448
	21127	+ str r3, [r4, #1748]
	21128	+.L3431:
	21129	+ mov r0, #1
	21130	+ b .L3408
	21131	+.L3415:
	21132	+ strh ip, [r2, r3] @ movhi
	21133	+ add r3, r4, #880
	21134	+ ldrh r3, [r3]
	21135	+ cmp r3, #17
	21136	+ bhi .L3416
	21137	+ b .L3414
	21138	+.L3417:
	21139	+ ldr r2, .L3447+16
	21140	+ movw r3, #3444
20733	21141	ldrh r2, [r2, r3]
20734	21142	movw r3, #65535
20735	21143	cmp r2, r3
20736		- bne .L3511
20737		- b .L3500
20738		-.L3504:
20739		- ldr r3, [fp, #4]
20740		- cmp r0, r3
20741		- bne .L3523
20742		-.L3503:
20743		- add r7, r7, #1
20744		-.L3501:
20745		- ldrh r3, [r9]
20746		- uxth r8, r7
20747		- cmp r3, r8
20748		- bls .L3526
	21144	+ bne .L3431
	21145	+ b .L3420
	21146	+.L3425:
	21147	+ uxth r8, r6
	21148	+ ldr fp, [r4, #-1504]
	21149	+ ldr r3, [r4, #-1284]
20749	21150	mul r8, r10, r8
20750		- ldr r3, [r5, #-1508]
20751		- ldr r2, [r5, #-1284]
20752		- add fp, r3, r8
20753		- ldr r0, [fp, #8]
20754		- cmp r0, r2
20755		- bcs .L3523
20756		- add r1, sp, #12
20757		- mov r2, #0
20758		- str r3, [sp, #4]
20759		- bl log2phys
20760		- ldr r3, [sp, #4]
20761		- ldr r0, [sp, #12]
20762		- ldr r3, [r3, r8]
	21151	+ add r7, fp, r8
	21152	+ ldr r0, [r7, #8]
20763	21153	cmp r0, r3
20764		- bne .L3504
	21154	+ bcc .L3422
	21155	+.L3443:
	21156	+ ldrh r0, [r5]
	21157	+ b .L3444
	21158	+.L3422:
	21159	+ mov r2, #0
	21160	+ add r1, sp, #4
	21161	+ bl log2phys
	21162	+ ldr r0, [fp, r8]
	21163	+ ldr r3, [sp, #4]
	21164	+ cmp r0, r3
	21165	+ bne .L3424
20765	21166	ubfx r0, r0, #10, #16
20766	21167	bl P2V_block_in_plane
20767		- add r1, fp, #4
20768	21168	mov r2, #1
20769	21169	mov r8, r0
20770		- ldr r0, [fp, #8]
	21170	+ add r1, r7, #4
	21171	+ ldr r0, [r7, #8]
20771	21172	bl log2phys
20772	21173	mov r0, r8
20773		- b .L3524
20774		-.L3523:
20775		- ldrh r0, [r4]
20776		-.L3524:
	21174	+.L3444:
20777	21175	bl decrement_vpc_count
20778		- b .L3503
20779		-.L3526:
20780		- movw r0, #65535
20781		- bl decrement_vpc_count
20782		- ldrb r3, [r5, #-2744] @ zero_extendqisi2
20783		- cmp r3, #0
20784		- beq .L3506
20785		- ldr r0, .L3527+16
20786		- ldrh r1, [r4]
20787		- bl printk
20788		-.L3506:
20789		- ldrh r0, [r4]
20790		- ldr r2, [r5, #-1408]
20791		- mov r3, r0, asl #1
20792		- ldrh r3, [r2, r3]
20793		- cmp r3, #0
20794		- beq .L3507
20795		- bl INSERT_DATA_LIST
20796		- b .L3508
20797		-.L3507:
	21176	+ b .L3423
	21177	+.L3424:
	21178	+ ldr r2, [r7, #4]
	21179	+ cmp r3, r2
	21180	+ bne .L3443
	21181	+.L3423:
	21182	+ add r6, r6, #1
	21183	+ b .L3421
	21184	+.L3427:
20798	21185	bl INSERT_FREE_LIST
20799		-.L3508:
20800		- movw r3, #1766
20801		- mvn r8, #0
20802		- strh r8, [r4] @ movhi
20803		- mov r4, #0
20804		- strh r4, [r6, r3] @ movhi
20805		- movw r3, #1764
20806		- strh r4, [r6, r3] @ movhi
20807		- bl l2p_flush
20808		- bl FtlVpcTblFlush
20809		- movw r3, #1164
20810		- strh r8, [r6, r3] @ movhi
20811		- ldr r3, [r5, #-1872]
20812		- ldr r7, .L3527
20813		- cmp r3, r4
20814		- add r1, r7, #880
20815		- beq .L3509
20816		- ldr r3, [r7, #-1568]
20817		- cmp r3, #39
20818		- bhi .L3509
20819		- ldr r2, .L3527+4
20820		- movw r3, #1160
20821		- ldrh r3, [r2, r3]
20822		- ldrh r2, [r1]
20823		- cmp r2, r3
20824		- subcc r7, r7, #1520
20825		- movcc r3, r3, asl #1
20826		- strcch r3, [r7, #-12] @ movhi
20827		- b .L3525
20828		-.L3509:
20829		- movw r3, #1160
20830		- ldrh r1, [r1]
20831		- ldrh r2, [r6, r3]
20832		- ldr r3, .L3527
20833		- add r0, r2, r2, asl #1
20834		- cmp r1, r0, asr #2
20835		- ble .L3525
20836		- ldrb r0, [r3, #-2744] @ zero_extendqisi2
20837		- sub r3, r3, #1520
	21186	+ b .L3428
	21187	+.L3429:
	21188	+ ldrh r3, [r3]
	21189	+ add r1, r2, r2, lsl #1
	21190	+ cmp r3, r1, asr #2
	21191	+ ble .L3445
	21192	+ ldrb r0, [r4, #-2740] @ zero_extendqisi2
	21193	+ ldr r3, .L3447+24
20838	21194	cmp r0, #0
20839	21195	moveq r2, #20
20840		- streqh r2, [r3, #-12] @ movhi
20841		- beq .L3490
	21196	+ strheq r2, [r3, #-8] @ movhi
	21197	+ beq .L3408
20842	21198	sub r2, r2, #2
20843		- strh r2, [r3, #-12] @ movhi
20844		-.L3525:
20845		- mov r0, #0
20846		- b .L3490
20847		-.L3511:
20848		- mov r0, #1
20849		-.L3490:
20850		- add sp, sp, #20
20851		- @ sp needed
20852		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
20853		-.L3528:
	21199	+ b .L3446
	21200	+.L3448:
20854	21201	.align 2
20855		-.L3527:
	21202	+.L3447:
20856	21203	.word .LANCHOR2
20857		- .word .LANCHOR4
20858		- .word .LANCHOR4+1766
20859		- .word .LANCHOR1
	21204	+ .word .LANCHOR2+1758
20860	21205	.word .LC161
	21206	+ .word .LANCHOR2+880
	21207	+ .word .LANCHOR1
	21208	+ .word .LANCHOR2+980
	21209	+ .word .LANCHOR2-1520
20861	21210	.fnend
20862	21211	.size FtlGcFreeTempBlock, .-FtlGcFreeTempBlock
20863	21212	.align 2
20864	21213	.global FtlGcPageRecovery
	21214	+ .syntax unified
	21215	+ .arm
	21216	+ .fpu softvfp
20865	21217	.type FtlGcPageRecovery, %function
20866	21218	FtlGcPageRecovery:
20867	21219	.fnstart
20868	21220	@ args = 0, pretend = 0, frame = 0
20869	21221	@ frame_needed = 0, uses_anonymous_args = 0
20870		- stmfd sp!, {r3, r4, r5, lr}
20871		- .save {r3, r4, r5, lr}
20872		- ldr r4, .L3532
20873		- ldr r5, .L3532+4
20874		- mov r0, r4
20875		- ldrh r1, [r5, #-4]
	21222	+ push {r4, r5, r6, lr}
	21223	+ .save {r4, r5, r6, lr}
	21224	+ ldr r4, .L3452
	21225	+ sub r5, r4, #1664
	21226	+ add r6, r4, #980
	21227	+ ldrh r1, [r5, #-2]
	21228	+ mov r0, r6
20876	21229	bl FtlGcScanTempBlk
20877		- ldrh r2, [r4, #2]
20878		- ldrh r3, [r5, #-4]
	21230	+ ldrh r2, [r6, #2]
	21231	+ ldrh r3, [r5, #-2]
20879	21232	cmp r2, r3
20880		- ldmccfd sp!, {r3, r4, r5, pc}
20881		- add r0, r4, #48
	21233	+ popcc {r4, r5, r6, pc}
	21234	+ add r0, r6, #48
20882	21235	bl FtlMapBlkWriteDumpData
20883	21236	mov r0, #0
20884	21237	bl FtlGcFreeTempBlock
20885		- ldr r3, .L3532+8
20886		- mov r2, #0
20887		- str r2, [r3, #1756]
20888		- ldmfd sp!, {r3, r4, r5, pc}
20889		-.L3533:
	21238	+ mov r3, #0
	21239	+ str r3, [r4, #1748]
	21240	+ pop {r4, r5, r6, pc}
	21241	+.L3453:
20890	21242	.align 2
20891		-.L3532:
20892		- .word .LANCHOR2+980
20893		- .word .LANCHOR2-1664
20894		- .word .LANCHOR4
	21243	+.L3452:
	21244	+ .word .LANCHOR2
20895	21245	.fnend
20896	21246	.size FtlGcPageRecovery, .-FtlGcPageRecovery
20897	21247	.align 2
20898	21248	.global FtlPowerLostRecovery
	21249	+ .syntax unified
	21250	+ .arm
	21251	+ .fpu softvfp
20899	21252	.type FtlPowerLostRecovery, %function
20900	21253	FtlPowerLostRecovery:
20901	21254	.fnstart
20902	21255	@ args = 0, pretend = 0, frame = 0
20903	21256	@ frame_needed = 0, uses_anonymous_args = 0
20904		- stmfd sp!, {r4, r5, r6, lr}
	21257	+ push {r4, r5, r6, lr}
20905	21258	.save {r4, r5, r6, lr}
20906	21259	mov r5, #0
20907		- ldr r4, .L3536
20908		- ldr r3, .L3536+4
	21260	+ ldr r4, .L3456
20909	21261	add r6, r4, #884
20910		- add r4, r4, #932
	21262	+ str r5, [r4, #1800]
20911	21263	mov r0, r6
20912		- str r5, [r3, #1808]
	21264	+ add r4, r4, #932
20913	21265	bl FtlRecoverySuperblock
20914	21266	mov r0, r6
20915	21267	bl FtlSlcSuperblockCheck
..	..	@@ -20921,47 +21273,50 @@
20921	21273	movw r0, #65535
20922	21274	bl decrement_vpc_count
20923	21275	mov r0, r5
20924		- ldmfd sp!, {r4, r5, r6, pc}
20925		-.L3537:
	21276	+ pop {r4, r5, r6, pc}
	21277	+.L3457:
20926	21278	.align 2
20927		-.L3536:
	21279	+.L3456:
20928	21280	.word .LANCHOR2
20929		- .word .LANCHOR4
20930	21281	.fnend
20931	21282	.size FtlPowerLostRecovery, .-FtlPowerLostRecovery
20932	21283	.align 2
20933	21284	.global FtlSysBlkInit
	21285	+ .syntax unified
	21286	+ .arm
	21287	+ .fpu softvfp
20934	21288	.type FtlSysBlkInit, %function
20935	21289	FtlSysBlkInit:
20936	21290	.fnstart
20937	21291	@ args = 0, pretend = 0, frame = 0
20938	21292	@ frame_needed = 0, uses_anonymous_args = 0
20939		- stmfd sp!, {r4, r5, r6, r7, r8, lr}
	21293	+ push {r4, r5, r6, r7, r8, lr}
20940	21294	.save {r4, r5, r6, r7, r8, lr}
20941		- movw r3, #1804
20942		- ldr r7, .L3556
20943	21295	mov r2, #0
20944		- ldr r4, .L3556+4
20945		- strh r2, [r7, r3] @ movhi
20946		- movw r3, #1802
	21296	+ ldr r4, .L3476
	21297	+ movw r3, #1796
	21298	+ strh r2, [r4, r3] @ movhi
20947	21299	mvn r2, #0
20948		- strh r2, [r7, r3] @ movhi
20949		- ldr r3, [r4, #-1732]
20950		- uxth r0, r3
	21300	+ movw r3, #1794
	21301	+ strh r2, [r4, r3] @ movhi
	21302	+ sub r3, r4, #1728
	21303	+ ldrh r0, [r3]
20951	21304	bl FtlFreeSysBlkQueueInit
20952	21305	bl FtlScanSysBlk
20953	21306	movw r3, #1128
20954	21307	ldrh r2, [r4, r3]
20955	21308	movw r3, #65535
20956	21309	cmp r2, r3
20957		- bne .L3539
20958		-.L3541:
20959		- mvn r8, #0
20960		- b .L3540
20961		-.L3539:
	21310	+ bne .L3459
	21311	+.L3461:
	21312	+ mvn r7, #0
	21313	+.L3458:
	21314	+ mov r0, r7
	21315	+ pop {r4, r5, r6, r7, r8, pc}
	21316	+.L3459:
20962	21317	bl FtlLoadSysInfo
20963		- subs r8, r0, #0
20964		- bne .L3541
	21318	+ subs r7, r0, #0
	21319	+ bne .L3461
20965	21320	bl FtlLoadMapInfo
20966	21321	bl FtlLoadVonderInfo
20967	21322	bl Ftl_load_ext_data
..	..	@@ -20971,58 +21326,49 @@
20971	21326	bl FtlPowerLostRecovery
20972	21327	mov r0, #1
20973	21328	bl FtlUpdateVaildLpn
20974		- sub r3, r4, #1616
20975	21329	ldr r2, [r4, #-1364]
	21330	+ sub r3, r4, #1616
	21331	+ ldrh r1, [r3, #-10]
20976	21332	mov r0, #12
20977		- ldrh r1, [r3, #-14]
20978		- mov r3, r8
20979		-.L3542:
	21333	+ mov r3, r7
	21334	+.L3462:
20980	21335	cmp r3, r1
20981		- bge .L3547
	21336	+ bge .L3467
20982	21337	mla ip, r0, r3, r2
20983	21338	ldr ip, [ip, #4]
20984	21339	cmp ip, #0
20985		- bge .L3543
20986		-.L3547:
20987		- ldr r5, .L3556+8
	21340	+ bge .L3463
	21341	+.L3467:
	21342	+ ldr r5, .L3476+4
20988	21343	cmp r3, r1
20989		- add r6, r5, #68
20990	21344	ldrh r2, [r5, #28]
	21345	+ add r6, r5, #68
20991	21346	add r2, r2, #1
20992	21347	strh r2, [r5, #28] @ movhi
20993		- bge .L3554
20994		- b .L3544
20995		-.L3543:
20996		- add r3, r3, #1
20997		- b .L3542
20998		-.L3554:
20999		- movw r3, #1804
21000		- ldrh r3, [r7, r3]
21001		- cmp r3, #0
21002		- beq .L3548
21003		-.L3544:
	21348	+ bge .L3474
	21349	+.L3464:
21004	21350	ldrh r3, [r6]
21005		- ldr r1, [r4, #-1408]
21006		- ldr ip, .L3556+12
21007		- mov r3, r3, asl #1
	21351	+ ldr r1, [r4, #-1404]
21008	21352	ldrh r0, [r6, #4]
	21353	+ ldr ip, .L3476+8
	21354	+ lsl r3, r3, #1
21009	21355	ldrh r2, [r1, r3]
21010		- rsb r2, r0, r2
	21356	+ sub r2, r2, r0
21011	21357	strh r2, [r1, r3] @ movhi
21012		- ldrh r3, [ip, #-4]
21013	21358	mov r2, #0
21014		- ldr lr, [r4, #-1408]
	21359	+ ldrh r3, [ip, #-2]
	21360	+ ldr lr, [r4, #-1404]
21015	21361	strb r2, [r4, #890]
21016	21362	strh r3, [r6, #2] @ movhi
21017		- ldr r3, .L3556+16
	21363	+ ldr r3, .L3476+12
21018	21364	strh r2, [r6, #4] @ movhi
21019	21365	ldrh r1, [r3]
21020		- ldrh r7, [r3, #4]
21021		- mov r1, r1, asl #1
	21366	+ ldrh r8, [r3, #4]
	21367	+ lsl r1, r1, #1
21022	21368	ldrh r0, [lr, r1]
21023		- rsb r0, r7, r0
	21369	+ sub r0, r0, r8
21024	21370	strh r0, [lr, r1] @ movhi
21025		- ldrh r1, [ip, #-4]
	21371	+ ldrh r1, [ip, #-2]
21026	21372	strh r2, [r3, #4] @ movhi
21027	21373	strb r2, [r4, #938]
21028	21374	strh r1, [r3, #2] @ movhi
..	..	@@ -21032,1811 +21378,1784 @@
21032	21378	bl l2p_flush
21033	21379	bl FtlVpcTblFlush
21034	21380	bl FtlVpcTblFlush
21035		-.L3548:
	21381	+ b .L3468
	21382	+.L3463:
	21383	+ add r3, r3, #1
	21384	+ b .L3462
	21385	+.L3474:
	21386	+ movw r3, #1796
	21387	+ ldrh r3, [r4, r3]
	21388	+ cmp r3, #0
	21389	+ bne .L3464
	21390	+.L3468:
21036	21391	ldrh r0, [r6]
21037	21392	movw r3, #65535
21038		- ldr r7, .L3556+20
21039	21393	cmp r0, r3
21040		- beq .L3549
21041		- ldrh r3, [r7, #4]
	21394	+ beq .L3469
	21395	+ ldrh r3, [r6, #4]
21042	21396	cmp r3, #0
21043		- bne .L3549
21044		- ldrh r3, [r7, #52]
21045		- add r4, r7, #48
	21397	+ bne .L3469
	21398	+ ldr r4, .L3476+12
	21399	+ ldrh r3, [r4, #4]
21046	21400	cmp r3, #0
21047		- bne .L3549
	21401	+ bne .L3469
21048	21402	bl FtlGcRefreshOpenBlock
21049		- ldrh r0, [r7, #48]
	21403	+ ldrh r0, [r4]
21050	21404	bl FtlGcRefreshOpenBlock
21051	21405	bl FtlVpcTblFlush
21052		- mov r0, r7
	21406	+ sub r0, r4, #48
21053	21407	bl allocate_new_data_superblock
21054	21408	mov r0, r4
21055	21409	bl allocate_new_data_superblock
21056		-.L3549:
21057		- ldr r3, .L3556+24
21058		- ldrb r3, [r3] @ zero_extendqisi2
	21410	+.L3469:
	21411	+ ldr r3, .L3476+16
	21412	+ ldrb r3, [r3, #36] @ zero_extendqisi2
21059	21413	cmp r3, #0
21060		- bne .L3550
	21414	+ bne .L3470
21061	21415	ldrh r3, [r5, #28]
21062	21416	tst r3, #31
21063		- bne .L3540
21064		-.L3550:
	21417	+ bne .L3458
	21418	+.L3470:
21065	21419	bl FtlVpcCheckAndModify
21066		-.L3540:
21067		- mov r0, r8
21068		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
21069		-.L3557:
	21420	+ b .L3458
	21421	+.L3477:
21070	21422	.align 2
21071		-.L3556:
21072		- .word .LANCHOR4
	21423	+.L3476:
21073	21424	.word .LANCHOR2
21074	21425	.word .LANCHOR2+816
21075	21426	.word .LANCHOR2-1664
21076	21427	.word .LANCHOR2+932
21077		- .word .LANCHOR2+884
21078	21428	.word .LANCHOR0
21079	21429	.fnend
21080	21430	.size FtlSysBlkInit, .-FtlSysBlkInit
21081	21431	.align 2
21082	21432	.global FtlLowFormat
	21433	+ .syntax unified
	21434	+ .arm
	21435	+ .fpu softvfp
21083	21436	.type FtlLowFormat, %function
21084	21437	FtlLowFormat:
21085	21438	.fnstart
21086		- @ args = 0, pretend = 0, frame = 16
	21439	+ @ args = 0, pretend = 0, frame = 8
21087	21440	@ frame_needed = 0, uses_anonymous_args = 0
21088		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	21441	+ push {r0, r1, r2, r4, r5, r6, r7, r8, r9, r10, fp, lr}
21089	21442	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
21090		- .pad #20
21091		- sub sp, sp, #20
21092		- ldr r4, .L3593
	21443	+ .pad #12
	21444	+ ldr r4, .L3510
21093	21445	ldr r5, [r4, #-1280]
21094	21446	cmp r5, #0
21095		- bne .L3560
21096		- sub r6, r4, #1632
	21447	+ bne .L3480
	21448	+ sub r6, r4, #1616
21097	21449	mov r1, r5
	21450	+ ldrh r2, [r6, #-12]
21098	21451	ldr r0, [r4, #-1372]
21099		- ldrh r2, [r6]
21100		- mov r2, r2, asl #2
	21452	+ lsl r2, r2, #2
21101	21453	bl ftl_memset
21102		- ldrh r2, [r6]
	21454	+ ldrh r2, [r6, #-12]
21103	21455	mov r1, r5
21104	21456	ldr r0, [r4, #-1376]
21105		- mov r2, r2, asl #2
	21457	+ lsl r2, r2, #2
21106	21458	bl ftl_memset
21107		- ldr r3, [r4, #-1732]
21108		- str r5, [r4, #-1616]
	21459	+ sub r3, r4, #1728
21109	21460	str r5, [r4, #-1612]
21110		- uxth r0, r3
	21461	+ ldrh r0, [r3]
	21462	+ str r5, [r4, #-1608]
21111	21463	bl FtlFreeSysBlkQueueInit
21112	21464	bl FtlLoadBbt
21113	21465	cmp r0, #0
21114		- beq .L3561
	21466	+ beq .L3481
21115	21467	bl FtlMakeBbt
21116		-.L3561:
21117		- ldr r0, .L3593
	21468	+.L3481:
	21469	+ ldr r0, .L3510+4
21118	21470	mov r2, #0
21119		- ldr ip, .L3593+4
21120		- ldr lr, .L3593+8
21121		-.L3562:
21122		- ldrh r1, [ip]
	21471	+.L3482:
	21472	+ ldr r7, .L3510+8
21123	21473	uxth r3, r2
21124	21474	add r2, r2, #1
21125		- cmp r3, r1, asl #7
21126		- bge .L3590
21127		- ldr r5, [r0, #-1456]
21128		- mvn r1, r3
21129		- orr r1, r3, r1, asl #16
21130		- str r1, [r5, r3, asl #2]
21131		- ldr r1, [r0, #-1452]
21132		- str lr, [r1, r3, asl #2]
21133		- b .L3562
21134		-.L3590:
21135		- ldr r9, .L3593+12
21136		- mov r7, #0
21137		- add r10, r9, #2
21138		- ldrh r5, [r9]
21139		-.L3564:
21140		- ldrh r3, [r10]
21141		- ldr r6, .L3593
21142		- cmp r3, r5
21143		- ldr r8, .L3593+16
21144		- bls .L3591
	21475	+ ldrh r1, [r7]
	21476	+ cmp r3, r1, lsl #7
	21477	+ blt .L3483
	21478	+ sub r7, r7, #52
	21479	+ ldrh r6, [r7, #-12]
	21480	+ mov r5, #0
	21481	+.L3484:
	21482	+ ldrh r3, [r7, #-10]
	21483	+ cmp r3, r6
	21484	+ bhi .L3485
	21485	+ ldr r10, .L3510+12
	21486	+ sub r3, r5, #3
	21487	+ ldrh r1, [r10, #-4]
	21488	+ cmp r3, r1, lsl #1
	21489	+ blt .L3486
21145	21490	mov r0, r5
21146		- mov r1, #1
21147		- bl FtlLowFormatEraseBlock
21148		- add r5, r5, #1
21149		- uxth r5, r5
21150		- add r0, r7, r0
21151		- uxth r7, r0
21152		- b .L3564
21153		-.L3591:
21154		- ldrh r1, [r9, #-8]
21155		- sub r3, r7, #3
21156		- sub r5, r6, #1728
21157		- cmp r3, r1, asl #1
21158		- blt .L3566
21159		- mov r0, r7
21160		- mov r7, #0
	21491	+ mov r5, #0
21161	21492	bl __aeabi_uidiv
21162		- ldr r3, [r6, #-1636]
	21493	+ ldr r3, [r4, #-1632]
21163	21494	add r0, r0, r3
21164	21495	uxth r0, r0
21165	21496	bl FtlSysBlkNumInit
21166		- ldr r0, [r6, #-1732]
21167		- uxth r0, r0
	21497	+ sub r3, r4, #1728
	21498	+ ldrh r0, [r3]
21168	21499	bl FtlFreeSysBlkQueueInit
21169		- ldrh r5, [r5]
21170		-.L3567:
21171		- ldrh r3, [r8]
21172		- cmp r3, r5
21173		- bls .L3566
21174		- mov r0, r5
21175		- mov r1, #1
21176		- bl FtlLowFormatEraseBlock
21177		- add r5, r5, #1
21178		- uxth r5, r5
21179		- add r0, r7, r0
21180		- uxth r7, r0
21181		- b .L3567
21182		-.L3566:
21183		- mov r5, #0
21184		- mov r6, r5
21185		-.L3569:
21186		- ldrh r1, [r9]
21187		- uxth r0, r5
21188		- ldr r10, .L3593
21189		- add r5, r5, #1
21190		- cmp r1, r0
21191		- sub r2, r10, #1728
21192		- bls .L3592
21193		- mov r1, #0
21194		- bl FtlLowFormatEraseBlock
21195		- add r0, r6, r0
21196		- uxth r6, r0
21197		- b .L3569
21198		-.L3592:
21199		- sub r5, r10, #1712
21200		- ldr ip, [r10, #-1724]
21201		- ldrh r8, [r2, #-8]
21202		- ldrh r1, [r5, #-14]
21203		- mov r0, ip
21204		- str ip, [sp, #8]
21205		- str r1, [r10, #-1544]
21206		- mov r1, r8
21207		- bl __aeabi_uidiv
21208		- movw r2, #1160
21209		- ubfx r3, r0, #5, #16
21210		- mov fp, r0
21211		- str r0, [r10, #-1284]
21212		- add r1, r3, #36
21213		- ldr r0, .L3593+20
21214		- str r5, [sp, #4]
21215		- str r3, [sp]
21216		- strh r1, [r0, r2] @ movhi
21217		- mov r1, #24
21218		- mul r1, r1, r8
21219		- mov r5, r0
21220		- ldr ip, [sp, #8]
21221		- cmp r6, r1
21222		- ble .L3571
21223		- rsb r0, r6, ip
21224		- mov r1, r8
21225		- str r2, [sp, #8]
21226		- bl __aeabi_uidiv
21227		- ldr r2, [sp, #8]
21228		- str r0, [r10, #-1284]
21229		- mov r0, r0, lsr #5
21230		- add r0, r0, #24
21231		- strh r0, [r5, r2] @ movhi
21232		-.L3571:
21233		- ldr r3, [r4, #-1872]
21234		- cmp r3, #1
21235		- bne .L3572
21236		- movw r2, #1160
21237		- mov r0, r6
21238		- ldrh r3, [r5, r2]
21239		- mov r1, r8
21240		- str r2, [sp, #12]
21241		- str r3, [sp, #8]
21242		- bl __aeabi_uidiv
21243		- ldr r3, [sp, #8]
21244		- ldr r2, [sp, #12]
21245		- uxtah r0, r3, r0
21246		- add r3, r3, r0, asr #2
21247		- strh r3, [r5, r2] @ movhi
21248		-.L3572:
21249		- ldrb r3, [r4, #-2744] @ zero_extendqisi2
21250		- cmp r3, #0
21251		- beq .L3573
21252		- movw r2, #1160
21253		- mov r0, r6
21254		- ldrh r3, [r5, r2]
21255		- mov r1, r8
21256		- str r2, [sp, #12]
21257		- str r3, [sp, #8]
21258		- bl __aeabi_uidiv
21259		- ldr r3, [sp, #8]
21260		- ldr r2, [sp, #12]
21261		- uxtah r0, r3, r0
21262		- add r3, r3, r0, asr #2
21263		- strh r3, [r5, r2] @ movhi
21264		-.L3573:
21265		- ldr ip, .L3593
21266		- sub r2, ip, #1664
21267		- ldrh r3, [r2, #-10]
21268		- cmp r3, #0
21269		- beq .L3575
21270		- movw r1, #1160
21271		- ldrh r0, [r5, r1]
21272		- add r0, r0, r3, lsr #1
21273		- strh r0, [r5, r1] @ movhi
21274		- mul r0, r8, r3
21275		- cmp r0, r6
21276		- strgt fp, [ip, #-1284]
21277		- addgt r3, r3, #32
21278		- ldrgt r0, [sp]
21279		- addgt r3, r0, r3
21280		- ldrgt r0, .L3593+20
21281		- strgth r3, [r0, r1] @ movhi
21282		-.L3575:
21283		- movw r3, #1160
21284		- ldr r10, .L3593+24
21285		- ldrh r1, [r5, r3]
21286		- ldr r3, [r4, #-1284]
21287		- rsb r3, r1, r3
21288		- mul r8, r8, r3
21289		- ldrh r3, [r2, #-4]
21290		- str r8, [r5, #1156]
21291		- mul r8, r3, r8
21292		- ldrh r3, [r10, #-14]
21293		- str r8, [r4, #-1284]
21294		- mul r8, r3, r8
21295		- str r8, [r4, #-2740]
21296		- bl FtlBbmTblFlush
	21500	+ ldrh r6, [r7, #-12]
	21501	+.L3487:
	21502	+ ldrh r3, [r7, #-10]
	21503	+ cmp r3, r6
	21504	+ bhi .L3488
	21505	+.L3486:
	21506	+ mov r6, #0
	21507	+ mov r8, r6
	21508	+.L3489:
	21509	+ ldrh r3, [r7, #-12]
	21510	+ uxth r0, r6
	21511	+ add r6, r6, #1
	21512	+ cmp r3, r0
	21513	+ bhi .L3490
	21514	+ ldrh r3, [r7, #-10]
21297	21515	ldr r2, [r4, #-1720]
21298		- add r1, r6, r7
21299		- ldrh r3, [r10, #-6]
	21516	+ ldrh r6, [r10, #-4]
	21517	+ str r3, [r4, #-1540]
	21518	+ mov r0, r2
	21519	+ str r2, [sp, #4]
	21520	+ mov r1, r6
	21521	+ bl __aeabi_uidiv
	21522	+ ldr r3, .L3510+16
	21523	+ ubfx r10, r0, #5, #16
	21524	+ add r1, r10, #36
	21525	+ mov fp, r0
	21526	+ str r0, [r4, #-1284]
	21527	+ strh r1, [r3] @ movhi
	21528	+ mov r1, #24
	21529	+ mul r1, r1, r6
	21530	+ mov r9, r3
	21531	+ cmp r8, r1
	21532	+ ble .L3491
	21533	+ ldr r2, [sp, #4]
	21534	+ mov r1, r6
	21535	+ sub r0, r2, r8
	21536	+ bl __aeabi_uidiv
	21537	+ str r0, [r4, #-1284]
	21538	+ lsr r0, r0, #5
	21539	+ add r0, r0, #24
	21540	+ strh r0, [r9] @ movhi
	21541	+.L3491:
	21542	+ ldr r2, [r4, #-1868]
	21543	+ cmp r2, #1
	21544	+ bne .L3492
	21545	+ ldrh r2, [r9]
	21546	+ mov r1, r6
	21547	+ mov r0, r8
	21548	+ str r2, [sp, #4]
	21549	+ bl __aeabi_uidiv
	21550	+ ldr r2, [sp, #4]
	21551	+ uxtah r0, r2, r0
	21552	+ add r2, r2, r0, asr #2
	21553	+ strh r2, [r9] @ movhi
	21554	+.L3492:
	21555	+ ldrb r2, [r4, #-2740] @ zero_extendqisi2
	21556	+ cmp r2, #0
	21557	+ beq .L3493
	21558	+ ldrh r2, [r9]
	21559	+ mov r1, r6
	21560	+ mov r0, r8
	21561	+ str r2, [sp, #4]
	21562	+ bl __aeabi_uidiv
	21563	+ ldr r2, [sp, #4]
	21564	+ uxtah r0, r2, r0
	21565	+ add r2, r2, r0, asr #2
	21566	+ strh r2, [r9] @ movhi
	21567	+.L3493:
	21568	+ ldr r1, .L3510+20
	21569	+ ldrh r2, [r1, #-8]
	21570	+ cmp r2, #0
	21571	+ beq .L3495
	21572	+ ldrh r0, [r9]
	21573	+ add r0, r0, r2, lsr #1
	21574	+ strh r0, [r9] @ movhi
	21575	+ mul r0, r6, r2
	21576	+ cmp r8, r0
	21577	+ addlt r2, r2, #32
	21578	+ strlt fp, [r4, #-1284]
	21579	+ addlt r2, r10, r2
	21580	+ strhlt r2, [r9] @ movhi
	21581	+.L3495:
	21582	+ ldrh r2, [r9]
	21583	+ ldr r3, [r4, #-1284]
	21584	+ sub r3, r3, r2
	21585	+ mul r6, r6, r3
	21586	+ ldrh r3, [r1, #-2]
	21587	+ str r6, [r4, #1148]
	21588	+ mul r6, r6, r3
	21589	+ ldr r3, .L3510+24
	21590	+ ldrh r3, [r3, #-12]
	21591	+ str r6, [r4, #-1284]
	21592	+ mul r6, r6, r3
	21593	+ str r6, [r4, #-2736]
	21594	+ bl FtlBbmTblFlush
	21595	+ ldr r3, .L3510+24
	21596	+ add r1, r5, r8
	21597	+ ldr r2, [r4, #-1716]
	21598	+ ldrh r3, [r3, #-4]
21300	21599	add r3, r3, r2, lsr #3
21301	21600	cmp r1, r3
21302		- bls .L3577
21303		- ldr r0, .L3593+28
21304		- mov r2, r2, lsr #5
	21601	+ bls .L3497
	21602	+ lsr r2, r2, #5
	21603	+ ldr r0, .L3510+28
21305	21604	bl printk
21306		-.L3577:
21307		- ldr r3, [sp, #4]
	21605	+.L3497:
	21606	+ ldrh r2, [r7, #-10]
21308	21607	mov r1, #0
21309		- ldr r0, [r4, #-1408]
21310		- mvn r7, #0
21311		- ldr r6, .L3593+32
21312		- ldrh r2, [r3, #-14]
21313		- sub fp, r6, #884
21314		- mov r10, r6
21315		- mov r2, r2, asl #1
	21608	+ ldr r5, .L3510+32
	21609	+ mvn r6, #0
	21610	+ ldr r0, [r4, #-1404]
	21611	+ lsl r2, r2, #1
21316	21612	bl ftl_memset
21317		- movw r2, #1164
21318		- strh r7, [r5, r2] @ movhi
21319	21613	mov r3, #0
21320		- ldr r2, .L3593+36
21321		- mov r1, #255
21322		- ldr r0, [r4, #-1396]
	21614	+ movw r2, #1156
	21615	+ strh r3, [r5, #2] @ movhi
	21616	+ sub r5, r5, #272
21323	21617	str r3, [r4, #1124]
21324		- strh r3, [r2, #2] @ movhi
21325		- ldrh r2, [r9]
21326		- strb r3, [r5, #1170]
21327		- strb r3, [r5, #1172]
21328		- mov r2, r2, lsr #3
21329		- strh r3, [r6, #2] @ movhi
	21618	+ mov r1, #255
	21619	+ strh r6, [r4, r2] @ movhi
	21620	+ strb r3, [r4, #1162]
	21621	+ ldrh r2, [r7, #-12]
	21622	+ mov r7, r5
	21623	+ strb r3, [r4, #1164]
	21624	+ strh r3, [r5, #2] @ movhi
21330	21625	strb r3, [r4, #890]
21331		- strh r3, [r6] @ movhi
	21626	+ strh r3, [r5] @ movhi
21332	21627	mov r3, #1
21333	21628	strb r3, [r4, #892]
	21629	+ lsr r2, r2, #3
	21630	+ ldr r3, .L3510+36
	21631	+ ldr r0, [r3, #32]
21334	21632	bl ftl_memset
21335		-.L3578:
21336		- ldr r9, .L3593
21337		- add r8, r9, #884
21338		- mov r0, r8
	21633	+.L3498:
	21634	+ mov r0, r7
21339	21635	bl make_superblock
21340	21636	ldrb r3, [r4, #891] @ zero_extendqisi2
21341	21637	cmp r3, #0
21342		- ldrh r3, [r6]
21343		- bne .L3579
21344		- ldr r2, [fp, #-1408]
21345		- mov r3, r3, asl #1
21346		- strh r7, [r2, r3] @ movhi
21347		- ldrh r3, [r10]
	21638	+ ldrh r3, [r5]
	21639	+ bne .L3499
	21640	+ ldr r2, [r4, #-1404]
	21641	+ lsl r3, r3, #1
	21642	+ strh r6, [r2, r3] @ movhi
	21643	+ ldrh r3, [r5]
21348	21644	add r3, r3, #1
21349		- strh r3, [r10] @ movhi
21350		- b .L3578
21351		-.L3579:
21352		- ldr r2, [r9, #-1616]
21353		- mov r3, r3, asl #1
21354		- ldrh r1, [r8, #4]
21355		- mvn fp, #0
21356		- str r2, [r9, #896]
	21645	+ strh r3, [r5] @ movhi
	21646	+ b .L3498
	21647	+.L3483:
	21648	+ ldr ip, [r4, #-1452]
	21649	+ mvn r1, r3
	21650	+ orr r1, r3, r1, lsl #16
	21651	+ str r1, [ip, r3, lsl #2]
	21652	+ ldr r1, [r4, #-1448]
	21653	+ str r0, [r1, r3, lsl #2]
	21654	+ b .L3482
	21655	+.L3485:
	21656	+ mov r0, r6
	21657	+ mov r1, #1
	21658	+ bl FtlLowFormatEraseBlock
	21659	+ add r6, r6, #1
	21660	+ add r5, r5, r0
	21661	+ uxth r5, r5
	21662	+ uxth r6, r6
	21663	+ b .L3484
	21664	+.L3488:
	21665	+ mov r0, r6
	21666	+ mov r1, #1
	21667	+ bl FtlLowFormatEraseBlock
	21668	+ add r6, r6, #1
	21669	+ add r5, r5, r0
	21670	+ uxth r5, r5
	21671	+ uxth r6, r6
	21672	+ b .L3487
	21673	+.L3490:
	21674	+ mov r1, #0
	21675	+ bl FtlLowFormatEraseBlock
	21676	+ add r8, r8, r0
	21677	+ uxth r8, r8
	21678	+ b .L3489
	21679	+.L3499:
	21680	+ ldr r2, [r4, #-1612]
	21681	+ lsl r3, r3, #1
	21682	+ ldrh r1, [r5, #4]
	21683	+ mvn r6, #0
	21684	+ str r2, [r4, #896]
21357	21685	add r2, r2, #1
21358		- str r2, [r9, #-1616]
21359		- ldr r2, [r9, #-1408]
	21686	+ str r2, [r4, #-1612]
	21687	+ ldr r2, [r4, #-1404]
21360	21688	strh r1, [r2, r3] @ movhi
21361		- add r2, r9, #932
21362		- mov r3, #0
21363		- strb r3, [r9, #938]
21364		- strh r3, [r2, #2] @ movhi
21365		- mov r7, r2
21366		- ldrh r3, [r8]
21367		- mov r10, r2
21368		- add r3, r3, #1
21369		- strh r3, [r2] @ movhi
21370		- mov r3, #1
21371		- strb r3, [r9, #940]
21372		-.L3580:
21373		- ldr r6, .L3593
21374		- add r8, r6, #932
21375		- mov r0, r8
	21689	+ mov r2, #0
	21690	+ ldr r3, .L3510+40
	21691	+ strb r2, [r4, #938]
	21692	+ strh r2, [r3, #2] @ movhi
	21693	+ mov r7, r3
	21694	+ ldrh r2, [r5]
	21695	+ mov r5, r3
	21696	+ add r2, r2, #1
	21697	+ strh r2, [r3] @ movhi
	21698	+ mov r2, #1
	21699	+ strb r2, [r4, #940]
	21700	+.L3500:
	21701	+ mov r0, r7
21376	21702	bl make_superblock
21377	21703	ldrb r3, [r4, #939] @ zero_extendqisi2
21378	21704	cmp r3, #0
21379		- ldrh r3, [r7]
21380		- bne .L3581
21381		- ldr r2, [r9, #-1408]
21382		- mov r3, r3, asl #1
21383		- strh fp, [r2, r3] @ movhi
21384		- ldrh r3, [r10]
	21705	+ ldrh r3, [r5]
	21706	+ bne .L3501
	21707	+ ldr r2, [r4, #-1404]
	21708	+ lsl r3, r3, #1
	21709	+ strh r6, [r2, r3] @ movhi
	21710	+ ldrh r3, [r5]
21385	21711	add r3, r3, #1
21386		- strh r3, [r10] @ movhi
21387		- b .L3580
21388		-.L3581:
21389		- ldr r2, [r6, #-1616]
21390		- mov r3, r3, asl #1
21391		- ldrh r1, [r8, #4]
21392		- mvn r4, #0
21393		- str r2, [r6, #944]
	21712	+ strh r3, [r5] @ movhi
	21713	+ b .L3500
	21714	+.L3501:
	21715	+ ldr r2, [r4, #-1612]
	21716	+ lsl r3, r3, #1
	21717	+ ldrh r1, [r5, #4]
	21718	+ mvn r6, #0
	21719	+ ldr r5, .L3510+44
	21720	+ str r2, [r4, #944]
21394	21721	add r2, r2, #1
21395		- str r2, [r6, #-1616]
21396		- ldr r2, [r6, #-1408]
	21722	+ str r2, [r4, #-1612]
	21723	+ ldr r2, [r4, #-1404]
21397	21724	strh r1, [r2, r3] @ movhi
21398		- add r3, r6, #980
21399		- strh r4, [r3] @ movhi
	21725	+ strh r6, [r5], #148 @ movhi
21400	21726	bl FtlFreeSysBlkQueueOut
21401		- ldr r3, .L3593+40
21402		- movw r2, #1128
21403		- strh r4, [r3, #4] @ movhi
21404		- strh r0, [r6, r2] @ movhi
21405		- mov r2, #0
21406		- strh r2, [r3, #2] @ movhi
21407		- ldr r2, [r5, #1156]
21408		- strh r2, [r3, #6] @ movhi
21409		- ldr r3, [r6, #-1616]
21410		- str r3, [r6, #1136]
	21727	+ movw r3, #1128
	21728	+ strh r6, [r5, #4] @ movhi
	21729	+ strh r0, [r4, r3] @ movhi
	21730	+ mov r3, #0
	21731	+ strh r3, [r5, #2] @ movhi
	21732	+ ldr r3, [r4, #1148]
	21733	+ strh r3, [r5, #6] @ movhi
	21734	+ ldr r3, [r4, #-1612]
	21735	+ str r3, [r4, #1136]
21411	21736	add r3, r3, #1
21412		- str r3, [r6, #-1616]
	21737	+ str r3, [r4, #-1612]
21413	21738	bl FtlVpcTblFlush
21414	21739	bl FtlSysBlkInit
21415	21740	cmp r0, #0
21416		- ldreq r3, .L3593+44
	21741	+ ldreq r3, .L3510+48
21417	21742	moveq r2, #1
21418		- streq r2, [r3, #3444]
21419		-.L3560:
	21743	+ streq r2, [r3, #3440]
	21744	+.L3480:
21420	21745	mov r0, #0
21421		- add sp, sp, #20
	21746	+ add sp, sp, #12
21422	21747	@ sp needed
21423		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
21424		-.L3594:
	21748	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	21749	+.L3511:
21425	21750	.align 2
21426		-.L3593:
	21751	+.L3510:
21427	21752	.word .LANCHOR2
21428		- .word .LANCHOR2-1662
21429	21753	.word 168778952
	21754	+ .word .LANCHOR2-1660
21430	21755	.word .LANCHOR2-1728
21431		- .word .LANCHOR2-1726
21432		- .word .LANCHOR4
	21756	+ .word .LANCHOR2+1152
	21757	+ .word .LANCHOR2-1664
21433	21758	.word .LANCHOR2-1648
21434	21759	.word .LC162
21435		- .word .LANCHOR2+884
21436		- .word .LANCHOR4+1164
21437		- .word .LANCHOR2+1128
	21760	+ .word .LANCHOR2+1156
	21761	+ .word .LANCHOR0
	21762	+ .word .LANCHOR2+932
	21763	+ .word .LANCHOR2+980
21438	21764	.word .LANCHOR1
21439	21765	.fnend
21440	21766	.size FtlLowFormat, .-FtlLowFormat
21441	21767	.align 2
21442	21768	.global FtlReInitForSDUpdata
	21769	+ .syntax unified
	21770	+ .arm
	21771	+ .fpu softvfp
21443	21772	.type FtlReInitForSDUpdata, %function
21444	21773	FtlReInitForSDUpdata:
21445	21774	.fnstart
21446	21775	@ args = 0, pretend = 0, frame = 16
21447	21776	@ frame_needed = 0, uses_anonymous_args = 0
21448		- stmfd sp!, {r0, r1, r2, r3, r4, lr}
21449		- .save {r4, lr}
21450		- .pad #16
21451		- ldr r4, .L3624
21452		- ldrb r3, [r4, #-2744] @ zero_extendqisi2
	21777	+ push {r4, r5, lr}
	21778	+ .save {r4, r5, lr}
	21779	+ .pad #20
	21780	+ sub sp, sp, #20
	21781	+ ldr r4, .L3548
	21782	+ ldrb r3, [r4, #-2740] @ zero_extendqisi2
21453	21783	cmp r3, #0
21454		- beq .L3596
21455		-.L3598:
21456		- mov r0, #0
21457		- b .L3597
21458		-.L3596:
21459		- ldr r3, .L3624+4
	21784	+ beq .L3513
	21785	+.L3515:
	21786	+ mov r5, #0
	21787	+.L3512:
	21788	+ mov r0, r5
	21789	+ add sp, sp, #20
	21790	+ @ sp needed
	21791	+ pop {r4, r5, pc}
	21792	+.L3513:
	21793	+ ldr r3, .L3548+4
21460	21794	ldr r0, [r3]
21461	21795	bl FlashInit
21462		- cmp r0, #0
21463		- bne .L3598
	21796	+ subs r5, r0, #0
	21797	+ bne .L3515
21464	21798	bl FlashLoadFactorBbt
21465	21799	cmp r0, #0
21466		- beq .L3599
	21800	+ beq .L3516
21467	21801	bl FlashMakeFactorBbt
21468		-.L3599:
21469		- ldr r0, [r4, #-1776]
	21802	+.L3516:
	21803	+ ldr r0, [r4, #-1772]
21470	21804	bl FlashReadIdbDataRaw
21471	21805	cmp r0, #0
21472		- beq .L3600
21473		- mov r1, #0
	21806	+ beq .L3517
21474	21807	mov r2, #16
	21808	+ mov r1, #0
21475	21809	mov r0, sp
21476	21810	bl FlashReadFacBbtData
	21811	+ ldr r1, [sp]
21477	21812	mov r3, #0
21478	21813	mov r2, r3
21479		- mov ip, #1
21480		- ldr r1, [sp]
21481		-.L3601:
21482		- ands lr, r1, ip, asl r2
21483		- add r0, r3, #1
	21814	+ mov r0, #1
	21815	+.L3519:
	21816	+ ands ip, r1, r0, lsl r2
21484	21817	add r2, r2, #1
21485		- movne r3, r0
	21818	+ addne r3, r3, #1
21486	21819	cmp r2, #16
21487		- bne .L3601
	21820	+ bne .L3519
21488	21821	cmp r3, #6
21489		- ldrls r3, .L3624+8
21490		- bls .L3620
	21822	+ ldrls r3, .L3548+8
	21823	+ bls .L3545
21491	21824	mov r2, #0
21492		- mov ip, #1
21493		-.L3604:
21494		- ands lr, r1, ip, asl r2
21495		- add r0, r3, #1
	21825	+ mov r0, #1
	21826	+.L3523:
	21827	+ ands ip, r1, r0, lsl r2
21496	21828	add r2, r2, #1
21497		- movne r3, r0
	21829	+ addne r3, r3, #1
21498	21830	cmp r2, #24
21499		- bne .L3604
	21831	+ bne .L3523
21500	21832	cmp r3, #17
21501		- ldr r3, .L3624+8
	21833	+ ldr r3, .L3548+8
21502	21834	movhi r2, #36
21503		-.L3620:
21504		- strb r2, [r3, #1]
21505		- ldr r3, .L3624+8
21506		- ldrb r2, [r3, #1] @ zero_extendqisi2
21507		- ldr r3, .L3624+12
	21835	+.L3545:
	21836	+ strb r2, [r3, #37]
	21837	+ ldr r3, .L3548+8
	21838	+ ldrb r2, [r3, #37] @ zero_extendqisi2
	21839	+ ldr r3, .L3548+12
21508	21840	strh r2, [r3, #26] @ movhi
21509		-.L3600:
21510		- ldr r1, .L3624+16
21511		- ldr r0, .L3624+20
	21841	+.L3517:
	21842	+ ldr r1, .L3548+16
	21843	+ ldr r0, .L3548+20
21512	21844	bl printk
21513		- ldr r0, .L3624+12
	21845	+ ldr r0, .L3548+12
21514	21846	bl FtlConstantsInit
21515	21847	bl FtlVariablesInit
21516		- ldr r0, [r4, #-1732]
	21848	+ ldr r0, [r4, #-1728]
21517	21849	mov r4, #1
21518	21850	uxth r0, r0
21519	21851	bl FtlFreeSysBlkQueueInit
21520		-.L3606:
	21852	+.L3525:
21521	21853	bl FtlLoadBbt
21522	21854	cmp r0, #0
21523		- beq .L3607
21524		-.L3622:
	21855	+ beq .L3526
	21856	+.L3547:
21525	21857	bl FtlLowFormat
21526	21858	cmp r4, #3
21527		- addls r4, r4, #1
21528		- bls .L3606
21529		-.L3623:
21530		- mvn r0, #0
21531		- b .L3597
21532		-.L3607:
	21859	+ mvnhi r5, #0
	21860	+ bhi .L3512
	21861	+.L3527:
	21862	+ add r4, r4, #1
	21863	+ b .L3525
	21864	+.L3526:
21533	21865	bl FtlSysBlkInit
21534	21866	cmp r0, #0
21535		- bne .L3622
21536		- ldr r3, .L3624+24
	21867	+ bne .L3547
	21868	+ ldr r3, .L3548+24
21537	21869	mov r2, #1
21538		- str r2, [r3, #3444]
21539		-.L3597:
21540		- add sp, sp, #16
21541		- @ sp needed
21542		- ldmfd sp!, {r4, pc}
21543		-.L3625:
	21870	+ str r2, [r3, #3440]
	21871	+ b .L3512
	21872	+.L3549:
21544	21873	.align 2
21545		-.L3624:
	21874	+.L3548:
21546	21875	.word .LANCHOR2
21547	21876	.word RK29_NANDC_REG_BASE
21548	21877	.word .LANCHOR0
21549		- .word .LANCHOR2-2772
	21878	+ .word .LANCHOR2-2768
21550	21879	.word .LC145
21551		- .word .LC48
	21880	+ .word .LC49
21552	21881	.word .LANCHOR1
21553	21882	.fnend
21554	21883	.size FtlReInitForSDUpdata, .-FtlReInitForSDUpdata
21555	21884	.align 2
21556	21885	.global Ftl_gc_temp_data_write_back
	21886	+ .syntax unified
	21887	+ .arm
	21888	+ .fpu softvfp
21557	21889	.type Ftl_gc_temp_data_write_back, %function
21558	21890	Ftl_gc_temp_data_write_back:
21559	21891	.fnstart
21560	21892	@ args = 0, pretend = 0, frame = 0
21561	21893	@ frame_needed = 0, uses_anonymous_args = 0
21562		- stmfd sp!, {r4, r5, r6, r7, r8, lr}
21563		- .save {r4, r5, r6, r7, r8, lr}
21564		- ldr r4, .L3643
	21894	+ push {r4, r5, r6, lr}
	21895	+ .save {r4, r5, r6, lr}
	21896	+ ldr r4, .L3566
21565	21897	ldr r3, [r4, #-1280]
21566	21898	cmp r3, #0
21567		- beq .L3627
21568		-.L3630:
	21899	+ beq .L3551
	21900	+.L3554:
21569	21901	mov r0, #0
21570		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
21571		-.L3627:
21572		- ldrb r3, [r4, #-2744] @ zero_extendqisi2
21573		- ldr r6, .L3643+4
	21902	+ pop {r4, r5, r6, pc}
	21903	+.L3551:
	21904	+ ldrb r3, [r4, #-2740] @ zero_extendqisi2
21574	21905	cmp r3, #0
21575		- beq .L3629
21576		- ldr r3, [r6, #1740]
	21906	+ beq .L3553
	21907	+ ldr r3, [r4, #1732]
21577	21908	tst r3, #1
21578		- beq .L3629
	21909	+ beq .L3553
21579	21910	add r3, r4, #980
21580	21911	ldrh r3, [r3, #4]
21581	21912	cmp r3, #0
21582		- bne .L3630
21583		-.L3629:
21584		- mov r2, #0
21585		- ldr r0, [r4, #-1500]
21586		- ldr r1, [r6, #1740]
21587		- mov r3, r2
	21913	+ bne .L3554
	21914	+.L3553:
	21915	+ mov r3, #0
	21916	+ mov r5, #0
	21917	+ mov r6, #36
	21918	+ mov r2, r3
	21919	+ ldr r1, [r4, #1732]
	21920	+ ldr r0, [r4, #-1496]
21588	21921	bl FlashProgPages
21589		- mov r7, #0
21590		- mov r8, #36
21591		-.L3631:
21592		- ldr r1, [r6, #1740]
21593		- uxth r3, r7
21594		- ldr r5, .L3643+4
	21922	+.L3555:
	21923	+ ldr r1, [r4, #1732]
	21924	+ uxth r3, r5
21595	21925	cmp r3, r1
21596		- bcs .L3642
21597		- mul r3, r8, r3
21598		- ldr r0, [r4, #-1500]
21599		- ldr r2, .L3643
21600		- add r7, r7, #1
21601		- add r1, r0, r3
21602		- ldr lr, [r0, r3]
21603		- ldr ip, [r1, #12]
21604		- cmn lr, #1
21605		- bne .L3632
21606		- add r0, r2, #980
21607		- ldr ip, [r2, #-1408]
21608		- mov r4, #0
21609		- ldrh r1, [r0]
21610		- mov r1, r1, asl #1
21611		- strh r4, [ip, r1] @ movhi
21612		- ldr r2, [r2, #-1500]
21613		- ldr r1, [r5, #1308]
	21926	+ bcc .L3557
	21927	+ ldr r0, [r4, #-1496]
	21928	+ bl FtlGcBufFree
	21929	+ mov r3, #0
	21930	+ str r3, [r4, #1732]
	21931	+ ldr r3, .L3566+4
	21932	+ ldrh r3, [r3, #4]
	21933	+ cmp r3, #0
	21934	+ bne .L3554
	21935	+ mov r0, #1
	21936	+ bl FtlGcFreeTempBlock
	21937	+ b .L3565
	21938	+.L3557:
	21939	+ mul r3, r6, r3
	21940	+ ldr r2, [r4, #-1496]
	21941	+ add r5, r5, #1
	21942	+ ldr ip, [r2, r3]
	21943	+ add r1, r2, r3
	21944	+ ldr r0, [r1, #12]
	21945	+ cmn ip, #1
	21946	+ bne .L3556
	21947	+ ldr r1, .L3566+4
	21948	+ mov lr, #0
	21949	+ ldr r0, [r4, #-1404]
	21950	+ ldrh r2, [r1]
	21951	+ lsl r2, r2, #1
	21952	+ strh lr, [r0, r2] @ movhi
	21953	+ ldr r2, [r4, #1300]
	21954	+ strh ip, [r1] @ movhi
	21955	+ add r2, r2, #1
	21956	+ str r2, [r4, #1300]
	21957	+ ldr r2, [r4, #-1496]
21614	21958	add r3, r2, r3
21615		- strh lr, [r0] @ movhi
21616		- add r1, r1, #1
21617		- str r1, [r5, #1308]
21618	21959	ldr r0, [r3, #4]
21619	21960	ubfx r0, r0, #10, #16
21620	21961	bl FtlBbmMapBadBlock
21621	21962	bl FtlBbmTblFlush
21622	21963	bl FtlGcPageVarInit
21623		- b .L3641
21624		-.L3632:
21625		- ldr r0, [ip, #12]
	21964	+.L3565:
	21965	+ mov r0, #1
	21966	+ pop {r4, r5, r6, pc}
	21967	+.L3556:
	21968	+ ldr r2, [r0, #8]
21626	21969	ldr r1, [r1, #4]
21627		- ldr r2, [ip, #8]
	21970	+ ldr r0, [r0, #12]
21628	21971	bl FtlGcUpdatePage
21629		- b .L3631
21630		-.L3642:
21631		- ldr r0, [r4, #-1500]
21632		- bl FtlGcBufFree
21633		- mov r3, #0
21634		- str r3, [r5, #1740]
21635		- ldr r3, .L3643+8
21636		- ldrh r3, [r3, #4]
21637		- cmp r3, #0
21638		- bne .L3630
21639		- mov r0, #1
21640		- bl FtlGcFreeTempBlock
21641		-.L3641:
21642		- mov r0, #1
21643		- ldmfd sp!, {r4, r5, r6, r7, r8, pc}
21644		-.L3644:
	21972	+ b .L3555
	21973	+.L3567:
21645	21974	.align 2
21646		-.L3643:
	21975	+.L3566:
21647	21976	.word .LANCHOR2
21648		- .word .LANCHOR4
21649	21977	.word .LANCHOR2+980
21650	21978	.fnend
21651	21979	.size Ftl_gc_temp_data_write_back, .-Ftl_gc_temp_data_write_back
21652	21980	.align 2
21653	21981	.global Ftl_get_new_temp_ppa
	21982	+ .syntax unified
	21983	+ .arm
	21984	+ .fpu softvfp
21654	21985	.type Ftl_get_new_temp_ppa, %function
21655	21986	Ftl_get_new_temp_ppa:
21656	21987	.fnstart
21657	21988	@ args = 0, pretend = 0, frame = 0
21658	21989	@ frame_needed = 0, uses_anonymous_args = 0
21659		- ldr r3, .L3649
	21990	+ ldr r3, .L3575
21660	21991	movw r2, #65535
21661		- stmfd sp!, {r4, lr}
21662		- .save {r4, lr}
21663	21992	ldrh r1, [r3]
21664	21993	cmp r1, r2
21665		- beq .L3646
	21994	+ beq .L3569
21666	21995	ldrh r3, [r3, #4]
21667	21996	cmp r3, #0
21668		- bne .L3647
21669		-.L3646:
	21997	+ ldrne r0, .L3575
	21998	+ bne .L3574
	21999	+.L3569:
	22000	+ push {r4, r5, r6, lr}
	22001	+ .save {r4, r5, r6, lr}
	22002	+ mov r4, #0
	22003	+ ldr r5, .L3575+4
21670	22004	bl FtlCacheWriteBack
21671	22005	mov r0, #0
21672	22006	bl FtlGcFreeTempBlock
21673		- ldr r0, .L3649+4
21674		- mov r4, #0
21675		- add r0, r0, #980
21676		- strb r4, [r0, #8]
	22007	+ add r0, r5, #980
	22008	+ strb r4, [r5, #988]
21677	22009	bl allocate_data_superblock
21678		- ldr r3, .L3649+8
21679		- movw r2, #1764
21680		- strh r4, [r3, r2] @ movhi
21681		- movw r2, #1766
21682		- strh r4, [r3, r2] @ movhi
	22010	+ movw r3, #1756
	22011	+ strh r4, [r5, r3] @ movhi
	22012	+ movw r3, #1758
	22013	+ strh r4, [r5, r3] @ movhi
21683	22014	bl l2p_flush
21684	22015	mov r0, r4
21685	22016	bl FtlEctTblFlush
21686	22017	bl FtlVpcTblFlush
21687		-.L3647:
21688		- ldr r0, .L3649
21689		- ldmfd sp!, {r4, lr}
	22018	+ pop {r4, r5, r6, lr}
	22019	+ ldr r0, .L3575
	22020	+.L3574:
21690	22021	b get_new_active_ppa
21691		-.L3650:
	22022	+.L3576:
21692	22023	.align 2
21693		-.L3649:
	22024	+.L3575:
21694	22025	.word .LANCHOR2+980
21695	22026	.word .LANCHOR2
21696		- .word .LANCHOR4
21697	22027	.fnend
21698	22028	.size Ftl_get_new_temp_ppa, .-Ftl_get_new_temp_ppa
21699	22029	.align 2
21700	22030	.global ftl_read
	22031	+ .syntax unified
	22032	+ .arm
	22033	+ .fpu softvfp
21701	22034	.type ftl_read, %function
21702	22035	ftl_read:
21703	22036	.fnstart
21704	22037	@ args = 0, pretend = 0, frame = 56
21705	22038	@ frame_needed = 0, uses_anonymous_args = 0
21706		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	22039	+ ldr ip, .L3621
	22040	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
21707	22041	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
21708		- mov r4, r1
21709		- ldr r1, .L3699
21710	22042	.pad #84
21711	22043	sub sp, sp, #84
21712		- ldr r1, [r1, #3444]
21713		- cmp r1, #1
21714		- bne .L3676
	22044	+ ldr ip, [ip, #3440]
	22045	+ cmp ip, #1
	22046	+ bne .L3601
21715	22047	cmp r0, #16
21716	22048	mov r8, r3
21717		- mov r9, r2
21718		- bne .L3653
21719		- mov r1, r2
21720		- add r0, r4, #256
	22049	+ str r2, [sp, #28]
	22050	+ mov r5, r1
	22051	+ bne .L3579
21721	22052	mov r2, r3
	22053	+ ldr r1, [sp, #28]
	22054	+ add r0, r5, #256
21722	22055	bl FtlVendorPartRead
21723		- b .L3652
21724		-.L3653:
21725		- ldr r5, .L3699+4
21726		- ldr r3, [r5, #-2740]
	22056	+ mov r10, r0
	22057	+.L3577:
	22058	+ mov r0, r10
	22059	+ add sp, sp, #84
	22060	+ @ sp needed
	22061	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	22062	+.L3579:
	22063	+ ldr r4, .L3621+4
	22064	+ ldr r2, [sp, #28]
	22065	+ ldr r3, [r4, #-2736]
21727	22066	cmp r2, r3
21728		- cmpls r4, r3
21729		- bcs .L3676
21730		- add r2, r4, r2
21731		- str r2, [sp, #40]
21732		- cmp r2, r3
21733		- bhi .L3676
21734		- sub r3, r5, #1648
21735		- mov r0, r4
21736		- ldrh r6, [r3, #-14]
	22067	+ cmpls r1, r3
	22068	+ bcs .L3601
	22069	+ add r2, r1, r2
	22070	+ cmp r3, r2
	22071	+ str r2, [sp, #44]
	22072	+ bcc .L3601
	22073	+ sub r3, r4, #1648
	22074	+ mov r0, r5
	22075	+ ldrh r6, [r3, #-12]
21737	22076	mov r1, r6
21738	22077	bl __aeabi_uidiv
	22078	+ ldr r3, [sp, #44]
21739	22079	mov r1, r6
21740		- ldr r3, [sp, #40]
21741		- str r0, [sp, #32]
	22080	+ str r0, [sp, #36]
21742	22081	sub r0, r3, #1
21743	22082	bl __aeabi_uidiv
21744		- ldr r2, .L3699+8
21745		- ldr r3, [sp, #32]
21746		- str r0, [sp, #36]
21747		- rsb r3, r3, #1
21748		- ldr r1, [sp, #36]
21749		- add r3, r3, r0
21750		- str r3, [sp, #28]
21751		- ldr r3, [r2, #1728]
21752		- ldr r0, [sp, #32]
21753		- add r3, r9, r3
21754		- str r3, [r2, #1728]
21755		- ldr r3, [r5, #-1588]
	22083	+ ldr r3, [sp, #36]
	22084	+ mov r1, r0
21756	22085	ldr r2, [sp, #28]
21757		- add r3, r2, r3
21758		- str r3, [r5, #-1588]
	22086	+ str r0, [sp, #40]
	22087	+ rsb r3, r3, #1
	22088	+ add r3, r3, r0
	22089	+ ldr r0, [sp, #36]
	22090	+ str r3, [sp, #32]
	22091	+ ldr r3, [r4, #1720]
	22092	+ add r3, r3, r2
	22093	+ ldr r2, [sp, #32]
	22094	+ str r3, [r4, #1720]
	22095	+ ldr r3, [r4, #-1584]
	22096	+ add r3, r3, r2
	22097	+ str r3, [r4, #-1584]
21759	22098	bl FtlCacheMetchLpa
21760	22099	cmp r0, #0
21761		- beq .L3654
	22100	+ beq .L3580
21762	22101	bl FtlCacheWriteBack
21763		-.L3654:
21764		- ldr r6, [sp, #32]
	22102	+.L3580:
	22103	+ ldr r6, [sp, #36]
21765	22104	mov r3, #0
21766		- ldr r5, .L3699+4
	22105	+ ldr r4, .L3621+4
21767	22106	mov r7, r3
21768		- str r3, [sp, #24]
21769		- str r3, [sp, #48]
	22107	+ mov r10, r3
21770	22108	str r3, [sp, #52]
21771		-.L3655:
21772		- ldr r3, [sp, #28]
	22109	+ str r3, [sp, #48]
	22110	+.L3581:
	22111	+ ldr r3, [sp, #32]
21773	22112	cmp r3, #0
21774		- beq .L3698
21775		- mov r0, r6
21776		- add r1, sp, #76
	22113	+ bne .L3598
	22114	+ ldr r3, .L3621+8
	22115	+ ldrh r3, [r3, #-2]
	22116	+ cmp r3, #0
	22117	+ beq .L3577
	22118	+ mov r1, #1
	22119	+ ldr r0, [sp, #32]
	22120	+ bl ftl_do_gc
	22121	+ b .L3577
	22122	+.L3598:
21777	22123	mov r2, #0
	22124	+ add r1, sp, #76
	22125	+ mov r0, r6
21778	22126	bl log2phys
21779	22127	ldr r3, [sp, #76]
21780	22128	cmn r3, #1
21781		- bne .L3694
21782		- mov r10, #0
21783		-.L3656:
21784		- ldr r3, .L3699+12
21785		- ldrh r0, [r3]
21786		- cmp r10, r0
21787		- bcs .L3660
21788		- mla r0, r0, r6, r10
21789		- ldr r2, [sp, #40]
21790		- cmp r0, r4
21791		- movcs r3, #1
21792		- movcc r3, #0
21793		- cmp r0, r2
21794		- movcs r3, #0
21795		- cmp r3, #0
21796		- beq .L3658
21797		- rsb r0, r4, r0
21798		- mov r1, #0
21799		- mov r2, #512
21800		- add r0, r8, r0, asl #9
21801		- bl ftl_memset
21802		-.L3658:
21803		- add r10, r10, #1
21804		- b .L3656
21805		-.L3694:
21806		- ldr r2, [r5, #-1504]
21807		- mov r10, #36
21808		- mla r10, r10, r7, r2
21809		- str r3, [r10, #4]
21810		- ldr r3, [sp, #32]
21811		- cmp r6, r3
21812		- bne .L3661
21813		- ldr r3, [r5, #-1456]
21814		- mov r0, r4
21815		- str r3, [r10, #8]
21816		- ldr r3, .L3699+12
21817		- ldrh fp, [r3]
21818		- mov r1, fp
21819		- bl __aeabi_uidivmod
21820		- rsb r3, r1, fp
21821		- str r1, [sp, #56]
21822		- cmp r3, r9
21823		- movcs r3, r9
21824		- cmp r3, fp
21825		- str r3, [sp, #48]
21826		- streq r8, [r10, #8]
21827		- b .L3662
21828		-.L3661:
	22129	+ moveq r9, #0
	22130	+ beq .L3583
	22131	+ ldr r2, [r4, #-1500]
	22132	+ mov r9, #36
	22133	+ mla r9, r9, r7, r2
	22134	+ str r3, [r9, #4]
21829	22135	ldr r3, [sp, #36]
21830	22136	cmp r6, r3
21831		- bne .L3663
21832		- ldr r3, [r5, #-1452]
21833		- ldr r1, [sp, #40]
21834		- str r3, [r10, #8]
21835		- ldr r3, .L3699+12
21836		- ldrh r2, [r3]
21837		- mul r3, r2, r6
21838		- rsb r1, r3, r1
21839		- str r1, [sp, #24]
21840		- cmp r1, r2
21841		- bne .L3662
21842		- b .L3696
21843		-.L3663:
21844		- ldr r3, .L3699+12
21845		- ldrh r3, [r3]
21846		- mul r3, r3, r6
21847		-.L3696:
21848		- rsb r3, r4, r3
21849		- add r3, r8, r3, asl #9
21850		- str r3, [r10, #8]
21851		-.L3662:
21852		- ldr r3, .L3699+16
21853		- ldr r2, [r5, #-1440]
21854		- str r6, [r10, #16]
21855		- ldrh r3, [r3]
21856		- mul r3, r3, r7
	22137	+ bne .L3587
	22138	+ ldr r3, [r4, #-1452]
	22139	+ mov r0, r5
	22140	+ str r3, [r9, #8]
	22141	+ ldr r3, .L3621+12
	22142	+ ldrh fp, [r3, #-12]
	22143	+ mov r1, fp
	22144	+ bl __aeabi_uidivmod
	22145	+ ldr r2, [sp, #28]
	22146	+ sub r3, fp, r1
	22147	+ str r1, [sp, #56]
	22148	+ cmp r2, r3
	22149	+ movcc r3, r2
	22150	+ cmp r3, fp
	22151	+ str r3, [sp, #48]
	22152	+ streq r8, [r9, #8]
	22153	+.L3588:
	22154	+ ldr r3, .L3621+12
	22155	+ ldr r2, [r4, #-1436]
	22156	+ str r6, [r9, #16]
	22157	+ ldrh r3, [r3, #-6]
	22158	+ mul r3, r7, r3
21857	22159	add r7, r7, #1
21858	22160	bic r3, r3, #3
21859	22161	add r3, r2, r3
21860		- str r3, [r10, #12]
21861		-.L3660:
21862		- ldr r3, [sp, #28]
	22162	+ str r3, [r9, #12]
	22163	+ b .L3586
	22164	+.L3585:
	22165	+ mla r0, r0, r6, r9
	22166	+ ldr r2, [sp, #44]
	22167	+ cmp r5, r0
	22168	+ movls r3, #1
	22169	+ movhi r3, #0
	22170	+ cmp r2, r0
	22171	+ movls r3, #0
	22172	+ cmp r3, #0
	22173	+ beq .L3584
	22174	+ sub r0, r0, r5
	22175	+ mov r2, #512
	22176	+ mov r1, #0
	22177	+ add r0, r8, r0, lsl #9
	22178	+ bl ftl_memset
	22179	+.L3584:
	22180	+ add r9, r9, #1
	22181	+.L3583:
	22182	+ ldr r3, .L3621+16
	22183	+ ldrh r0, [r3]
	22184	+ cmp r9, r0
	22185	+ bcc .L3585
	22186	+.L3586:
	22187	+ ldr r3, [sp, #32]
21863	22188	add r6, r6, #1
21864	22189	subs r3, r3, #1
21865		- str r3, [sp, #28]
21866		- beq .L3664
21867		- ldr r3, .L3699+20
	22190	+ str r3, [sp, #32]
	22191	+ beq .L3590
	22192	+ ldr r3, .L3621+20
21868	22193	ldrh r3, [r3]
21869		- cmp r7, r3, asl #3
21870		- bne .L3655
21871		-.L3664:
	22194	+ cmp r7, r3, lsl #3
	22195	+ bne .L3581
	22196	+.L3590:
21872	22197	cmp r7, #0
21873		- beq .L3655
21874		- ldr r0, [r5, #-1504]
21875		- mov r1, r7
	22198	+ beq .L3581
21876	22199	mov r2, #0
21877		- ldr fp, .L3699+8
	22200	+ mov r1, r7
	22201	+ ldr r0, [r4, #-1500]
	22202	+ mov fp, #0
21878	22203	bl FlashReadPages
	22204	+ ldr r3, [sp, #52]
	22205	+ lsl r3, r3, #9
	22206	+ str r3, [sp, #68]
21879	22207	ldr r3, [sp, #56]
21880		- mov r3, r3, asl #9
	22208	+ lsl r3, r3, #9
21881	22209	str r3, [sp, #60]
21882	22210	ldr r3, [sp, #48]
21883		- mov r3, r3, asl #9
	22211	+ lsl r3, r3, #9
21884	22212	str r3, [sp, #64]
21885		- ldr r3, [sp, #24]
21886		- mov r3, r3, asl #9
21887		- str r3, [sp, #68]
21888		- mov r3, #0
21889		- str r3, [sp, #44]
21890		-.L3671:
21891		- ldr r3, [sp, #44]
21892		- mov ip, #36
21893		- ldr r1, [sp, #32]
21894		- mul r10, ip, r3
21895		- ldr r3, [r5, #-1504]
21896		- add r3, r3, r10
	22213	+.L3597:
	22214	+ mov r9, #36
	22215	+ ldr r3, [r4, #-1500]
	22216	+ mul r9, r9, fp
	22217	+ ldr r1, [sp, #36]
	22218	+ add r3, r3, r9
21897	22219	ldr r2, [r3, #16]
21898		- cmp r2, r1
21899		- bne .L3666
	22220	+ cmp r1, r2
	22221	+ bne .L3592
21900	22222	ldr r1, [r3, #8]
21901		- ldr r3, [r5, #-1456]
	22223	+ ldr r3, [r4, #-1452]
21902	22224	cmp r1, r3
21903		- bne .L3667
	22225	+ bne .L3593
21904	22226	ldr r3, [sp, #60]
21905	22227	mov r0, r8
21906	22228	ldr r2, [sp, #64]
21907	22229	add r1, r1, r3
21908		- b .L3697
21909		-.L3666:
21910		- ldr r1, [sp, #36]
21911		- cmp r2, r1
21912		- bne .L3667
21913		- ldr r1, [r3, #8]
21914		- ldr r3, [r5, #-1452]
21915		- cmp r1, r3
21916		- bne .L3667
21917		- ldr r3, .L3699+12
21918		- ldr r2, [sp, #68]
21919		- ldrh r0, [r3]
21920		- ldr r3, [sp, #36]
21921		- mul r0, r0, r3
21922		- rsb r0, r4, r0
21923		- add r0, r8, r0, asl #9
21924		-.L3697:
	22230	+.L3620:
21925	22231	bl ftl_memcpy
21926		-.L3667:
21927		- ldr r2, [r5, #-1504]
21928		- add r3, r2, r10
21929		- ldr r1, [r2, r10]
21930		- cmn r1, #1
21931		- streq r1, [sp, #52]
21932		- ldreq r2, [fp, #1284]
21933		- addeq r2, r2, #1
21934		- streq r2, [fp, #1284]
	22232	+.L3593:
	22233	+ ldr r3, [r4, #-1500]
	22234	+ ldr r2, [r3, r9]
	22235	+ add r1, r3, r9
	22236	+ cmn r2, #1
	22237	+ ldreq r3, [r4, #1276]
	22238	+ moveq r10, r2
	22239	+ addeq r3, r3, #1
	22240	+ streq r3, [r4, #1276]
	22241	+ ldr r3, [r1, #12]
	22242	+ ldr r2, [r1, #16]
	22243	+ ldr r3, [r3, #8]
	22244	+ cmp r2, r3
	22245	+ beq .L3595
	22246	+ ldr r3, [r4, #1276]
	22247	+ add r3, r3, #1
	22248	+ str r3, [r4, #1276]
	22249	+ ldr r2, [r1, #8]
	22250	+ ldr r3, [r1, #12]
	22251	+ ldr r0, [r2, #4]
	22252	+ str r0, [sp, #16]
	22253	+ ldr r2, [r2]
	22254	+ ldr r0, .L3621+24
	22255	+ str r2, [sp, #12]
21935	22256	ldr r2, [r3, #12]
21936		- ldr r1, [r3, #16]
21937		- ldr r2, [r2, #8]
21938		- cmp r1, r2
21939		- beq .L3669
21940		- ldr r2, [fp, #1284]
21941		- ldr r0, .L3699+24
21942		- add r2, r2, #1
21943		- str r2, [fp, #1284]
21944		- ldr lr, [r3, #12]
	22257	+ str r2, [sp, #8]
21945	22258	ldr r2, [r3, #8]
21946		- ldr r1, [lr, #4]
21947		- str r1, [sp]
21948		- ldr r1, [lr, #8]
21949		- str r1, [sp, #4]
21950		- ldr r1, [lr, #12]
21951		- str r1, [sp, #8]
21952		- ldr r1, [r2]
21953		- str r1, [sp, #12]
21954		- ldr r2, [r2, #4]
21955		- str r2, [sp, #16]
21956		- ldr r1, [r3, #16]
	22259	+ str r2, [sp, #4]
21957	22260	ldr r2, [r3, #4]
21958		- ldr r3, [lr]
	22261	+ str r2, [sp]
	22262	+ ldr r2, [r1, #4]
	22263	+ ldr r3, [r3]
	22264	+ ldr r1, [r1, #16]
21959	22265	bl printk
21960		-.L3669:
21961		- ldr r3, [r5, #-1504]
21962		- add r2, r3, r10
21963		- ldr r3, [r3, r10]
	22266	+.L3595:
	22267	+ ldr r3, [r4, #-1500]
	22268	+ add r2, r3, r9
	22269	+ ldr r3, [r3, r9]
21964	22270	cmp r3, #256
21965		- bne .L3670
	22271	+ bne .L3596
21966	22272	ldr r0, [r2, #4]
21967	22273	ubfx r0, r0, #10, #16
21968	22274	bl P2V_block_in_plane
21969	22275	bl FtlGcRefreshBlock
21970		-.L3670:
21971		- ldr r3, [sp, #44]
21972		- add r3, r3, #1
21973		- str r3, [sp, #44]
21974		- cmp r3, r7
21975		- bne .L3671
	22276	+.L3596:
	22277	+ add fp, fp, #1
	22278	+ cmp r7, fp
	22279	+ bne .L3597
21976	22280	mov r7, #0
21977		- b .L3655
21978		-.L3698:
21979		- ldr r3, .L3699+28
21980		- ldrh r3, [r3, #-6]
21981		- cmp r3, #0
21982		- beq .L3673
21983		- ldr r0, [sp, #28]
21984		- mov r1, #1
21985		- bl ftl_do_gc
21986		-.L3673:
21987		- ldr r0, [sp, #52]
21988		- b .L3652
21989		-.L3676:
21990		- mvn r0, #0
21991		-.L3652:
21992		- add sp, sp, #84
21993		- @ sp needed
21994		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
21995		-.L3700:
	22281	+ b .L3581
	22282	+.L3587:
	22283	+ ldr r3, [sp, #40]
	22284	+ cmp r6, r3
	22285	+ bne .L3589
	22286	+ ldr r3, [r4, #-1448]
	22287	+ ldr r1, [sp, #44]
	22288	+ str r3, [r9, #8]
	22289	+ ldr r3, .L3621+12
	22290	+ ldrh r2, [r3, #-12]
	22291	+ mul r3, r2, r6
	22292	+ sub r1, r1, r3
	22293	+ cmp r2, r1
	22294	+ str r1, [sp, #52]
	22295	+ bne .L3588
	22296	+.L3619:
	22297	+ sub r3, r3, r5
	22298	+ add r3, r8, r3, lsl #9
	22299	+ str r3, [r9, #8]
	22300	+ b .L3588
	22301	+.L3589:
	22302	+ ldr r3, .L3621+12
	22303	+ ldrh r3, [r3, #-12]
	22304	+ mul r3, r6, r3
	22305	+ b .L3619
	22306	+.L3592:
	22307	+ ldr r1, [sp, #40]
	22308	+ cmp r1, r2
	22309	+ bne .L3593
	22310	+ ldr r1, [r3, #8]
	22311	+ ldr r3, [r4, #-1448]
	22312	+ cmp r1, r3
	22313	+ bne .L3593
	22314	+ ldr r3, .L3621+16
	22315	+ ldr r2, [sp, #68]
	22316	+ ldrh r0, [r3]
	22317	+ ldr r3, [sp, #40]
	22318	+ mul r0, r3, r0
	22319	+ sub r0, r0, r5
	22320	+ add r0, r8, r0, lsl #9
	22321	+ b .L3620
	22322	+.L3601:
	22323	+ mvn r10, #0
	22324	+ b .L3577
	22325	+.L3622:
21996	22326	.align 2
21997		-.L3699:
	22327	+.L3621:
21998	22328	.word .LANCHOR1
21999	22329	.word .LANCHOR2
22000		- .word .LANCHOR4
22001		- .word .LANCHOR2-1662
22002		- .word .LANCHOR2-1656
22003		- .word .LANCHOR2-1736
22004		- .word .LC58
22005	22330	.word .LANCHOR2-1520
	22331	+ .word .LANCHOR2-1648
	22332	+ .word .LANCHOR2-1660
	22333	+ .word .LANCHOR2-1732
	22334	+ .word .LC58
22006	22335	.fnend
22007	22336	.size ftl_read, .-ftl_read
22008	22337	.align 2
22009	22338	.global ftl_vendor_read
	22339	+ .syntax unified
	22340	+ .arm
	22341	+ .fpu softvfp
22010	22342	.type ftl_vendor_read, %function
22011	22343	ftl_vendor_read:
22012	22344	.fnstart
22013	22345	@ args = 0, pretend = 0, frame = 0
22014	22346	@ frame_needed = 0, uses_anonymous_args = 0
22015		- str lr, [sp, #-4]!
22016		- .save {lr}
22017		- mov ip, r1
22018		- mov lr, r0
	22347	+ @ link register save eliminated.
22019	22348	mov r3, r2
22020		- mov r1, lr
	22349	+ mov r2, r1
	22350	+ mov r1, r0
22021	22351	mov r0, #16
22022		- mov r2, ip
22023		- ldr lr, [sp], #4
22024	22352	b ftl_read
22025	22353	.fnend
22026	22354	.size ftl_vendor_read, .-ftl_vendor_read
22027	22355	.align 2
22028	22356	.global ftl_sys_read
	22357	+ .syntax unified
	22358	+ .arm
	22359	+ .fpu softvfp
22029	22360	.type ftl_sys_read, %function
22030	22361	ftl_sys_read:
22031	22362	.fnstart
22032	22363	@ args = 0, pretend = 0, frame = 0
22033	22364	@ frame_needed = 0, uses_anonymous_args = 0
22034	22365	@ link register save eliminated.
22035		- mov ip, r1
22036	22366	mov r3, r2
	22367	+ mov r2, r1
22037	22368	add r1, r0, #256
22038		- mov r2, ip
22039	22369	mov r0, #16
22040	22370	b ftl_read
22041	22371	.fnend
22042	22372	.size ftl_sys_read, .-ftl_sys_read
22043	22373	.align 2
22044	22374	.global FtlInit
	22375	+ .syntax unified
	22376	+ .arm
	22377	+ .fpu softvfp
22045	22378	.type FtlInit, %function
22046	22379	FtlInit:
22047	22380	.fnstart
22048	22381	@ args = 0, pretend = 0, frame = 0
22049	22382	@ frame_needed = 0, uses_anonymous_args = 0
22050		- stmfd sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
22051		- .save {r3, r4, r5, r6, r7, r8, r9, lr}
	22383	+ push {r4, r5, r6, r7, r8, lr}
	22384	+ .save {r4, r5, r6, r7, r8, lr}
22052	22385	mvn r3, #0
22053		- ldr r2, .L3721
22054		- ldr r5, .L3721+4
22055		- ldr r6, .L3721+8
22056		- ldr r1, .L3721+12
22057		- ldr r0, .L3721+16
22058		- str r3, [r6, #3444]
	22386	+ ldr r6, .L3642
	22387	+ ldr r4, .L3642+4
	22388	+ ldr r1, .L3642+8
	22389	+ str r3, [r6, #3440]
22059	22390	mov r3, #0
22060		- str r3, [r2, #1956]
22061		- str r3, [r5, #-1280]
	22391	+ ldr r0, .L3642+12
	22392	+ str r3, [r4, #1948]
	22393	+ str r3, [r4, #-1280]
22062	22394	bl printk
22063		- ldr r0, .L3721+20
	22395	+ sub r0, r4, #2768
22064	22396	bl FtlConstantsInit
22065	22397	bl FtlMemInit
22066	22398	bl FtlVariablesInit
22067		- ldr r3, [r5, #-1732]
22068		- uxth r0, r3
	22399	+ sub r3, r4, #1728
	22400	+ ldrh r0, [r3]
22069	22401	bl FtlFreeSysBlkQueueInit
22070	22402	bl FtlLoadBbt
22071	22403	cmp r0, #0
22072		- ldrne r0, .L3721+24
22073		- bne .L3720
22074		- bl FtlSysBlkInit
22075		- subs r4, r0, #0
22076		- beq .L3707
22077		- ldr r0, .L3721+28
22078		-.L3720:
22079		- ldr r1, .L3721+32
	22404	+ beq .L3626
	22405	+ ldr r1, .L3642+16
	22406	+ ldr r0, .L3642+20
	22407	+.L3641:
22080	22408	bl printk
22081		- b .L3706
22082		-.L3707:
	22409	+.L3627:
	22410	+ mov r0, #0
	22411	+ pop {r4, r5, r6, r7, r8, pc}
	22412	+.L3626:
	22413	+ bl FtlSysBlkInit
	22414	+ subs r5, r0, #0
	22415	+ ldrne r1, .L3642+16
	22416	+ ldrne r0, .L3642+24
	22417	+ bne .L3641
	22418	+.L3628:
22083	22419	mov r1, #1
22084		- str r1, [r6, #3444]
	22420	+ str r1, [r6, #3440]
22085	22421	bl ftl_do_gc
22086		- add r3, r5, #880
	22422	+ add r3, r4, #880
22087	22423	ldrh r7, [r3]
22088	22424	mov r6, r3
22089	22425	cmp r7, #15
22090		- bhi .L3708
22091		- ldr r8, .L3721+36
22092		- movw r5, #65535
22093		- ldr r9, .L3721+40
22094		-.L3711:
	22426	+ bhi .L3629
	22427	+ add r8, r3, #276
	22428	+ sub r4, r4, #1536
	22429	+.L3632:
22095	22430	ldrh r3, [r8]
22096		- cmp r3, r5
22097		- bne .L3709
22098		- ldrh r3, [r9]
22099		- cmp r3, r5
22100		- bne .L3709
22101		- and r0, r4, #63
	22431	+ movw r2, #65535
	22432	+ cmp r3, r2
	22433	+ bne .L3630
	22434	+ ldrh r2, [r4]
	22435	+ cmp r2, r3
	22436	+ bne .L3630
	22437	+ and r0, r5, #63
22102	22438	bl List_get_gc_head_node
22103	22439	uxth r0, r0
22104	22440	bl FtlGcRefreshBlock
22105		-.L3709:
22106		- mov r0, #1
22107		- mov r1, r0
22108		- bl ftl_do_gc
22109		- mov r0, #0
	22441	+.L3630:
22110	22442	mov r1, #1
	22443	+ mov r0, r1
	22444	+ bl ftl_do_gc
	22445	+ mov r1, #1
	22446	+ mov r0, #0
22111	22447	bl ftl_do_gc
22112	22448	ldrh r2, [r6]
22113	22449	add r3, r7, #2
22114	22450	cmp r2, r3
22115		- bhi .L3706
22116		- add r4, r4, #1
22117		- cmp r4, #4096
22118		- bne .L3711
22119		- b .L3706
22120		-.L3708:
22121		- ldrb r3, [r5, #-2744] @ zero_extendqisi2
	22451	+ bhi .L3627
	22452	+ add r5, r5, #1
	22453	+ cmp r5, #4096
	22454	+ bne .L3632
	22455	+ b .L3627
	22456	+.L3629:
	22457	+ ldrb r3, [r4, #-2740] @ zero_extendqisi2
22122	22458	cmp r3, #0
22123		- beq .L3706
	22459	+ beq .L3627
22124	22460	mov r4, #128
22125		-.L3713:
22126		- mov r0, #1
22127		- mov r1, r0
	22461	+.L3634:
	22462	+ mov r1, #1
	22463	+ mov r0, r1
22128	22464	bl ftl_do_gc
22129	22465	subs r4, r4, #1
22130		- bne .L3713
22131		-.L3706:
22132		- mov r0, #0
22133		- ldmfd sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
22134		-.L3722:
	22466	+ bne .L3634
	22467	+ b .L3627
	22468	+.L3643:
22135	22469	.align 2
22136		-.L3721:
22137		- .word .LANCHOR4
22138		- .word .LANCHOR2
	22470	+.L3642:
22139	22471	.word .LANCHOR1
	22472	+ .word .LANCHOR2
22140	22473	.word .LC145
22141		- .word .LC48
22142		- .word .LANCHOR2-2772
	22474	+ .word .LC49
	22475	+ .word .LANCHOR3+224
22143	22476	.word .LC163
22144	22477	.word .LC164
22145		- .word .LANCHOR3+240
22146		- .word .LANCHOR4+1164
22147		- .word .LANCHOR2-1540
22148	22478	.fnend
22149	22479	.size FtlInit, .-FtlInit
22150	22480	.align 2
22151	22481	.global ftl_write
	22482	+ .syntax unified
	22483	+ .arm
	22484	+ .fpu softvfp
22152	22485	.type ftl_write, %function
22153	22486	ftl_write:
22154	22487	.fnstart
22155		- @ args = 0, pretend = 0, frame = 96
	22488	+ @ args = 0, pretend = 0, frame = 80
22156	22489	@ frame_needed = 0, uses_anonymous_args = 0
22157		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
	22490	+ push {r4, r5, r6, r7, r8, r9, r10, fp, lr}
22158	22491	.save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
22159		- .pad #100
22160		- sub sp, sp, #100
22161		- ldr r10, .L3797
22162		- str r3, [sp, #8]
22163		- ldr r3, [r10, #-1280]
	22492	+ mov fp, r3
	22493	+ ldr r4, .L3712
	22494	+ .pad #84
	22495	+ sub sp, sp, #84
	22496	+ ldr r3, [r4, #-1280]
22164	22497	cmp r3, #0
22165		- bne .L3764
22166		- mov r8, r2
22167		- ldr r2, .L3797+4
22168		- ldr r2, [r2, #3444]
	22498	+ bne .L3685
	22499	+ mov r9, r2
	22500	+ ldr r2, .L3712+4
	22501	+ ldr r2, [r2, #3440]
22169	22502	cmp r2, #1
22170	22503	movne r0, r3
22171		- bne .L3724
	22504	+ bne .L3644
22172	22505	cmp r0, #16
22173	22506	mov r7, r1
22174		- bne .L3725
22175		- add r0, r1, #256
22176		- ldr r2, [sp, #8]
22177		- mov r1, r8
	22507	+ bne .L3646
	22508	+ mov r2, fp
	22509	+ mov r1, r9
	22510	+ add r0, r7, #256
22178	22511	bl FtlVendorPartWrite
22179		- b .L3724
22180		-.L3725:
22181		- ldr r3, [r10, #-2740]
22182		- cmp r8, r3
	22512	+.L3644:
	22513	+ add sp, sp, #84
	22514	+ @ sp needed
	22515	+ pop {r4, r5, r6, r7, r8, r9, r10, fp, pc}
	22516	+.L3646:
	22517	+ ldr r3, [r4, #-2736]
	22518	+ cmp r9, r3
22183	22519	cmpls r1, r3
22184		- bcs .L3767
22185		- add r5, r1, r8
22186		- cmp r5, r3
22187		- bhi .L3767
22188		- ldr r6, .L3797+8
	22520	+ bcs .L3688
	22521	+ add r6, r1, r9
	22522	+ cmp r3, r6
	22523	+ bcc .L3688
22189	22524	mov r3, #2048
22190		- mov r0, r1
22191		- str r3, [r6, #1960]
22192		- sub r3, r10, #1648
22193		- ldrh r4, [r3, #-14]
22194		- mov r1, r4
	22525	+ mov r0, r7
	22526	+ str r3, [r4, #1952]
	22527	+ sub r3, r4, #1648
	22528	+ ldrh r5, [r3, #-12]
	22529	+ mov r1, r5
22195	22530	bl __aeabi_uidiv
22196		- mov r1, r4
22197		- str r0, [sp, #12]
22198		- sub r0, r5, #1
	22531	+ mov r1, r5
	22532	+ str r0, [sp]
	22533	+ sub r0, r6, #1
22199	22534	bl __aeabi_uidiv
22200		- cmp r8, r4, asl #1
22201		- ldr r2, [sp, #12]
22202		- str r0, [sp, #28]
22203		- rsb r5, r2, r0
22204		- add r3, r5, #1
22205		- str r3, [sp, #4]
22206		- ldr r2, [sp, #4]
22207		- ldr r3, [r10, #-1604]
22208		- add r3, r2, r3
22209		- ldr r2, [r10, #-1516]
22210		- str r3, [r10, #-1604]
22211		- ldr r3, [r6, #1724]
22212		- add r3, r8, r3
22213		- str r3, [r6, #1724]
	22535	+ ldr r2, [sp]
	22536	+ cmp r9, r5, lsl #1
	22537	+ ldr r3, [r4, #-1600]
	22538	+ str r0, [sp, #24]
	22539	+ sub r6, r0, r2
	22540	+ ldr r2, [r4, #-1512]
	22541	+ add r8, r6, #1
	22542	+ add r3, r3, r8
	22543	+ str r3, [r4, #-1600]
	22544	+ ldr r3, [r4, #1716]
	22545	+ add r3, r3, r9
	22546	+ str r3, [r4, #1716]
22214	22547	movcs r3, #1
22215	22548	movcc r3, #0
22216	22549	cmp r2, #0
22217		- str r3, [sp, #24]
22218		- beq .L3727
	22550	+ str r3, [sp, #16]
	22551	+ beq .L3689
22219	22552	mov r3, #36
22220		- ldr r9, [r10, #-1484]
22221	22553	mul r3, r3, r2
22222		- ldr r2, [sp, #12]
	22554	+ ldr r2, [r4, #-1480]
22223	22555	sub r3, r3, #36
22224		- add r9, r9, r3
22225		- ldr r3, [r9, #16]
22226		- cmp r2, r3
22227		- bne .L3728
22228		- ldr r3, [r10, #-1596]
22229		- mov r1, r4
	22556	+ add r10, r2, r3
	22557	+ ldr r3, [sp]
	22558	+ ldr r2, [r10, #16]
	22559	+ cmp r3, r2
	22560	+ strne fp, [sp, #12]
	22561	+ bne .L3649
	22562	+ ldr r2, [r4, #-1592]
	22563	+ mov r1, r5
22230	22564	mov r0, r7
22231		- add r3, r3, #1
22232		- str r3, [r10, #-1596]
22233		- ldr r3, [r6, #1964]
22234		- add r3, r3, #1
22235		- str r3, [r6, #1964]
	22565	+ add r2, r2, #1
	22566	+ str r2, [r4, #-1592]
	22567	+ ldr r2, [r4, #1956]
	22568	+ add r2, r2, #1
	22569	+ str r2, [r4, #1956]
22236	22570	bl __aeabi_uidivmod
22237		- ldr r0, [r9, #8]
22238		- rsb r4, r1, r4
22239		- add r0, r0, r1, asl #9
22240		- cmp r4, r8
22241		- ldr r1, [sp, #8]
22242		- movcs r4, r8
22243		- mov r10, r4, asl #9
22244		- mov r2, r10
	22571	+ sub r5, r5, r1
	22572	+ ldr r3, [r10, #8]
	22573	+ cmp r9, r5
	22574	+ mov r0, r1
	22575	+ movcc r5, r9
	22576	+ mov r1, fp
	22577	+ lsl r8, r5, #9
	22578	+ add r0, r3, r0, lsl #9
	22579	+ mov r2, r8
22245	22580	bl ftl_memcpy
22246		- cmp r5, #0
22247		- bne .L3729
22248		- ldr r3, [r6, #1964]
	22581	+ cmp r6, #0
	22582	+ bne .L3650
	22583	+ ldr r3, [r4, #1956]
22249	22584	cmp r3, #2
22250		- ble .L3764
22251		-.L3729:
22252		- ldr r3, [sp, #8]
22253		- rsb r8, r4, r8
22254		- add r7, r7, r4
22255		- str r5, [sp, #4]
22256		- add r3, r3, r10
22257		- str r3, [sp, #8]
22258		- ldr r3, [sp, #12]
22259		- add r3, r3, #1
	22585	+ bgt .L3650
	22586	+.L3685:
	22587	+ mov r0, #0
	22588	+ b .L3644
	22589	+.L3650:
	22590	+ add r3, fp, r8
	22591	+ sub r9, r9, r5
22260	22592	str r3, [sp, #12]
22261		-.L3728:
	22593	+ add r7, r7, r5
	22594	+ ldr r3, [sp]
	22595	+ mov r8, r6
	22596	+ add r3, r3, #1
	22597	+ str r3, [sp]
	22598	+.L3649:
22262	22599	mov r3, #0
22263		- str r3, [r6, #1964]
22264		-.L3727:
22265		- ldr r0, [sp, #12]
22266		- ldr r1, [sp, #28]
	22600	+ str r3, [r4, #1956]
	22601	+.L3648:
	22602	+ ldr r1, [sp, #24]
	22603	+ ldr r0, [sp]
22267	22604	bl FtlCacheMetchLpa
22268	22605	cmp r0, #0
22269		- beq .L3730
	22606	+ beq .L3651
22270	22607	bl FtlCacheWriteBack
22271		-.L3730:
22272		- ldr r5, .L3797+12
22273		- mov r3, #0
22274		- str r3, [sp, #16]
22275		- sub r4, r5, #884
22276		- str r3, [sp, #32]
22277		- str r5, [r6, #1948]
22278		- ldr r6, [sp, #12]
22279		-.L3731:
22280		- ldr r3, [sp, #4]
22281		- cmp r3, #0
22282		- beq .L3796
22283		- ldrh r2, [r5, #4]
22284		- cmp r2, #0
22285		- bne .L3732
22286		- ldr r3, .L3797+12
22287		- ldr r9, .L3797+4
22288		- cmp r5, r3
22289		- bne .L3733
22290		- add r0, r5, #48
22291		- ldrh r10, [r0, #4]
22292		- cmp r10, #0
22293		- bne .L3734
22294		- bl allocate_new_data_superblock
22295		- str r10, [r9, #3452]
22296		-.L3734:
22297		- ldr r0, .L3797+12
22298		- bl allocate_new_data_superblock
22299		- ldr r3, [r9, #3452]
22300		- cmp r3, #0
22301		- ldrne r5, .L3797+16
22302		- bne .L3735
22303		-.L3736:
22304		- ldr r5, .L3797+12
22305		- b .L3735
22306		-.L3733:
22307		- ldrh r3, [r3, #4]
22308		- str r2, [r9, #3452]
22309		- cmp r3, #0
22310		- bne .L3736
22311		- mov r0, r5
22312		- bl allocate_new_data_superblock
22313		-.L3735:
22314		- ldrh r3, [r5, #4]
22315		- cmp r3, #0
22316		- bne .L3737
22317		- mov r0, r5
22318		- bl allocate_new_data_superblock
22319		-.L3737:
22320		- ldr r3, .L3797+8
22321		- str r5, [r3, #1948]
22322		-.L3732:
22323		- ldr r3, [r4, #-1520]
22324		- ldr r1, [r4, #-1516]
22325		- ldrh r2, [r5, #4]
22326		- rsb r3, r1, r3
22327		- cmp r2, r3
22328		- movcs r2, r3
22329		- ldr r3, [sp, #4]
22330		- cmp r2, r3
22331		- movcc r3, r2
22332		- str r3, [sp, #44]
22333		- mov r3, #0
22334		-.L3794:
22335		- str r3, [sp, #20]
22336		- ldr r3, [sp, #20]
22337		- ldr r2, [sp, #44]
22338		- cmp r3, r2
22339		- beq .L3739
22340		- ldrh r3, [r5, #4]
22341		- cmp r3, #0
22342		- beq .L3739
22343		- ldr r3, [sp, #28]
22344		- ldr r2, [sp, #20]
22345		- rsb ip, r3, r6
22346		- ldr r3, [sp, #24]
22347		- clz ip, ip
22348		- mov ip, ip, lsr #5
22349		- and r3, ip, r3
22350		- cmp r2, #0
22351		- moveq r3, #0
22352		- andne r3, r3, #1
22353		- cmp r3, #0
22354		- beq .L3740
22355		- ldr r3, .L3797+20
22356		- ldrh r2, [r3]
22357		- add r3, r8, r7
22358		- mls r3, r2, r6, r3
22359		- cmp r3, r2
22360		- bne .L3739
22361		-.L3740:
22362		- add r1, sp, #56
22363		- mov r2, #0
22364		- mov r0, r6
22365		- str ip, [sp, #52]
22366		- bl log2phys
22367		- mov r0, r5
22368		- bl get_new_active_ppa
22369		- ldr r10, [r4, #-1516]
22370		- ldr r1, [r4, #-1484]
22371		- mov r3, #36
22372		- ldr fp, .L3797+24
22373		- mla r1, r3, r10, r1
22374		- ldrh r2, [fp]
22375		- str r6, [r1, #16]
22376		- str r0, [r1, #4]
22377		- mul r0, r10, r2
22378		- str r3, [sp, #48]
22379		- bic r3, r0, #3
22380		- str r3, [sp, #36]
22381		- ldr r0, [sp, #36]
22382		- ldr r3, [r4, #-1432]
22383		- add r9, r3, r0
22384		- ldrh r0, [fp, #-2]
22385		- str r9, [r1, #12]
22386		- str r3, [sp, #40]
22387		- mul r10, r10, r0
22388		- ldr r0, [r4, #-1460]
22389		- bic r10, r10, #3
22390		- add r10, r0, r10
22391		- mov r0, r9
22392		- str r10, [r1, #8]
22393		- mov r1, #0
22394		- bl ftl_memset
22395		- ldr r3, [sp, #12]
22396		- ldr ip, [sp, #52]
22397		- rsb r10, r3, r6
22398		- clz r10, r10
22399		- mov r10, r10, lsr #5
22400		- orrs r3, r10, ip
22401		- ldr r3, [sp, #48]
22402		- beq .L3741
22403		- cmp r10, #0
22404		- beq .L3742
22405		- ldrh fp, [fp, #-6]
22406		- mov r0, r7
22407		- mov r1, fp
22408		- bl __aeabi_uidivmod
22409		- rsb r2, r1, fp
22410		- mov r3, r1
22411		- cmp r2, r8
22412		- str r1, [sp, #32]
22413		- movcc r3, r2
22414		- movcs r3, r8
22415		- str r3, [sp, #16]
22416		- b .L3743
22417		-.L3742:
22418		- cmp ip, #0
22419		- beq .L3743
22420		- ldr r3, .L3797+20
22421		- add r2, r8, r7
22422		- str r10, [sp, #32]
22423		- ldrh r1, [r3]
22424		- smulbb r1, r1, r6
22425		- rsb r2, r1, r2
22426		- uxth r3, r2
22427		- str r3, [sp, #16]
22428		-.L3743:
22429		- ldr r3, .L3797+20
22430		- ldr r2, [sp, #16]
22431		- ldrh r3, [r3]
22432		- cmp r2, r3
22433		- bne .L3744
22434		- cmp r10, #0
22435		- ldr r0, .L3797
22436		- moveq r3, r2
22437		- ldr r2, .L3797
22438		- muleq r1, r6, r3
22439		- ldreq r3, [sp, #8]
22440		- ldr r2, [r2, #-1516]
22441		- ldr r0, [r0, #-1484]
22442		- rsbeq r1, r7, r1
22443		- ldrne r1, [sp, #8]
22444		- addeq r1, r3, r1, asl #9
22445		- ldr r3, [sp, #24]
22446		- cmp r3, #0
22447		- mov r3, #36
22448		- mla r3, r3, r2, r0
22449		- strne r1, [r3, #8]
22450		- bne .L3747
22451		- ldr r0, [r3, #8]
22452		- ldr r3, .L3797+28
22453		- ldrh r2, [r3]
22454		- b .L3792
22455		-.L3744:
22456		- ldr r2, [sp, #56]
22457		- mov r3, #36
22458		- cmn r2, #1
22459		- beq .L3748
22460		- ldr r1, [r4, #-1484]
22461		- add r0, sp, #60
22462		- str r2, [sp, #64]
22463		- ldr r2, [r4, #-1516]
22464		- str r6, [sp, #76]
22465		- mla r3, r3, r2, r1
22466		- mov r1, #1
22467		- ldr r2, [r3, #8]
22468		- ldr r3, [r3, #12]
22469		- str r2, [sp, #68]
22470		- mov r2, #0
22471		- str r3, [sp, #72]
22472		- bl FlashReadPages
22473		- ldr r3, [sp, #60]
22474		- cmn r3, #1
22475		- ldreq r2, .L3797+8
22476		- ldreq r3, [r2, #1284]
22477		- addeq r3, r3, #1
22478		- streq r3, [r2, #1284]
22479		- beq .L3751
22480		-.L3749:
22481		- ldr r3, [r9, #8]
22482		- cmp r3, r6
22483		- beq .L3751
22484		- ldr r2, .L3797+8
22485		- ldr r0, .L3797+32
22486		- ldr r3, [r2, #1284]
22487		- add r3, r3, #1
22488		- str r3, [r2, #1284]
22489		- mov r2, r6
22490		- ldr r1, [r9, #8]
22491		- bl printk
22492		- b .L3751
22493		-.L3748:
22494		- ldr r2, [r4, #-1516]
22495		- ldr r1, [r4, #-1484]
22496		- mla r3, r3, r2, r1
22497		- mov r1, #0
22498		- ldr r0, [r3, #8]
22499		- ldr r3, .L3797+28
22500		- ldrh r2, [r3]
22501		- bl ftl_memset
22502		-.L3751:
22503		- cmp r10, #0
22504		- mov r3, #36
22505		- beq .L3752
22506		- ldr r1, [r4, #-1484]
22507		- ldr r2, [r4, #-1516]
22508		- mla r3, r3, r2, r1
22509		- ldr r1, [sp, #8]
22510		- ldr r0, [r3, #8]
22511		- ldr r3, [sp, #32]
22512		- add r0, r0, r3, asl #9
22513		- b .L3795
22514		-.L3752:
22515		- ldr r1, [r4, #-1516]
22516		- ldr r2, [r4, #-1484]
22517		- mla r3, r3, r1, r2
22518		- ldr r2, .L3797+20
22519		- ldrh r1, [r2]
22520		- ldr r0, [r3, #8]
22521		- mul r1, r1, r6
22522		- ldr r3, [sp, #8]
22523		- rsb r1, r7, r1
22524		- add r1, r3, r1, asl #9
22525		-.L3795:
22526		- ldr r3, [sp, #16]
22527		- mov r2, r3, asl #9
22528		- b .L3792
22529		-.L3741:
22530		- ldr r2, [sp, #24]
22531		- cmp r2, #0
22532		- ldr r2, [r4, #-1516]
22533		- beq .L3753
22534		- ldr r1, [r4, #-1484]
22535		- mla r3, r3, r2, r1
22536		- ldr r2, .L3797+20
22537		- ldrh fp, [r2]
22538		- ldr r2, [sp, #8]
22539		- mul fp, fp, r6
22540		- rsb fp, r7, fp
22541		- add fp, r2, fp, asl #9
22542		- str fp, [r3, #8]
22543		- b .L3747
22544		-.L3753:
22545		- ldr r0, [r4, #-1484]
22546		- mla r3, r3, r2, r0
22547		- ldr r2, .L3797+20
22548		- ldrh r1, [r2]
22549		- ldrh r2, [fp, #-2]
22550		- ldr r0, [r3, #8]
22551		- mul r1, r1, r6
22552		- ldr r3, [sp, #8]
22553		- rsb r1, r7, r1
22554		- add r1, r3, r1, asl #9
22555		-.L3792:
22556		- bl ftl_memcpy
22557		-.L3747:
22558		- ldr r3, .L3797+36
22559		- ldr r2, [sp, #40]
22560		- ldr r1, [sp, #36]
22561		- strh r3, [r2, r1] @ movhi
22562		- ldr r3, [r4, #-1612]
22563		- str r6, [r9, #8]
22564		- add r6, r6, #1
22565		- str r3, [r9, #4]
22566		- add r3, r3, #1
22567		- cmn r3, #1
22568		- moveq r3, #0
22569		- str r3, [r4, #-1612]
22570		- ldr r3, [sp, #56]
22571		- str r3, [r9, #12]
22572		- ldrh r3, [r5]
22573		- strh r3, [r9, #2] @ movhi
22574		- ldr r3, [r4, #-1516]
22575		- add r3, r3, #1
22576		- str r3, [r4, #-1516]
22577		- ldr r3, [sp, #20]
22578		- add r3, r3, #1
22579		- b .L3794
22580		-.L3739:
22581		- ldr r3, [sp, #4]
22582		- ldr r2, [sp, #20]
22583		- ldr r1, [sp, #24]
22584		- rsb r3, r2, r3
22585		- ldr r2, [r4, #-1520]
	22608	+.L3651:
	22609	+ ldr r5, .L3712+8
	22610	+ ldr r6, [sp]
	22611	+ sub r10, r5, #884
	22612	+ str r5, [r4, #1940]
	22613	+ sub r3, r10, #1648
22586	22614	str r3, [sp, #4]
22587		- ldr r3, [r4, #-1516]
22588		- cmp r3, r2
22589		- orrcs r1, r1, #1
22590		- cmp r1, #0
22591		- bne .L3757
22592		- ldrh r3, [r5, #4]
22593		- cmp r3, #0
22594		- beq .L3757
22595		-.L3759:
22596		- mov r3, #0
22597		- str r3, [sp, #24]
22598		- b .L3731
22599		-.L3757:
22600		- bl FtlCacheWriteBack
22601		- ldr r2, .L3797
22602		- mov r3, #0
22603		- str r3, [r2, #-1516]
22604		- ldr r3, [sp, #4]
22605		- cmp r3, #1
22606		- bhi .L3731
22607		- b .L3759
22608		-.L3796:
22609		- mov r0, r3
22610		- ldr r2, [sp, #12]
22611		- ldr r3, [sp, #28]
22612		- rsb r1, r2, r3
	22615	+.L3652:
	22616	+ cmp r8, #0
	22617	+ bne .L3680
	22618	+ ldr r3, [sp, #24]
	22619	+ mov r0, r8
	22620	+ ldr r2, [sp]
	22621	+ sub r1, r3, r2
22613	22622	bl ftl_do_gc
22614		- ldr r1, .L3797+40
22615		- ldrh r3, [r1]
22616		- mov r6, r1
	22623	+ ldr r2, .L3712+12
	22624	+ ldrh r3, [r2]
	22625	+ mov r6, r2
22617	22626	cmp r3, #5
22618		- bls .L3770
	22627	+ bls .L3681
22619	22628	cmp r3, #31
22620		- bhi .L3764
22621		- ldr r3, .L3797+44
22622		- ldrb r3, [r3] @ zero_extendqisi2
	22629	+ bhi .L3685
	22630	+ ldr r3, .L3712+16
	22631	+ ldrb r3, [r3, #36] @ zero_extendqisi2
22623	22632	cmp r3, #0
22624		- bne .L3764
22625		-.L3770:
22626		- ldr r5, .L3797+48
22627		- ldr r4, [sp, #4]
22628		- ldr r7, .L3797+52
22629		- add r8, r5, #2
22630		-.L3783:
	22633	+ bne .L3685
	22634	+.L3681:
	22635	+ ldr r5, .L3712
	22636	+ ldr r7, .L3712+20
	22637	+ sub r4, r5, #1520
	22638	+.L3684:
22631	22639	ldrh r2, [r7]
22632	22640	movw r3, #65535
22633	22641	cmp r2, r3
22634		- bne .L3763
22635		- ldrh r3, [r5]
	22642	+ bne .L3683
	22643	+ ldr r3, .L3712+24
	22644	+ ldrh r3, [r3]
22636	22645	cmp r3, r2
22637		- bne .L3763
22638		- ldrh r2, [r8]
	22646	+ bne .L3683
	22647	+ ldrh r2, [r4, #-14]
22639	22648	cmp r2, r3
22640		- bne .L3763
22641		- and r0, r4, #7
	22649	+ bne .L3683
	22650	+ and r0, r8, #7
22642	22651	bl List_get_gc_head_node
22643	22652	uxth r0, r0
22644	22653	bl FtlGcRefreshBlock
22645		-.L3763:
22646		- ldr r2, .L3797+56
22647		- mov r0, #1
22648		- mov r1, r0
22649		- mov r3, #128
22650		- strh r3, [r2] @ movhi
22651		- strh r3, [r2, #-2] @ movhi
22652		- bl ftl_do_gc
22653		- mov r0, #0
	22654	+.L3683:
22654	22655	mov r1, #1
	22656	+ mov r3, #128
	22657	+ mov r0, r1
	22658	+ strh r3, [r4, #-6] @ movhi
	22659	+ strh r3, [r4, #-8] @ movhi
22655	22660	bl ftl_do_gc
22656		- ldr r3, .L3797
22657		- ldr r3, [r3, #-1280]
	22661	+ mov r1, #1
	22662	+ mov r0, #0
	22663	+ bl ftl_do_gc
	22664	+ ldr r3, [r5, #-1280]
22658	22665	cmp r3, #0
22659		- bne .L3764
	22666	+ bne .L3685
22660	22667	ldrh r3, [r6]
22661	22668	cmp r3, #2
22662		- bhi .L3764
22663		- add r4, r4, #1
22664		- cmp r4, #256
22665		- bne .L3783
22666		- b .L3764
22667		-.L3767:
	22669	+ bhi .L3685
	22670	+ add r8, r8, #1
	22671	+ cmp r8, #256
	22672	+ bne .L3684
	22673	+ b .L3685
	22674	+.L3689:
	22675	+ str fp, [sp, #12]
	22676	+ b .L3648
	22677	+.L3680:
	22678	+ ldrh r1, [r5, #4]
	22679	+ cmp r1, #0
	22680	+ bne .L3653
	22681	+ ldr r2, .L3712+8
	22682	+ ldr r4, .L3712+4
	22683	+ cmp r5, r2
	22684	+ bne .L3654
	22685	+ add r0, r5, #48
	22686	+ ldrh fp, [r0, #4]
	22687	+ cmp fp, #0
	22688	+ bne .L3655
	22689	+ bl allocate_new_data_superblock
	22690	+ str fp, [r4, #3448]
	22691	+.L3655:
	22692	+ ldr r0, .L3712+8
	22693	+ bl allocate_new_data_superblock
	22694	+ ldr r5, .L3712+8
	22695	+ ldr r2, [r4, #3448]
	22696	+ add r0, r5, #48
	22697	+ cmp r2, #0
	22698	+ movne r5, r0
	22699	+.L3656:
	22700	+ ldrh r2, [r5, #4]
	22701	+ cmp r2, #0
	22702	+ bne .L3657
	22703	+ mov r0, r5
	22704	+ bl allocate_new_data_superblock
	22705	+.L3657:
	22706	+ str r5, [r10, #1940]
	22707	+.L3653:
	22708	+ ldr r1, [r10, #-1512]
	22709	+ ldr r2, [r10, #-1516]
	22710	+ sub r2, r2, r1
	22711	+ ldrh r1, [r5, #4]
	22712	+ cmp r2, r8
	22713	+ movcs r2, r8
	22714	+ cmp r1, r2
	22715	+ movcc r3, r1
	22716	+ movcs r3, r2
	22717	+ str r3, [sp, #36]
	22718	+ mov r3, #0
	22719	+.L3710:
	22720	+ str r3, [sp, #20]
	22721	+ ldr r3, [sp, #20]
	22722	+ ldr r2, [sp, #36]
	22723	+ cmp r3, r2
	22724	+ bne .L3676
	22725	+.L3659:
	22726	+ ldr r3, [sp, #20]
	22727	+ ldr r2, [r10, #-1512]
	22728	+ ldr r1, [r10, #-1516]
	22729	+ sub r8, r8, r3
	22730	+ ldr r3, [sp, #16]
	22731	+ cmp r2, r1
	22732	+ orrcs r3, r3, #1
	22733	+ cmp r3, #0
	22734	+ bne .L3677
	22735	+ ldrh r2, [r5, #4]
	22736	+ cmp r2, #0
	22737	+ beq .L3677
	22738	+.L3679:
	22739	+ mov r3, #0
	22740	+ str r3, [sp, #16]
	22741	+ b .L3652
	22742	+.L3654:
	22743	+ str r1, [r4, #3448]
	22744	+ ldrh r1, [r2, #4]
	22745	+ cmp r1, #0
	22746	+ movne r5, r2
	22747	+ bne .L3657
	22748	+ mov r0, r5
	22749	+ bl allocate_new_data_superblock
	22750	+ b .L3656
	22751	+.L3676:
	22752	+ ldrh r2, [r5, #4]
	22753	+ cmp r2, #0
	22754	+ beq .L3659
	22755	+ ldr r3, [sp, #24]
	22756	+ sub r4, r3, r6
	22757	+ ldr r3, [sp, #16]
	22758	+ clz r4, r4
	22759	+ lsr r4, r4, #5
	22760	+ and r2, r4, r3
	22761	+ ldr r3, [sp, #20]
	22762	+ cmp r3, #0
	22763	+ moveq r2, #0
	22764	+ andne r2, r2, #1
	22765	+ cmp r2, #0
	22766	+ beq .L3660
	22767	+ ldr r2, .L3712+28
	22768	+ ldrh r1, [r2]
	22769	+ add r2, r7, r9
	22770	+ mls r2, r1, r6, r2
	22771	+ cmp r1, r2
	22772	+ bne .L3659
	22773	+.L3660:
	22774	+ mov r2, #0
	22775	+ add r1, sp, #40
	22776	+ mov r0, r6
	22777	+ mov fp, #36
	22778	+ bl log2phys
	22779	+ mov r0, r5
	22780	+ bl get_new_active_ppa
	22781	+ ldr r1, [r10, #-1512]
	22782	+ ldr ip, [r10, #-1480]
	22783	+ ldr r3, [sp, #4]
	22784	+ mla ip, fp, r1, ip
	22785	+ ldrh r2, [r3, #-6]
	22786	+ str r0, [ip, #4]
	22787	+ mul r0, r2, r1
	22788	+ str r6, [ip, #16]
	22789	+ bic r3, r0, #3
	22790	+ str r3, [sp, #28]
	22791	+ ldr r0, [sp, #28]
	22792	+ ldr r3, [r10, #-1428]
	22793	+ str r3, [sp, #32]
	22794	+ add r3, r3, r0
	22795	+ str r3, [sp, #8]
	22796	+ str r3, [ip, #12]
	22797	+ ldr r3, [sp, #4]
	22798	+ ldrh r0, [r3, #-8]
	22799	+ mul r1, r1, r0
	22800	+ ldr r0, [r10, #-1456]
	22801	+ bic r1, r1, #3
	22802	+ add r1, r0, r1
	22803	+ ldr r0, [sp, #8]
	22804	+ str r1, [ip, #8]
	22805	+ mov r1, #0
	22806	+ bl ftl_memset
	22807	+ ldr r3, [sp]
	22808	+ cmp r3, r6
	22809	+ orreq r4, r4, #1
	22810	+ cmp r4, #0
	22811	+ beq .L3661
	22812	+ cmp r3, r6
	22813	+ bne .L3662
	22814	+ ldr r3, [sp, #4]
	22815	+ mov r0, r7
	22816	+ ldrh r4, [r3, #-12]
	22817	+ mov r1, r4
	22818	+ bl __aeabi_uidivmod
	22819	+ sub r4, r4, r1
	22820	+ mov fp, r1
	22821	+ cmp r4, r9
	22822	+ movcs r4, r9
	22823	+.L3663:
	22824	+ ldr r3, [sp, #4]
	22825	+ ldrh r2, [r3, #-12]
	22826	+ cmp r2, r4
	22827	+ bne .L3664
	22828	+ ldr r3, [sp]
	22829	+ cmp r3, r6
	22830	+ mulne r1, r4, r6
	22831	+ ldrne r3, [sp, #12]
	22832	+ ldreq r1, [sp, #12]
	22833	+ subne r1, r1, r7
	22834	+ addne r1, r3, r1, lsl #9
	22835	+ ldr r3, [sp, #16]
	22836	+ cmp r3, #0
	22837	+ beq .L3666
	22838	+ ldr r2, [r10, #-1512]
	22839	+ mov ip, #36
	22840	+ ldr r0, [r10, #-1480]
	22841	+ mla r2, ip, r2, r0
	22842	+ str r1, [r2, #8]
	22843	+.L3667:
	22844	+ ldr r2, .L3712+32
	22845	+ ldr r3, [sp, #32]
	22846	+ ldr r1, [sp, #28]
	22847	+ strh r2, [r3, r1] @ movhi
	22848	+ ldr r3, [sp, #8]
	22849	+ ldr r2, [r10, #-1608]
	22850	+ str r2, [r3, #4]
	22851	+ add r2, r2, #1
	22852	+ cmn r2, #1
	22853	+ ldr r3, [sp, #8]
	22854	+ moveq r2, #0
	22855	+ str r2, [r10, #-1608]
	22856	+ ldr r2, [sp, #40]
	22857	+ str r6, [r3, #8]
	22858	+ add r6, r6, #1
	22859	+ str r2, [r3, #12]
	22860	+ ldrh r2, [r5]
	22861	+ strh r2, [r3, #2] @ movhi
	22862	+ ldr r2, [r10, #-1512]
	22863	+ ldr r3, [sp, #20]
	22864	+ add r2, r2, #1
	22865	+ str r2, [r10, #-1512]
	22866	+ add r3, r3, #1
	22867	+ b .L3710
	22868	+.L3662:
	22869	+ ldr r3, [sp, #4]
	22870	+ add r4, r7, r9
	22871	+ mov fp, #0
	22872	+ ldrh r2, [r3, #-12]
	22873	+ smulbb r2, r2, r6
	22874	+ sub r4, r4, r2
	22875	+ uxth r4, r4
	22876	+ b .L3663
	22877	+.L3666:
	22878	+ ldr r2, [r10, #-1480]
	22879	+ mov ip, #36
	22880	+ ldr r0, [r10, #-1512]
	22881	+ ldr r3, [sp, #4]
	22882	+ mla r0, ip, r0, r2
	22883	+ ldrh r2, [r3, #-8]
	22884	+.L3711:
	22885	+ ldr r0, [r0, #8]
	22886	+ b .L3708
	22887	+.L3664:
	22888	+ ldr r2, [sp, #40]
	22889	+ cmn r2, #1
	22890	+ beq .L3668
	22891	+ ldr r1, [r10, #-1480]
	22892	+ mov r0, #36
	22893	+ str r2, [sp, #48]
	22894	+ ldr r2, [r10, #-1512]
	22895	+ str r6, [sp, #60]
	22896	+ mla r2, r0, r2, r1
	22897	+ add r0, sp, #44
	22898	+ ldr r1, [r2, #8]
	22899	+ ldr r2, [r2, #12]
	22900	+ str r1, [sp, #52]
	22901	+ mov r1, #1
	22902	+ str r2, [sp, #56]
	22903	+ mov r2, #0
	22904	+ bl FlashReadPages
	22905	+ ldr r2, [sp, #44]
	22906	+ cmn r2, #1
	22907	+ ldreq r2, [r10, #1276]
	22908	+ addeq r2, r2, #1
	22909	+ streq r2, [r10, #1276]
	22910	+ beq .L3671
	22911	+ ldr r3, [sp, #8]
	22912	+ ldr r2, [r3, #8]
	22913	+ cmp r6, r2
	22914	+ beq .L3671
	22915	+ ldr r2, [r10, #1276]
	22916	+ ldr r0, .L3712+36
	22917	+ add r2, r2, #1
	22918	+ str r2, [r10, #1276]
	22919	+ mov r2, r6
	22920	+ ldr r1, [r3, #8]
	22921	+ bl printk
	22922	+.L3671:
	22923	+ ldr r3, [sp]
	22924	+ lsl r2, r4, #9
	22925	+ cmp r3, r6
	22926	+ bne .L3672
	22927	+ ldr r0, [r10, #-1480]
	22928	+ mov ip, #36
	22929	+ ldr r1, [r10, #-1512]
	22930	+ mla r1, ip, r1, r0
	22931	+ ldr r0, [r1, #8]
	22932	+ ldr r1, [sp, #12]
	22933	+ add r0, r0, fp, lsl #9
	22934	+.L3708:
	22935	+ bl ftl_memcpy
	22936	+ b .L3667
	22937	+.L3668:
	22938	+ ldr r2, [r10, #-1480]
	22939	+ mov r1, #36
	22940	+ ldr r0, [r10, #-1512]
	22941	+ ldr r3, [sp, #4]
	22942	+ mla r0, r1, r0, r2
	22943	+ ldrh r2, [r3, #-8]
	22944	+ mov r1, #0
	22945	+ ldr r0, [r0, #8]
	22946	+ bl ftl_memset
	22947	+ b .L3671
	22948	+.L3672:
	22949	+ ldr r1, .L3712+28
	22950	+ mov lr, #36
	22951	+ ldr r0, [r10, #-1512]
	22952	+ ldr ip, [r10, #-1480]
	22953	+ ldrh r1, [r1]
	22954	+ ldr r3, [sp, #12]
	22955	+ mla r0, lr, r0, ip
	22956	+ mul r1, r6, r1
	22957	+ sub r1, r1, r7
	22958	+ add r1, r3, r1, lsl #9
	22959	+ b .L3711
	22960	+.L3661:
	22961	+ ldr r3, [sp, #16]
	22962	+ cmp r3, #0
	22963	+ beq .L3673
	22964	+ ldr r2, [r10, #-1512]
	22965	+ ldr r1, [r10, #-1480]
	22966	+ ldr r3, [sp, #4]
	22967	+ mla fp, fp, r2, r1
	22968	+ ldrh r2, [r3, #-12]
	22969	+ ldr r3, [sp, #12]
	22970	+ mul r2, r6, r2
	22971	+ sub r2, r2, r7
	22972	+ add r2, r3, r2, lsl #9
	22973	+ str r2, [fp, #8]
	22974	+ b .L3667
	22975	+.L3673:
	22976	+ ldr r3, [sp, #4]
	22977	+ ldr r2, [r10, #-1512]
	22978	+ ldr r0, [r10, #-1480]
	22979	+ ldrh r1, [r3, #-12]
	22980	+ mla fp, fp, r2, r0
	22981	+ ldrh r2, [r3, #-8]
	22982	+ ldr r3, [sp, #12]
	22983	+ mul r1, r6, r1
	22984	+ ldr r0, [fp, #8]
	22985	+ sub r1, r1, r7
	22986	+ add r1, r3, r1, lsl #9
	22987	+ b .L3708
	22988	+.L3677:
	22989	+ bl FtlCacheWriteBack
	22990	+ cmp r8, #1
	22991	+ mov r2, #0
	22992	+ str r2, [r10, #-1512]
	22993	+ bhi .L3652
	22994	+ b .L3679
	22995	+.L3688:
22668	22996	mvn r0, #0
22669		- b .L3724
22670		-.L3764:
22671		- mov r0, #0
22672		-.L3724:
22673		- add sp, sp, #100
22674		- @ sp needed
22675		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
22676		-.L3798:
	22997	+ b .L3644
	22998	+.L3713:
22677	22999	.align 2
22678		-.L3797:
	23000	+.L3712:
22679	23001	.word .LANCHOR2
22680	23002	.word .LANCHOR1
22681		- .word .LANCHOR4
22682	23003	.word .LANCHOR2+884
22683		- .word .LANCHOR2+932
22684		- .word .LANCHOR2-1662
22685		- .word .LANCHOR2-1656
22686		- .word .LANCHOR2-1658
22687		- .word .LC165
22688		- .word -3947
22689	23004	.word .LANCHOR2+880
22690	23005	.word .LANCHOR0
22691		- .word .LANCHOR2-1540
22692		- .word .LANCHOR4+1164
22693		- .word .LANCHOR2-1530
	23006	+ .word .LANCHOR2+1156
	23007	+ .word .LANCHOR2-1536
	23008	+ .word .LANCHOR2-1660
	23009	+ .word -3947
	23010	+ .word .LC165
22694	23011	.fnend
22695	23012	.size ftl_write, .-ftl_write
22696	23013	.align 2
22697	23014	.global ftl_vendor_write
	23015	+ .syntax unified
	23016	+ .arm
	23017	+ .fpu softvfp
22698	23018	.type ftl_vendor_write, %function
22699	23019	ftl_vendor_write:
22700	23020	.fnstart
22701	23021	@ args = 0, pretend = 0, frame = 0
22702	23022	@ frame_needed = 0, uses_anonymous_args = 0
22703		- str lr, [sp, #-4]!
22704		- .save {lr}
22705		- mov ip, r1
22706		- mov lr, r0
	23023	+ @ link register save eliminated.
22707	23024	mov r3, r2
22708		- mov r1, lr
	23025	+ mov r2, r1
	23026	+ mov r1, r0
22709	23027	mov r0, #16
22710		- mov r2, ip
22711		- ldr lr, [sp], #4
22712	23028	b ftl_write
22713	23029	.fnend
22714	23030	.size ftl_vendor_write, .-ftl_vendor_write
22715	23031	.align 2
22716	23032	.global ftl_sys_write
	23033	+ .syntax unified
	23034	+ .arm
	23035	+ .fpu softvfp
22717	23036	.type ftl_sys_write, %function
22718	23037	ftl_sys_write:
22719	23038	.fnstart
22720	23039	@ args = 0, pretend = 0, frame = 0
22721	23040	@ frame_needed = 0, uses_anonymous_args = 0
22722	23041	@ link register save eliminated.
22723		- mov ip, r1
22724	23042	mov r3, r2
	23043	+ mov r2, r1
22725	23044	add r1, r0, #256
22726		- mov r2, ip
22727	23045	mov r0, #16
22728	23046	b ftl_write
22729	23047	.fnend
22730	23048	.size ftl_sys_write, .-ftl_sys_write
22731	23049	.align 2
22732	23050	.global ftl_fix_nand_power_lost_error
	23051	+ .syntax unified
	23052	+ .arm
	23053	+ .fpu softvfp
22733	23054	.type ftl_fix_nand_power_lost_error, %function
22734	23055	ftl_fix_nand_power_lost_error:
22735	23056	.fnstart
22736	23057	@ args = 0, pretend = 0, frame = 48
22737	23058	@ frame_needed = 0, uses_anonymous_args = 0
22738		- stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, lr}
22739		- .save {r4, r5, r6, r7, r8, r9, r10, fp, lr}
22740		- .pad #52
22741		- sub sp, sp, #52
22742		- ldr r4, .L3818
22743		- ldrb r3, [r4, #-2744] @ zero_extendqisi2
	23059	+ push {r4, r5, r6, r7, r8, r9, r10, lr}
	23060	+ .save {r4, r5, r6, r7, r8, r9, r10, lr}
	23061	+ .pad #48
	23062	+ sub sp, sp, #48
	23063	+ ldr r4, .L3731
	23064	+ ldrb r3, [r4, #-2740] @ zero_extendqisi2
22744	23065	cmp r3, #0
22745		- beq .L3802
22746		- ldr r8, .L3818+4
22747		- movw r3, #1802
22748		- add r9, r4, #884
	23066	+ beq .L3716
	23067	+ movw r3, #1794
	23068	+ add r8, r4, #884
	23069	+ ldrh r6, [r4, r3]
22749	23070	add r5, r4, #932
22750		- ldr r0, .L3818+8
22751		- ldrh r7, [r8, r3]
22752		- ldr r3, [r4, #-1408]
22753		- mov r6, r7, asl #1
22754		- mov r1, r7
22755		- ldrh r2, [r3, r6]
	23071	+ ldr r3, [r4, #-1404]
	23072	+ ldr r0, .L3731+4
	23073	+ mov r1, r6
	23074	+ lsl r7, r6, #1
	23075	+ ldrh r2, [r3, r7]
22756	23076	bl printk
22757		- ldrh r0, [r9]
	23077	+ ldrh r0, [r8]
22758	23078	bl FtlGcRefreshOpenBlock
22759	23079	ldrh r0, [r5]
22760	23080	bl FtlGcRefreshOpenBlock
22761		- mov r0, r9
	23081	+ mov r0, r8
22762	23082	bl allocate_new_data_superblock
22763	23083	mov r0, r5
22764		- bl allocate_new_data_superblock
22765	23084	movw r5, #4097
22766		-.L3804:
	23085	+ bl allocate_new_data_superblock
	23086	+.L3718:
22767	23087	subs r5, r5, #1
22768		- beq .L3808
22769		- mov r0, #1
22770		- mov r1, r0
	23088	+ beq .L3722
	23089	+ mov r1, #1
	23090	+ mov r0, r1
22771	23091	bl ftl_do_gc
22772		- ldr r3, [r4, #-1408]
22773		- ldrh r3, [r3, r6]
	23092	+ ldr r3, [r4, #-1404]
	23093	+ ldrh r3, [r3, r7]
22774	23094	cmp r3, #0
22775		- bne .L3804
22776		-.L3808:
22777		- ldr r3, [r4, #-1408]
22778		- mov r1, r7
22779		- ldr r0, .L3818+8
22780		- ldr r9, .L3818
22781		- ldrh r2, [r3, r6]
	23095	+ bne .L3718
	23096	+.L3722:
	23097	+ ldr r3, [r4, #-1404]
	23098	+ mov r1, r6
	23099	+ ldr r0, .L3731+4
	23100	+ ldrh r2, [r3, r7]
22782	23101	bl printk
22783		- ldr r3, [r4, #-1408]
22784		- ldrh r5, [r3, r6]
	23102	+ ldr r3, [r4, #-1404]
	23103	+ ldrh r5, [r3, r7]
22785	23104	cmp r5, #0
22786		- bne .L3806
	23105	+ bne .L3720
22787	23106	add r0, sp, #48
22788		- movw r10, #65535
22789		- mov fp, #36
22790		- strh r7, [r0, #-48]! @ movhi
	23107	+ movw r9, #65535
	23108	+ strh r6, [r0, #-48]! @ movhi
	23109	+ mov r10, #36
22791	23110	bl make_superblock
22792		- sub r3, r9, #1728
22793		- ldr r9, [r9, #-1492]
22794		- ldrh lr, [r3, #-8]
22795		- mov r3, r5
22796		- mov ip, r3
	23111	+ ldr r3, .L3731+8
22797	23112	add r0, sp, #14
22798		-.L3809:
22799		- uxth r2, r3
22800		- cmp r2, lr
22801		- bcs .L3817
22802		- ldrh r2, [r0, #2]!
22803		- add r3, r3, #1
22804		- cmp r2, r10
22805		- movne r2, r2, asl #10
22806		- mlane r1, fp, r5, r9
	23113	+ ldr r8, [r4, #-1488]
	23114	+ mov r2, r5
	23115	+ mov ip, r5
	23116	+ ldrh lr, [r3, #-4]
	23117	+.L3723:
	23118	+ uxth r3, r2
	23119	+ cmp lr, r3
	23120	+ bhi .L3725
	23121	+ ldr r3, [r4, #-1404]
	23122	+ mov r1, r6
	23123	+ ldr r0, .L3731+12
	23124	+ ldrh r2, [r3, r7]
	23125	+ bl printk
	23126	+ mov r2, r5
	23127	+ mov r1, #0
	23128	+ ldr r0, [r4, #-1488]
	23129	+ bl FlashEraseBlocks
	23130	+ mov r2, r5
	23131	+ mov r1, #1
	23132	+ ldr r0, [r4, #-1488]
	23133	+ bl FlashEraseBlocks
	23134	+.L3720:
	23135	+ mvn r2, #0
	23136	+ movw r3, #1794
	23137	+ strh r2, [r4, r3] @ movhi
	23138	+.L3716:
	23139	+ add sp, sp, #48
	23140	+ @ sp needed
	23141	+ pop {r4, r5, r6, r7, r8, r9, r10, pc}
	23142	+.L3725:
	23143	+ ldrh r3, [r0, #2]!
	23144	+ add r2, r2, #1
	23145	+ cmp r3, r9
	23146	+ mlane r1, r10, r5, r8
	23147	+ lslne r3, r3, #10
22807	23148	addne r5, r5, #1
22808	23149	uxthne r5, r5
22809		- stmneib r1, {r2, ip}
	23150	+ stmibne r1, {r3, ip}
22810	23151	strne ip, [r1, #12]
22811		- b .L3809
22812		-.L3817:
22813		- ldr r3, [r4, #-1408]
22814		- mov r1, r7
22815		- ldr r0, .L3818+12
22816		- ldrh r2, [r3, r6]
22817		- bl printk
22818		- mov r1, #0
22819		- mov r2, r5
22820		- ldr r0, [r4, #-1492]
22821		- bl FlashEraseBlocks
22822		- ldr r0, [r4, #-1492]
22823		- mov r1, #1
22824		- mov r2, r5
22825		- bl FlashEraseBlocks
22826		-.L3806:
22827		- movw r3, #1802
22828		- mvn r2, #0
22829		- strh r2, [r8, r3] @ movhi
22830		-.L3802:
22831		- add sp, sp, #52
22832		- @ sp needed
22833		- ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, fp, pc}
22834		-.L3819:
	23152	+ b .L3723
	23153	+.L3732:
22835	23154	.align 2
22836		-.L3818:
	23155	+.L3731:
22837	23156	.word .LANCHOR2
22838		- .word .LANCHOR4
22839	23157	.word .LC166
	23158	+ .word .LANCHOR2-1728
22840	23159	.word .LC167
22841	23160	.fnend
22842	23161	.size ftl_fix_nand_power_lost_error, .-ftl_fix_nand_power_lost_error
..	..	@@ -23068,13 +23387,7 @@
23068	23387	.global DieCsIndex
23069	23388	.global read_retry_cur_offset
23070	23389	.section .rodata
23071		- .align 2
23072		-.LANCHOR3 = . + 0
23073		-.LC0:
23074		- .byte 60
23075		- .byte 40
23076		- .byte 24
23077		- .byte 16
	23390	+ .set .LANCHOR3,. + 0
23078	23391	.type samsung_14nm_slc_rr, %object
23079	23392	.size samsung_14nm_slc_rr, 26
23080	23393	samsung_14nm_slc_rr:
..	..	@@ -23104,7 +23417,6 @@
23104	23417	.byte -125
23105	23418	.byte -115
23106	23419	.byte 100
23107		- .space 2
23108	23420	.type samsung_14nm_mlc_rr, %object
23109	23421	.size samsung_14nm_mlc_rr, 104
23110	23422	samsung_14nm_mlc_rr:
..	..	@@ -23212,390 +23524,37 @@
23212	23524	.byte 18
23213	23525	.byte 9
23214	23526	.byte 8
23215		- .type __func__.20378, %object
23216		- .size __func__.20378, 11
23217		-__func__.20378:
	23527	+ .type __func__.23800, %object
	23528	+ .size __func__.23800, 11
	23529	+__func__.23800:
23218	23530	.ascii "FtlMemInit\000"
23219		- .space 1
23220		- .type __func__.21125, %object
23221		- .size __func__.21125, 12
23222		-__func__.21125:
	23531	+ .type __func__.24547, %object
	23532	+ .size __func__.24547, 12
	23533	+__func__.24547:
23223	23534	.ascii "FtlCheckVpc\000"
23224		- .type __func__.21157, %object
23225		- .size __func__.21157, 17
23226		-__func__.21157:
	23535	+ .type __func__.24579, %object
	23536	+ .size __func__.24579, 17
	23537	+__func__.24579:
23227	23538	.ascii "FtlDumpBlockInfo\000"
23228		- .space 3
23229		- .type __func__.21176, %object
23230		- .size __func__.21176, 16
23231		-__func__.21176:
	23539	+ .type __func__.24598, %object
	23540	+ .size __func__.24598, 16
	23541	+__func__.24598:
23232	23542	.ascii "FtlScanAllBlock\000"
23233		- .type __func__.21444, %object
23234		- .size __func__.21444, 17
23235		-__func__.21444:
	23543	+ .type __func__.24866, %object
	23544	+ .size __func__.24866, 17
	23545	+__func__.24866:
23236	23546	.ascii "ftl_scan_all_ppa\000"
23237		- .space 3
23238		- .type __func__.21424, %object
23239		- .size __func__.21424, 21
23240		-__func__.21424:
	23547	+ .type __func__.24846, %object
	23548	+ .size __func__.24846, 21
	23549	+__func__.24846:
23241	23550	.ascii "FtlVpcCheckAndModify\000"
23242		- .space 3
23243		- .type __func__.20451, %object
23244		- .size __func__.20451, 8
23245		-__func__.20451:
	23551	+ .type __func__.23873, %object
	23552	+ .size __func__.23873, 8
	23553	+__func__.23873:
23246	23554	.ascii "FtlInit\000"
23247		- .section .rodata.str1.1,"aMS",%progbits,1
23248		-.LC1:
23249		- .ascii "FlashEraseBlocks pageAddr error %x\012\000"
23250		-.LC2:
23251		- .ascii "otp error! %d\000"
23252		-.LC3:
23253		- .ascii "rr\000"
23254		-.LC4:
23255		- .ascii "%d statReg->V6.mtrans_cnt=%d flReg.V6.page_num=%d\012"
23256		- .ascii "\000"
23257		-.LC5:
23258		- .ascii "nandc:\000"
23259		-.LC6:
23260		- .ascii "%d flReg.d32=%x %x\012\000"
23261		-.LC7:
23262		- .ascii "sdr read ok %x ecc=%d\012\000"
23263		-.LC8:
23264		- .ascii "sync para %d\012\000"
23265		-.LC9:
23266		- .ascii "TOG mode Read error %x %x\012\000"
23267		-.LC10:
23268		- .ascii "read retry status %x %x %x\012\000"
23269		-.LC11:
23270		- .ascii "micron RR %d row=%x,count %d,status=%d\012\000"
23271		-.LC12:
23272		- .ascii "samsung RR %d row=%x,count %d,status=%d\012\000"
23273		-.LC13:
23274		- .ascii "ECC:%d\012\000"
23275		-.LC14:
23276		- .ascii "No.%d FLASH ID:%x %x %x %x %x %x\012\000"
23277		-.LC15:
23278		- .ascii "FlashLoadPhyInfo fail %x!!\012\000"
23279		-.LC16:
23280		- .ascii "Read pageadd=%x ecc=%x err=%x\012\000"
23281		-.LC17:
23282		- .ascii "data:\000"
23283		-.LC18:
23284		- .ascii "spare:\000"
23285		-.LC19:
23286		- .ascii "ReadRetry pageadd=%x ecc=%x err=%x\012\000"
23287		-.LC20:
23288		- .ascii "FLFB:%d %d\012\000"
23289		-.LC21:
23290		- .ascii "BBT:\000"
23291		-.LC22:
23292		- .ascii "prog error: = %x\012\000"
23293		-.LC23:
23294		- .ascii "prog read error: = %x\012\000"
23295		-.LC24:
23296		- .ascii "prog read REFRESH: = %x\012\000"
23297		-.LC25:
23298		- .ascii "prog read s error: = %x %x %x\012\000"
23299		-.LC26:
23300		- .ascii "prog read d error: = %x %x %x\012\000"
23301		-.LC27:
23302		- .ascii "FlashMakeFactorBbt %d\012\000"
23303		-.LC28:
23304		- .ascii "bad block:%d %d\012\000"
23305		-.LC29:
23306		- .ascii "FMFB:%d %d\012\000"
23307		-.LC30:
23308		- .ascii "E:bad block:%d\012\000"
23309		-.LC31:
23310		- .ascii "FMFB:Save %d %d\012\000"
23311		-.LC32:
23312		- .ascii "%s error allocating memory. return -1\012\000"
23313		-.LC33:
23314		- .ascii "phyBlk = 0x%x die = %d block_in_die = 0x%x 0x%8x\012"
23315		- .ascii "\000"
23316		-.LC34:
23317		- .ascii "FtlBbmTblFlush id=%x,page=%x,previd=%x cnt=%d\012\000"
23318		-.LC35:
23319		- .ascii "FtlBbmTblFlush error:%x\012\000"
23320		-.LC36:
23321		- .ascii "FtlBbmTblFlush error = %x error count = %d\012\000"
23322		-.LC37:
23323		- .ascii "FtlFreeSysBlkQueueOut free count = %d\012\000"
23324		-.LC38:
23325		- .ascii "FtlFreeSysBlkQueueOut = %x, free count = %d, error\012"
23326		- .ascii "\000"
23327		-.LC39:
23328		- .ascii "FtlFreeSysBlkQueueOut = %x, free count = %d\012\000"
23329		-.LC40:
23330		- .ascii "FtlMapWritePage error = %x\012\000"
23331		-.LC41:
23332		- .ascii "FtlMapWritePage error = %x error count = %d\012\000"
23333		-.LC42:
23334		- .ascii "page map lost: %x %x\012\000"
23335		-.LC43:
23336		- .ascii "region_id = %x phyAddr = %x\012\000"
23337		-.LC44:
23338		- .ascii "map_ppn:\000"
23339		-.LC45:
23340		- .ascii "load_l2p_region refresh = %x phyAddr = %x\012\000"
23341		-.LC46:
23342		- .ascii "FtlVendorPartRead refresh = %x phyAddr = %x\012\000"
23343		-.LC47:
23344		- .ascii "FtlVpcTblFlush error = %x error count = %d\012\000"
23345		-.LC48:
23346		- .ascii "%s\012\000"
23347		-.LC49:
23348		- .ascii "no ect\000"
23349		-.LC50:
23350		- .ascii "...%s enter...\012\000"
23351		-.LC51:
23352		- .ascii "FtlCheckVpc2 %x = %x %x\012\000"
23353		-.LC52:
23354		- .ascii "free blk vpc error %x = %x %x\012\000"
23355		-.LC53:
23356		- .ascii "error_flag %x\012\000"
23357		-.LC54:
23358		- .ascii "id = %x,%x addr= %x,spare= %x %x %x %x data = %x\012"
23359		- .ascii "\000"
23360		-.LC55:
23361		- .ascii ":\000"
23362		-.LC56:
23363		- .ascii "Ftlscanalldata = %x\012\000"
23364		-.LC57:
23365		- .ascii "scan lpa = %x ppa= %x\012\000"
23366		-.LC58:
23367		- .ascii "lba = %x,addr= %x,spare= %x %x %x %x data=%x %x\012"
23368		- .ascii "\000"
23369		-.LC59:
23370		- .ascii "phyBlk = %x,addr= %x,spare= %x %x %x %x data=%x %x\012"
23371		- .ascii "\000"
23372		-.LC60:
23373		- .ascii "id = %x,%x addr= %x,spare= %x %x %x %x data=%x %x\012"
23374		- .ascii "\000"
23375		-.LC61:
23376		- .ascii "Mblk:\000"
23377		-.LC62:
23378		- .ascii "L2P:\000"
23379		-.LC63:
23380		- .ascii "L2PC:\000"
23381		-.LC64:
23382		- .ascii "id = %x,%x addr= %x,spare= %x %x %x %x data= %x\012"
23383		- .ascii "\000"
23384		-.LC65:
23385		- .ascii "superBlkID = %x vpc=%x\012\000"
23386		-.LC66:
23387		- .ascii "flashmode = %x pagenum = %x %x\012\000"
23388		-.LC67:
23389		- .ascii "blk = %x vpc=%x mode = %x\012\000"
23390		-.LC68:
23391		- .ascii "mlc id = %x,%x addr= %x,spare= %x %x %x %x data=%x "
23392		- .ascii "%x\012\000"
23393		-.LC69:
23394		- .ascii "slc id = %x,%x addr= %x,spare= %x %x %x %x data=%x "
23395		- .ascii "%x\012\000"
23396		-.LC70:
23397		- .ascii "slc mode\000"
23398		-.LC71:
23399		- .ascii "ftl_scan_all_ppa blk %x page %x flag: %x\012\000"
23400		-.LC72:
23401		- .ascii "ftl_scan_all_ppa blk %x page %x flag: %x .........."
23402		- .ascii "..... is bad block\012\000"
23403		-.LC73:
23404		- .ascii "addr= %x, status= %d,spare= %x %x %x %x data=%x %x\012"
23405		- .ascii "\000"
23406		-.LC74:
23407		- .ascii "%s finished\012\000"
23408		-.LC75:
23409		- .ascii "FLASH INFO:\012\000"
23410		-.LC76:
23411		- .ascii "FLASH ID: %x\012\000"
23412		-.LC77:
23413		- .ascii "Device Capacity: %d MB\012\000"
23414		-.LC78:
23415		- .ascii "FMWAIT: %x %x %x %x\012\000"
23416		-.LC79:
23417		- .ascii "FTL INFO:\012\000"
23418		-.LC80:
23419		- .ascii "g_MaxLpn = 0x%x\012\000"
23420		-.LC81:
23421		- .ascii "g_VaildLpn = 0x%x\012\000"
23422		-.LC82:
23423		- .ascii "read_page_count = 0x%x\012\000"
23424		-.LC83:
23425		- .ascii "discard_page_count = 0x%x\012\000"
23426		-.LC84:
23427		- .ascii "write_page_count = 0x%x\012\000"
23428		-.LC85:
23429		- .ascii "cache_write_count = 0x%x\012\000"
23430		-.LC86:
23431		- .ascii "l2p_write_count = 0x%x\012\000"
23432		-.LC87:
23433		- .ascii "gc_page_count = 0x%x\012\000"
23434		-.LC88:
23435		- .ascii "totle_write = %d MB\012\000"
23436		-.LC89:
23437		- .ascii "totle_read = %d MB\012\000"
23438		-.LC90:
23439		- .ascii "GSV = 0x%x\012\000"
23440		-.LC91:
23441		- .ascii "GDV = 0x%x\012\000"
23442		-.LC92:
23443		- .ascii "bad blk num = %d %d\012\000"
23444		-.LC93:
23445		- .ascii "free_superblocks = 0x%x\012\000"
23446		-.LC94:
23447		- .ascii "mlc_EC = 0x%x\012\000"
23448		-.LC95:
23449		- .ascii "slc_EC = 0x%x\012\000"
23450		-.LC96:
23451		- .ascii "avg_EC = 0x%x\012\000"
23452		-.LC97:
23453		- .ascii "sys_EC = 0x%x\012\000"
23454		-.LC98:
23455		- .ascii "max_EC = 0x%x\012\000"
23456		-.LC99:
23457		- .ascii "min_EC = 0x%x\012\000"
23458		-.LC100:
23459		- .ascii "PLT = 0x%x\012\000"
23460		-.LC101:
23461		- .ascii "POT = 0x%x\012\000"
23462		-.LC102:
23463		- .ascii "MaxSector = 0x%x\012\000"
23464		-.LC103:
23465		- .ascii "init_sys_blks_pp = 0x%x\012\000"
23466		-.LC104:
23467		- .ascii "sys_blks_pp = 0x%x\012\000"
23468		-.LC105:
23469		- .ascii "free sysblock = 0x%x\012\000"
23470		-.LC106:
23471		- .ascii "data_blks_pp = 0x%x\012\000"
23472		-.LC107:
23473		- .ascii "data_op_blks_pp = 0x%x\012\000"
23474		-.LC108:
23475		- .ascii "max_data_blks = 0x%x\012\000"
23476		-.LC109:
23477		- .ascii "Sys.id = 0x%x\012\000"
23478		-.LC110:
23479		- .ascii "Bbt.id = 0x%x\012\000"
23480		-.LC111:
23481		- .ascii "ACT.page = 0x%x\012\000"
23482		-.LC112:
23483		- .ascii "ACT.plane = 0x%x\012\000"
23484		-.LC113:
23485		- .ascii "ACT.id = 0x%x\012\000"
23486		-.LC114:
23487		- .ascii "ACT.mode = 0x%x\012\000"
23488		-.LC115:
23489		- .ascii "ACT.a_pages = 0x%x\012\000"
23490		-.LC116:
23491		- .ascii "ACT VPC = 0x%x\012\000"
23492		-.LC117:
23493		- .ascii "BUF.page = 0x%x\012\000"
23494		-.LC118:
23495		- .ascii "BUF.plane = 0x%x\012\000"
23496		-.LC119:
23497		- .ascii "BUF.id = 0x%x\012\000"
23498		-.LC120:
23499		- .ascii "BUF.mode = 0x%x\012\000"
23500		-.LC121:
23501		- .ascii "BUF.a_pages = 0x%x\012\000"
23502		-.LC122:
23503		- .ascii "BUF VPC = 0x%x\012\000"
23504		-.LC123:
23505		- .ascii "TMP.page = 0x%x\012\000"
23506		-.LC124:
23507		- .ascii "TMP.plane = 0x%x\012\000"
23508		-.LC125:
23509		- .ascii "TMP.id = 0x%x\012\000"
23510		-.LC126:
23511		- .ascii "TMP.mode = 0x%x\012\000"
23512		-.LC127:
23513		- .ascii "TMP.a_pages = 0x%x\012\000"
23514		-.LC128:
23515		- .ascii "GC.page = 0x%x\012\000"
23516		-.LC129:
23517		- .ascii "GC.plane = 0x%x\012\000"
23518		-.LC130:
23519		- .ascii "GC.id = 0x%x\012\000"
23520		-.LC131:
23521		- .ascii "GC.mode = 0x%x\012\000"
23522		-.LC132:
23523		- .ascii "GC.a_pages = 0x%x\012\000"
23524		-.LC133:
23525		- .ascii "WR_CHK = 0x%x %x %x %x\012\000"
23526		-.LC134:
23527		- .ascii "Read Err = 0x%x\012\000"
23528		-.LC135:
23529		- .ascii "Prog Err = 0x%x\012\000"
23530		-.LC136:
23531		- .ascii "gc_free_blk_th= 0x%x\012\000"
23532		-.LC137:
23533		- .ascii "gc_merge_free_blk_th= 0x%x\012\000"
23534		-.LC138:
23535		- .ascii "gc_skip_write_count= 0x%x\012\000"
23536		-.LC139:
23537		- .ascii "gc_blk_index= 0x%x\012\000"
23538		-.LC140:
23539		- .ascii "free min EC= 0x%x\012\000"
23540		-.LC141:
23541		- .ascii "free max EC= 0x%x\012\000"
23542		-.LC142:
23543		- .ascii "GC__SB VPC = 0x%x\012\000"
23544		-.LC143:
23545		- .ascii "%d. [0x%x]=0x%x 0x%x 0x%x\012\000"
23546		-.LC144:
23547		- .ascii "free %d. [0x%x] 0x%x 0x%x\012\000"
23548		-.LC145:
23549		- .ascii "FTL version: 5.0.63 20200923\000"
23550		-.LC146:
23551		- .ascii "swblk %x ,avg = %x max= %x vpc= %x,ec=%x ,max ec=%x"
23552		- .ascii "\012\000"
23553		-.LC147:
23554		- .ascii "FtlGcScanTempBlk Error ID %x %x!!!!!!! \012\000"
23555		-.LC148:
23556		- .ascii "FtlGcScanTempBlkError ID %x %x!!!!!!!\012\000"
23557		-.LC149:
23558		- .ascii "FtlGcRefreshBlock 0x%x\012\000"
23559		-.LC150:
23560		- .ascii "FtlGcMarkBadPhyBlk %d 0x%x\012\000"
23561		-.LC151:
23562		- .ascii "FtlGcFreeBadSuperBlk 0x%x\012\000"
23563		-.LC152:
23564		- .ascii "decrement_vpc_count %x = %d\012\000"
23565		-.LC153:
23566		- .ascii "decrement_vpc_count %x = %d in free list\012\000"
23567		-.LC154:
23568		- .ascii "RSB refresh addr %x\012\000"
23569		-.LC155:
23570		- .ascii "spuer block %x vpn is 0\012 \000"
23571		-.LC156:
23572		- .ascii "g_recovery_ppa %x ver %x\012 \000"
23573		-.LC157:
23574		- .ascii "FtlCheckVpc %x = %x %x\012\000"
23575		-.LC158:
23576		- .ascii "%d GC datablk = %x vpc %x %x\012\000"
23577		-.LC159:
23578		- .ascii "SWL %x, FSB = %x vpc= %x,ec=%x th=%x\012\000"
23579		-.LC160:
23580		- .ascii "Ftlwrite decrement_vpc_count %x = %d\012\000"
23581		-.LC161:
23582		- .ascii "GC des block %x done\012\000"
23583		-.LC162:
23584		- .ascii "too many bad block = %d %d\012\000"
23585		-.LC163:
23586		- .ascii "...%s: no bad block mapping table, format device\012"
23587		- .ascii "\000"
23588		-.LC164:
23589		- .ascii "...%s FtlSysBlkInit error ,format device!\012\000"
23590		-.LC165:
23591		- .ascii "FtlWrite: lpa error:%x %x\012\000"
23592		-.LC166:
23593		- .ascii "fix power lost blk = %x vpc=%x\012\000"
23594		-.LC167:
23595		- .ascii "erase power lost blk = %x vpc=%x\012\000"
23596	23555	.data
23597	23556	.align 2
23598		-.LANCHOR1 = . + 0
	23557	+ .set .LANCHOR1,. + 0
23599	23558	.type random_seed, %object
23600	23559	.size random_seed, 256
23601	23560	random_seed:
..	..	@@ -23727,6 +23686,230 @@
23727	23686	.short 28406
23728	23687	.short 17598
23729	23688	.short 28087
	23689	+ .type ToshibaA19RefValue, %object
	23690	+ .size ToshibaA19RefValue, 45
	23691	+ToshibaA19RefValue:
	23692	+ .byte 4
	23693	+ .byte 5
	23694	+ .byte 6
	23695	+ .byte 7
	23696	+ .byte 13
	23697	+ .byte 0
	23698	+ .byte 0
	23699	+ .byte 0
	23700	+ .byte 0
	23701	+ .byte 0
	23702	+ .byte 4
	23703	+ .byte 4
	23704	+ .byte 124
	23705	+ .byte 126
	23706	+ .byte 0
	23707	+ .byte 0
	23708	+ .byte 124
	23709	+ .byte 120
	23710	+ .byte 120
	23711	+ .byte 0
	23712	+ .byte 124
	23713	+ .byte 118
	23714	+ .byte 116
	23715	+ .byte 114
	23716	+ .byte 0
	23717	+ .byte 8
	23718	+ .byte 8
	23719	+ .byte 0
	23720	+ .byte 0
	23721	+ .byte 0
	23722	+ .byte 11
	23723	+ .byte 126
	23724	+ .byte 118
	23725	+ .byte 116
	23726	+ .byte 0
	23727	+ .byte 16
	23728	+ .byte 118
	23729	+ .byte 114
	23730	+ .byte 112
	23731	+ .byte 0
	23732	+ .byte 2
	23733	+ .byte 0
	23734	+ .byte 126
	23735	+ .byte 124
	23736	+ .byte 0
	23737	+ .type Toshiba15RefValue, %object
	23738	+ .size Toshiba15RefValue, 95
	23739	+Toshiba15RefValue:
	23740	+ .byte 4
	23741	+ .byte 5
	23742	+ .byte 6
	23743	+ .byte 7
	23744	+ .byte 13
	23745	+ .byte 0
	23746	+ .byte 0
	23747	+ .byte 0
	23748	+ .byte 0
	23749	+ .byte 0
	23750	+ .byte 0
	23751	+ .byte 0
	23752	+ .byte 0
	23753	+ .byte 0
	23754	+ .byte 0
	23755	+ .byte 2
	23756	+ .byte 4
	23757	+ .byte 2
	23758	+ .byte 0
	23759	+ .byte 0
	23760	+ .byte 8
	23761	+ .byte 8
	23762	+ .byte 0
	23763	+ .byte 0
	23764	+ .byte 0
	23765	+ .byte 124
	23766	+ .byte 0
	23767	+ .byte 124
	23768	+ .byte 124
	23769	+ .byte 0
	23770	+ .byte 122
	23771	+ .byte 0
	23772	+ .byte 122
	23773	+ .byte 122
	23774	+ .byte 0
	23775	+ .byte 11
	23776	+ .byte 126
	23777	+ .byte 118
	23778	+ .byte 116
	23779	+ .byte 0
	23780	+ .byte 120
	23781	+ .byte 2
	23782	+ .byte 120
	23783	+ .byte 122
	23784	+ .byte 0
	23785	+ .byte 126
	23786	+ .byte 4
	23787	+ .byte 126
	23788	+ .byte 122
	23789	+ .byte 0
	23790	+ .byte 16
	23791	+ .byte 118
	23792	+ .byte 114
	23793	+ .byte 112
	23794	+ .byte 0
	23795	+ .byte 118
	23796	+ .byte 4
	23797	+ .byte 118
	23798	+ .byte 120
	23799	+ .byte 0
	23800	+ .byte 4
	23801	+ .byte 4
	23802	+ .byte 4
	23803	+ .byte 118
	23804	+ .byte 0
	23805	+ .byte 2
	23806	+ .byte 0
	23807	+ .byte 126
	23808	+ .byte 124
	23809	+ .byte 0
	23810	+ .byte 6
	23811	+ .byte 10
	23812	+ .byte 6
	23813	+ .byte 2
	23814	+ .byte 0
	23815	+ .byte 116
	23816	+ .byte 124
	23817	+ .byte 116
	23818	+ .byte 118
	23819	+ .byte 0
	23820	+ .byte 4
	23821	+ .byte 4
	23822	+ .byte 124
	23823	+ .byte 126
	23824	+ .byte 0
	23825	+ .byte 0
	23826	+ .byte 124
	23827	+ .byte 120
	23828	+ .byte 120
	23829	+ .byte 0
	23830	+ .byte 124
	23831	+ .byte 118
	23832	+ .byte 116
	23833	+ .byte 114
	23834	+ .byte 0
	23835	+ .type ToshibaRefValue, %object
	23836	+ .size ToshibaRefValue, 8
	23837	+ToshibaRefValue:
	23838	+ .byte 0
	23839	+ .byte 4
	23840	+ .byte 124
	23841	+ .byte 120
	23842	+ .byte 116
	23843	+ .byte 8
	23844	+ .byte 12
	23845	+ .byte 112
	23846	+ .type SamsungRefValue, %object
	23847	+ .size SamsungRefValue, 64
	23848	+SamsungRefValue:
	23849	+ .byte -89
	23850	+ .byte -92
	23851	+ .byte -91
	23852	+ .byte -90
	23853	+ .byte 0
	23854	+ .byte 0
	23855	+ .byte 0
	23856	+ .byte 0
	23857	+ .byte 5
	23858	+ .byte 10
	23859	+ .byte 0
	23860	+ .byte 0
	23861	+ .byte 40
	23862	+ .byte 0
	23863	+ .byte -20
	23864	+ .byte -40
	23865	+ .byte -19
	23866	+ .byte -11
	23867	+ .byte -19
	23868	+ .byte -26
	23869	+ .byte 10
	23870	+ .byte 15
	23871	+ .byte 5
	23872	+ .byte 0
	23873	+ .byte 15
	23874	+ .byte 10
	23875	+ .byte -5
	23876	+ .byte -20
	23877	+ .byte -24
	23878	+ .byte -17
	23879	+ .byte -24
	23880	+ .byte -36
	23881	+ .byte -15
	23882	+ .byte -5
	23883	+ .byte -2
	23884	+ .byte -16
	23885	+ .byte 10
	23886	+ .byte 0
	23887	+ .byte -5
	23888	+ .byte -20
	23889	+ .byte -48
	23890	+ .byte -30
	23891	+ .byte -48
	23892	+ .byte -62
	23893	+ .byte 20
	23894	+ .byte 15
	23895	+ .byte -5
	23896	+ .byte -20
	23897	+ .byte -24
	23898	+ .byte -5
	23899	+ .byte -24
	23900	+ .byte -36
	23901	+ .byte 30
	23902	+ .byte 20
	23903	+ .byte -5
	23904	+ .byte -20
	23905	+ .byte -5
	23906	+ .byte -1
	23907	+ .byte -5
	23908	+ .byte -8
	23909	+ .byte 7
	23910	+ .byte 12
	23911	+ .byte 2
	23912	+ .byte 0
23730	23913	.type gNandParaInfo, %object
23731	23914	.size gNandParaInfo, 32
23732	23915	gNandParaInfo:
..	..	@@ -26070,232 +26253,6 @@
26070	26253	.byte 0
26071	26254	.byte 0
26072	26255	.space 14
26073		- .type ToshibaA19RefValue, %object
26074		- .size ToshibaA19RefValue, 45
26075		-ToshibaA19RefValue:
26076		- .byte 4
26077		- .byte 5
26078		- .byte 6
26079		- .byte 7
26080		- .byte 13
26081		- .byte 0
26082		- .byte 0
26083		- .byte 0
26084		- .byte 0
26085		- .byte 0
26086		- .byte 4
26087		- .byte 4
26088		- .byte 124
26089		- .byte 126
26090		- .byte 0
26091		- .byte 0
26092		- .byte 124
26093		- .byte 120
26094		- .byte 120
26095		- .byte 0
26096		- .byte 124
26097		- .byte 118
26098		- .byte 116
26099		- .byte 114
26100		- .byte 0
26101		- .byte 8
26102		- .byte 8
26103		- .byte 0
26104		- .byte 0
26105		- .byte 0
26106		- .byte 11
26107		- .byte 126
26108		- .byte 118
26109		- .byte 116
26110		- .byte 0
26111		- .byte 16
26112		- .byte 118
26113		- .byte 114
26114		- .byte 112
26115		- .byte 0
26116		- .byte 2
26117		- .byte 0
26118		- .byte 126
26119		- .byte 124
26120		- .byte 0
26121		- .space 3
26122		- .type Toshiba15RefValue, %object
26123		- .size Toshiba15RefValue, 95
26124		-Toshiba15RefValue:
26125		- .byte 4
26126		- .byte 5
26127		- .byte 6
26128		- .byte 7
26129		- .byte 13
26130		- .byte 0
26131		- .byte 0
26132		- .byte 0
26133		- .byte 0
26134		- .byte 0
26135		- .byte 0
26136		- .byte 0
26137		- .byte 0
26138		- .byte 0
26139		- .byte 0
26140		- .byte 2
26141		- .byte 4
26142		- .byte 2
26143		- .byte 0
26144		- .byte 0
26145		- .byte 8
26146		- .byte 8
26147		- .byte 0
26148		- .byte 0
26149		- .byte 0
26150		- .byte 124
26151		- .byte 0
26152		- .byte 124
26153		- .byte 124
26154		- .byte 0
26155		- .byte 122
26156		- .byte 0
26157		- .byte 122
26158		- .byte 122
26159		- .byte 0
26160		- .byte 11
26161		- .byte 126
26162		- .byte 118
26163		- .byte 116
26164		- .byte 0
26165		- .byte 120
26166		- .byte 2
26167		- .byte 120
26168		- .byte 122
26169		- .byte 0
26170		- .byte 126
26171		- .byte 4
26172		- .byte 126
26173		- .byte 122
26174		- .byte 0
26175		- .byte 16
26176		- .byte 118
26177		- .byte 114
26178		- .byte 112
26179		- .byte 0
26180		- .byte 118
26181		- .byte 4
26182		- .byte 118
26183		- .byte 120
26184		- .byte 0
26185		- .byte 4
26186		- .byte 4
26187		- .byte 4
26188		- .byte 118
26189		- .byte 0
26190		- .byte 2
26191		- .byte 0
26192		- .byte 126
26193		- .byte 124
26194		- .byte 0
26195		- .byte 6
26196		- .byte 10
26197		- .byte 6
26198		- .byte 2
26199		- .byte 0
26200		- .byte 116
26201		- .byte 124
26202		- .byte 116
26203		- .byte 118
26204		- .byte 0
26205		- .byte 4
26206		- .byte 4
26207		- .byte 124
26208		- .byte 126
26209		- .byte 0
26210		- .byte 0
26211		- .byte 124
26212		- .byte 120
26213		- .byte 120
26214		- .byte 0
26215		- .byte 124
26216		- .byte 118
26217		- .byte 116
26218		- .byte 114
26219		- .byte 0
26220		- .space 1
26221		- .type ToshibaRefValue, %object
26222		- .size ToshibaRefValue, 8
26223		-ToshibaRefValue:
26224		- .byte 0
26225		- .byte 4
26226		- .byte 124
26227		- .byte 120
26228		- .byte 116
26229		- .byte 8
26230		- .byte 12
26231		- .byte 112
26232		- .type SamsungRefValue, %object
26233		- .size SamsungRefValue, 64
26234		-SamsungRefValue:
26235		- .byte -89
26236		- .byte -92
26237		- .byte -91
26238		- .byte -90
26239		- .byte 0
26240		- .byte 0
26241		- .byte 0
26242		- .byte 0
26243		- .byte 5
26244		- .byte 10
26245		- .byte 0
26246		- .byte 0
26247		- .byte 40
26248		- .byte 0
26249		- .byte -20
26250		- .byte -40
26251		- .byte -19
26252		- .byte -11
26253		- .byte -19
26254		- .byte -26
26255		- .byte 10
26256		- .byte 15
26257		- .byte 5
26258		- .byte 0
26259		- .byte 15
26260		- .byte 10
26261		- .byte -5
26262		- .byte -20
26263		- .byte -24
26264		- .byte -17
26265		- .byte -24
26266		- .byte -36
26267		- .byte -15
26268		- .byte -5
26269		- .byte -2
26270		- .byte -16
26271		- .byte 10
26272		- .byte 0
26273		- .byte -5
26274		- .byte -20
26275		- .byte -48
26276		- .byte -30
26277		- .byte -48
26278		- .byte -62
26279		- .byte 20
26280		- .byte 15
26281		- .byte -5
26282		- .byte -20
26283		- .byte -24
26284		- .byte -5
26285		- .byte -24
26286		- .byte -36
26287		- .byte 30
26288		- .byte 20
26289		- .byte -5
26290		- .byte -20
26291		- .byte -5
26292		- .byte -1
26293		- .byte -5
26294		- .byte -8
26295		- .byte 7
26296		- .byte 12
26297		- .byte 2
26298		- .byte 0
26299	26256	.type refValueDefault, %object
26300	26257	.size refValueDefault, 28
26301	26258	refValueDefault:
..	..	@@ -26371,9 +26328,16 @@
26371	26328	.word 1
26372	26329	.bss
26373	26330	.align 2
26374		-.LANCHOR0 = . + 0
26375		-.LANCHOR2 = . + 8184
26376		-.LANCHOR4 = . + 16368
	26331	+ .set .LANCHOR0,. + 0
	26332	+ .set .LANCHOR2,. + 8184
	26333	+ .type gNandChipMap, %object
	26334	+ .size gNandChipMap, 32
	26335	+gNandChipMap:
	26336	+ .space 32
	26337	+ .type p_blk_mode_table, %object
	26338	+ .size p_blk_mode_table, 4
	26339	+p_blk_mode_table:
	26340	+ .space 4
26377	26341	.type g_slc2KBNand, %object
26378	26342	.size g_slc2KBNand, 1
26379	26343	g_slc2KBNand:
..	..	@@ -26392,10 +26356,6 @@
26392	26356	gNandRandomizer:
26393	26357	.space 1
26394	26358	.space 3
26395		- .type gNandChipMap, %object
26396		- .size gNandChipMap, 32
26397		-gNandChipMap:
26398		- .space 32
26399	26359	.type gpNandParaInfo, %object
26400	26360	.size gpNandParaInfo, 4
26401	26361	gpNandParaInfo:
..	..	@@ -26618,11 +26578,11 @@
26618	26578	.size gMultiPageReadEn, 1
26619	26579	gMultiPageReadEn:
26620	26580	.space 1
26621		- .space 2
26622	26581	.type FbbtBlk, %object
26623	26582	.size FbbtBlk, 16
26624	26583	FbbtBlk:
26625	26584	.space 16
	26585	+ .space 2
26626	26586	.type c_ftl_nand_sys_blks_per_plane, %object
26627	26587	.size c_ftl_nand_sys_blks_per_plane, 4
26628	26588	c_ftl_nand_sys_blks_per_plane:
..	..	@@ -26663,7 +26623,6 @@
26663	26623	.type c_ftl_nand_planes_per_die, %object
26664	26624	.size c_ftl_nand_planes_per_die, 2
26665	26625	c_ftl_nand_planes_per_die:
26666		- .space 2
26667	26626	.space 2
26668	26627	.type p_plane_order_table, %object
26669	26628	.size p_plane_order_table, 32
..	..	@@ -26716,6 +26675,7 @@
26716	26675	.type c_ftl_nand_reserved_blks, %object
26717	26676	.size c_ftl_nand_reserved_blks, 2
26718	26677	c_ftl_nand_reserved_blks:
	26678	+ .space 2
26719	26679	.space 2
26720	26680	.type DeviceCapacity, %object
26721	26681	.size DeviceCapacity, 4
..	..	@@ -27007,10 +26967,6 @@
27007	26967	.size p_map_block_valid_page_count, 4
27008	26968	p_map_block_valid_page_count:
27009	26969	.space 4
27010		- .type p_blk_mode_table, %object
27011		- .size p_blk_mode_table, 4
27012		-p_blk_mode_table:
27013		- .space 4
27014	26970	.type p_vendor_block_table, %object
27015	26971	.size p_vendor_block_table, 4
27016	26972	p_vendor_block_table:
..	..	@@ -27150,10 +27106,6 @@
27150	27106	g_totle_map_block:
27151	27107	.space 2
27152	27108	.space 2
27153		- .type check_valid_page_count_table, %object
27154		- .size check_valid_page_count_table, 8192
27155		-check_valid_page_count_table:
27156		- .space 8192
27157	27109	.type g_MaxLbn, %object
27158	27110	.size g_MaxLbn, 4
27159	27111	g_MaxLbn:
..	..	@@ -27275,6 +27227,10 @@
27275	27227	.size last_cache_match_count, 4
27276	27228	last_cache_match_count:
27277	27229	.space 4
	27230	+ .type check_valid_page_count_table, %object
	27231	+ .size check_valid_page_count_table, 8192
	27232	+check_valid_page_count_table:
	27233	+ .space 8192
27278	27234	.type g_gc_refresh_block_temp_tbl, %object
27279	27235	.size g_gc_refresh_block_temp_tbl, 34
27280	27236	g_gc_refresh_block_temp_tbl:
..	..	@@ -27304,3 +27260,352 @@
27304	27260	.size gFlashSdrModeEn, 1
27305	27261	gFlashSdrModeEn:
27306	27262	.space 1
	27263	+ .section .rodata.str1.1,"aMS",%progbits,1
	27264	+.LC1:
	27265	+ .ascii "FlashEraseBlocks pageAddr error %x\012\000"
	27266	+.LC2:
	27267	+ .ascii "otp error! %d\000"
	27268	+.LC3:
	27269	+ .ascii "rr\000"
	27270	+.LC4:
	27271	+ .ascii "%d statReg->V6.mtrans_cnt=%d flReg.V6.page_num=%d\012"
	27272	+ .ascii "\000"
	27273	+.LC5:
	27274	+ .ascii "nandc:\000"
	27275	+.LC6:
	27276	+ .ascii "%d flReg.d32=%x %x\012\000"
	27277	+.LC7:
	27278	+ .ascii "sdr read ok %x ecc=%d\012\000"
	27279	+.LC8:
	27280	+ .ascii "sync para %d\012\000"
	27281	+.LC9:
	27282	+ .ascii "TOG mode Read error %x %x\012\000"
	27283	+.LC10:
	27284	+ .ascii "read retry status %x %x %x\012\000"
	27285	+.LC11:
	27286	+ .ascii "micron RR %d row=%x,count %d,status=%d\012\000"
	27287	+.LC12:
	27288	+ .ascii "samsung RR %d row=%x,count %d,status=%d\012\000"
	27289	+.LC13:
	27290	+ .ascii "ECC:%d\012\000"
	27291	+.LC14:
	27292	+ .ascii "No.%d FLASH ID:%x %x %x %x %x %x\012\000"
	27293	+.LC15:
	27294	+ .ascii "FlashLoadPhyInfo fail %x!!\012\000"
	27295	+.LC16:
	27296	+ .ascii "Read pageadd=%x ecc=%x err=%x\012\000"
	27297	+.LC17:
	27298	+ .ascii "data:\000"
	27299	+.LC18:
	27300	+ .ascii "spare:\000"
	27301	+.LC19:
	27302	+ .ascii "ReadRetry pageadd=%x ecc=%x err=%x\012\000"
	27303	+.LC20:
	27304	+ .ascii "FLFB:%d %d\012\000"
	27305	+.LC21:
	27306	+ .ascii "BBT:\000"
	27307	+.LC22:
	27308	+ .ascii "prog error: = %x\012\000"
	27309	+.LC23:
	27310	+ .ascii "prog read error: = %x\012\000"
	27311	+.LC24:
	27312	+ .ascii "prog read REFRESH: = %x\012\000"
	27313	+.LC25:
	27314	+ .ascii "prog read s error: = %x %x %x\012\000"
	27315	+.LC26:
	27316	+ .ascii "prog read d error: = %x %x %x\012\000"
	27317	+.LC27:
	27318	+ .ascii "FlashMakeFactorBbt %d\012\000"
	27319	+.LC28:
	27320	+ .ascii "bad block:%d %d\012\000"
	27321	+.LC29:
	27322	+ .ascii "FMFB:%d %d\012\000"
	27323	+.LC30:
	27324	+ .ascii "E:bad block:%d\012\000"
	27325	+.LC31:
	27326	+ .ascii "FMFB:Save %d %d\012\000"
	27327	+.LC32:
	27328	+ .ascii "%s error allocating memory. return -1\012\000"
	27329	+.LC33:
	27330	+ .ascii "phyBlk = 0x%x die = %d block_in_die = 0x%x 0x%8x\012"
	27331	+ .ascii "\000"
	27332	+.LC34:
	27333	+ .ascii "FtlBbmTblFlush id=%x,page=%x,previd=%x cnt=%d\012\000"
	27334	+.LC35:
	27335	+ .ascii "FtlBbmTblFlush error:%x\012\000"
	27336	+.LC36:
	27337	+ .ascii "FtlBbmTblFlush error = %x error count = %d\012\000"
	27338	+.LC37:
	27339	+ .ascii "FtlFreeSysBlkQueueOut free count = %d\012\000"
	27340	+.LC38:
	27341	+ .ascii "FtlFreeSysBlkQueueOut = %x, free count = %d, error\012"
	27342	+ .ascii "\000"
	27343	+.LC39:
	27344	+ .ascii "FtlFreeSysBlkQueueOut = %x, free count = %d\012\000"
	27345	+.LC40:
	27346	+ .ascii "FtlMapWritePage error = %x\012\000"
	27347	+.LC41:
	27348	+ .ascii "FtlMapWritePage error = %x error count = %d\012\000"
	27349	+.LC42:
	27350	+ .ascii "page map lost: %x %x\012\000"
	27351	+.LC43:
	27352	+ .ascii "region_id = %x phyAddr = %x\012\000"
	27353	+.LC44:
	27354	+ .ascii "map_ppn:\000"
	27355	+.LC45:
	27356	+ .ascii "load_l2p_region refresh = %x phyAddr = %x\012\000"
	27357	+.LC46:
	27358	+ .ascii "FtlVendorPartRead refresh = %x phyAddr = %x\012\000"
	27359	+.LC47:
	27360	+ .ascii "FtlVpcTblFlush error = %x error count = %d\012\000"
	27361	+.LC48:
	27362	+ .ascii "no ect\000"
	27363	+.LC49:
	27364	+ .ascii "%s\012\000"
	27365	+.LC50:
	27366	+ .ascii "...%s enter...\012\000"
	27367	+.LC51:
	27368	+ .ascii "FtlCheckVpc2 %x = %x %x\012\000"
	27369	+.LC52:
	27370	+ .ascii "free blk vpc error %x = %x %x\012\000"
	27371	+.LC53:
	27372	+ .ascii "error_flag %x\012\000"
	27373	+.LC54:
	27374	+ .ascii "id = %x,%x addr= %x,spare= %x %x %x %x data = %x\012"
	27375	+ .ascii "\000"
	27376	+.LC55:
	27377	+ .ascii ":\000"
	27378	+.LC56:
	27379	+ .ascii "Ftlscanalldata = %x\012\000"
	27380	+.LC57:
	27381	+ .ascii "scan lpa = %x ppa= %x\012\000"
	27382	+.LC58:
	27383	+ .ascii "lba = %x,addr= %x,spare= %x %x %x %x data=%x %x\012"
	27384	+ .ascii "\000"
	27385	+.LC59:
	27386	+ .ascii "phyBlk = %x,addr= %x,spare= %x %x %x %x data=%x %x\012"
	27387	+ .ascii "\000"
	27388	+.LC60:
	27389	+ .ascii "id = %x,%x addr= %x,spare= %x %x %x %x data=%x %x\012"
	27390	+ .ascii "\000"
	27391	+.LC61:
	27392	+ .ascii "Mblk:\000"
	27393	+.LC62:
	27394	+ .ascii "L2P:\000"
	27395	+.LC63:
	27396	+ .ascii "L2PC:\000"
	27397	+.LC64:
	27398	+ .ascii "id = %x,%x addr= %x,spare= %x %x %x %x data= %x\012"
	27399	+ .ascii "\000"
	27400	+.LC65:
	27401	+ .ascii "superBlkID = %x vpc=%x\012\000"
	27402	+.LC66:
	27403	+ .ascii "flashmode = %x pagenum = %x %x\012\000"
	27404	+.LC67:
	27405	+ .ascii "blk = %x vpc=%x mode = %x\012\000"
	27406	+.LC68:
	27407	+ .ascii "mlc id = %x,%x addr= %x,spare= %x %x %x %x data=%x "
	27408	+ .ascii "%x\012\000"
	27409	+.LC69:
	27410	+ .ascii "slc id = %x,%x addr= %x,spare= %x %x %x %x data=%x "
	27411	+ .ascii "%x\012\000"
	27412	+.LC70:
	27413	+ .ascii "slc mode\000"
	27414	+.LC71:
	27415	+ .ascii "ftl_scan_all_ppa blk %x page %x flag: %x\012\000"
	27416	+.LC72:
	27417	+ .ascii "ftl_scan_all_ppa blk %x page %x flag: %x .........."
	27418	+ .ascii "..... is bad block\012\000"
	27419	+.LC73:
	27420	+ .ascii "addr= %x, status= %d,spare= %x %x %x %x data=%x %x\012"
	27421	+ .ascii "\000"
	27422	+.LC74:
	27423	+ .ascii "%s finished\012\000"
	27424	+.LC75:
	27425	+ .ascii "FLASH INFO:\012\000"
	27426	+.LC76:
	27427	+ .ascii "FLASH ID: %x\012\000"
	27428	+.LC77:
	27429	+ .ascii "Device Capacity: %d MB\012\000"
	27430	+.LC78:
	27431	+ .ascii "FMWAIT: %x %x %x %x\012\000"
	27432	+.LC79:
	27433	+ .ascii "FTL INFO:\012\000"
	27434	+.LC80:
	27435	+ .ascii "g_MaxLpn = 0x%x\012\000"
	27436	+.LC81:
	27437	+ .ascii "g_VaildLpn = 0x%x\012\000"
	27438	+.LC82:
	27439	+ .ascii "read_page_count = 0x%x\012\000"
	27440	+.LC83:
	27441	+ .ascii "discard_page_count = 0x%x\012\000"
	27442	+.LC84:
	27443	+ .ascii "write_page_count = 0x%x\012\000"
	27444	+.LC85:
	27445	+ .ascii "cache_write_count = 0x%x\012\000"
	27446	+.LC86:
	27447	+ .ascii "l2p_write_count = 0x%x\012\000"
	27448	+.LC87:
	27449	+ .ascii "gc_page_count = 0x%x\012\000"
	27450	+.LC88:
	27451	+ .ascii "totle_write = %d MB\012\000"
	27452	+.LC89:
	27453	+ .ascii "totle_read = %d MB\012\000"
	27454	+.LC90:
	27455	+ .ascii "GSV = 0x%x\012\000"
	27456	+.LC91:
	27457	+ .ascii "GDV = 0x%x\012\000"
	27458	+.LC92:
	27459	+ .ascii "bad blk num = %d %d\012\000"
	27460	+.LC93:
	27461	+ .ascii "free_superblocks = 0x%x\012\000"
	27462	+.LC94:
	27463	+ .ascii "mlc_EC = 0x%x\012\000"
	27464	+.LC95:
	27465	+ .ascii "slc_EC = 0x%x\012\000"
	27466	+.LC96:
	27467	+ .ascii "avg_EC = 0x%x\012\000"
	27468	+.LC97:
	27469	+ .ascii "sys_EC = 0x%x\012\000"
	27470	+.LC98:
	27471	+ .ascii "max_EC = 0x%x\012\000"
	27472	+.LC99:
	27473	+ .ascii "min_EC = 0x%x\012\000"
	27474	+.LC100:
	27475	+ .ascii "PLT = 0x%x\012\000"
	27476	+.LC101:
	27477	+ .ascii "POT = 0x%x\012\000"
	27478	+.LC102:
	27479	+ .ascii "MaxSector = 0x%x\012\000"
	27480	+.LC103:
	27481	+ .ascii "init_sys_blks_pp = 0x%x\012\000"
	27482	+.LC104:
	27483	+ .ascii "sys_blks_pp = 0x%x\012\000"
	27484	+.LC105:
	27485	+ .ascii "free sysblock = 0x%x\012\000"
	27486	+.LC106:
	27487	+ .ascii "data_blks_pp = 0x%x\012\000"
	27488	+.LC107:
	27489	+ .ascii "data_op_blks_pp = 0x%x\012\000"
	27490	+.LC108:
	27491	+ .ascii "max_data_blks = 0x%x\012\000"
	27492	+.LC109:
	27493	+ .ascii "Sys.id = 0x%x\012\000"
	27494	+.LC110:
	27495	+ .ascii "Bbt.id = 0x%x\012\000"
	27496	+.LC111:
	27497	+ .ascii "ACT.page = 0x%x\012\000"
	27498	+.LC112:
	27499	+ .ascii "ACT.plane = 0x%x\012\000"
	27500	+.LC113:
	27501	+ .ascii "ACT.id = 0x%x\012\000"
	27502	+.LC114:
	27503	+ .ascii "ACT.mode = 0x%x\012\000"
	27504	+.LC115:
	27505	+ .ascii "ACT.a_pages = 0x%x\012\000"
	27506	+.LC116:
	27507	+ .ascii "ACT VPC = 0x%x\012\000"
	27508	+.LC117:
	27509	+ .ascii "BUF.page = 0x%x\012\000"
	27510	+.LC118:
	27511	+ .ascii "BUF.plane = 0x%x\012\000"
	27512	+.LC119:
	27513	+ .ascii "BUF.id = 0x%x\012\000"
	27514	+.LC120:
	27515	+ .ascii "BUF.mode = 0x%x\012\000"
	27516	+.LC121:
	27517	+ .ascii "BUF.a_pages = 0x%x\012\000"
	27518	+.LC122:
	27519	+ .ascii "BUF VPC = 0x%x\012\000"
	27520	+.LC123:
	27521	+ .ascii "TMP.page = 0x%x\012\000"
	27522	+.LC124:
	27523	+ .ascii "TMP.plane = 0x%x\012\000"
	27524	+.LC125:
	27525	+ .ascii "TMP.id = 0x%x\012\000"
	27526	+.LC126:
	27527	+ .ascii "TMP.mode = 0x%x\012\000"
	27528	+.LC127:
	27529	+ .ascii "TMP.a_pages = 0x%x\012\000"
	27530	+.LC128:
	27531	+ .ascii "GC.page = 0x%x\012\000"
	27532	+.LC129:
	27533	+ .ascii "GC.plane = 0x%x\012\000"
	27534	+.LC130:
	27535	+ .ascii "GC.id = 0x%x\012\000"
	27536	+.LC131:
	27537	+ .ascii "GC.mode = 0x%x\012\000"
	27538	+.LC132:
	27539	+ .ascii "GC.a_pages = 0x%x\012\000"
	27540	+.LC133:
	27541	+ .ascii "WR_CHK = 0x%x %x %x %x\012\000"
	27542	+.LC134:
	27543	+ .ascii "Read Err = 0x%x\012\000"
	27544	+.LC135:
	27545	+ .ascii "Prog Err = 0x%x\012\000"
	27546	+.LC136:
	27547	+ .ascii "gc_free_blk_th= 0x%x\012\000"
	27548	+.LC137:
	27549	+ .ascii "gc_merge_free_blk_th= 0x%x\012\000"
	27550	+.LC138:
	27551	+ .ascii "gc_skip_write_count= 0x%x\012\000"
	27552	+.LC139:
	27553	+ .ascii "gc_blk_index= 0x%x\012\000"
	27554	+.LC140:
	27555	+ .ascii "free min EC= 0x%x\012\000"
	27556	+.LC141:
	27557	+ .ascii "free max EC= 0x%x\012\000"
	27558	+.LC142:
	27559	+ .ascii "GC__SB VPC = 0x%x\012\000"
	27560	+.LC143:
	27561	+ .ascii "%d. [0x%x]=0x%x 0x%x 0x%x\012\000"
	27562	+.LC144:
	27563	+ .ascii "free %d. [0x%x] 0x%x 0x%x\012\000"
	27564	+.LC145:
	27565	+ .ascii "FTL version: 5.0.63 20210616\000"
	27566	+.LC146:
	27567	+ .ascii "swblk %x ,avg = %x max= %x vpc= %x,ec=%x ,max ec=%x"
	27568	+ .ascii "\012\000"
	27569	+.LC147:
	27570	+ .ascii "FtlGcScanTempBlk Error ID %x %x!!!!!!! \012\000"
	27571	+.LC148:
	27572	+ .ascii "FtlGcScanTempBlkError ID %x %x!!!!!!!\012\000"
	27573	+.LC149:
	27574	+ .ascii "FtlGcRefreshBlock 0x%x\012\000"
	27575	+.LC150:
	27576	+ .ascii "FtlGcMarkBadPhyBlk %d 0x%x\012\000"
	27577	+.LC151:
	27578	+ .ascii "FtlGcFreeBadSuperBlk 0x%x\012\000"
	27579	+.LC152:
	27580	+ .ascii "decrement_vpc_count %x = %d\012\000"
	27581	+.LC153:
	27582	+ .ascii "decrement_vpc_count %x = %d in free list\012\000"
	27583	+.LC154:
	27584	+ .ascii "RSB refresh addr %x\012\000"
	27585	+.LC155:
	27586	+ .ascii "spuer block %x vpn is 0\012 \000"
	27587	+.LC156:
	27588	+ .ascii "g_recovery_ppa %x ver %x\012 \000"
	27589	+.LC157:
	27590	+ .ascii "FtlCheckVpc %x = %x %x\012\000"
	27591	+.LC158:
	27592	+ .ascii "%d GC datablk = %x vpc %x %x\012\000"
	27593	+.LC159:
	27594	+ .ascii "SWL %x, FSB = %x vpc= %x,ec=%x th=%x\012\000"
	27595	+.LC160:
	27596	+ .ascii "Ftlwrite decrement_vpc_count %x = %d\012\000"
	27597	+.LC161:
	27598	+ .ascii "GC des block %x done\012\000"
	27599	+.LC162:
	27600	+ .ascii "too many bad block = %d %d\012\000"
	27601	+.LC163:
	27602	+ .ascii "...%s: no bad block mapping table, format device\012"
	27603	+ .ascii "\000"
	27604	+.LC164:
	27605	+ .ascii "...%s FtlSysBlkInit error ,format device!\012\000"
	27606	+.LC165:
	27607	+ .ascii "FtlWrite: lpa error:%x %x\012\000"
	27608	+.LC166:
	27609	+ .ascii "fix power lost blk = %x vpc=%x\012\000"
	27610	+.LC167:
	27611	+ .ascii "erase power lost blk = %x vpc=%x\012\000"