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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/phy/qualcomm/phy-qcom-qmp.h
....@@ -1,4 +1,4 @@
1
-// SPDX-License-Identifier: GPL-2.0
1
+/* SPDX-License-Identifier: GPL-2.0 */
22 /*
33  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
44  */
....@@ -127,7 +127,7 @@
127127 #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB		0x1DC
128128 #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB		0x1E0
129129 
130
-/* Only for QMP V3 PHY - DP COM registers */
130
+/* Only for QMP V3 & V4 PHY - DP COM registers */
131131 #define QPHY_V3_DP_COM_PHY_MODE_CTRL			0x00
132132 #define QPHY_V3_DP_COM_SW_RESET				0x04
133133 #define QPHY_V3_DP_COM_POWER_DOWN_CTRL			0x08
....@@ -137,6 +137,9 @@
137137 #define QPHY_V3_DP_COM_RESET_OVRD_CTRL			0x1c
138138 
139139 /* Only for QMP V3 PHY - QSERDES COM registers */
140
+#define QSERDES_V3_COM_ATB_SEL1				0x000
141
+#define QSERDES_V3_COM_ATB_SEL2				0x004
142
+#define QSERDES_V3_COM_FREQ_UPDATE			0x008
140143 #define QSERDES_V3_COM_BG_TIMER				0x00c
141144 #define QSERDES_V3_COM_SSC_EN_CENTER			0x010
142145 #define QSERDES_V3_COM_SSC_ADJ_PER1			0x014
....@@ -146,6 +149,13 @@
146149 #define QSERDES_V3_COM_SSC_STEP_SIZE1			0x024
147150 #define QSERDES_V3_COM_SSC_STEP_SIZE2			0x028
148151 #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN		0x034
152
+# define QSERDES_V3_COM_BIAS_EN				0x0001
153
+# define QSERDES_V3_COM_BIAS_EN_MUX			0x0002
154
+# define QSERDES_V3_COM_CLKBUF_R_EN			0x0004
155
+# define QSERDES_V3_COM_CLKBUF_L_EN			0x0008
156
+# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL		0x0010
157
+# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L		0x0020
158
+# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R		0x0040
149159 #define QSERDES_V3_COM_CLK_ENABLE1			0x038
150160 #define QSERDES_V3_COM_SYS_CLK_CTRL			0x03c
151161 #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE		0x040
....@@ -176,6 +186,7 @@
176186 #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1		0x0c4
177187 #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1		0x0c8
178188 #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1		0x0cc
189
+#define QSERDES_V3_COM_INTEGLOOP_INITVAL		0x0d0
179190 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0		0x0d8
180191 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0		0x0dc
181192 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1		0x0e0
....@@ -186,6 +197,8 @@
186197 #define QSERDES_V3_COM_VCO_TUNE2_MODE0			0x0f8
187198 #define QSERDES_V3_COM_VCO_TUNE1_MODE1			0x0fc
188199 #define QSERDES_V3_COM_VCO_TUNE2_MODE1			0x100
200
+#define QSERDES_V3_COM_VCO_TUNE_INITVAL1		0x104
201
+#define QSERDES_V3_COM_VCO_TUNE_INITVAL2		0x108
189202 #define QSERDES_V3_COM_VCO_TUNE_TIMER1			0x11c
190203 #define QSERDES_V3_COM_VCO_TUNE_TIMER2			0x120
191204 #define QSERDES_V3_COM_CLK_SELECT			0x138
....@@ -201,20 +214,52 @@
201214 #define QSERDES_V3_COM_DEBUG_BUS2			0x170
202215 #define QSERDES_V3_COM_DEBUG_BUS3			0x174
203216 #define QSERDES_V3_COM_DEBUG_BUS_SEL			0x178
217
+#define QSERDES_V3_COM_CMN_MODE				0x184
204218 
205219 /* Only for QMP V3 PHY - TX registers */
220
+#define QSERDES_V3_TX_BIST_MODE_LANENO			0x000
221
+#define QSERDES_V3_TX_CLKBUF_ENABLE			0x008
222
+#define QSERDES_V3_TX_TX_EMP_POST1_LVL			0x00c
223
+# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK		0x001f
224
+# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN		0x0020
225
+
226
+#define QSERDES_V3_TX_TX_DRV_LVL			0x01c
227
+# define DP_PHY_TXn_TX_DRV_LVL_MASK			0x001f
228
+# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN			0x0020
229
+
230
+#define QSERDES_V3_TX_RESET_TSYNC_EN			0x024
231
+#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN		0x028
232
+
233
+#define QSERDES_V3_TX_TX_BAND				0x02c
234
+#define QSERDES_V3_TX_SLEW_CNTL				0x030
235
+#define QSERDES_V3_TX_INTERFACE_SELECT			0x034
236
+#define QSERDES_V3_TX_RES_CODE_LANE_TX			0x03c
237
+#define QSERDES_V3_TX_RES_CODE_LANE_RX			0x040
206238 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX		0x044
207239 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX		0x048
208240 #define QSERDES_V3_TX_DEBUG_BUS_SEL			0x058
241
+#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN		0x05c
209242 #define QSERDES_V3_TX_HIGHZ_DRVR_EN			0x060
243
+#define QSERDES_V3_TX_TX_POL_INV			0x064
244
+#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN	0x068
210245 #define QSERDES_V3_TX_LANE_MODE_1			0x08c
211246 #define QSERDES_V3_TX_RCV_DETECT_LVL_2			0x0a4
247
+#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN			0x0c0
248
+#define QSERDES_V3_TX_TX_INTERFACE_MODE			0x0c4
249
+#define QSERDES_V3_TX_VMODE_CTRL1			0x0f0
212250 
213251 /* Only for QMP V3 PHY - RX registers */
252
+#define QSERDES_V3_RX_UCDR_FO_GAIN			0x008
214253 #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF			0x00c
215254 #define QSERDES_V3_RX_UCDR_SO_GAIN			0x014
255
+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF		0x024
256
+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER		0x028
257
+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN			0x02c
216258 #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN		0x030
217259 #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034
260
+#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c
261
+#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH		0x040
262
+#define QSERDES_V3_RX_UCDR_PI_CONTROLS			0x044
218263 #define QSERDES_V3_RX_RX_TERM_BW			0x07c
219264 #define QSERDES_V3_RX_VGA_CAL_CNTRL1			0x0bc
220265 #define QSERDES_V3_RX_VGA_CAL_CNTRL2			0x0c0
....@@ -232,6 +277,7 @@
232277 #define QSERDES_V3_RX_RX_BAND				0x110
233278 #define QSERDES_V3_RX_RX_INTERFACE_MODE			0x11c
234279 #define QSERDES_V3_RX_RX_MODE_00			0x164
280
+#define QSERDES_V3_RX_RX_MODE_01			0x168
235281 
236282 /* Only for QMP V3 PHY - PCS registers */
237283 #define QPHY_V3_PCS_POWER_DOWN_CONTROL			0x004
....@@ -241,6 +287,8 @@
241287 #define QPHY_V3_PCS_TXMGN_V3				0x018
242288 #define QPHY_V3_PCS_TXMGN_V4				0x01c
243289 #define QPHY_V3_PCS_TXMGN_LS				0x020
290
+#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL		0x02c
291
+#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL		0x034
244292 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0			0x024
245293 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0			0x028
246294 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1			0x02c
....@@ -269,6 +317,7 @@
269317 #define QPHY_V3_PCS_TSYNC_RSYNC_TIME			0x08c
270318 #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x0a0
271319 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK		0x0a4
320
+#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME		0x0a8
272321 #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK		0x0b0
273322 #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME		0x0b8
274323 #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME		0x0bc
....@@ -277,11 +326,484 @@
277326 #define QPHY_V3_PCS_FLL_CNT_VAL_L			0x0cc
278327 #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL			0x0d0
279328 #define QPHY_V3_PCS_FLL_MAN_CODE			0x0d4
329
+#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL			0x134
330
+#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME			0x138
331
+#define QPHY_V3_PCS_RX_SIGDET_CTRL1			0x13c
332
+#define QPHY_V3_PCS_RX_SIGDET_CTRL2			0x140
333
+#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB	0x1a8
334
+#define QPHY_V3_PCS_OSC_DTCT_ACTIONS			0x1ac
335
+#define QPHY_V3_PCS_SIGDET_CNTRL			0x1b0
336
+#define QPHY_V3_PCS_TX_MID_TERM_CTRL1			0x1bc
337
+#define QPHY_V3_PCS_MULTI_LANE_CTRL1			0x1c4
280338 #define QPHY_V3_PCS_RX_SIGDET_LVL			0x1d8
339
+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB	0x1dc
340
+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB	0x1e0
281341 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1			0x20c
282342 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2			0x210
283343 
284344 /* Only for QMP V3 PHY - PCS_MISC registers */
285345 #define QPHY_V3_PCS_MISC_CLAMP_ENABLE			0x0c
346
+#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2		0x2c
347
+#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1	0x44
348
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2		0x54
349
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4		0x5c
350
+#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5		0x60
351
+
352
+/* Only for QMP V3 PHY - DP PHY registers */
353
+#define QSERDES_V3_DP_PHY_REVISION_ID0			0x000
354
+#define QSERDES_V3_DP_PHY_REVISION_ID1			0x004
355
+#define QSERDES_V3_DP_PHY_REVISION_ID2			0x008
356
+#define QSERDES_V3_DP_PHY_REVISION_ID3			0x00c
357
+#define QSERDES_V3_DP_PHY_CFG				0x010
358
+#define QSERDES_V3_DP_PHY_PD_CTL			0x018
359
+# define DP_PHY_PD_CTL_PWRDN				0x001
360
+# define DP_PHY_PD_CTL_PSR_PWRDN			0x002
361
+# define DP_PHY_PD_CTL_AUX_PWRDN			0x004
362
+# define DP_PHY_PD_CTL_LANE_0_1_PWRDN			0x008
363
+# define DP_PHY_PD_CTL_LANE_2_3_PWRDN			0x010
364
+# define DP_PHY_PD_CTL_PLL_PWRDN			0x020
365
+# define DP_PHY_PD_CTL_DP_CLAMP_EN			0x040
366
+#define QSERDES_V3_DP_PHY_MODE				0x01c
367
+#define QSERDES_V3_DP_PHY_AUX_CFG0			0x020
368
+#define QSERDES_V3_DP_PHY_AUX_CFG1			0x024
369
+#define QSERDES_V3_DP_PHY_AUX_CFG2			0x028
370
+#define QSERDES_V3_DP_PHY_AUX_CFG3			0x02c
371
+#define QSERDES_V3_DP_PHY_AUX_CFG4			0x030
372
+#define QSERDES_V3_DP_PHY_AUX_CFG5			0x034
373
+#define QSERDES_V3_DP_PHY_AUX_CFG6			0x038
374
+#define QSERDES_V3_DP_PHY_AUX_CFG7			0x03c
375
+#define QSERDES_V3_DP_PHY_AUX_CFG8			0x040
376
+#define QSERDES_V3_DP_PHY_AUX_CFG9			0x044
377
+
378
+#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK		0x048
379
+# define PHY_AUX_STOP_ERR_MASK				0x01
380
+# define PHY_AUX_DEC_ERR_MASK				0x02
381
+# define PHY_AUX_SYNC_ERR_MASK				0x04
382
+# define PHY_AUX_ALIGN_ERR_MASK				0x08
383
+# define PHY_AUX_REQ_ERR_MASK				0x10
384
+
385
+#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR		0x04c
386
+#define QSERDES_V3_DP_PHY_AUX_BIST_CFG			0x050
387
+
388
+#define QSERDES_V3_DP_PHY_VCO_DIV			0x064
389
+#define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL		0x06c
390
+#define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL		0x088
391
+
392
+#define QSERDES_V3_DP_PHY_SPARE0			0x0ac
393
+#define DP_PHY_SPARE0_MASK				0x0f
394
+#define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT		0x04(0x0004)
395
+
396
+#define QSERDES_V3_DP_PHY_STATUS			0x0c0
397
+
398
+/* Only for QMP V4 PHY - QSERDES COM registers */
399
+#define QSERDES_V4_COM_SSC_EN_CENTER			0x010
400
+#define QSERDES_V4_COM_SSC_PER1				0x01c
401
+#define QSERDES_V4_COM_SSC_PER2				0x020
402
+#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0		0x024
403
+#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0		0x028
404
+#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1		0x030
405
+#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1		0x034
406
+#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE		0x050
407
+#define QSERDES_V4_COM_PLL_IVCO				0x058
408
+#define QSERDES_V4_COM_CMN_IPTRIM			0x060
409
+#define QSERDES_V4_COM_CP_CTRL_MODE0			0x074
410
+#define QSERDES_V4_COM_CP_CTRL_MODE1			0x078
411
+#define QSERDES_V4_COM_PLL_RCTRL_MODE0			0x07c
412
+#define QSERDES_V4_COM_PLL_RCTRL_MODE1			0x080
413
+#define QSERDES_V4_COM_PLL_CCTRL_MODE0			0x084
414
+#define QSERDES_V4_COM_PLL_CCTRL_MODE1			0x088
415
+#define QSERDES_V4_COM_SYSCLK_EN_SEL			0x094
416
+#define QSERDES_V4_COM_LOCK_CMP_EN			0x0a4
417
+#define QSERDES_V4_COM_LOCK_CMP1_MODE0			0x0ac
418
+#define QSERDES_V4_COM_LOCK_CMP2_MODE0			0x0b0
419
+#define QSERDES_V4_COM_LOCK_CMP1_MODE1			0x0b4
420
+#define QSERDES_V4_COM_DEC_START_MODE0			0x0bc
421
+#define QSERDES_V4_COM_LOCK_CMP2_MODE1			0x0b8
422
+#define QSERDES_V4_COM_DEC_START_MODE1			0x0c4
423
+#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0		0x0cc
424
+#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0		0x0d0
425
+#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0		0x0d4
426
+#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1		0x0d8
427
+#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1		0x0dc
428
+#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1		0x0e0
429
+#define QSERDES_V4_COM_VCO_TUNE_MAP			0x10c
430
+#define QSERDES_V4_COM_VCO_TUNE1_MODE0			0x110
431
+#define QSERDES_V4_COM_VCO_TUNE2_MODE0			0x114
432
+#define QSERDES_V4_COM_VCO_TUNE1_MODE1			0x118
433
+#define QSERDES_V4_COM_VCO_TUNE2_MODE1			0x11c
434
+#define QSERDES_V4_COM_VCO_TUNE_INITVAL2		0x124
435
+#define QSERDES_V4_COM_HSCLK_SEL			0x158
436
+#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL		0x15c
437
+#define QSERDES_V4_COM_CORECLK_DIV_MODE1		0x16c
438
+#define QSERDES_V4_COM_SVS_MODE_CLK_SEL			0x184
439
+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0x1ac
440
+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1b0
441
+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0x1b4
442
+#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL		0x1bc
443
+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1b8
444
+
445
+/* Only for QMP V4 PHY - TX registers */
446
+#define QSERDES_V4_TX_RES_CODE_LANE_TX			0x34
447
+#define QSERDES_V4_TX_RES_CODE_LANE_RX			0x38
448
+#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 		0x3c
449
+#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 		0x40
450
+#define QSERDES_V4_TX_LANE_MODE_1			0x84
451
+#define QSERDES_V4_TX_LANE_MODE_2			0x88
452
+#define QSERDES_V4_TX_RCV_DETECT_LVL_2			0x9c
453
+#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0xd8
454
+#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0xdC
455
+#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1	0xe0
456
+#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1	0xe4
457
+#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN			0xb8
458
+#define QSERDES_V4_TX_PI_QEC_CTRL		0x104
459
+
460
+/* Only for QMP V4 PHY - RX registers */
461
+#define QSERDES_V4_RX_UCDR_FO_GAIN			0x008
462
+#define QSERDES_V4_RX_UCDR_SO_GAIN			0x014
463
+#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN		0x030
464
+#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034
465
+#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c
466
+#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH		0x040
467
+#define QSERDES_V4_RX_UCDR_PI_CONTROLS			0x044
468
+#define QSERDES_V4_RX_UCDR_PI_CTRL2			0x048
469
+#define QSERDES_V4_RX_UCDR_SB2_THRESH1			0x04c
470
+#define QSERDES_V4_RX_UCDR_SB2_THRESH2			0x050
471
+#define QSERDES_V4_RX_UCDR_SB2_GAIN1			0x054
472
+#define QSERDES_V4_RX_UCDR_SB2_GAIN2			0x058
473
+#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE			0x060
474
+#define QSERDES_V4_RX_AC_JTAG_ENABLE			0x068
475
+#define QSERDES_V4_RX_AC_JTAG_MODE			0x078
476
+#define QSERDES_V4_RX_RX_TERM_BW			0x080
477
+#define QSERDES_V4_RX_VGA_CAL_CNTRL1			0x0d4
478
+#define QSERDES_V4_RX_VGA_CAL_CNTRL2			0x0d8
479
+#define QSERDES_V4_RX_GM_CAL				0x0dc
480
+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2		0x0ec
481
+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3		0x0f0
482
+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4		0x0f4
483
+#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW		0x0f8
484
+#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH		0x0fc
485
+#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME		0x100
486
+#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x110
487
+#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2		0x114
488
+#define QSERDES_V4_RX_SIGDET_CNTRL			0x11c
489
+#define QSERDES_V4_RX_SIGDET_LVL			0x120
490
+#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL		0x124
491
+#define QSERDES_V4_RX_RX_BAND				0x128
492
+#define QSERDES_V4_RX_RX_MODE_00_LOW			0x170
493
+#define QSERDES_V4_RX_RX_MODE_00_HIGH			0x174
494
+#define QSERDES_V4_RX_RX_MODE_00_HIGH2			0x178
495
+#define QSERDES_V4_RX_RX_MODE_00_HIGH3			0x17c
496
+#define QSERDES_V4_RX_RX_MODE_00_HIGH4			0x180
497
+#define QSERDES_V4_RX_RX_MODE_01_LOW			0x184
498
+#define QSERDES_V4_RX_RX_MODE_01_HIGH			0x188
499
+#define QSERDES_V4_RX_RX_MODE_01_HIGH2			0x18c
500
+#define QSERDES_V4_RX_RX_MODE_01_HIGH3			0x190
501
+#define QSERDES_V4_RX_RX_MODE_01_HIGH4			0x194
502
+#define QSERDES_V4_RX_RX_MODE_10_LOW			0x198
503
+#define QSERDES_V4_RX_RX_MODE_10_HIGH			0x19c
504
+#define QSERDES_V4_RX_RX_MODE_10_HIGH2			0x1a0
505
+#define QSERDES_V4_RX_RX_MODE_10_HIGH3			0x1a4
506
+#define QSERDES_V4_RX_RX_MODE_10_HIGH4			0x1a8
507
+#define QSERDES_V4_RX_DFE_EN_TIMER			0x1b4
508
+#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET		0x1b8
509
+#define QSERDES_V4_RX_DCC_CTRL1				0x1bc
510
+#define QSERDES_V4_RX_VTH_CODE				0x1c4
511
+
512
+/* Only for QMP V4 PHY - UFS PCS registers */
513
+#define QPHY_V4_PCS_UFS_PHY_START				0x000
514
+#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL			0x004
515
+#define QPHY_V4_PCS_UFS_SW_RESET				0x008
516
+#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB		0x00c
517
+#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB		0x010
518
+#define QPHY_V4_PCS_UFS_PLL_CNTL				0x02c
519
+#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL			0x030
520
+#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL			0x038
521
+#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL			0x060
522
+#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY			0x074
523
+#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY			0x0b4
524
+#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL			0x124
525
+#define QPHY_V4_PCS_UFS_LINECFG_DISABLE				0x148
526
+#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME			0x150
527
+#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2				0x158
528
+#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND			0x160
529
+#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND				0x168
530
+#define QPHY_V4_PCS_UFS_READY_STATUS			0x180
531
+#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1			0x1d8
532
+#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1			0x1e0
533
+
534
+/* PCIE GEN3 COM registers */
535
+#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER			0x14
536
+#define PCIE_GEN3_QHP_COM_SSC_PER1			0x20
537
+#define PCIE_GEN3_QHP_COM_SSC_PER2			0x24
538
+#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1		0x28
539
+#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2		0x2c
540
+#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1		0x34
541
+#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1		0x38
542
+#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN		0x54
543
+#define PCIE_GEN3_QHP_COM_CLK_ENABLE1			0x58
544
+#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0		0x6c
545
+#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0		0x70
546
+#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1		0x78
547
+#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1		0x7c
548
+#define PCIE_GEN3_QHP_COM_BGV_TRIM			0x98
549
+#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0			0xb4
550
+#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1			0xb8
551
+#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0		0xc0
552
+#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1		0xc4
553
+#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0		0xcc
554
+#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1		0xd0
555
+#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL			0xdc
556
+#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2			0xf0
557
+#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN			0xf8
558
+#define PCIE_GEN3_QHP_COM_DEC_START_MODE0		0x100
559
+#define PCIE_GEN3_QHP_COM_DEC_START_MODE1		0x108
560
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0		0x11c
561
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0		0x120
562
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0		0x124
563
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1		0x128
564
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1		0x12c
565
+#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1		0x130
566
+#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0		0x150
567
+#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1		0x158
568
+#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP			0x178
569
+#define PCIE_GEN3_QHP_COM_BG_CTRL			0x1c8
570
+#define PCIE_GEN3_QHP_COM_CLK_SELECT			0x1cc
571
+#define PCIE_GEN3_QHP_COM_HSCLK_SEL1			0x1d0
572
+#define PCIE_GEN3_QHP_COM_CORECLK_DIV			0x1e0
573
+#define PCIE_GEN3_QHP_COM_CORE_CLK_EN			0x1e8
574
+#define PCIE_GEN3_QHP_COM_CMN_CONFIG			0x1f0
575
+#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL		0x1fc
576
+#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1		0x21c
577
+#define PCIE_GEN3_QHP_COM_CMN_MODE			0x224
578
+#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1			0x228
579
+#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2			0x22c
580
+
581
+/* PCIE GEN3 QHP Lane registers */
582
+#define PCIE_GEN3_QHP_L0_DRVR_CTRL0			0xc
583
+#define PCIE_GEN3_QHP_L0_DRVR_CTRL1			0x10
584
+#define PCIE_GEN3_QHP_L0_DRVR_CTRL2			0x14
585
+#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN			0x18
586
+#define PCIE_GEN3_QHP_L0_TX_BAND_MODE			0x60
587
+#define PCIE_GEN3_QHP_L0_LANE_MODE			0x64
588
+#define PCIE_GEN3_QHP_L0_PARALLEL_RATE			0x7c
589
+#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0			0xc0
590
+#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1			0xc4
591
+#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2			0xc8
592
+#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1		0xd0
593
+#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2		0xd4
594
+#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0		0xd8
595
+#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1		0xdc
596
+#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2		0xe0
597
+#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE		0xfc
598
+#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE			0x100
599
+#define PCIE_GEN3_QHP_L0_RXENGINE_EN0			0x108
600
+#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME		0x114
601
+#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME		0x118
602
+#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME		0x11c
603
+#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME		0x120
604
+#define PCIE_GEN3_QHP_L0_VGA_GAIN			0x124
605
+#define PCIE_GEN3_QHP_L0_DFE_GAIN			0x128
606
+#define PCIE_GEN3_QHP_L0_EQ_GAIN			0x130
607
+#define PCIE_GEN3_QHP_L0_OFFSET_GAIN			0x134
608
+#define PCIE_GEN3_QHP_L0_PRE_GAIN			0x138
609
+#define PCIE_GEN3_QHP_L0_VGA_INITVAL			0x13c
610
+#define PCIE_GEN3_QHP_L0_EQ_INTVAL			0x154
611
+#define PCIE_GEN3_QHP_L0_EDAC_INITVAL			0x160
612
+#define PCIE_GEN3_QHP_L0_RXEQ_INITB0			0x168
613
+#define PCIE_GEN3_QHP_L0_RXEQ_INITB1			0x16c
614
+#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1		0x178
615
+#define PCIE_GEN3_QHP_L0_RXEQ_CTRL			0x180
616
+#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0		0x184
617
+#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1		0x188
618
+#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2		0x18c
619
+#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0		0x190
620
+#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1		0x194
621
+#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2		0x198
622
+#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG			0x19c
623
+#define PCIE_GEN3_QHP_L0_RX_BAND			0x1a4
624
+#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0		0x1c0
625
+#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1		0x1c4
626
+#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2		0x1c8
627
+#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES			0x230
628
+#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL			0x234
629
+#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL		0x238
630
+#define PCIE_GEN3_QHP_L0_DCC_GAIN			0x2a4
631
+#define PCIE_GEN3_QHP_L0_RSM_START			0x2a8
632
+#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL			0x2ac
633
+#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL			0x2b0
634
+#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0			0x2b8
635
+#define PCIE_GEN3_QHP_L0_TS0_TIMER			0x2c0
636
+#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE		0x2c4
637
+#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET		0x2cc
638
+
639
+/* PCIE GEN3 PCS registers */
640
+#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB		0x2c
641
+#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB		0x40
642
+#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB		0x54
643
+#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB		0x68
644
+#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG		0x15c
645
+#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5		0x16c
646
+#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG		0x174
647
+
648
+/* Only for QMP V4 PHY - USB/PCIe PCS registers */
649
+#define QPHY_V4_PCS_SW_RESET				0x000
650
+#define QPHY_V4_PCS_REVISION_ID0			0x004
651
+#define QPHY_V4_PCS_REVISION_ID1			0x008
652
+#define QPHY_V4_PCS_REVISION_ID2			0x00c
653
+#define QPHY_V4_PCS_REVISION_ID3			0x010
654
+#define QPHY_V4_PCS_PCS_STATUS1				0x014
655
+#define QPHY_V4_PCS_PCS_STATUS2				0x018
656
+#define QPHY_V4_PCS_PCS_STATUS3				0x01c
657
+#define QPHY_V4_PCS_PCS_STATUS4				0x020
658
+#define QPHY_V4_PCS_PCS_STATUS5				0x024
659
+#define QPHY_V4_PCS_PCS_STATUS6				0x028
660
+#define QPHY_V4_PCS_PCS_STATUS7				0x02c
661
+#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS			0x030
662
+#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS			0x034
663
+#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS			0x038
664
+#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS			0x03c
665
+#define QPHY_V4_PCS_POWER_DOWN_CONTROL			0x040
666
+#define QPHY_V4_PCS_START_CONTROL			0x044
667
+#define QPHY_V4_PCS_INSIG_SW_CTRL1			0x048
668
+#define QPHY_V4_PCS_INSIG_SW_CTRL2			0x04c
669
+#define QPHY_V4_PCS_INSIG_SW_CTRL3			0x050
670
+#define QPHY_V4_PCS_INSIG_SW_CTRL4			0x054
671
+#define QPHY_V4_PCS_INSIG_SW_CTRL5			0x058
672
+#define QPHY_V4_PCS_INSIG_SW_CTRL6			0x05c
673
+#define QPHY_V4_PCS_INSIG_SW_CTRL7			0x060
674
+#define QPHY_V4_PCS_INSIG_SW_CTRL8			0x064
675
+#define QPHY_V4_PCS_INSIG_MX_CTRL1			0x068
676
+#define QPHY_V4_PCS_INSIG_MX_CTRL2			0x06c
677
+#define QPHY_V4_PCS_INSIG_MX_CTRL3			0x070
678
+#define QPHY_V4_PCS_INSIG_MX_CTRL4			0x074
679
+#define QPHY_V4_PCS_INSIG_MX_CTRL5			0x078
680
+#define QPHY_V4_PCS_INSIG_MX_CTRL7			0x07c
681
+#define QPHY_V4_PCS_INSIG_MX_CTRL8			0x080
682
+#define QPHY_V4_PCS_OUTSIG_SW_CTRL1			0x084
683
+#define QPHY_V4_PCS_OUTSIG_MX_CTRL1			0x088
684
+#define QPHY_V4_PCS_CLAMP_ENABLE			0x08c
685
+#define QPHY_V4_PCS_POWER_STATE_CONFIG1			0x090
686
+#define QPHY_V4_PCS_POWER_STATE_CONFIG2			0x094
687
+#define QPHY_V4_PCS_FLL_CNTRL1				0x098
688
+#define QPHY_V4_PCS_FLL_CNTRL2				0x09c
689
+#define QPHY_V4_PCS_FLL_CNT_VAL_L			0x0a0
690
+#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL			0x0a4
691
+#define QPHY_V4_PCS_FLL_MAN_CODE			0x0a8
692
+#define QPHY_V4_PCS_TEST_CONTROL1			0x0ac
693
+#define QPHY_V4_PCS_TEST_CONTROL2			0x0b0
694
+#define QPHY_V4_PCS_TEST_CONTROL3			0x0b4
695
+#define QPHY_V4_PCS_TEST_CONTROL4			0x0b8
696
+#define QPHY_V4_PCS_TEST_CONTROL5			0x0bc
697
+#define QPHY_V4_PCS_TEST_CONTROL6			0x0c0
698
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1			0x0c4
699
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2			0x0c8
700
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3			0x0cc
701
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4			0x0d0
702
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5			0x0d4
703
+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6			0x0d8
704
+#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1			0x0dc
705
+#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2			0x0e0
706
+#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3			0x0e4
707
+#define QPHY_V4_PCS_BIST_CTRL				0x0e8
708
+#define QPHY_V4_PCS_PRBS_POLY0				0x0ec
709
+#define QPHY_V4_PCS_PRBS_POLY1				0x0f0
710
+#define QPHY_V4_PCS_FIXED_PAT0				0x0f4
711
+#define QPHY_V4_PCS_FIXED_PAT1				0x0f8
712
+#define QPHY_V4_PCS_FIXED_PAT2				0x0fc
713
+#define QPHY_V4_PCS_FIXED_PAT3				0x100
714
+#define QPHY_V4_PCS_FIXED_PAT4				0x104
715
+#define QPHY_V4_PCS_FIXED_PAT5				0x108
716
+#define QPHY_V4_PCS_FIXED_PAT6				0x10c
717
+#define QPHY_V4_PCS_FIXED_PAT7				0x110
718
+#define QPHY_V4_PCS_FIXED_PAT8				0x114
719
+#define QPHY_V4_PCS_FIXED_PAT9				0x118
720
+#define QPHY_V4_PCS_FIXED_PAT10				0x11c
721
+#define QPHY_V4_PCS_FIXED_PAT11				0x120
722
+#define QPHY_V4_PCS_FIXED_PAT12				0x124
723
+#define QPHY_V4_PCS_FIXED_PAT13				0x128
724
+#define QPHY_V4_PCS_FIXED_PAT14				0x12c
725
+#define QPHY_V4_PCS_FIXED_PAT15				0x130
726
+#define QPHY_V4_PCS_TXMGN_CONFIG			0x134
727
+#define QPHY_V4_PCS_G12S1_TXMGN_V0			0x138
728
+#define QPHY_V4_PCS_G12S1_TXMGN_V1			0x13c
729
+#define QPHY_V4_PCS_G12S1_TXMGN_V2			0x140
730
+#define QPHY_V4_PCS_G12S1_TXMGN_V3			0x144
731
+#define QPHY_V4_PCS_G12S1_TXMGN_V4			0x148
732
+#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS			0x14c
733
+#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS			0x150
734
+#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS			0x154
735
+#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS			0x158
736
+#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS			0x15c
737
+#define QPHY_V4_PCS_G3S2_TXMGN_MAIN			0x160
738
+#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS			0x164
739
+#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB			0x168
740
+#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB		0x16c
741
+#define QPHY_V4_PCS_G3S2_PRE_GAIN			0x170
742
+#define QPHY_V4_PCS_G3S2_POST_GAIN			0x174
743
+#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET		0x178
744
+#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS			0x17c
745
+#define QPHY_V4_PCS_G3S2_POST_GAIN_RS			0x180
746
+#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS		0x184
747
+#define QPHY_V4_PCS_RX_SIGDET_LVL			0x188
748
+#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL		0x18c
749
+#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L		0x190
750
+#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H		0x194
751
+#define QPHY_V4_PCS_RATE_SLEW_CNTRL1			0x198
752
+#define QPHY_V4_PCS_RATE_SLEW_CNTRL2			0x19c
753
+#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x1a0
754
+#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L	0x1a4
755
+#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H	0x1a8
756
+#define QPHY_V4_PCS_TSYNC_RSYNC_TIME			0x1ac
757
+#define QPHY_V4_PCS_CDR_RESET_TIME			0x1b0
758
+#define QPHY_V4_PCS_TSYNC_DLY_TIME			0x1b4
759
+#define QPHY_V4_PCS_ELECIDLE_DLY_SEL			0x1b8
760
+#define QPHY_V4_PCS_CMN_ACK_OUT_SEL			0x1bc
761
+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1		0x1c0
762
+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2		0x1c4
763
+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3		0x1c8
764
+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4		0x1cc
765
+#define QPHY_V4_PCS_PCS_TX_RX_CONFIG			0x1d0
766
+#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL			0x1d4
767
+#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG			0x1d8
768
+#define QPHY_V4_PCS_EQ_CONFIG1				0x1dc
769
+#define QPHY_V4_PCS_EQ_CONFIG2				0x1e0
770
+#define QPHY_V4_PCS_EQ_CONFIG3				0x1e4
771
+#define QPHY_V4_PCS_EQ_CONFIG4				0x1e8
772
+#define QPHY_V4_PCS_EQ_CONFIG5				0x1ec
773
+#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1		0x300
774
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS		0x304
775
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL		0x308
776
+#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2		0x30c
777
+#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS	0x310
778
+#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR		0x314
779
+#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0x318
780
+#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART		0x31c
781
+#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL		0x320
782
+#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START	0x324
783
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME		0x328
784
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME		0x32c
785
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME		0x330
786
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2	0x334
787
+#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x338
788
+#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L		0x33c
789
+#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H		0x340
790
+#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD		0x344
791
+#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY		0x348
792
+#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH		0x34c
793
+#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL		0x350
794
+#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL	0x354
795
+#define QPHY_V4_PCS_USB3_TEST_CONTROL			0x358
796
+
797
+/* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */
798
+#define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL	0x618
799
+#define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2	0x638
800
+
801
+/* Only for QMP V4 PHY - PCS_MISC registers */
802
+#define QPHY_V4_PCS_MISC_TYPEC_CTRL			0x00
803
+#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL		0x04
804
+#define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1		0x08
805
+#define QPHY_V4_PCS_MISC_CLAMP_ENABLE			0x0c
806
+#define QPHY_V4_PCS_MISC_TYPEC_STATUS			0x10
807
+#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS		0x14
286808 
287809 #endif