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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/phy/broadcom/phy-brcm-sata.c
....@@ -1,17 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Broadcom SATA3 AHCI Controller PHY Driver
34  *
45  * Copyright (C) 2016 Broadcom
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License as published by
8
- * the Free Software Foundation; either version 2, or (at your option)
9
- * any later version.
10
- *
11
- * This program is distributed in the hope that it will be useful,
12
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
- * GNU General Public License for more details.
156  */
167 
178 #include <linux/delay.h>
....@@ -42,11 +33,13 @@
4233 #define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE		0x8
4334 
4435 enum brcm_sata_phy_version {
36
+	BRCM_SATA_PHY_STB_16NM,
4537 	BRCM_SATA_PHY_STB_28NM,
4638 	BRCM_SATA_PHY_STB_40NM,
4739 	BRCM_SATA_PHY_IPROC_NS2,
4840 	BRCM_SATA_PHY_IPROC_NSP,
4941 	BRCM_SATA_PHY_IPROC_SR,
42
+	BRCM_SATA_PHY_DSL_28NM,
5043 };
5144 
5245 enum brcm_sata_phy_rxaeq_mode {
....@@ -96,7 +89,10 @@
9689 	PLLCONTROL_0_FREQ_DET_RESTART		= BIT(13),
9790 	PLLCONTROL_0_FREQ_MONITOR		= BIT(12),
9891 	PLLCONTROL_0_SEQ_START			= BIT(15),
92
+	PLL_CAP_CHARGE_TIME			= 0x83,
93
+	PLL_VCO_CAL_THRESH			= 0x84,
9994 	PLL_CAP_CONTROL				= 0x85,
95
+	PLL_FREQ_DET_TIME			= 0x86,
10096 	PLL_ACTRL2				= 0x8b,
10197 	PLL_ACTRL2_SELDIV_MASK			= 0x1f,
10298 	PLL_ACTRL2_SELDIV_SHIFT			= 9,
....@@ -106,10 +102,16 @@
106102 	PLL1_ACTRL2				= 0x82,
107103 	PLL1_ACTRL3				= 0x83,
108104 	PLL1_ACTRL4				= 0x84,
105
+	PLL1_ACTRL5				= 0x85,
106
+	PLL1_ACTRL6				= 0x86,
107
+	PLL1_ACTRL7				= 0x87,
108
+	PLL1_ACTRL8				= 0x88,
109109 
110110 	TX_REG_BANK				= 0x070,
111111 	TX_ACTRL0				= 0x80,
112112 	TX_ACTRL0_TXPOL_FLIP			= BIT(6),
113
+	TX_ACTRL5				= 0x85,
114
+	TX_ACTRL5_SSC_EN			= BIT(11),
113115 
114116 	AEQRX_REG_BANK_0			= 0xd0,
115117 	AEQ_CONTROL1				= 0x81,
....@@ -118,7 +120,10 @@
118120 	AEQ_FRC_EQ				= 0x83,
119121 	AEQ_FRC_EQ_FORCE			= BIT(0),
120122 	AEQ_FRC_EQ_FORCE_VAL			= BIT(1),
123
+	AEQ_RFZ_FRC_VAL				= BIT(8),
121124 	AEQRX_REG_BANK_1			= 0xe0,
125
+	AEQRX_SLCAL0_CTRL0			= 0x82,
126
+	AEQRX_SLCAL1_CTRL0			= 0x86,
122127 
123128 	OOB_REG_BANK				= 0x150,
124129 	OOB1_REG_BANK				= 0x160,
....@@ -152,34 +157,34 @@
152157 	TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK	= 0x3ff,
153158 
154159 	RXPMD_REG_BANK				= 0x1c0,
160
+	RXPMD_RX_CDR_CONTROL1			= 0x81,
161
+	RXPMD_RX_PPM_VAL_MASK			= 0x1ff,
162
+	RXPMD_RXPMD_EN_FRC			= BIT(12),
163
+	RXPMD_RXPMD_EN_FRC_VAL			= BIT(13),
164
+	RXPMD_RX_CDR_CDR_PROP_BW		= 0x82,
165
+	RXPMD_G_CDR_PROP_BW_MASK		= 0x7,
166
+	RXPMD_G1_CDR_PROP_BW_SHIFT		= 0,
167
+	RXPMD_G2_CDR_PROP_BW_SHIFT		= 3,
168
+	RXPMD_G3_CDR_PROB_BW_SHIFT		= 6,
169
+	RXPMD_RX_CDR_CDR_ACQ_INTEG_BW		= 0x83,
170
+	RXPMD_G_CDR_ACQ_INT_BW_MASK		= 0x7,
171
+	RXPMD_G1_CDR_ACQ_INT_BW_SHIFT		= 0,
172
+	RXPMD_G2_CDR_ACQ_INT_BW_SHIFT		= 3,
173
+	RXPMD_G3_CDR_ACQ_INT_BW_SHIFT		= 6,
174
+	RXPMD_RX_CDR_CDR_LOCK_INTEG_BW		= 0x84,
175
+	RXPMD_G_CDR_LOCK_INT_BW_MASK		= 0x7,
176
+	RXPMD_G1_CDR_LOCK_INT_BW_SHIFT		= 0,
177
+	RXPMD_G2_CDR_LOCK_INT_BW_SHIFT		= 3,
178
+	RXPMD_G3_CDR_LOCK_INT_BW_SHIFT		= 6,
155179 	RXPMD_RX_FREQ_MON_CONTROL1		= 0x87,
180
+	RXPMD_MON_CORRECT_EN			= BIT(8),
181
+	RXPMD_MON_MARGIN_VAL_MASK		= 0xff,
156182 };
157183 
158184 enum sata_phy_ctrl_regs {
159185 	PHY_CTRL_1				= 0x0,
160186 	PHY_CTRL_1_RESET			= BIT(0),
161187 };
162
-
163
-static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port)
164
-{
165
-	struct brcm_sata_phy *priv = port->phy_priv;
166
-	u32 size = 0;
167
-
168
-	switch (priv->version) {
169
-	case BRCM_SATA_PHY_STB_28NM:
170
-	case BRCM_SATA_PHY_IPROC_NS2:
171
-		size = SATA_PCB_REG_28NM_SPACE_SIZE;
172
-		break;
173
-	case BRCM_SATA_PHY_STB_40NM:
174
-		size = SATA_PCB_REG_40NM_SPACE_SIZE;
175
-		break;
176
-	default:
177
-		dev_err(priv->dev, "invalid phy version\n");
178
-		break;
179
-	}
180
-
181
-	return priv->phy_base + (port->portnum * size);
182
-}
183188 
184189 static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
185190 {
....@@ -198,10 +203,17 @@
198203 	return priv->ctrl_base + (port->portnum * size);
199204 }
200205 
201
-static void brcm_sata_phy_wr(void __iomem *pcb_base, u32 bank,
206
+static void brcm_sata_phy_wr(struct brcm_sata_port *port, u32 bank,
202207 			     u32 ofs, u32 msk, u32 value)
203208 {
209
+	struct brcm_sata_phy *priv = port->phy_priv;
210
+	void __iomem *pcb_base = priv->phy_base;
204211 	u32 tmp;
212
+
213
+	if (priv->version == BRCM_SATA_PHY_STB_40NM)
214
+		bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
215
+	else
216
+		pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
205217 
206218 	writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
207219 	tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
....@@ -209,8 +221,16 @@
209221 	writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
210222 }
211223 
212
-static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs)
224
+static u32 brcm_sata_phy_rd(struct brcm_sata_port *port, u32 bank, u32 ofs)
213225 {
226
+	struct brcm_sata_phy *priv = port->phy_priv;
227
+	void __iomem *pcb_base = priv->phy_base;
228
+
229
+	if (priv->version == BRCM_SATA_PHY_STB_40NM)
230
+		bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
231
+	else
232
+		pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
233
+
214234 	writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
215235 	return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
216236 }
....@@ -222,16 +242,15 @@
222242 
223243 static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
224244 {
225
-	void __iomem *base = brcm_sata_pcb_base(port);
226245 	struct brcm_sata_phy *priv = port->phy_priv;
227246 	u32 tmp;
228247 
229248 	/* override the TX spread spectrum setting */
230249 	tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
231
-	brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
250
+	brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
232251 
233252 	/* set fixed min freq */
234
-	brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
253
+	brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
235254 			 ~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
236255 			 STB_FMIN_VAL_DEFAULT);
237256 
....@@ -243,7 +262,7 @@
243262 		tmp = STB_FMAX_VAL_DEFAULT;
244263 	}
245264 
246
-	brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
265
+	brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
247266 			  ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
248267 }
249268 
....@@ -252,7 +271,6 @@
252271 
253272 static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port)
254273 {
255
-	void __iomem *base = brcm_sata_pcb_base(port);
256274 	u32 tmp = 0, reg = 0;
257275 
258276 	switch (port->rxaeq_mode) {
....@@ -273,8 +291,8 @@
273291 		break;
274292 	}
275293 
276
-	brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
277
-	brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
294
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
295
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
278296 
279297 	return 0;
280298 }
....@@ -286,6 +304,93 @@
286304 	return brcm_stb_sata_rxaeq_init(port);
287305 }
288306 
307
+static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
308
+{
309
+	u32 tmp, value;
310
+
311
+	/* Reduce CP tail current to 1/16th of its default value */
312
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
313
+
314
+	/* Turn off CP tail current boost */
315
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
316
+
317
+	/* Set a specific AEQ equalizer value */
318
+	tmp = AEQ_FRC_EQ_FORCE_VAL | AEQ_FRC_EQ_FORCE;
319
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
320
+			 ~(tmp | AEQ_RFZ_FRC_VAL |
321
+			   AEQ_FRC_EQ_VAL_MASK << AEQ_FRC_EQ_VAL_SHIFT),
322
+			 tmp | 32 << AEQ_FRC_EQ_VAL_SHIFT);
323
+
324
+	/* Set RX PPM val center frequency */
325
+	if (port->ssc_en)
326
+		value = 0x52;
327
+	else
328
+		value = 0;
329
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
330
+			 ~RXPMD_RX_PPM_VAL_MASK, value);
331
+
332
+	/* Set proportional loop bandwith Gen1/2/3 */
333
+	tmp = RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G1_CDR_PROP_BW_SHIFT |
334
+	      RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G2_CDR_PROP_BW_SHIFT |
335
+	      RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G3_CDR_PROB_BW_SHIFT;
336
+	if (port->ssc_en)
337
+		value = 2 << RXPMD_G1_CDR_PROP_BW_SHIFT |
338
+			2 << RXPMD_G2_CDR_PROP_BW_SHIFT |
339
+			2 << RXPMD_G3_CDR_PROB_BW_SHIFT;
340
+	else
341
+		value = 1 << RXPMD_G1_CDR_PROP_BW_SHIFT |
342
+			1 << RXPMD_G2_CDR_PROP_BW_SHIFT |
343
+			1 << RXPMD_G3_CDR_PROB_BW_SHIFT;
344
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
345
+			 value);
346
+
347
+	/* Set CDR integral loop acquisition bandwidth for Gen1/2/3 */
348
+	tmp = RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G1_CDR_ACQ_INT_BW_SHIFT |
349
+	      RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G2_CDR_ACQ_INT_BW_SHIFT |
350
+	      RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
351
+	if (port->ssc_en)
352
+		value = 1 << RXPMD_G1_CDR_ACQ_INT_BW_SHIFT |
353
+			1 << RXPMD_G2_CDR_ACQ_INT_BW_SHIFT |
354
+			1 << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
355
+	else
356
+		value = 0;
357
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
358
+			 ~tmp, value);
359
+
360
+	/* Set CDR integral loop locking bandwidth to 1 for Gen 1/2/3 */
361
+	tmp = RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G1_CDR_LOCK_INT_BW_SHIFT |
362
+	      RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G2_CDR_LOCK_INT_BW_SHIFT |
363
+	      RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
364
+	if (port->ssc_en)
365
+		value = 1 << RXPMD_G1_CDR_LOCK_INT_BW_SHIFT |
366
+			1 << RXPMD_G2_CDR_LOCK_INT_BW_SHIFT |
367
+			1 << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
368
+	else
369
+		value = 0;
370
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
371
+			 ~tmp, value);
372
+
373
+	/* Set no guard band and clamp CDR */
374
+	tmp = RXPMD_MON_CORRECT_EN | RXPMD_MON_MARGIN_VAL_MASK;
375
+	if (port->ssc_en)
376
+		value = 0x51;
377
+	else
378
+		value = 0;
379
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
380
+			 ~tmp, RXPMD_MON_CORRECT_EN | value);
381
+
382
+	/* Turn on/off SSC */
383
+	brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
384
+			 port->ssc_en ? TX_ACTRL5_SSC_EN : 0);
385
+
386
+	return 0;
387
+}
388
+
389
+static int brcm_stb_sata_16nm_init(struct brcm_sata_port *port)
390
+{
391
+	return brcm_stb_sata_16nm_ssc_init(port);
392
+}
393
+
289394 /* NS2 SATA PLL1 defaults were characterized by H/W group */
290395 #define NS2_PLL1_ACTRL2_MAGIC	0x1df8
291396 #define NS2_PLL1_ACTRL3_MAGIC	0x2b00
....@@ -295,7 +400,6 @@
295400 {
296401 	int try;
297402 	unsigned int val;
298
-	void __iomem *base = brcm_sata_pcb_base(port);
299403 	void __iomem *ctrl_base = brcm_sata_ctrl_base(port);
300404 	struct device *dev = port->phy_priv->dev;
301405 
....@@ -305,24 +409,24 @@
305409 	val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
306410 	val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
307411 	val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
308
-	brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
412
+	brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
309413 	val = 0x0;
310414 	val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
311415 	val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
312416 	val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
313
-	brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
417
+	brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
314418 
315419 	/* Configure PHY PLL register bank 1 */
316420 	val = NS2_PLL1_ACTRL2_MAGIC;
317
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
421
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
318422 	val = NS2_PLL1_ACTRL3_MAGIC;
319
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
423
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
320424 	val = NS2_PLL1_ACTRL4_MAGIC;
321
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
425
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
322426 
323427 	/* Configure PHY BLOCK0 register bank */
324428 	/* Set oob_clk_sel to refclk/2 */
325
-	brcm_sata_phy_wr(base, BLOCK0_REG_BANK, BLOCK0_SPARE,
429
+	brcm_sata_phy_wr(port, BLOCK0_REG_BANK, BLOCK0_SPARE,
326430 			 ~BLOCK0_SPARE_OOB_CLK_SEL_MASK,
327431 			 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2);
328432 
....@@ -335,7 +439,7 @@
335439 	/* Wait for PHY PLL lock by polling pll_lock bit */
336440 	try = 50;
337441 	while (try) {
338
-		val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
442
+		val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
339443 					BLOCK0_XGXSSTATUS);
340444 		if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
341445 			break;
....@@ -355,9 +459,7 @@
355459 
356460 static int brcm_nsp_sata_init(struct brcm_sata_port *port)
357461 {
358
-	struct brcm_sata_phy *priv = port->phy_priv;
359462 	struct device *dev = port->phy_priv->dev;
360
-	void __iomem *base = priv->phy_base;
361463 	unsigned int oob_bank;
362464 	unsigned int val, try;
363465 
....@@ -374,36 +476,36 @@
374476 	val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
375477 	val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
376478 	val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
377
-	brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val);
479
+	brcm_sata_phy_wr(port, oob_bank, OOB_CTRL1, 0x0, val);
378480 
379481 	val = 0x0;
380482 	val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
381483 	val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
382484 	val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
383
-	brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val);
485
+	brcm_sata_phy_wr(port, oob_bank, OOB_CTRL2, 0x0, val);
384486 
385487 
386
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2,
488
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL2,
387489 		~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT),
388490 		0x0c << PLL_ACTRL2_SELDIV_SHIFT);
389491 
390
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL,
492
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CONTROL,
391493 						0xff0, 0x4f0);
392494 
393495 	val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
394
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
496
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
395497 								~val, val);
396498 	val = PLLCONTROL_0_SEQ_START;
397
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
499
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
398500 								~val, 0);
399501 	mdelay(10);
400
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
502
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
401503 								~val, val);
402504 
403505 	/* Wait for pll_seq_done bit */
404506 	try = 50;
405507 	while (--try) {
406
-		val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
508
+		val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
407509 					BLOCK0_XGXSSTATUS);
408510 		if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
409511 			break;
....@@ -430,27 +532,25 @@
430532 
431533 static int brcm_sr_sata_init(struct brcm_sata_port *port)
432534 {
433
-	struct brcm_sata_phy *priv = port->phy_priv;
434535 	struct device *dev = port->phy_priv->dev;
435
-	void __iomem *base = priv->phy_base;
436536 	unsigned int val, try;
437537 
438538 	/* Configure PHY PLL register bank 1 */
439539 	val = SR_PLL1_ACTRL2_MAGIC;
440
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
540
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
441541 	val = SR_PLL1_ACTRL3_MAGIC;
442
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
542
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
443543 	val = SR_PLL1_ACTRL4_MAGIC;
444
-	brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
544
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
445545 
446546 	/* Configure PHY PLL register bank 0 */
447547 	val = SR_PLL0_ACTRL6_MAGIC;
448
-	brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
548
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
449549 
450550 	/* Wait for PHY PLL lock by polling pll_lock bit */
451551 	try = 50;
452552 	do {
453
-		val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
553
+		val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
454554 					BLOCK0_XGXSSTATUS);
455555 		if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
456556 			break;
....@@ -465,7 +565,7 @@
465565 	}
466566 
467567 	/* Invert Tx polarity */
468
-	brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL0,
568
+	brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL0,
469569 			 ~TX_ACTRL0_TXPOL_FLIP, TX_ACTRL0_TXPOL_FLIP);
470570 
471571 	/* Configure OOB control to handle 100MHz reference clock */
....@@ -473,11 +573,65 @@
473573 		(0x4 << OOB_CTRL1_BURST_MIN_SHIFT) |
474574 		(0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) |
475575 		(0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT));
476
-	brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
576
+	brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
477577 	val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) |
478578 		(0x2 << OOB_CTRL2_BURST_CNT_SHIFT) |
479579 		(0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT));
480
-	brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
580
+	brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
581
+
582
+	return 0;
583
+}
584
+
585
+static int brcm_dsl_sata_init(struct brcm_sata_port *port)
586
+{
587
+	struct device *dev = port->phy_priv->dev;
588
+	unsigned int try;
589
+	u32 tmp;
590
+
591
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
592
+
593
+	brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
594
+
595
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
596
+			 0, 0x3089);
597
+	usleep_range(1000, 2000);
598
+
599
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
600
+			 0, 0x3088);
601
+	usleep_range(1000, 2000);
602
+
603
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
604
+			 0, 0x3000);
605
+
606
+	brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
607
+			 0, 0x3000);
608
+	usleep_range(1000, 2000);
609
+
610
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
611
+
612
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
613
+
614
+	brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
615
+	usleep_range(1000, 2000);
616
+
617
+	/* Acquire PLL lock */
618
+	try = 50;
619
+	while (try) {
620
+		tmp = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
621
+				       BLOCK0_XGXSSTATUS);
622
+		if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
623
+			break;
624
+		msleep(20);
625
+		try--;
626
+	};
627
+
628
+	if (!try) {
629
+		/* PLL did not lock; give up */
630
+		dev_err(dev, "port%d PLL did not lock\n", port->portnum);
631
+		return -ETIMEDOUT;
632
+	}
633
+
634
+	dev_dbg(dev, "port%d initialized\n", port->portnum);
481635 
482636 	return 0;
483637 }
....@@ -488,6 +642,9 @@
488642 	struct brcm_sata_port *port = phy_get_drvdata(phy);
489643 
490644 	switch (port->phy_priv->version) {
645
+	case BRCM_SATA_PHY_STB_16NM:
646
+		rc = brcm_stb_sata_16nm_init(port);
647
+		break;
491648 	case BRCM_SATA_PHY_STB_28NM:
492649 	case BRCM_SATA_PHY_STB_40NM:
493650 		rc = brcm_stb_sata_init(port);
....@@ -501,6 +658,9 @@
501658 	case BRCM_SATA_PHY_IPROC_SR:
502659 		rc = brcm_sr_sata_init(port);
503660 		break;
661
+	case BRCM_SATA_PHY_DSL_28NM:
662
+		rc = brcm_dsl_sata_init(port);
663
+		break;
504664 	default:
505665 		rc = -ENODEV;
506666 	}
....@@ -510,10 +670,9 @@
510670 
511671 static void brcm_stb_sata_calibrate(struct brcm_sata_port *port)
512672 {
513
-	void __iomem *base = brcm_sata_pcb_base(port);
514673 	u32 tmp = BIT(8);
515674 
516
-	brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
675
+	brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
517676 			 ~tmp, tmp);
518677 }
519678 
....@@ -542,6 +701,8 @@
542701 };
543702 
544703 static const struct of_device_id brcm_sata_phy_of_match[] = {
704
+	{ .compatible	= "brcm,bcm7216-sata-phy",
705
+	  .data = (void *)BRCM_SATA_PHY_STB_16NM },
545706 	{ .compatible	= "brcm,bcm7445-sata-phy",
546707 	  .data = (void *)BRCM_SATA_PHY_STB_28NM },
547708 	{ .compatible	= "brcm,bcm7425-sata-phy",
....@@ -552,6 +713,8 @@
552713 	  .data = (void *)BRCM_SATA_PHY_IPROC_NSP },
553714 	{ .compatible	= "brcm,iproc-sr-sata-phy",
554715 	  .data = (void *)BRCM_SATA_PHY_IPROC_SR },
716
+	{ .compatible	= "brcm,bcm63138-sata-phy",
717
+	  .data = (void *)BRCM_SATA_PHY_DSL_28NM },
555718 	{},
556719 };
557720 MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
....@@ -600,8 +763,8 @@
600763 		struct brcm_sata_port *port;
601764 
602765 		if (of_property_read_u32(child, "reg", &id)) {
603
-			dev_err(dev, "missing reg property in node %s\n",
604
-					child->name);
766
+			dev_err(dev, "missing reg property in node %pOFn\n",
767
+					child);
605768 			ret = -EINVAL;
606769 			goto put_child;
607770 		}