| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * RTL8XXXU mac80211 USB driver - 8192e specific subdriver |
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| 3 | 4 | * |
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| .. | .. |
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| 10 | 11 | * rtl8723au driver. As the Realtek 8xxx chips are very similar in |
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| 11 | 12 | * their programming interface, I have started adding support for |
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| 12 | 13 | * additional 8xxx chips like the 8192cu, 8188cus, etc. |
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| 13 | | - * |
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| 14 | | - * This program is free software; you can redistribute it and/or modify it |
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| 15 | | - * under the terms of version 2 of the GNU General Public License as |
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| 16 | | - * published by the Free Software Foundation. |
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| 17 | | - * |
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| 18 | | - * This program is distributed in the hope that it will be useful, but WITHOUT |
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| 19 | | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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| 20 | | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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| 21 | | - * more details. |
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| 22 | 14 | */ |
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| 23 | 15 | |
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| 24 | 16 | #include <linux/init.h> |
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| .. | .. |
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| 1066 | 1058 | u32 i, val32; |
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| 1067 | 1059 | int path_a_ok, path_b_ok; |
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| 1068 | 1060 | int retry = 2; |
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| 1069 | | - const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { |
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| 1061 | + static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { |
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| 1070 | 1062 | REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, |
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| 1071 | 1063 | REG_RX_WAIT_CCA, REG_TX_CCK_RFON, |
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| 1072 | 1064 | REG_TX_CCK_BBON, REG_TX_OFDM_RFON, |
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| .. | .. |
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| 1076 | 1068 | REG_RX_TO_RX, REG_STANDBY, |
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| 1077 | 1069 | REG_SLEEP, REG_PMPD_ANAEN |
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| 1078 | 1070 | }; |
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| 1079 | | - const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { |
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| 1071 | + static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { |
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| 1080 | 1072 | REG_TXPAUSE, REG_BEACON_CTRL, |
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| 1081 | 1073 | REG_BEACON_CTRL_1, REG_GPIO_MUXCFG |
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| 1082 | 1074 | }; |
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| 1083 | | - const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { |
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| 1075 | + static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { |
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| 1084 | 1076 | REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, |
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| 1085 | 1077 | REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, |
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| 1086 | 1078 | REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, |
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| .. | .. |
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| 1679 | 1671 | val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); |
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| 1680 | 1672 | val8 &= ~BIT(0); |
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| 1681 | 1673 | rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); |
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| 1674 | + |
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| 1675 | + /* |
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| 1676 | + * Fix transmission failure of rtl8192e. |
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| 1677 | + */ |
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| 1678 | + rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); |
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| 1682 | 1679 | } |
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| 1683 | 1680 | |
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| 1684 | 1681 | struct rtl8xxxu_fileops rtl8192eu_fops = { |
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| .. | .. |
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| 1705 | 1702 | .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), |
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| 1706 | 1703 | .has_s0s1 = 0, |
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| 1707 | 1704 | .gen2_thermal_meter = 1, |
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| 1705 | + .needs_full_init = 1, |
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| 1708 | 1706 | .adda_1t_init = 0x0fc01616, |
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| 1709 | 1707 | .adda_1t_path_on = 0x0fc01616, |
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| 1710 | 1708 | .adda_2t_path_on_a = 0x0fc01616, |
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