~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1037,7 +1037,7 @@
1037	1037	}
1038	1038
1039	1039	/*
1040		- * Configire PCIE after Ini init. SERDES values now come from ini file
	1040	+ * Configure PCIE after Ini init. SERDES values now come from ini file
1041	1041	* This enables PCIe low power mode.
1042	1042	*/
1043	1043	array = power_off ? &ah->iniPcieSerdes :
..	..	@@ -1099,17 +1099,22 @@
1099	1099	{
1100	1100	u32 dma_dbg_chain, dma_dbg_complete;
1101	1101	u8 dcu_chain_state, dcu_complete_state;
	1102	+ unsigned int dbg_reg, reg_offset;
1102	1103	int i;
1103	1104
1104		- for (i = 0; i < NUM_STATUS_READS; i++) {
1105		- if (queue < 6)
1106		- dma_dbg_chain = REG_READ(ah, AR_DMADBG_4);
1107		- else
1108		- dma_dbg_chain = REG_READ(ah, AR_DMADBG_5);
	1105	+ if (queue < 6) {
	1106	+ dbg_reg = AR_DMADBG_4;
	1107	+ reg_offset = queue * 5;
	1108	+ } else {
	1109	+ dbg_reg = AR_DMADBG_5;
	1110	+ reg_offset = (queue - 6) * 5;
	1111	+ }
1109	1112
	1113	+ for (i = 0; i < NUM_STATUS_READS; i++) {
	1114	+ dma_dbg_chain = REG_READ(ah, dbg_reg);
1110	1115	dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);
1111	1116
1112		- dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f;
	1117	+ dcu_chain_state = (dma_dbg_chain >> reg_offset) & 0x1f;
1113	1118	dcu_complete_state = dma_dbg_complete & 0x3;
1114	1119
1115	1120	if ((dcu_chain_state != 0x6) \|\| (dcu_complete_state != 0x1))
..	..	@@ -1128,6 +1133,7 @@
1128	1133	u8 dcu_chain_state, dcu_complete_state;
1129	1134	bool dcu_wait_frdone = false;
1130	1135	unsigned long chk_dcu = 0;
	1136	+ unsigned int reg_offset;
1131	1137	unsigned int i = 0;
1132	1138
1133	1139	dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);
..	..	@@ -1139,12 +1145,15 @@
1139	1145	goto exit;
1140	1146
1141	1147	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1142		- if (i < 6)
	1148	+ if (i < 6) {
1143	1149	chk_dbg = dma_dbg_4;
1144		- else
	1150	+ reg_offset = i * 5;
	1151	+ } else {
1145	1152	chk_dbg = dma_dbg_5;
	1153	+ reg_offset = (i - 6) * 5;
	1154	+ }
1146	1155
1147		- dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f;
	1156	+ dcu_chain_state = (chk_dbg >> reg_offset) & 0x1f;
1148	1157	if (dcu_chain_state == 0x6) {
1149	1158	dcu_wait_frdone = true;
1150	1159	chk_dcu \|= BIT(i);