forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/net/wireless/ath/ath10k/ce.h
....@@ -1,19 +1,8 @@
1
+/* SPDX-License-Identifier: ISC */
12 /*
23  * Copyright (c) 2005-2011 Atheros Communications Inc.
34  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
45  * Copyright (c) 2018 The Linux Foundation. All rights reserved.
5
- *
6
- * Permission to use, copy, modify, and/or distribute this software for any
7
- * purpose with or without fee is hereby granted, provided that the above
8
- * copyright notice and this permission notice appear in all copies.
9
- *
10
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
176  */
187 
198 #ifndef _CE_H_
....@@ -39,8 +28,8 @@
3928 #define CE_DESC_FLAGS_BYTE_SWAP      (1 << 1)
4029 #define CE_WCN3990_DESC_FLAGS_GATHER BIT(31)
4130 
42
-#define CE_DESC_FLAGS_GET_MASK		GENMASK(4, 0)
43
-#define CE_DESC_37BIT_ADDR_MASK		GENMASK_ULL(37, 0)
31
+#define CE_DESC_ADDR_MASK		GENMASK_ULL(34, 0)
32
+#define CE_DESC_ADDR_HI_MASK		GENMASK(4, 0)
4433 
4534 /* Following desc flags are used in QCA99X0 */
4635 #define CE_DESC_FLAGS_HOST_INT_DIS	(1 << 2)
....@@ -104,7 +93,7 @@
10493 	/* Host address space */
10594 	void *base_addr_owner_space_unaligned;
10695 	/* CE address space */
107
-	u32 base_addr_ce_space_unaligned;
96
+	dma_addr_t base_addr_ce_space_unaligned;
10897 
10998 	/*
11099 	 * Actual start of descriptors.
....@@ -115,13 +104,13 @@
115104 	void *base_addr_owner_space;
116105 
117106 	/* CE address space */
118
-	u32 base_addr_ce_space;
107
+	dma_addr_t base_addr_ce_space;
119108 
120109 	char *shadow_base_unaligned;
121110 	struct ce_desc_64 *shadow_base;
122111 
123112 	/* keep last */
124
-	void *per_transfer_context[0];
113
+	void *per_transfer_context[];
125114 };
126115 
127116 struct ath10k_ce_pipe {
....@@ -266,25 +255,31 @@
266255 /*==================CE Interrupt Handlers====================*/
267256 void ath10k_ce_per_engine_service_any(struct ath10k *ar);
268257 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
269
-int ath10k_ce_disable_interrupts(struct ath10k *ar);
258
+void ath10k_ce_disable_interrupt(struct ath10k *ar, int ce_id);
259
+void ath10k_ce_disable_interrupts(struct ath10k *ar);
260
+void ath10k_ce_enable_interrupt(struct ath10k *ar, int ce_id);
270261 void ath10k_ce_enable_interrupts(struct ath10k *ar);
271262 void ath10k_ce_dump_registers(struct ath10k *ar,
272263 			      struct ath10k_fw_crash_data *crash_data);
264
+
273265 void ath10k_ce_alloc_rri(struct ath10k *ar);
274266 void ath10k_ce_free_rri(struct ath10k *ar);
275267 
276268 /* ce_attr.flags values */
277269 /* Use NonSnooping PCIe accesses? */
278
-#define CE_ATTR_NO_SNOOP		1
270
+#define CE_ATTR_NO_SNOOP		BIT(0)
279271 
280272 /* Byte swap data words */
281
-#define CE_ATTR_BYTE_SWAP_DATA		2
273
+#define CE_ATTR_BYTE_SWAP_DATA		BIT(1)
282274 
283275 /* Swizzle descriptors? */
284
-#define CE_ATTR_SWIZZLE_DESCRIPTORS	4
276
+#define CE_ATTR_SWIZZLE_DESCRIPTORS	BIT(2)
285277 
286278 /* no interrupt on copy completion */
287
-#define CE_ATTR_DIS_INTR		8
279
+#define CE_ATTR_DIS_INTR		BIT(3)
280
+
281
+/* no interrupt, only polling */
282
+#define CE_ATTR_POLL			BIT(4)
288283 
289284 /* Attributes of an instance of a Copy Engine */
290285 struct ce_attr {
....@@ -331,6 +326,14 @@
331326 			      void *per_transfer_context,
332327 			      dma_addr_t buffer, u32 nbytes,
333328 			      u32 transfer_id, u32 flags);
329
+	void (*ce_set_src_ring_base_addr_hi)(struct ath10k *ar,
330
+					     u32 ce_ctrl_addr,
331
+					     u64 addr);
332
+	void (*ce_set_dest_ring_base_addr_hi)(struct ath10k *ar,
333
+					      u32 ce_ctrl_addr,
334
+					      u64 addr);
335
+	int (*ce_completed_send_next_nolock)(struct ath10k_ce_pipe *ce_state,
336
+					     void **per_transfer_contextp);
334337 };
335338 
336339 static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
....@@ -369,18 +372,14 @@
369372 	(((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
370373 		CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
371374 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS			0x0000
372
-#define CE_INTERRUPT_SUMMARY		(GENMASK(CE_COUNT_MAX - 1, 0))
373375 
374376 static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar)
375377 {
376378 	struct ath10k_ce *ce = ath10k_ce_priv(ar);
377379 
378
-	if (!ar->hw_params.per_ce_irq)
379
-		return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
380
-			ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
381
-			CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
382
-	else
383
-		return CE_INTERRUPT_SUMMARY;
380
+	return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
381
+		ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
382
+		CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
384383 }
385384 
386385 /* Host software's Copy Engine configuration. */
....@@ -419,7 +418,7 @@
419418 #define PIPEDIR_INOUT   3  /* bidirectional */
420419 
421420 /* Establish a mapping between a service/direction and a pipe. */
422
-struct service_to_pipe {
421
+struct ce_service_to_pipe {
423422 	__le32 service_id;
424423 	__le32 pipedir;
425424 	__le32 pipenum;