forked from ~ljy/RK356X_SDK_RELEASE

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hc
2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/net/ethernet/ni/nixge.c
....@@ -105,11 +105,17 @@
105105 #define NIXGE_MAX_JUMBO_FRAME_SIZE \
106106 	(NIXGE_JUMBO_MTU + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE)
107107 
108
+enum nixge_version {
109
+	NIXGE_V2,
110
+	NIXGE_V3,
111
+	NIXGE_VERSION_COUNT
112
+};
113
+
108114 struct nixge_hw_dma_bd {
109
-	u32 next;
110
-	u32 reserved1;
111
-	u32 phys;
112
-	u32 reserved2;
115
+	u32 next_lo;
116
+	u32 next_hi;
117
+	u32 phys_lo;
118
+	u32 phys_hi;
113119 	u32 reserved3;
114120 	u32 reserved4;
115121 	u32 cntrl;
....@@ -119,10 +125,38 @@
119125 	u32 app2;
120126 	u32 app3;
121127 	u32 app4;
122
-	u32 sw_id_offset;
123
-	u32 reserved5;
128
+	u32 sw_id_offset_lo;
129
+	u32 sw_id_offset_hi;
124130 	u32 reserved6;
125131 };
132
+
133
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
134
+#define nixge_hw_dma_bd_set_addr(bd, field, addr) \
135
+	do { \
136
+		(bd)->field##_lo = lower_32_bits((addr)); \
137
+		(bd)->field##_hi = upper_32_bits((addr)); \
138
+	} while (0)
139
+#else
140
+#define nixge_hw_dma_bd_set_addr(bd, field, addr) \
141
+	((bd)->field##_lo = lower_32_bits((addr)))
142
+#endif
143
+
144
+#define nixge_hw_dma_bd_set_phys(bd, addr) \
145
+	nixge_hw_dma_bd_set_addr((bd), phys, (addr))
146
+
147
+#define nixge_hw_dma_bd_set_next(bd, addr) \
148
+	nixge_hw_dma_bd_set_addr((bd), next, (addr))
149
+
150
+#define nixge_hw_dma_bd_set_offset(bd, addr) \
151
+	nixge_hw_dma_bd_set_addr((bd), sw_id_offset, (addr))
152
+
153
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
154
+#define nixge_hw_dma_bd_get_addr(bd, field) \
155
+	(dma_addr_t)((((u64)(bd)->field##_hi) << 32) | ((bd)->field##_lo))
156
+#else
157
+#define nixge_hw_dma_bd_get_addr(bd, field) \
158
+	(dma_addr_t)((bd)->field##_lo)
159
+#endif
126160 
127161 struct nixge_tx_skb {
128162 	struct sk_buff *skb;
....@@ -176,6 +210,15 @@
176210 	writel(val, priv->dma_regs + offset);
177211 }
178212 
213
+static void nixge_dma_write_desc_reg(struct nixge_priv *priv, off_t offset,
214
+				     dma_addr_t addr)
215
+{
216
+	writel(lower_32_bits(addr), priv->dma_regs + offset);
217
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
218
+	writel(upper_32_bits(addr), priv->dma_regs + offset + 4);
219
+#endif
220
+}
221
+
179222 static u32 nixge_dma_read_reg(const struct nixge_priv *priv, off_t offset)
180223 {
181224 	return readl(priv->dma_regs + offset);
....@@ -202,20 +245,30 @@
202245 static void nixge_hw_dma_bd_release(struct net_device *ndev)
203246 {
204247 	struct nixge_priv *priv = netdev_priv(ndev);
248
+	dma_addr_t phys_addr;
249
+	struct sk_buff *skb;
205250 	int i;
206251 
207
-	for (i = 0; i < RX_BD_NUM; i++) {
208
-		dma_unmap_single(ndev->dev.parent, priv->rx_bd_v[i].phys,
209
-				 NIXGE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
210
-		dev_kfree_skb((struct sk_buff *)
211
-			      (priv->rx_bd_v[i].sw_id_offset));
212
-	}
252
+	if (priv->rx_bd_v) {
253
+		for (i = 0; i < RX_BD_NUM; i++) {
254
+			phys_addr = nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[i],
255
+							     phys);
213256 
214
-	if (priv->rx_bd_v)
257
+			dma_unmap_single(ndev->dev.parent, phys_addr,
258
+					 NIXGE_MAX_JUMBO_FRAME_SIZE,
259
+					 DMA_FROM_DEVICE);
260
+
261
+			skb = (struct sk_buff *)(uintptr_t)
262
+				nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[i],
263
+							 sw_id_offset);
264
+			dev_kfree_skb(skb);
265
+		}
266
+
215267 		dma_free_coherent(ndev->dev.parent,
216268 				  sizeof(*priv->rx_bd_v) * RX_BD_NUM,
217269 				  priv->rx_bd_v,
218270 				  priv->rx_bd_p);
271
+	}
219272 
220273 	if (priv->tx_skb)
221274 		devm_kfree(ndev->dev.parent, priv->tx_skb);
....@@ -231,6 +284,7 @@
231284 {
232285 	struct nixge_priv *priv = netdev_priv(ndev);
233286 	struct sk_buff *skb;
287
+	dma_addr_t phys;
234288 	u32 cr;
235289 	int i;
236290 
....@@ -240,9 +294,9 @@
240294 	priv->rx_bd_ci = 0;
241295 
242296 	/* Allocate the Tx and Rx buffer descriptors. */
243
-	priv->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
244
-					    sizeof(*priv->tx_bd_v) * TX_BD_NUM,
245
-					    &priv->tx_bd_p, GFP_KERNEL);
297
+	priv->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
298
+					   sizeof(*priv->tx_bd_v) * TX_BD_NUM,
299
+					   &priv->tx_bd_p, GFP_KERNEL);
246300 	if (!priv->tx_bd_v)
247301 		goto out;
248302 
....@@ -252,34 +306,37 @@
252306 	if (!priv->tx_skb)
253307 		goto out;
254308 
255
-	priv->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
256
-					    sizeof(*priv->rx_bd_v) * RX_BD_NUM,
257
-					    &priv->rx_bd_p, GFP_KERNEL);
309
+	priv->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
310
+					   sizeof(*priv->rx_bd_v) * RX_BD_NUM,
311
+					   &priv->rx_bd_p, GFP_KERNEL);
258312 	if (!priv->rx_bd_v)
259313 		goto out;
260314 
261315 	for (i = 0; i < TX_BD_NUM; i++) {
262
-		priv->tx_bd_v[i].next = priv->tx_bd_p +
263
-				      sizeof(*priv->tx_bd_v) *
264
-				      ((i + 1) % TX_BD_NUM);
316
+		nixge_hw_dma_bd_set_next(&priv->tx_bd_v[i],
317
+					 priv->tx_bd_p +
318
+					 sizeof(*priv->tx_bd_v) *
319
+					 ((i + 1) % TX_BD_NUM));
265320 	}
266321 
267322 	for (i = 0; i < RX_BD_NUM; i++) {
268
-		priv->rx_bd_v[i].next = priv->rx_bd_p +
269
-				      sizeof(*priv->rx_bd_v) *
270
-				      ((i + 1) % RX_BD_NUM);
323
+		nixge_hw_dma_bd_set_next(&priv->rx_bd_v[i],
324
+					 priv->rx_bd_p
325
+					 + sizeof(*priv->rx_bd_v) *
326
+					 ((i + 1) % RX_BD_NUM));
271327 
272328 		skb = netdev_alloc_skb_ip_align(ndev,
273329 						NIXGE_MAX_JUMBO_FRAME_SIZE);
274330 		if (!skb)
275331 			goto out;
276332 
277
-		priv->rx_bd_v[i].sw_id_offset = (u32)skb;
278
-		priv->rx_bd_v[i].phys =
279
-			dma_map_single(ndev->dev.parent,
280
-				       skb->data,
281
-				       NIXGE_MAX_JUMBO_FRAME_SIZE,
282
-				       DMA_FROM_DEVICE);
333
+		nixge_hw_dma_bd_set_offset(&priv->rx_bd_v[i], (uintptr_t)skb);
334
+		phys = dma_map_single(ndev->dev.parent, skb->data,
335
+				      NIXGE_MAX_JUMBO_FRAME_SIZE,
336
+				      DMA_FROM_DEVICE);
337
+
338
+		nixge_hw_dma_bd_set_phys(&priv->rx_bd_v[i], phys);
339
+
283340 		priv->rx_bd_v[i].cntrl = NIXGE_MAX_JUMBO_FRAME_SIZE;
284341 	}
285342 
....@@ -312,18 +369,18 @@
312369 	/* Populate the tail pointer and bring the Rx Axi DMA engine out of
313370 	 * halted state. This will make the Rx side ready for reception.
314371 	 */
315
-	nixge_dma_write_reg(priv, XAXIDMA_RX_CDESC_OFFSET, priv->rx_bd_p);
372
+	nixge_dma_write_desc_reg(priv, XAXIDMA_RX_CDESC_OFFSET, priv->rx_bd_p);
316373 	cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
317374 	nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,
318375 			    cr | XAXIDMA_CR_RUNSTOP_MASK);
319
-	nixge_dma_write_reg(priv, XAXIDMA_RX_TDESC_OFFSET, priv->rx_bd_p +
376
+	nixge_dma_write_desc_reg(priv, XAXIDMA_RX_TDESC_OFFSET, priv->rx_bd_p +
320377 			    (sizeof(*priv->rx_bd_v) * (RX_BD_NUM - 1)));
321378 
322379 	/* Write to the RS (Run-stop) bit in the Tx channel control register.
323380 	 * Tx channel is now ready to run. But only after we write to the
324381 	 * tail pointer register that the Tx channel will start transmitting.
325382 	 */
326
-	nixge_dma_write_reg(priv, XAXIDMA_TX_CDESC_OFFSET, priv->tx_bd_p);
383
+	nixge_dma_write_desc_reg(priv, XAXIDMA_TX_CDESC_OFFSET, priv->tx_bd_p);
327384 	cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
328385 	nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,
329386 			    cr | XAXIDMA_CR_RUNSTOP_MASK);
....@@ -446,12 +503,13 @@
446503 	return 0;
447504 }
448505 
449
-static int nixge_start_xmit(struct sk_buff *skb, struct net_device *ndev)
506
+static netdev_tx_t nixge_start_xmit(struct sk_buff *skb,
507
+				    struct net_device *ndev)
450508 {
451509 	struct nixge_priv *priv = netdev_priv(ndev);
452510 	struct nixge_hw_dma_bd *cur_p;
453511 	struct nixge_tx_skb *tx_skb;
454
-	dma_addr_t tail_p;
512
+	dma_addr_t tail_p, cur_phys;
455513 	skb_frag_t *frag;
456514 	u32 num_frag;
457515 	u32 ii;
....@@ -466,15 +524,16 @@
466524 		return NETDEV_TX_OK;
467525 	}
468526 
469
-	cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
470
-				     skb_headlen(skb), DMA_TO_DEVICE);
471
-	if (dma_mapping_error(ndev->dev.parent, cur_p->phys))
527
+	cur_phys = dma_map_single(ndev->dev.parent, skb->data,
528
+				  skb_headlen(skb), DMA_TO_DEVICE);
529
+	if (dma_mapping_error(ndev->dev.parent, cur_phys))
472530 		goto drop;
531
+	nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
473532 
474533 	cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
475534 
476535 	tx_skb->skb = NULL;
477
-	tx_skb->mapping = cur_p->phys;
536
+	tx_skb->mapping = cur_phys;
478537 	tx_skb->size = skb_headlen(skb);
479538 	tx_skb->mapped_as_page = false;
480539 
....@@ -485,16 +544,17 @@
485544 		tx_skb = &priv->tx_skb[priv->tx_bd_tail];
486545 		frag = &skb_shinfo(skb)->frags[ii];
487546 
488
-		cur_p->phys = skb_frag_dma_map(ndev->dev.parent, frag, 0,
489
-					       skb_frag_size(frag),
490
-					       DMA_TO_DEVICE);
491
-		if (dma_mapping_error(ndev->dev.parent, cur_p->phys))
547
+		cur_phys = skb_frag_dma_map(ndev->dev.parent, frag, 0,
548
+					    skb_frag_size(frag),
549
+					    DMA_TO_DEVICE);
550
+		if (dma_mapping_error(ndev->dev.parent, cur_phys))
492551 			goto frag_err;
552
+		nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
493553 
494554 		cur_p->cntrl = skb_frag_size(frag);
495555 
496556 		tx_skb->skb = NULL;
497
-		tx_skb->mapping = cur_p->phys;
557
+		tx_skb->mapping = cur_phys;
498558 		tx_skb->size = skb_frag_size(frag);
499559 		tx_skb->mapped_as_page = true;
500560 	}
....@@ -506,7 +566,7 @@
506566 
507567 	tail_p = priv->tx_bd_p + sizeof(*priv->tx_bd_v) * priv->tx_bd_tail;
508568 	/* Start the transfer */
509
-	nixge_dma_write_reg(priv, XAXIDMA_TX_TDESC_OFFSET, tail_p);
569
+	nixge_dma_write_desc_reg(priv, XAXIDMA_TX_TDESC_OFFSET, tail_p);
510570 	++priv->tx_bd_tail;
511571 	priv->tx_bd_tail %= TX_BD_NUM;
512572 
....@@ -537,7 +597,7 @@
537597 	struct nixge_priv *priv = netdev_priv(ndev);
538598 	struct sk_buff *skb, *new_skb;
539599 	struct nixge_hw_dma_bd *cur_p;
540
-	dma_addr_t tail_p = 0;
600
+	dma_addr_t tail_p = 0, cur_phys = 0;
541601 	u32 packets = 0;
542602 	u32 length = 0;
543603 	u32 size = 0;
....@@ -549,13 +609,15 @@
549609 		tail_p = priv->rx_bd_p + sizeof(*priv->rx_bd_v) *
550610 			 priv->rx_bd_ci;
551611 
552
-		skb = (struct sk_buff *)(cur_p->sw_id_offset);
612
+		skb = (struct sk_buff *)(uintptr_t)
613
+			nixge_hw_dma_bd_get_addr(cur_p, sw_id_offset);
553614 
554615 		length = cur_p->status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
555616 		if (length > NIXGE_MAX_JUMBO_FRAME_SIZE)
556617 			length = NIXGE_MAX_JUMBO_FRAME_SIZE;
557618 
558
-		dma_unmap_single(ndev->dev.parent, cur_p->phys,
619
+		dma_unmap_single(ndev->dev.parent,
620
+				 nixge_hw_dma_bd_get_addr(cur_p, phys),
559621 				 NIXGE_MAX_JUMBO_FRAME_SIZE,
560622 				 DMA_FROM_DEVICE);
561623 
....@@ -579,16 +641,17 @@
579641 		if (!new_skb)
580642 			return packets;
581643 
582
-		cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
583
-					     NIXGE_MAX_JUMBO_FRAME_SIZE,
584
-					     DMA_FROM_DEVICE);
585
-		if (dma_mapping_error(ndev->dev.parent, cur_p->phys)) {
644
+		cur_phys = dma_map_single(ndev->dev.parent, new_skb->data,
645
+					  NIXGE_MAX_JUMBO_FRAME_SIZE,
646
+					  DMA_FROM_DEVICE);
647
+		if (dma_mapping_error(ndev->dev.parent, cur_phys)) {
586648 			/* FIXME: bail out and clean up */
587649 			netdev_err(ndev, "Failed to map ...\n");
588650 		}
651
+		nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
589652 		cur_p->cntrl = NIXGE_MAX_JUMBO_FRAME_SIZE;
590653 		cur_p->status = 0;
591
-		cur_p->sw_id_offset = (u32)new_skb;
654
+		nixge_hw_dma_bd_set_offset(cur_p, (uintptr_t)new_skb);
592655 
593656 		++priv->rx_bd_ci;
594657 		priv->rx_bd_ci %= RX_BD_NUM;
....@@ -599,7 +662,7 @@
599662 	ndev->stats.rx_bytes += size;
600663 
601664 	if (tail_p)
602
-		nixge_dma_write_reg(priv, XAXIDMA_RX_TDESC_OFFSET, tail_p);
665
+		nixge_dma_write_desc_reg(priv, XAXIDMA_RX_TDESC_OFFSET, tail_p);
603666 
604667 	return packets;
605668 }
....@@ -637,6 +700,7 @@
637700 	struct nixge_priv *priv = netdev_priv(_ndev);
638701 	struct net_device *ndev = _ndev;
639702 	unsigned int status;
703
+	dma_addr_t phys;
640704 	u32 cr;
641705 
642706 	status = nixge_dma_read_reg(priv, XAXIDMA_TX_SR_OFFSET);
....@@ -650,9 +714,11 @@
650714 		return IRQ_NONE;
651715 	}
652716 	if (status & XAXIDMA_IRQ_ERROR_MASK) {
717
+		phys = nixge_hw_dma_bd_get_addr(&priv->tx_bd_v[priv->tx_bd_ci],
718
+						phys);
719
+
653720 		netdev_err(ndev, "DMA Tx error 0x%x\n", status);
654
-		netdev_err(ndev, "Current BD is at: 0x%x\n",
655
-			   (priv->tx_bd_v[priv->tx_bd_ci]).phys);
721
+		netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);
656722 
657723 		cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
658724 		/* Disable coalesce, delay timer and error interrupts */
....@@ -678,6 +744,7 @@
678744 	struct nixge_priv *priv = netdev_priv(_ndev);
679745 	struct net_device *ndev = _ndev;
680746 	unsigned int status;
747
+	dma_addr_t phys;
681748 	u32 cr;
682749 
683750 	status = nixge_dma_read_reg(priv, XAXIDMA_RX_SR_OFFSET);
....@@ -697,9 +764,10 @@
697764 		return IRQ_NONE;
698765 	}
699766 	if (status & XAXIDMA_IRQ_ERROR_MASK) {
767
+		phys = nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[priv->rx_bd_ci],
768
+						phys);
700769 		netdev_err(ndev, "DMA Rx error 0x%x\n", status);
701
-		netdev_err(ndev, "Current BD is at: 0x%x\n",
702
-			   (priv->rx_bd_v[priv->rx_bd_ci]).phys);
770
+		netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);
703771 
704772 		cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
705773 		/* Disable coalesce, delay timer and error interrupts */
....@@ -720,9 +788,9 @@
720788 	return IRQ_HANDLED;
721789 }
722790 
723
-static void nixge_dma_err_handler(unsigned long data)
791
+static void nixge_dma_err_handler(struct tasklet_struct *t)
724792 {
725
-	struct nixge_priv *lp = (struct nixge_priv *)data;
793
+	struct nixge_priv *lp = from_tasklet(lp, t, dma_err_tasklet);
726794 	struct nixge_hw_dma_bd *cur_p;
727795 	struct nixge_tx_skb *tx_skb;
728796 	u32 cr, i;
....@@ -735,10 +803,10 @@
735803 		tx_skb = &lp->tx_skb[i];
736804 		nixge_tx_skb_unmap(lp, tx_skb);
737805 
738
-		cur_p->phys = 0;
806
+		nixge_hw_dma_bd_set_phys(cur_p, 0);
739807 		cur_p->cntrl = 0;
740808 		cur_p->status = 0;
741
-		cur_p->sw_id_offset = 0;
809
+		nixge_hw_dma_bd_set_offset(cur_p, 0);
742810 	}
743811 
744812 	for (i = 0; i < RX_BD_NUM; i++) {
....@@ -779,18 +847,18 @@
779847 	/* Populate the tail pointer and bring the Rx Axi DMA engine out of
780848 	 * halted state. This will make the Rx side ready for reception.
781849 	 */
782
-	nixge_dma_write_reg(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
850
+	nixge_dma_write_desc_reg(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
783851 	cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET);
784852 	nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET,
785853 			    cr | XAXIDMA_CR_RUNSTOP_MASK);
786
-	nixge_dma_write_reg(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
854
+	nixge_dma_write_desc_reg(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
787855 			    (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
788856 
789857 	/* Write to the RS (Run-stop) bit in the Tx channel control register.
790858 	 * Tx channel is now ready to run. But only after we write to the
791859 	 * tail pointer register that the Tx channel will start transmitting
792860 	 */
793
-	nixge_dma_write_reg(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
861
+	nixge_dma_write_desc_reg(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
794862 	cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET);
795863 	nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET,
796864 			    cr | XAXIDMA_CR_RUNSTOP_MASK);
....@@ -812,8 +880,7 @@
812880 	phy_start(phy);
813881 
814882 	/* Enable tasklets for Axi DMA error handling */
815
-	tasklet_init(&priv->dma_err_tasklet, nixge_dma_err_handler,
816
-		     (unsigned long)priv);
883
+	tasklet_setup(&priv->dma_err_tasklet, nixge_dma_err_handler);
817884 
818885 	napi_enable(&priv->napi);
819886 
....@@ -833,6 +900,7 @@
833900 err_rx_irq:
834901 	free_irq(priv->tx_irq, ndev);
835902 err_tx_irq:
903
+	napi_disable(&priv->napi);
836904 	phy_stop(phy);
837905 	phy_disconnect(phy);
838906 	tasklet_kill(&priv->dma_err_tasklet);
....@@ -924,7 +992,7 @@
924992 				       struct ethtool_drvinfo *ed)
925993 {
926994 	strlcpy(ed->driver, "nixge", sizeof(ed->driver));
927
-	strlcpy(ed->bus_info, "platform", sizeof(ed->driver));
995
+	strlcpy(ed->bus_info, "platform", sizeof(ed->bus_info));
928996 }
929997 
930998 static int nixge_ethtools_get_coalesce(struct net_device *ndev,
....@@ -953,27 +1021,6 @@
9531021 		return -EBUSY;
9541022 	}
9551023 
956
-	if (ecoalesce->rx_coalesce_usecs ||
957
-	    ecoalesce->rx_coalesce_usecs_irq ||
958
-	    ecoalesce->rx_max_coalesced_frames_irq ||
959
-	    ecoalesce->tx_coalesce_usecs ||
960
-	    ecoalesce->tx_coalesce_usecs_irq ||
961
-	    ecoalesce->tx_max_coalesced_frames_irq ||
962
-	    ecoalesce->stats_block_coalesce_usecs ||
963
-	    ecoalesce->use_adaptive_rx_coalesce ||
964
-	    ecoalesce->use_adaptive_tx_coalesce ||
965
-	    ecoalesce->pkt_rate_low ||
966
-	    ecoalesce->rx_coalesce_usecs_low ||
967
-	    ecoalesce->rx_max_coalesced_frames_low ||
968
-	    ecoalesce->tx_coalesce_usecs_low ||
969
-	    ecoalesce->tx_max_coalesced_frames_low ||
970
-	    ecoalesce->pkt_rate_high ||
971
-	    ecoalesce->rx_coalesce_usecs_high ||
972
-	    ecoalesce->rx_max_coalesced_frames_high ||
973
-	    ecoalesce->tx_coalesce_usecs_high ||
974
-	    ecoalesce->tx_max_coalesced_frames_high ||
975
-	    ecoalesce->rate_sample_interval)
976
-		return -EOPNOTSUPP;
9771024 	if (ecoalesce->rx_max_coalesced_frames)
9781025 		priv->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
9791026 	if (ecoalesce->tx_max_coalesced_frames)
....@@ -1017,6 +1064,7 @@
10171064 }
10181065 
10191066 static const struct ethtool_ops nixge_ethtool_ops = {
1067
+	.supported_coalesce_params = ETHTOOL_COALESCE_MAX_FRAMES,
10201068 	.get_drvinfo    = nixge_ethtools_get_drvinfo,
10211069 	.get_coalesce   = nixge_ethtools_get_coalesce,
10221070 	.set_coalesce   = nixge_ethtools_set_coalesce,
....@@ -1165,11 +1213,60 @@
11651213 	return mac;
11661214 }
11671215 
1216
+/* Match table for of_platform binding */
1217
+static const struct of_device_id nixge_dt_ids[] = {
1218
+	{ .compatible = "ni,xge-enet-2.00", .data = (void *)NIXGE_V2 },
1219
+	{ .compatible = "ni,xge-enet-3.00", .data = (void *)NIXGE_V3 },
1220
+	{},
1221
+};
1222
+MODULE_DEVICE_TABLE(of, nixge_dt_ids);
1223
+
1224
+static int nixge_of_get_resources(struct platform_device *pdev)
1225
+{
1226
+	const struct of_device_id *of_id;
1227
+	enum nixge_version version;
1228
+	struct resource *ctrlres;
1229
+	struct resource *dmares;
1230
+	struct net_device *ndev;
1231
+	struct nixge_priv *priv;
1232
+
1233
+	ndev = platform_get_drvdata(pdev);
1234
+	priv = netdev_priv(ndev);
1235
+	of_id = of_match_node(nixge_dt_ids, pdev->dev.of_node);
1236
+	if (!of_id)
1237
+		return -ENODEV;
1238
+
1239
+	version = (enum nixge_version)of_id->data;
1240
+	if (version <= NIXGE_V2)
1241
+		dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1242
+	else
1243
+		dmares = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1244
+						      "dma");
1245
+
1246
+	priv->dma_regs = devm_ioremap_resource(&pdev->dev, dmares);
1247
+	if (IS_ERR(priv->dma_regs)) {
1248
+		netdev_err(ndev, "failed to map dma regs\n");
1249
+		return PTR_ERR(priv->dma_regs);
1250
+	}
1251
+	if (version <= NIXGE_V2) {
1252
+		priv->ctrl_regs = priv->dma_regs + NIXGE_REG_CTRL_OFFSET;
1253
+	} else {
1254
+		ctrlres = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1255
+						       "ctrl");
1256
+		priv->ctrl_regs = devm_ioremap_resource(&pdev->dev, ctrlres);
1257
+	}
1258
+	if (IS_ERR(priv->ctrl_regs)) {
1259
+		netdev_err(ndev, "failed to map ctrl regs\n");
1260
+		return PTR_ERR(priv->ctrl_regs);
1261
+	}
1262
+	return 0;
1263
+}
1264
+
11681265 static int nixge_probe(struct platform_device *pdev)
11691266 {
1267
+	struct device_node *mn, *phy_node;
11701268 	struct nixge_priv *priv;
11711269 	struct net_device *ndev;
1172
-	struct resource *dmares;
11731270 	const u8 *mac_addr;
11741271 	int err;
11751272 
....@@ -1201,61 +1298,71 @@
12011298 	priv->dev = &pdev->dev;
12021299 
12031300 	netif_napi_add(ndev, &priv->napi, nixge_poll, NAPI_POLL_WEIGHT);
1204
-
1205
-	dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1206
-	priv->dma_regs = devm_ioremap_resource(&pdev->dev, dmares);
1207
-	if (IS_ERR(priv->dma_regs)) {
1208
-		netdev_err(ndev, "failed to map dma regs\n");
1209
-		return PTR_ERR(priv->dma_regs);
1210
-	}
1211
-	priv->ctrl_regs = priv->dma_regs + NIXGE_REG_CTRL_OFFSET;
1301
+	err = nixge_of_get_resources(pdev);
1302
+	if (err)
1303
+		goto free_netdev;
12121304 	__nixge_hw_set_mac_address(ndev);
12131305 
12141306 	priv->tx_irq = platform_get_irq_byname(pdev, "tx");
12151307 	if (priv->tx_irq < 0) {
12161308 		netdev_err(ndev, "could not find 'tx' irq");
1217
-		return priv->tx_irq;
1309
+		err = priv->tx_irq;
1310
+		goto free_netdev;
12181311 	}
12191312 
12201313 	priv->rx_irq = platform_get_irq_byname(pdev, "rx");
12211314 	if (priv->rx_irq < 0) {
12221315 		netdev_err(ndev, "could not find 'rx' irq");
1223
-		return priv->rx_irq;
1316
+		err = priv->rx_irq;
1317
+		goto free_netdev;
12241318 	}
12251319 
12261320 	priv->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
12271321 	priv->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
12281322 
1229
-	err = nixge_mdio_setup(priv, pdev->dev.of_node);
1323
+	mn = of_get_child_by_name(pdev->dev.of_node, "mdio");
1324
+	if (mn) {
1325
+		err = nixge_mdio_setup(priv, mn);
1326
+		of_node_put(mn);
1327
+		if (err) {
1328
+			netdev_err(ndev, "error registering mdio bus");
1329
+			goto free_netdev;
1330
+		}
1331
+	}
1332
+
1333
+	err = of_get_phy_mode(pdev->dev.of_node, &priv->phy_mode);
12301334 	if (err) {
1231
-		netdev_err(ndev, "error registering mdio bus");
1232
-		goto free_netdev;
1233
-	}
1234
-
1235
-	priv->phy_mode = of_get_phy_mode(pdev->dev.of_node);
1236
-	if ((int)priv->phy_mode < 0) {
12371335 		netdev_err(ndev, "not find \"phy-mode\" property\n");
1238
-		err = -EINVAL;
12391336 		goto unregister_mdio;
12401337 	}
12411338 
1242
-	priv->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1243
-	if (!priv->phy_node) {
1244
-		netdev_err(ndev, "not find \"phy-handle\" property\n");
1245
-		err = -EINVAL;
1246
-		goto unregister_mdio;
1339
+	phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1340
+	if (!phy_node && of_phy_is_fixed_link(pdev->dev.of_node)) {
1341
+		err = of_phy_register_fixed_link(pdev->dev.of_node);
1342
+		if (err < 0) {
1343
+			netdev_err(ndev, "broken fixed-link specification\n");
1344
+			goto unregister_mdio;
1345
+		}
1346
+		phy_node = of_node_get(pdev->dev.of_node);
12471347 	}
1348
+	priv->phy_node = phy_node;
12481349 
12491350 	err = register_netdev(priv->ndev);
12501351 	if (err) {
12511352 		netdev_err(ndev, "register_netdev() error (%i)\n", err);
1252
-		goto unregister_mdio;
1353
+		goto free_phy;
12531354 	}
12541355 
12551356 	return 0;
12561357 
1358
+free_phy:
1359
+	if (of_phy_is_fixed_link(pdev->dev.of_node))
1360
+		of_phy_deregister_fixed_link(pdev->dev.of_node);
1361
+	of_node_put(phy_node);
1362
+
12571363 unregister_mdio:
1258
-	mdiobus_unregister(priv->mii_bus);
1364
+	if (priv->mii_bus)
1365
+		mdiobus_unregister(priv->mii_bus);
12591366 
12601367 free_netdev:
12611368 	free_netdev(ndev);
....@@ -1270,19 +1377,17 @@
12701377 
12711378 	unregister_netdev(ndev);
12721379 
1273
-	mdiobus_unregister(priv->mii_bus);
1380
+	if (of_phy_is_fixed_link(pdev->dev.of_node))
1381
+		of_phy_deregister_fixed_link(pdev->dev.of_node);
1382
+	of_node_put(priv->phy_node);
1383
+
1384
+	if (priv->mii_bus)
1385
+		mdiobus_unregister(priv->mii_bus);
12741386 
12751387 	free_netdev(ndev);
12761388 
12771389 	return 0;
12781390 }
1279
-
1280
-/* Match table for of_platform binding */
1281
-static const struct of_device_id nixge_dt_ids[] = {
1282
-	{ .compatible = "ni,xge-enet-2.00", },
1283
-	{},
1284
-};
1285
-MODULE_DEVICE_TABLE(of, nixge_dt_ids);
12861391 
12871392 static struct platform_driver nixge_driver = {
12881393 	.probe		= nixge_probe,