.. | .. |
---|
756 | 756 | * Allocate the hardware ring and PCI DMA bus address space for said. |
---|
757 | 757 | */ |
---|
758 | 758 | size_t hwlen = nelem * hwsize + stat_size; |
---|
759 | | - void *hwring = dma_zalloc_coherent(dev, hwlen, busaddrp, GFP_KERNEL); |
---|
| 759 | + void *hwring = dma_alloc_coherent(dev, hwlen, busaddrp, GFP_KERNEL); |
---|
760 | 760 | |
---|
761 | 761 | if (!hwring) |
---|
762 | 762 | return NULL; |
---|
.. | .. |
---|
1154 | 1154 | * |
---|
1155 | 1155 | * Add a packet to an SGE Ethernet TX queue. Runs with softirqs disabled. |
---|
1156 | 1156 | */ |
---|
1157 | | -int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev) |
---|
| 1157 | +netdev_tx_t t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev) |
---|
1158 | 1158 | { |
---|
1159 | 1159 | u32 wr_mid; |
---|
1160 | 1160 | u64 cntrl, *end; |
---|
.. | .. |
---|
1692 | 1692 | * restore_rx_bufs - put back a packet's RX buffers |
---|
1693 | 1693 | * @gl: the packet gather list |
---|
1694 | 1694 | * @fl: the SGE Free List |
---|
1695 | | - * @nfrags: how many fragments in @si |
---|
| 1695 | + * @frags: how many fragments in @si |
---|
1696 | 1696 | * |
---|
1697 | 1697 | * Called when we find out that the current packet, @si, can't be |
---|
1698 | 1698 | * processed right away for some reason. This is a very rare event and |
---|
.. | .. |
---|
2044 | 2044 | */ |
---|
2045 | 2045 | irq_handler_t t4vf_intr_handler(struct adapter *adapter) |
---|
2046 | 2046 | { |
---|
2047 | | - BUG_ON((adapter->flags & (USING_MSIX|USING_MSI)) == 0); |
---|
2048 | | - if (adapter->flags & USING_MSIX) |
---|
| 2047 | + BUG_ON((adapter->flags & |
---|
| 2048 | + (CXGB4VF_USING_MSIX | CXGB4VF_USING_MSI)) == 0); |
---|
| 2049 | + if (adapter->flags & CXGB4VF_USING_MSIX) |
---|
2049 | 2050 | return t4vf_sge_intr_msix; |
---|
2050 | 2051 | else |
---|
2051 | 2052 | return t4vf_intr_msi; |
---|
.. | .. |
---|
2053 | 2054 | |
---|
2054 | 2055 | /** |
---|
2055 | 2056 | * sge_rx_timer_cb - perform periodic maintenance of SGE RX queues |
---|
2056 | | - * @data: the adapter |
---|
| 2057 | + * @t: Rx timer |
---|
2057 | 2058 | * |
---|
2058 | 2059 | * Runs periodically from a timer to perform maintenance of SGE RX queues. |
---|
2059 | 2060 | * |
---|
.. | .. |
---|
2112 | 2113 | |
---|
2113 | 2114 | /** |
---|
2114 | 2115 | * sge_tx_timer_cb - perform periodic maintenance of SGE Tx queues |
---|
2115 | | - * @data: the adapter |
---|
| 2116 | + * @t: Tx timer |
---|
2116 | 2117 | * |
---|
2117 | 2118 | * Runs periodically from a timer to perform maintenance of SGE TX queues. |
---|
2118 | 2119 | * |
---|
.. | .. |
---|
2209 | 2210 | struct port_info *pi = netdev_priv(dev); |
---|
2210 | 2211 | struct fw_iq_cmd cmd, rpl; |
---|
2211 | 2212 | int ret, iqandst, flsz = 0; |
---|
2212 | | - int relaxed = !(adapter->flags & ROOT_NO_RELAXED_ORDERING); |
---|
| 2213 | + int relaxed = !(adapter->flags & CXGB4VF_ROOT_NO_RELAXED_ORDERING); |
---|
2213 | 2214 | |
---|
2214 | 2215 | /* |
---|
2215 | 2216 | * If we're using MSI interrupts and we're not initializing the |
---|
.. | .. |
---|
2218 | 2219 | * the Forwarded Interrupt Queue must be set up before any other |
---|
2219 | 2220 | * ingress queue ... |
---|
2220 | 2221 | */ |
---|
2221 | | - if ((adapter->flags & USING_MSI) && rspq != &adapter->sge.intrq) { |
---|
| 2222 | + if ((adapter->flags & CXGB4VF_USING_MSI) && |
---|
| 2223 | + rspq != &adapter->sge.intrq) { |
---|
2222 | 2224 | iqandst = SGE_INTRDST_IQ; |
---|
2223 | 2225 | intr_dest = adapter->sge.intrq.abs_id; |
---|
2224 | 2226 | } else |
---|
.. | .. |
---|
2268 | 2270 | cmd.iqaddr = cpu_to_be64(rspq->phys_addr); |
---|
2269 | 2271 | |
---|
2270 | 2272 | if (fl) { |
---|
2271 | | - enum chip_type chip = |
---|
| 2273 | + unsigned int chip_ver = |
---|
2272 | 2274 | CHELSIO_CHIP_VERSION(adapter->params.chip); |
---|
2273 | 2275 | /* |
---|
2274 | 2276 | * Allocate the ring for the hardware free list (with space |
---|
.. | .. |
---|
2319 | 2321 | */ |
---|
2320 | 2322 | cmd.fl0dcaen_to_fl0cidxfthresh = |
---|
2321 | 2323 | cpu_to_be16( |
---|
2322 | | - FW_IQ_CMD_FL0FBMIN_V(chip <= CHELSIO_T5 ? |
---|
2323 | | - FETCHBURSTMIN_128B_X : |
---|
2324 | | - FETCHBURSTMIN_64B_X) | |
---|
2325 | | - FW_IQ_CMD_FL0FBMAX_V((chip <= CHELSIO_T5) ? |
---|
| 2324 | + FW_IQ_CMD_FL0FBMIN_V(chip_ver <= CHELSIO_T5 |
---|
| 2325 | + ? FETCHBURSTMIN_128B_X |
---|
| 2326 | + : FETCHBURSTMIN_64B_T6_X) | |
---|
| 2327 | + FW_IQ_CMD_FL0FBMAX_V((chip_ver <= CHELSIO_T5) ? |
---|
2326 | 2328 | FETCHBURSTMAX_512B_X : |
---|
2327 | 2329 | FETCHBURSTMAX_256B_X)); |
---|
2328 | 2330 | cmd.fl0size = cpu_to_be16(flsz); |
---|
.. | .. |
---|
2403 | 2405 | * t4vf_sge_alloc_eth_txq - allocate an SGE Ethernet TX Queue |
---|
2404 | 2406 | * @adapter: the adapter |
---|
2405 | 2407 | * @txq: pointer to the new txq to be filled in |
---|
| 2408 | + * @dev: the network device |
---|
2406 | 2409 | * @devq: the network TX queue associated with the new txq |
---|
2407 | 2410 | * @iqid: the relative ingress queue ID to which events relating to |
---|
2408 | 2411 | * the new txq should be directed |
---|
.. | .. |
---|
2411 | 2414 | struct net_device *dev, struct netdev_queue *devq, |
---|
2412 | 2415 | unsigned int iqid) |
---|
2413 | 2416 | { |
---|
| 2417 | + unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip); |
---|
| 2418 | + struct port_info *pi = netdev_priv(dev); |
---|
| 2419 | + struct fw_eq_eth_cmd cmd, rpl; |
---|
2414 | 2420 | struct sge *s = &adapter->sge; |
---|
2415 | 2421 | int ret, nentries; |
---|
2416 | | - struct fw_eq_eth_cmd cmd, rpl; |
---|
2417 | | - struct port_info *pi = netdev_priv(dev); |
---|
2418 | 2422 | |
---|
2419 | 2423 | /* |
---|
2420 | 2424 | * Calculate the size of the hardware TX Queue (including the Status |
---|
.. | .. |
---|
2448 | 2452 | cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_ALLOC_F | |
---|
2449 | 2453 | FW_EQ_ETH_CMD_EQSTART_F | |
---|
2450 | 2454 | FW_LEN16(cmd)); |
---|
2451 | | - cmd.viid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_AUTOEQUEQE_F | |
---|
2452 | | - FW_EQ_ETH_CMD_VIID_V(pi->viid)); |
---|
| 2455 | + cmd.autoequiqe_to_viid = cpu_to_be32(FW_EQ_ETH_CMD_AUTOEQUEQE_F | |
---|
| 2456 | + FW_EQ_ETH_CMD_VIID_V(pi->viid)); |
---|
2453 | 2457 | cmd.fetchszm_to_iqid = |
---|
2454 | 2458 | cpu_to_be32(FW_EQ_ETH_CMD_HOSTFCMODE_V(SGE_HOSTFCMODE_STPG) | |
---|
2455 | 2459 | FW_EQ_ETH_CMD_PCIECHN_V(pi->port_id) | |
---|
2456 | 2460 | FW_EQ_ETH_CMD_IQID_V(iqid)); |
---|
2457 | 2461 | cmd.dcaen_to_eqsize = |
---|
2458 | | - cpu_to_be32(FW_EQ_ETH_CMD_FBMIN_V(SGE_FETCHBURSTMIN_64B) | |
---|
2459 | | - FW_EQ_ETH_CMD_FBMAX_V(SGE_FETCHBURSTMAX_512B) | |
---|
| 2462 | + cpu_to_be32(FW_EQ_ETH_CMD_FBMIN_V(chip_ver <= CHELSIO_T5 |
---|
| 2463 | + ? FETCHBURSTMIN_64B_X |
---|
| 2464 | + : FETCHBURSTMIN_64B_T6_X) | |
---|
| 2465 | + FW_EQ_ETH_CMD_FBMAX_V(FETCHBURSTMAX_512B_X) | |
---|
2460 | 2466 | FW_EQ_ETH_CMD_CIDXFTHRESH_V( |
---|
2461 | | - SGE_CIDXFLUSHTHRESH_32) | |
---|
| 2467 | + CIDXFLUSHTHRESH_32_X) | |
---|
2462 | 2468 | FW_EQ_ETH_CMD_EQSIZE_V(nentries)); |
---|
2463 | 2469 | cmd.eqaddr = cpu_to_be64(txq->q.phys_addr); |
---|
2464 | 2470 | |
---|