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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/net/ethernet/amazon/ena/ena_eth_io_defs.h
....@@ -1,57 +1,23 @@
1
+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
12 /*
2
- * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates.
3
- *
4
- * This software is available to you under a choice of one of two
5
- * licenses.  You may choose to be licensed under the terms of the GNU
6
- * General Public License (GPL) Version 2, available from the file
7
- * COPYING in the main directory of this source tree, or the
8
- * BSD license below:
9
- *
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- *     Redistribution and use in source and binary forms, with or
11
- *     without modification, are permitted provided that the following
12
- *     conditions are met:
13
- *
14
- *      - Redistributions of source code must retain the above
15
- *        copyright notice, this list of conditions and the following
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- *        disclaimer.
17
- *
18
- *      - Redistributions in binary form must reproduce the above
19
- *        copyright notice, this list of conditions and the following
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- *        disclaimer in the documentation and/or other materials
21
- *        provided with the distribution.
22
- *
23
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30
- * SOFTWARE.
3
+ * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
314  */
325 #ifndef _ENA_ETH_IO_H_
336 #define _ENA_ETH_IO_H_
347 
358 enum ena_eth_io_l3_proto_index {
36
-	ENA_ETH_IO_L3_PROTO_UNKNOWN	= 0,
37
-
38
-	ENA_ETH_IO_L3_PROTO_IPV4	= 8,
39
-
40
-	ENA_ETH_IO_L3_PROTO_IPV6	= 11,
41
-
42
-	ENA_ETH_IO_L3_PROTO_FCOE	= 21,
43
-
44
-	ENA_ETH_IO_L3_PROTO_ROCE	= 22,
9
+	ENA_ETH_IO_L3_PROTO_UNKNOWN                 = 0,
10
+	ENA_ETH_IO_L3_PROTO_IPV4                    = 8,
11
+	ENA_ETH_IO_L3_PROTO_IPV6                    = 11,
12
+	ENA_ETH_IO_L3_PROTO_FCOE                    = 21,
13
+	ENA_ETH_IO_L3_PROTO_ROCE                    = 22,
4514 };
4615 
4716 enum ena_eth_io_l4_proto_index {
48
-	ENA_ETH_IO_L4_PROTO_UNKNOWN		= 0,
49
-
50
-	ENA_ETH_IO_L4_PROTO_TCP			= 12,
51
-
52
-	ENA_ETH_IO_L4_PROTO_UDP			= 13,
53
-
54
-	ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE	= 23,
17
+	ENA_ETH_IO_L4_PROTO_UNKNOWN                 = 0,
18
+	ENA_ETH_IO_L4_PROTO_TCP                     = 12,
19
+	ENA_ETH_IO_L4_PROTO_UDP                     = 13,
20
+	ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE          = 23,
5521 };
5622 
5723 struct ena_eth_io_tx_desc {
....@@ -242,9 +208,13 @@
242208 	 *    checksum error detected, or, the controller didn't
243209 	 *    validate the checksum. This bit is valid only when
244210 	 *    l4_proto_idx indicates TCP/UDP packet, and,
245
-	 *    ipv4_frag is not set
211
+	 *    ipv4_frag is not set. This bit is valid only when
212
+	 *    l4_csum_checked below is set.
246213 	 * 15 : ipv4_frag - Indicates IPv4 fragmented packet
247
-	 * 23:16 : reserved16
214
+	 * 16 : l4_csum_checked - L4 checksum was verified
215
+	 *    (could be OK or error), when cleared the status of
216
+	 *    checksum is unknown
217
+	 * 23:17 : reserved17 - MBZ
248218 	 * 24 : phase
249219 	 * 25 : l3_csum2 - second checksum engine result
250220 	 * 26 : first - Indicates first descriptor in
....@@ -267,7 +237,9 @@
267237 
268238 	u16 sub_qid;
269239 
270
-	u16 reserved;
240
+	u8 offset;
241
+
242
+	u8 reserved;
271243 };
272244 
273245 /* 8-word format */
....@@ -303,114 +275,116 @@
303275 };
304276 
305277 /* tx_desc */
306
-#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
307
-#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
308
-#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
309
-#define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
310
-#define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
311
-#define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
312
-#define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
313
-#define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
314
-#define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
315
-#define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
316
-#define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
317
-#define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
318
-#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
319
-#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
320
-#define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
321
-#define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
322
-#define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
323
-#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
324
-#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
325
-#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
326
-#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
327
-#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
328
-#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
329
-#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
330
-#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
331
-#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
332
-#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
333
-#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
334
-#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
335
-#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
336
-#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
337
-#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
338
-#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
278
+#define ENA_ETH_IO_TX_DESC_LENGTH_MASK                      GENMASK(15, 0)
279
+#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT                  16
280
+#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK                   GENMASK(21, 16)
281
+#define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT                  23
282
+#define ENA_ETH_IO_TX_DESC_META_DESC_MASK                   BIT(23)
283
+#define ENA_ETH_IO_TX_DESC_PHASE_SHIFT                      24
284
+#define ENA_ETH_IO_TX_DESC_PHASE_MASK                       BIT(24)
285
+#define ENA_ETH_IO_TX_DESC_FIRST_SHIFT                      26
286
+#define ENA_ETH_IO_TX_DESC_FIRST_MASK                       BIT(26)
287
+#define ENA_ETH_IO_TX_DESC_LAST_SHIFT                       27
288
+#define ENA_ETH_IO_TX_DESC_LAST_MASK                        BIT(27)
289
+#define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT                   28
290
+#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK                    BIT(28)
291
+#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK                GENMASK(3, 0)
292
+#define ENA_ETH_IO_TX_DESC_DF_SHIFT                         4
293
+#define ENA_ETH_IO_TX_DESC_DF_MASK                          BIT(4)
294
+#define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT                     7
295
+#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK                      BIT(7)
296
+#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT               8
297
+#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK                GENMASK(12, 8)
298
+#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT                 13
299
+#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK                  BIT(13)
300
+#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT                 14
301
+#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK                  BIT(14)
302
+#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT           15
303
+#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK            BIT(15)
304
+#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT            17
305
+#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK             BIT(17)
306
+#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT                  22
307
+#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK                   GENMASK(31, 22)
308
+#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK                     GENMASK(15, 0)
309
+#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT              24
310
+#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK               GENMASK(31, 24)
339311 
340312 /* tx_meta_desc */
341
-#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
342
-#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
343
-#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
344
-#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
345
-#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
346
-#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
347
-#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
348
-#define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
349
-#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
350
-#define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
351
-#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
352
-#define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
353
-#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
354
-#define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
355
-#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
356
-#define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
357
-#define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
358
-#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
359
-#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
360
-#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
361
-#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
362
-#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
363
-#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
364
-#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
365
-#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
366
-#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
367
-#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
313
+#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK              GENMASK(9, 0)
314
+#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT             14
315
+#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK              BIT(14)
316
+#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT                16
317
+#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK                 GENMASK(19, 16)
318
+#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT         20
319
+#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK          BIT(20)
320
+#define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT            21
321
+#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK             BIT(21)
322
+#define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT             23
323
+#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK              BIT(23)
324
+#define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT                 24
325
+#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK                  BIT(24)
326
+#define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT                 26
327
+#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK                  BIT(26)
328
+#define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT                  27
329
+#define ENA_ETH_IO_TX_META_DESC_LAST_MASK                   BIT(27)
330
+#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT              28
331
+#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK               BIT(28)
332
+#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK              GENMASK(5, 0)
333
+#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK             GENMASK(7, 0)
334
+#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT            8
335
+#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK             GENMASK(15, 8)
336
+#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT   16
337
+#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK    GENMASK(21, 16)
338
+#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT                22
339
+#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK                 GENMASK(31, 22)
368340 
369341 /* tx_cdesc */
370
-#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
342
+#define ENA_ETH_IO_TX_CDESC_PHASE_MASK                      BIT(0)
371343 
372344 /* rx_desc */
373
-#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
374
-#define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
375
-#define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
376
-#define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
377
-#define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
378
-#define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
379
-#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
345
+#define ENA_ETH_IO_RX_DESC_PHASE_MASK                       BIT(0)
346
+#define ENA_ETH_IO_RX_DESC_FIRST_SHIFT                      2
347
+#define ENA_ETH_IO_RX_DESC_FIRST_MASK                       BIT(2)
348
+#define ENA_ETH_IO_RX_DESC_LAST_SHIFT                       3
349
+#define ENA_ETH_IO_RX_DESC_LAST_MASK                        BIT(3)
350
+#define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT                   4
351
+#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK                    BIT(4)
380352 
381353 /* rx_cdesc_base */
382
-#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
383
-#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
384
-#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
385
-#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
386
-#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
387
-#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
388
-#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
389
-#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
390
-#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
391
-#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
392
-#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
393
-#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
394
-#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
395
-#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
396
-#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
397
-#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
398
-#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
399
-#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
400
-#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
401
-#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
402
-#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
354
+#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK          GENMASK(4, 0)
355
+#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT         5
356
+#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK          GENMASK(6, 5)
357
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT         8
358
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK          GENMASK(12, 8)
359
+#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT          13
360
+#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK           BIT(13)
361
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT          14
362
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK           BIT(14)
363
+#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT            15
364
+#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK             BIT(15)
365
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT      16
366
+#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK       BIT(16)
367
+#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT                24
368
+#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK                 BIT(24)
369
+#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT             25
370
+#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK              BIT(25)
371
+#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT                26
372
+#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK                 BIT(26)
373
+#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT                 27
374
+#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK                  BIT(27)
375
+#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT               30
376
+#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK                BIT(30)
403377 
404378 /* intr_reg */
405
-#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
406
-#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
407
-#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
408
-#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
409
-#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
379
+#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK              GENMASK(14, 0)
380
+#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT             15
381
+#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK              GENMASK(29, 15)
382
+#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT               30
383
+#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK                BIT(30)
410384 
411385 /* numa_node_cfg_reg */
412
-#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
413
-#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
414
-#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
386
+#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK              GENMASK(7, 0)
387
+#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT          31
388
+#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK           BIT(31)
415389 
416
-#endif /*_ENA_ETH_IO_H_ */
390
+#endif /* _ENA_ETH_IO_H_ */