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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/net/dsa/mv88e6xxx/serdes.h
....@@ -1,14 +1,10 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * Marvell 88E6xxx SERDES manipulation, via SMI bus
34  *
45  * Copyright (c) 2008 Marvell Semiconductor
56  *
67  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or
11
- * (at your option) any later version.
128  */
139 
1410 #ifndef _MV88E6XXX_SERDES_H
....@@ -18,8 +14,21 @@
1814 
1915 #define MV88E6352_ADDR_SERDES		0x0f
2016 #define MV88E6352_SERDES_PAGE_FIBER	0x01
17
+#define MV88E6352_SERDES_IRQ		0x0b
18
+#define MV88E6352_SERDES_INT_ENABLE	0x12
19
+#define MV88E6352_SERDES_INT_SPEED_CHANGE	BIT(14)
20
+#define MV88E6352_SERDES_INT_DUPLEX_CHANGE	BIT(13)
21
+#define MV88E6352_SERDES_INT_PAGE_RX		BIT(12)
22
+#define MV88E6352_SERDES_INT_AN_COMPLETE	BIT(11)
23
+#define MV88E6352_SERDES_INT_LINK_CHANGE	BIT(10)
24
+#define MV88E6352_SERDES_INT_SYMBOL_ERROR	BIT(9)
25
+#define MV88E6352_SERDES_INT_FALSE_CARRIER	BIT(8)
26
+#define MV88E6352_SERDES_INT_FIFO_OVER_UNDER	BIT(7)
27
+#define MV88E6352_SERDES_INT_FIBRE_ENERGY	BIT(4)
28
+#define MV88E6352_SERDES_INT_STATUS	0x13
2129 
22
-#define MV88E6341_ADDR_SERDES		0x15
30
+
31
+#define MV88E6341_PORT5_LANE		0x15
2332 
2433 #define MV88E6390_PORT9_LANE0		0x09
2534 #define MV88E6390_PORT9_LANE1		0x12
....@@ -31,21 +40,14 @@
3140 #define MV88E6390_PORT10_LANE3		0x17
3241 
3342 /* 10GBASE-R and 10GBASE-X4/X2 */
34
-#define MV88E6390_PCS_CONTROL_1		0x1000
35
-#define MV88E6390_PCS_CONTROL_1_RESET		BIT(15)
36
-#define MV88E6390_PCS_CONTROL_1_LOOPBACK	BIT(14)
37
-#define MV88E6390_PCS_CONTROL_1_SPEED		BIT(13)
38
-#define MV88E6390_PCS_CONTROL_1_PDOWN		BIT(11)
43
+#define MV88E6390_10G_CTRL1		(0x1000 + MDIO_CTRL1)
44
+#define MV88E6390_10G_STAT1		(0x1000 + MDIO_STAT1)
3945 
4046 /* 1000BASE-X and SGMII */
41
-#define MV88E6390_SGMII_CONTROL		0x2000
42
-#define MV88E6390_SGMII_CONTROL_RESET		BIT(15)
43
-#define MV88E6390_SGMII_CONTROL_LOOPBACK	BIT(14)
44
-#define MV88E6390_SGMII_CONTROL_PDOWN		BIT(11)
45
-#define MV88E6390_SGMII_STATUS		0x2001
46
-#define MV88E6390_SGMII_STATUS_AN_DONE		BIT(5)
47
-#define MV88E6390_SGMII_STATUS_REMOTE_FAULT	BIT(4)
48
-#define MV88E6390_SGMII_STATUS_LINK		BIT(2)
47
+#define MV88E6390_SGMII_BMCR		(0x2000 + MII_BMCR)
48
+#define MV88E6390_SGMII_BMSR		(0x2000 + MII_BMSR)
49
+#define MV88E6390_SGMII_ADVERTISE	(0x2000 + MII_ADVERTISE)
50
+#define MV88E6390_SGMII_LPA		(0x2000 + MII_LPA)
4951 #define MV88E6390_SGMII_INT_ENABLE	0xa001
5052 #define MV88E6390_SGMII_INT_SPEED_CHANGE	BIT(14)
5153 #define MV88E6390_SGMII_INT_DUPLEX_CHANGE	BIT(13)
....@@ -56,22 +58,139 @@
5658 #define MV88E6390_SGMII_INT_SYMBOL_ERROR	BIT(8)
5759 #define MV88E6390_SGMII_INT_FALSE_CARRIER	BIT(7)
5860 #define MV88E6390_SGMII_INT_STATUS	0xa002
61
+#define MV88E6390_SGMII_PHY_STATUS	0xa003
62
+#define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK	GENMASK(15, 14)
63
+#define MV88E6390_SGMII_PHY_STATUS_SPEED_1000	0x8000
64
+#define MV88E6390_SGMII_PHY_STATUS_SPEED_100	0x4000
65
+#define MV88E6390_SGMII_PHY_STATUS_SPEED_10	0x0000
66
+#define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL	BIT(13)
67
+#define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11)
68
+#define MV88E6390_SGMII_PHY_STATUS_LINK		BIT(10)
69
+#define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE	BIT(3)
70
+#define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE	BIT(2)
5971 
60
-int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
61
-int mv88e6341_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on);
62
-int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on);
63
-int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on);
64
-int mv88e6390x_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on);
65
-int mv88e6390_serdes_irq_setup(struct mv88e6xxx_chip *chip, int port);
66
-void mv88e6390_serdes_irq_free(struct mv88e6xxx_chip *chip, int port);
72
+/* Packet generator pad packet checker */
73
+#define MV88E6390_PG_CONTROL		0xf010
74
+#define MV88E6390_PG_CONTROL_ENABLE_PC		BIT(0)
75
+
76
+u8 mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
77
+u8 mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
78
+u8 mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
79
+u8 mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
80
+int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
81
+				u8 lane, unsigned int mode,
82
+				phy_interface_t interface,
83
+				const unsigned long *advertise);
84
+int mv88e6390_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
85
+				u8 lane, unsigned int mode,
86
+				phy_interface_t interface,
87
+				const unsigned long *advertise);
88
+int mv88e6352_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
89
+				   u8 lane, struct phylink_link_state *state);
90
+int mv88e6390_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
91
+				   u8 lane, struct phylink_link_state *state);
92
+int mv88e6352_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port,
93
+				    u8 lane);
94
+int mv88e6390_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port,
95
+				    u8 lane);
96
+int mv88e6352_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
97
+				 u8 lane, int speed, int duplex);
98
+int mv88e6390_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
99
+				 u8 lane, int speed, int duplex);
100
+unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
101
+					  int port);
102
+unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
103
+					  int port);
104
+int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
105
+			   bool on);
106
+int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
107
+			   bool on);
108
+int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane,
109
+				bool enable);
110
+int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane,
111
+				bool enable);
112
+irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
113
+					u8 lane);
114
+irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
115
+					u8 lane);
67116 int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
68117 int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
69118 				 int port, uint8_t *data);
70119 int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
71120 			       uint64_t *data);
72
-int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port,
73
-				int lane);
74
-int mv88e6390_serdes_irq_disable(struct mv88e6xxx_chip *chip, int port,
75
-				 int lane);
121
+int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
122
+int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,
123
+				 int port, uint8_t *data);
124
+int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
125
+			       uint64_t *data);
126
+
127
+int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
128
+void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
129
+int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
130
+void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
131
+
132
+/* Return the (first) SERDES lane address a port is using, 0 otherwise. */
133
+static inline u8 mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
134
+					   int port)
135
+{
136
+	if (!chip->info->ops->serdes_get_lane)
137
+		return 0;
138
+
139
+	return chip->info->ops->serdes_get_lane(chip, port);
140
+}
141
+
142
+static inline int mv88e6xxx_serdes_power_up(struct mv88e6xxx_chip *chip,
143
+					    int port, u8 lane)
144
+{
145
+	if (!chip->info->ops->serdes_power)
146
+		return -EOPNOTSUPP;
147
+
148
+	return chip->info->ops->serdes_power(chip, port, lane, true);
149
+}
150
+
151
+static inline int mv88e6xxx_serdes_power_down(struct mv88e6xxx_chip *chip,
152
+					      int port, u8 lane)
153
+{
154
+	if (!chip->info->ops->serdes_power)
155
+		return -EOPNOTSUPP;
156
+
157
+	return chip->info->ops->serdes_power(chip, port, lane, false);
158
+}
159
+
160
+static inline unsigned int
161
+mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
162
+{
163
+	if (!chip->info->ops->serdes_irq_mapping)
164
+		return 0;
165
+
166
+	return chip->info->ops->serdes_irq_mapping(chip, port);
167
+}
168
+
169
+static inline int mv88e6xxx_serdes_irq_enable(struct mv88e6xxx_chip *chip,
170
+					      int port, u8 lane)
171
+{
172
+	if (!chip->info->ops->serdes_irq_enable)
173
+		return -EOPNOTSUPP;
174
+
175
+	return chip->info->ops->serdes_irq_enable(chip, port, lane, true);
176
+}
177
+
178
+static inline int mv88e6xxx_serdes_irq_disable(struct mv88e6xxx_chip *chip,
179
+					       int port, u8 lane)
180
+{
181
+	if (!chip->info->ops->serdes_irq_enable)
182
+		return -EOPNOTSUPP;
183
+
184
+	return chip->info->ops->serdes_irq_enable(chip, port, lane, false);
185
+}
186
+
187
+static inline irqreturn_t
188
+mv88e6xxx_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, u8 lane)
189
+{
190
+	if (!chip->info->ops->serdes_irq_status)
191
+		return IRQ_NONE;
192
+
193
+	return chip->info->ops->serdes_irq_status(chip, port, lane);
194
+}
76195 
77196 #endif