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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/mtd/nand/raw/fsmc_nand.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * ST Microelectronics
34  * Flexible Static Memory Controller (FSMC)
....@@ -10,10 +11,6 @@
1011  * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
1112  *  Copyright © 2007 STMicroelectronics Pvt. Ltd.
1213  *  Copyright © 2009 Alessandro Rubini
13
- *
14
- * This file is licensed under the terms of the GNU General Public
15
- * License version 2. This program is licensed "as is" without any
16
- * warranty of any kind, whether express or implied.
1714  */
1815 
1916 #include <linux/clk.h>
....@@ -42,15 +39,14 @@
4239 /* fsmc controller registers for NOR flash */
4340 #define CTRL			0x0
4441 	/* ctrl register definitions */
45
-	#define BANK_ENABLE		(1 << 0)
46
-	#define MUXED			(1 << 1)
42
+	#define BANK_ENABLE		BIT(0)
43
+	#define MUXED			BIT(1)
4744 	#define NOR_DEV			(2 << 2)
48
-	#define WIDTH_8			(0 << 4)
49
-	#define WIDTH_16		(1 << 4)
50
-	#define RSTPWRDWN		(1 << 6)
51
-	#define WPROT			(1 << 7)
52
-	#define WRT_ENABLE		(1 << 12)
53
-	#define WAIT_ENB		(1 << 13)
45
+	#define WIDTH_16		BIT(4)
46
+	#define RSTPWRDWN		BIT(6)
47
+	#define WPROT			BIT(7)
48
+	#define WRT_ENABLE		BIT(12)
49
+	#define WAIT_ENB		BIT(13)
5450 
5551 #define CTRL_TIM		0x4
5652 	/* ctrl_tim register definitions */
....@@ -58,43 +54,35 @@
5854 #define FSMC_NOR_BANK_SZ	0x8
5955 #define FSMC_NOR_REG_SIZE	0x40
6056 
61
-#define FSMC_NOR_REG(base, bank, reg)		(base + \
62
-						FSMC_NOR_BANK_SZ * (bank) + \
63
-						reg)
57
+#define FSMC_NOR_REG(base, bank, reg)	((base) +			\
58
+					 (FSMC_NOR_BANK_SZ * (bank)) +	\
59
+					 (reg))
6460 
6561 /* fsmc controller registers for NAND flash */
6662 #define FSMC_PC			0x00
6763 	/* pc register definitions */
68
-	#define FSMC_RESET		(1 << 0)
69
-	#define FSMC_WAITON		(1 << 1)
70
-	#define FSMC_ENABLE		(1 << 2)
71
-	#define FSMC_DEVTYPE_NAND	(1 << 3)
72
-	#define FSMC_DEVWID_8		(0 << 4)
73
-	#define FSMC_DEVWID_16		(1 << 4)
74
-	#define FSMC_ECCEN		(1 << 6)
75
-	#define FSMC_ECCPLEN_512	(0 << 7)
76
-	#define FSMC_ECCPLEN_256	(1 << 7)
77
-	#define FSMC_TCLR_1		(1)
64
+	#define FSMC_RESET		BIT(0)
65
+	#define FSMC_WAITON		BIT(1)
66
+	#define FSMC_ENABLE		BIT(2)
67
+	#define FSMC_DEVTYPE_NAND	BIT(3)
68
+	#define FSMC_DEVWID_16		BIT(4)
69
+	#define FSMC_ECCEN		BIT(6)
70
+	#define FSMC_ECCPLEN_256	BIT(7)
7871 	#define FSMC_TCLR_SHIFT		(9)
7972 	#define FSMC_TCLR_MASK		(0xF)
80
-	#define FSMC_TAR_1		(1)
8173 	#define FSMC_TAR_SHIFT		(13)
8274 	#define FSMC_TAR_MASK		(0xF)
8375 #define STS			0x04
8476 	/* sts register definitions */
85
-	#define FSMC_CODE_RDY		(1 << 15)
77
+	#define FSMC_CODE_RDY		BIT(15)
8678 #define COMM			0x08
8779 	/* comm register definitions */
88
-	#define FSMC_TSET_0		0
8980 	#define FSMC_TSET_SHIFT		0
9081 	#define FSMC_TSET_MASK		0xFF
91
-	#define FSMC_TWAIT_6		6
9282 	#define FSMC_TWAIT_SHIFT	8
9383 	#define FSMC_TWAIT_MASK		0xFF
94
-	#define FSMC_THOLD_4		4
9584 	#define FSMC_THOLD_SHIFT	16
9685 	#define FSMC_THOLD_MASK		0xFF
97
-	#define FSMC_THIZ_1		1
9886 	#define FSMC_THIZ_SHIFT		24
9987 	#define FSMC_THIZ_MASK		0xFF
10088 #define ATTRIB			0x0C
....@@ -106,13 +94,21 @@
10694 
10795 #define FSMC_BUSY_WAIT_TIMEOUT	(1 * HZ)
10896 
97
+/*
98
+ * According to SPEAr300 Reference Manual (RM0082)
99
+ *  TOUDEL = 7ns (Output delay from the flip-flops to the board)
100
+ *  TINDEL = 5ns (Input delay from the board to the flipflop)
101
+ */
102
+#define TOUTDEL	7000
103
+#define TINDEL	5000
104
+
109105 struct fsmc_nand_timings {
110
-	uint8_t tclr;
111
-	uint8_t tar;
112
-	uint8_t thiz;
113
-	uint8_t thold;
114
-	uint8_t twait;
115
-	uint8_t tset;
106
+	u8 tclr;
107
+	u8 tar;
108
+	u8 thiz;
109
+	u8 thold;
110
+	u8 twait;
111
+	u8 tset;
116112 };
117113 
118114 enum access_mode {
....@@ -123,18 +119,20 @@
123119 /**
124120  * struct fsmc_nand_data - structure for FSMC NAND device state
125121  *
122
+ * @base:		Inherit from the nand_controller struct
126123  * @pid:		Part ID on the AMBA PrimeCell format
127
- * @mtd:		MTD info for a NAND flash.
128124  * @nand:		Chip related info for a NAND flash.
129
- * @partitions:		Partition info for a NAND Flash.
130
- * @nr_partitions:	Total number of partition of a NAND flash.
131125  *
132126  * @bank:		Bank number for probed device.
127
+ * @dev:		Parent device
128
+ * @mode:		Access mode
133129  * @clk:		Clock structure for FSMC.
134130  *
135131  * @read_dma_chan:	DMA channel for read access
136132  * @write_dma_chan:	DMA channel for write access to NAND
137133  * @dma_access_complete: Completion structure
134
+ *
135
+ * @dev_timings:	NAND timings
138136  *
139137  * @data_pa:		NAND Physical port for Data.
140138  * @data_va:		NAND port for Data.
....@@ -143,6 +141,7 @@
143141  * @regs_va:		Registers base address for a given bank.
144142  */
145143 struct fsmc_nand_data {
144
+	struct nand_controller	base;
146145 	u32			pid;
147146 	struct nand_chip	nand;
148147 
....@@ -249,9 +248,9 @@
249248 	.free = fsmc_ecc4_ooblayout_free,
250249 };
251250 
252
-static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
251
+static inline struct fsmc_nand_data *nand_to_fsmc(struct nand_chip *chip)
253252 {
254
-	return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
253
+	return container_of(chip, struct fsmc_nand_data, nand);
255254 }
256255 
257256 /*
....@@ -263,8 +262,8 @@
263262 static void fsmc_nand_setup(struct fsmc_nand_data *host,
264263 			    struct fsmc_nand_timings *tims)
265264 {
266
-	uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
267
-	uint32_t tclr, tar, thiz, thold, twait, tset;
265
+	u32 value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
266
+	u32 tclr, tar, thiz, thold, twait, tset;
268267 
269268 	tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
270269 	tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
....@@ -274,13 +273,9 @@
274273 	tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
275274 
276275 	if (host->nand.options & NAND_BUSWIDTH_16)
277
-		writel_relaxed(value | FSMC_DEVWID_16,
278
-			       host->regs_va + FSMC_PC);
279
-	else
280
-		writel_relaxed(value | FSMC_DEVWID_8, host->regs_va + FSMC_PC);
276
+		value |= FSMC_DEVWID_16;
281277 
282
-	writel_relaxed(readl(host->regs_va + FSMC_PC) | tclr | tar,
283
-		       host->regs_va + FSMC_PC);
278
+	writel_relaxed(value | tclr | tar, host->regs_va + FSMC_PC);
284279 	writel_relaxed(thiz | thold | twait | tset, host->regs_va + COMM);
285280 	writel_relaxed(thiz | thold | twait | tset, host->regs_va + ATTRIB);
286281 }
....@@ -291,7 +286,7 @@
291286 {
292287 	unsigned long hclk = clk_get_rate(host->clk);
293288 	unsigned long hclkn = NSEC_PER_SEC / hclk;
294
-	uint32_t thiz, thold, twait, tset;
289
+	u32 thiz, thold, twait, tset, twait_min;
295290 
296291 	if (sdrt->tRC_min < 30000)
297292 		return -EOPNOTSUPP;
....@@ -323,13 +318,6 @@
323318 	else if (tims->thold > FSMC_THOLD_MASK)
324319 		tims->thold = FSMC_THOLD_MASK;
325320 
326
-	twait = max(sdrt->tRP_min, sdrt->tWP_min);
327
-	tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
328
-	if (tims->twait == 0)
329
-		tims->twait = 1;
330
-	else if (tims->twait > FSMC_TWAIT_MASK)
331
-		tims->twait = FSMC_TWAIT_MASK;
332
-
333321 	tset = max(sdrt->tCS_min - sdrt->tWP_min,
334322 		   sdrt->tCEA_max - sdrt->tREA_max);
335323 	tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
....@@ -338,14 +326,28 @@
338326 	else if (tims->tset > FSMC_TSET_MASK)
339327 		tims->tset = FSMC_TSET_MASK;
340328 
329
+	/*
330
+	 * According to SPEAr300 Reference Manual (RM0082) which gives more
331
+	 * information related to FSMSC timings than the SPEAr600 one (RM0305),
332
+	 *   twait >= tCEA - (tset * TCLK) + TOUTDEL + TINDEL
333
+	 */
334
+	twait_min = sdrt->tCEA_max - ((tims->tset + 1) * hclkn * 1000)
335
+		    + TOUTDEL + TINDEL;
336
+	twait = max3(sdrt->tRP_min, sdrt->tWP_min, twait_min);
337
+
338
+	tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
339
+	if (tims->twait == 0)
340
+		tims->twait = 1;
341
+	else if (tims->twait > FSMC_TWAIT_MASK)
342
+		tims->twait = FSMC_TWAIT_MASK;
343
+
341344 	return 0;
342345 }
343346 
344
-static int fsmc_setup_data_interface(struct mtd_info *mtd, int csline,
345
-				     const struct nand_data_interface *conf)
347
+static int fsmc_setup_interface(struct nand_chip *nand, int csline,
348
+				const struct nand_interface_config *conf)
346349 {
347
-	struct nand_chip *nand = mtd_to_nand(mtd);
348
-	struct fsmc_nand_data *host = nand_get_controller_data(nand);
350
+	struct fsmc_nand_data *host = nand_to_fsmc(nand);
349351 	struct fsmc_nand_timings tims;
350352 	const struct nand_sdr_timings *sdrt;
351353 	int ret;
....@@ -369,9 +371,9 @@
369371 /*
370372  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
371373  */
372
-static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
374
+static void fsmc_enable_hwecc(struct nand_chip *chip, int mode)
373375 {
374
-	struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
376
+	struct fsmc_nand_data *host = nand_to_fsmc(chip);
375377 
376378 	writel_relaxed(readl(host->regs_va + FSMC_PC) & ~FSMC_ECCPLEN_256,
377379 		       host->regs_va + FSMC_PC);
....@@ -386,18 +388,18 @@
386388  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
387389  * max of 8-bits)
388390  */
389
-static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
390
-				uint8_t *ecc)
391
+static int fsmc_read_hwecc_ecc4(struct nand_chip *chip, const u8 *data,
392
+				u8 *ecc)
391393 {
392
-	struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
393
-	uint32_t ecc_tmp;
394
+	struct fsmc_nand_data *host = nand_to_fsmc(chip);
395
+	u32 ecc_tmp;
394396 	unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
395397 
396398 	do {
397399 		if (readl_relaxed(host->regs_va + STS) & FSMC_CODE_RDY)
398400 			break;
399
-		else
400
-			cond_resched();
401
+
402
+		cond_resched();
401403 	} while (!time_after_eq(jiffies, deadline));
402404 
403405 	if (time_after_eq(jiffies, deadline)) {
....@@ -406,25 +408,25 @@
406408 	}
407409 
408410 	ecc_tmp = readl_relaxed(host->regs_va + ECC1);
409
-	ecc[0] = (uint8_t) (ecc_tmp >> 0);
410
-	ecc[1] = (uint8_t) (ecc_tmp >> 8);
411
-	ecc[2] = (uint8_t) (ecc_tmp >> 16);
412
-	ecc[3] = (uint8_t) (ecc_tmp >> 24);
411
+	ecc[0] = ecc_tmp;
412
+	ecc[1] = ecc_tmp >> 8;
413
+	ecc[2] = ecc_tmp >> 16;
414
+	ecc[3] = ecc_tmp >> 24;
413415 
414416 	ecc_tmp = readl_relaxed(host->regs_va + ECC2);
415
-	ecc[4] = (uint8_t) (ecc_tmp >> 0);
416
-	ecc[5] = (uint8_t) (ecc_tmp >> 8);
417
-	ecc[6] = (uint8_t) (ecc_tmp >> 16);
418
-	ecc[7] = (uint8_t) (ecc_tmp >> 24);
417
+	ecc[4] = ecc_tmp;
418
+	ecc[5] = ecc_tmp >> 8;
419
+	ecc[6] = ecc_tmp >> 16;
420
+	ecc[7] = ecc_tmp >> 24;
419421 
420422 	ecc_tmp = readl_relaxed(host->regs_va + ECC3);
421
-	ecc[8] = (uint8_t) (ecc_tmp >> 0);
422
-	ecc[9] = (uint8_t) (ecc_tmp >> 8);
423
-	ecc[10] = (uint8_t) (ecc_tmp >> 16);
424
-	ecc[11] = (uint8_t) (ecc_tmp >> 24);
423
+	ecc[8] = ecc_tmp;
424
+	ecc[9] = ecc_tmp >> 8;
425
+	ecc[10] = ecc_tmp >> 16;
426
+	ecc[11] = ecc_tmp >> 24;
425427 
426428 	ecc_tmp = readl_relaxed(host->regs_va + STS);
427
-	ecc[12] = (uint8_t) (ecc_tmp >> 16);
429
+	ecc[12] = ecc_tmp >> 16;
428430 
429431 	return 0;
430432 }
....@@ -434,22 +436,22 @@
434436  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
435437  * max of 1-bit)
436438  */
437
-static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
438
-				uint8_t *ecc)
439
+static int fsmc_read_hwecc_ecc1(struct nand_chip *chip, const u8 *data,
440
+				u8 *ecc)
439441 {
440
-	struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
441
-	uint32_t ecc_tmp;
442
+	struct fsmc_nand_data *host = nand_to_fsmc(chip);
443
+	u32 ecc_tmp;
442444 
443445 	ecc_tmp = readl_relaxed(host->regs_va + ECC1);
444
-	ecc[0] = (uint8_t) (ecc_tmp >> 0);
445
-	ecc[1] = (uint8_t) (ecc_tmp >> 8);
446
-	ecc[2] = (uint8_t) (ecc_tmp >> 16);
446
+	ecc[0] = ecc_tmp;
447
+	ecc[1] = ecc_tmp >> 8;
448
+	ecc[2] = ecc_tmp >> 16;
447449 
448450 	return 0;
449451 }
450452 
451453 /* Count the number of 0's in buff upto a max of max_bits */
452
-static int count_written_bits(uint8_t *buff, int size, int max_bits)
454
+static int count_written_bits(u8 *buff, int size, int max_bits)
453455 {
454456 	int k, written_bits = 0;
455457 
....@@ -470,7 +472,7 @@
470472 }
471473 
472474 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
473
-		enum dma_data_direction direction)
475
+		    enum dma_data_direction direction)
474476 {
475477 	struct dma_chan *chan;
476478 	struct dma_device *dma_dev;
....@@ -521,7 +523,7 @@
521523 
522524 	time_left =
523525 	wait_for_completion_timeout(&host->dma_access_complete,
524
-				msecs_to_jiffies(3000));
526
+				    msecs_to_jiffies(3000));
525527 	if (time_left == 0) {
526528 		dmaengine_terminate_all(chan);
527529 		dev_err(host->dev, "wait_for_completion_timeout\n");
....@@ -539,18 +541,19 @@
539541 
540542 /*
541543  * fsmc_write_buf - write buffer to chip
542
- * @mtd:	MTD device structure
544
+ * @host:	FSMC NAND controller
543545  * @buf:	data buffer
544546  * @len:	number of bytes to write
545547  */
546
-static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
548
+static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf,
549
+			   int len)
547550 {
548
-	struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
549551 	int i;
550552 
551
-	if (IS_ALIGNED((uintptr_t)buf, sizeof(uint32_t)) &&
552
-			IS_ALIGNED(len, sizeof(uint32_t))) {
553
-		uint32_t *p = (uint32_t *)buf;
553
+	if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
554
+	    IS_ALIGNED(len, sizeof(u32))) {
555
+		u32 *p = (u32 *)buf;
556
+
554557 		len = len >> 2;
555558 		for (i = 0; i < len; i++)
556559 			writel_relaxed(p[i], host->data_va);
....@@ -562,18 +565,18 @@
562565 
563566 /*
564567  * fsmc_read_buf - read chip data into buffer
565
- * @mtd:	MTD device structure
568
+ * @host:	FSMC NAND controller
566569  * @buf:	buffer to store date
567570  * @len:	number of bytes to read
568571  */
569
-static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
572
+static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len)
570573 {
571
-	struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
572574 	int i;
573575 
574
-	if (IS_ALIGNED((uintptr_t)buf, sizeof(uint32_t)) &&
575
-			IS_ALIGNED(len, sizeof(uint32_t))) {
576
-		uint32_t *p = (uint32_t *)buf;
576
+	if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
577
+	    IS_ALIGNED(len, sizeof(u32))) {
578
+		u32 *p = (u32 *)buf;
579
+
577580 		len = len >> 2;
578581 		for (i = 0; i < len; i++)
579582 			p[i] = readl_relaxed(host->data_va);
....@@ -585,49 +588,26 @@
585588 
586589 /*
587590  * fsmc_read_buf_dma - read chip data into buffer
588
- * @mtd:	MTD device structure
591
+ * @host:	FSMC NAND controller
589592  * @buf:	buffer to store date
590593  * @len:	number of bytes to read
591594  */
592
-static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
595
+static void fsmc_read_buf_dma(struct fsmc_nand_data *host, u8 *buf,
596
+			      int len)
593597 {
594
-	struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
595
-
596598 	dma_xfer(host, buf, len, DMA_FROM_DEVICE);
597599 }
598600 
599601 /*
600602  * fsmc_write_buf_dma - write buffer to chip
601
- * @mtd:	MTD device structure
603
+ * @host:	FSMC NAND controller
602604  * @buf:	data buffer
603605  * @len:	number of bytes to write
604606  */
605
-static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
606
-		int len)
607
+static void fsmc_write_buf_dma(struct fsmc_nand_data *host, const u8 *buf,
608
+			       int len)
607609 {
608
-	struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
609
-
610610 	dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
611
-}
612
-
613
-/* fsmc_select_chip - assert or deassert nCE */
614
-static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
615
-{
616
-	struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
617
-	u32 pc;
618
-
619
-	/* Support only one CS */
620
-	if (chipnr > 0)
621
-		return;
622
-
623
-	pc = readl(host->regs_va + FSMC_PC);
624
-	if (chipnr < 0)
625
-		writel_relaxed(pc & ~FSMC_ENABLE, host->regs_va + FSMC_PC);
626
-	else
627
-		writel_relaxed(pc | FSMC_ENABLE, host->regs_va + FSMC_PC);
628
-
629
-	/* nCE line must be asserted before starting any operation */
630
-	mb();
631611 }
632612 
633613 /*
....@@ -639,64 +619,53 @@
639619 static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
640620 			bool check_only)
641621 {
642
-	struct mtd_info *mtd = nand_to_mtd(chip);
643
-	struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
622
+	struct fsmc_nand_data *host = nand_to_fsmc(chip);
644623 	const struct nand_op_instr *instr = NULL;
645624 	int ret = 0;
646625 	unsigned int op_id;
647626 	int i;
648627 
628
+	if (check_only)
629
+		return 0;
630
+
649631 	pr_debug("Executing operation [%d instructions]:\n", op->ninstrs);
632
+
650633 	for (op_id = 0; op_id < op->ninstrs; op_id++) {
651634 		instr = &op->instrs[op_id];
652635 
636
+		nand_op_trace("  ", instr);
637
+
653638 		switch (instr->type) {
654639 		case NAND_OP_CMD_INSTR:
655
-			pr_debug("  ->CMD      [0x%02x]\n",
656
-				 instr->ctx.cmd.opcode);
657
-
658640 			writeb_relaxed(instr->ctx.cmd.opcode, host->cmd_va);
659641 			break;
660642 
661643 		case NAND_OP_ADDR_INSTR:
662
-			pr_debug("  ->ADDR     [%d cyc]",
663
-				 instr->ctx.addr.naddrs);
664
-
665644 			for (i = 0; i < instr->ctx.addr.naddrs; i++)
666645 				writeb_relaxed(instr->ctx.addr.addrs[i],
667646 					       host->addr_va);
668647 			break;
669648 
670649 		case NAND_OP_DATA_IN_INSTR:
671
-			pr_debug("  ->DATA_IN  [%d B%s]\n", instr->ctx.data.len,
672
-				 instr->ctx.data.force_8bit ?
673
-				 ", force 8-bit" : "");
674
-
675650 			if (host->mode == USE_DMA_ACCESS)
676
-				fsmc_read_buf_dma(mtd, instr->ctx.data.buf.in,
651
+				fsmc_read_buf_dma(host, instr->ctx.data.buf.in,
677652 						  instr->ctx.data.len);
678653 			else
679
-				fsmc_read_buf(mtd, instr->ctx.data.buf.in,
654
+				fsmc_read_buf(host, instr->ctx.data.buf.in,
680655 					      instr->ctx.data.len);
681656 			break;
682657 
683658 		case NAND_OP_DATA_OUT_INSTR:
684
-			pr_debug("  ->DATA_OUT [%d B%s]\n", instr->ctx.data.len,
685
-				 instr->ctx.data.force_8bit ?
686
-				 ", force 8-bit" : "");
687
-
688659 			if (host->mode == USE_DMA_ACCESS)
689
-				fsmc_write_buf_dma(mtd, instr->ctx.data.buf.out,
660
+				fsmc_write_buf_dma(host,
661
+						   instr->ctx.data.buf.out,
690662 						   instr->ctx.data.len);
691663 			else
692
-				fsmc_write_buf(mtd, instr->ctx.data.buf.out,
664
+				fsmc_write_buf(host, instr->ctx.data.buf.out,
693665 					       instr->ctx.data.len);
694666 			break;
695667 
696668 		case NAND_OP_WAITRDY_INSTR:
697
-			pr_debug("  ->WAITRDY  [max %d ms]\n",
698
-				 instr->ctx.waitrdy.timeout_ms);
699
-
700669 			ret = nand_soft_waitrdy(chip,
701670 						instr->ctx.waitrdy.timeout_ms);
702671 			break;
....@@ -711,7 +680,6 @@
711680 
712681 /*
713682  * fsmc_read_page_hwecc
714
- * @mtd:	mtd info structure
715683  * @chip:	nand chip info structure
716684  * @buf:	buffer to store read data
717685  * @oob_required:	caller expects OOB data read to chip->oob_poi
....@@ -723,33 +691,35 @@
723691  * After this read, fsmc hardware generates and reports error data bits(up to a
724692  * max of 8 bits)
725693  */
726
-static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
727
-				 uint8_t *buf, int oob_required, int page)
694
+static int fsmc_read_page_hwecc(struct nand_chip *chip, u8 *buf,
695
+				int oob_required, int page)
728696 {
697
+	struct mtd_info *mtd = nand_to_mtd(chip);
729698 	int i, j, s, stat, eccsize = chip->ecc.size;
730699 	int eccbytes = chip->ecc.bytes;
731700 	int eccsteps = chip->ecc.steps;
732
-	uint8_t *p = buf;
733
-	uint8_t *ecc_calc = chip->ecc.calc_buf;
734
-	uint8_t *ecc_code = chip->ecc.code_buf;
735
-	int off, len, group = 0;
701
+	u8 *p = buf;
702
+	u8 *ecc_calc = chip->ecc.calc_buf;
703
+	u8 *ecc_code = chip->ecc.code_buf;
704
+	int off, len, ret, group = 0;
736705 	/*
737
-	 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
706
+	 * ecc_oob is intentionally taken as u16. In 16bit devices, we
738707 	 * end up reading 14 bytes (7 words) from oob. The local array is
739708 	 * to maintain word alignment
740709 	 */
741
-	uint16_t ecc_oob[7];
742
-	uint8_t *oob = (uint8_t *)&ecc_oob[0];
710
+	u16 ecc_oob[7];
711
+	u8 *oob = (u8 *)&ecc_oob[0];
743712 	unsigned int max_bitflips = 0;
744713 
745714 	for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
746715 		nand_read_page_op(chip, page, s * eccsize, NULL, 0);
747
-		chip->ecc.hwctl(mtd, NAND_ECC_READ);
748
-		nand_read_data_op(chip, p, eccsize, false);
716
+		chip->ecc.hwctl(chip, NAND_ECC_READ);
717
+		ret = nand_read_data_op(chip, p, eccsize, false, false);
718
+		if (ret)
719
+			return ret;
749720 
750721 		for (j = 0; j < eccbytes;) {
751722 			struct mtd_oob_region oobregion;
752
-			int ret;
753723 
754724 			ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
755725 			if (ret)
....@@ -771,9 +741,9 @@
771741 		}
772742 
773743 		memcpy(&ecc_code[i], oob, chip->ecc.bytes);
774
-		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
744
+		chip->ecc.calculate(chip, p, &ecc_calc[i]);
775745 
776
-		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
746
+		stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
777747 		if (stat < 0) {
778748 			mtd->ecc_stats.failed++;
779749 		} else {
....@@ -793,16 +763,15 @@
793763  * @calc_ecc:	ecc calculated from read data
794764  *
795765  * calc_ecc is a 104 bit information containing maximum of 8 error
796
- * offset informations of 13 bits each in 512 bytes of read data.
766
+ * offset information of 13 bits each in 512 bytes of read data.
797767  */
798
-static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
799
-			     uint8_t *read_ecc, uint8_t *calc_ecc)
768
+static int fsmc_bch8_correct_data(struct nand_chip *chip, u8 *dat,
769
+				  u8 *read_ecc, u8 *calc_ecc)
800770 {
801
-	struct nand_chip *chip = mtd_to_nand(mtd);
802
-	struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
803
-	uint32_t err_idx[8];
804
-	uint32_t num_err, i;
805
-	uint32_t ecc1, ecc2, ecc3, ecc4;
771
+	struct fsmc_nand_data *host = nand_to_fsmc(chip);
772
+	u32 err_idx[8];
773
+	u32 num_err, i;
774
+	u32 ecc1, ecc2, ecc3, ecc4;
806775 
807776 	num_err = (readl_relaxed(host->regs_va + STS) >> 10) & 0xF;
808777 
....@@ -843,8 +812,8 @@
843812 	 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
844813 	 *
845814 	 * calc_ecc is a 104 bit information containing maximum of 8 error
846
-	 * offset informations of 13 bits each. calc_ecc is copied into a
847
-	 * uint64_t array and error offset indexes are populated in err_idx
815
+	 * offset information of 13 bits each. calc_ecc is copied into a
816
+	 * u64 array and error offset indexes are populated in err_idx
848817 	 * array
849818 	 */
850819 	ecc1 = readl_relaxed(host->regs_va + ECC1);
....@@ -863,11 +832,12 @@
863832 
864833 	i = 0;
865834 	while (num_err--) {
866
-		change_bit(0, (unsigned long *)&err_idx[i]);
867
-		change_bit(1, (unsigned long *)&err_idx[i]);
835
+		err_idx[i] ^= 3;
868836 
869837 		if (err_idx[i] < chip->ecc.size * 8) {
870
-			change_bit(err_idx[i], (unsigned long *)dat);
838
+			int err = err_idx[i];
839
+
840
+			dat[err >> 3] ^= BIT(err & 7);
871841 			i++;
872842 		}
873843 	}
....@@ -903,11 +873,13 @@
903873 		nand->options |= NAND_SKIP_BBTSCAN;
904874 
905875 	host->dev_timings = devm_kzalloc(&pdev->dev,
906
-				sizeof(*host->dev_timings), GFP_KERNEL);
876
+					 sizeof(*host->dev_timings),
877
+					 GFP_KERNEL);
907878 	if (!host->dev_timings)
908879 		return -ENOMEM;
880
+
909881 	ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
910
-						sizeof(*host->dev_timings));
882
+					sizeof(*host->dev_timings));
911883 	if (ret)
912884 		host->dev_timings = NULL;
913885 
....@@ -926,7 +898,21 @@
926898 static int fsmc_nand_attach_chip(struct nand_chip *nand)
927899 {
928900 	struct mtd_info *mtd = nand_to_mtd(nand);
929
-	struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
901
+	struct fsmc_nand_data *host = nand_to_fsmc(nand);
902
+
903
+	if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
904
+		nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
905
+
906
+	if (!nand->ecc.size)
907
+		nand->ecc.size = 512;
908
+
909
+	if (AMBA_REV_BITS(host->pid) >= 8) {
910
+		nand->ecc.read_page = fsmc_read_page_hwecc;
911
+		nand->ecc.calculate = fsmc_read_hwecc_ecc4;
912
+		nand->ecc.correct = fsmc_bch8_correct_data;
913
+		nand->ecc.bytes = 13;
914
+		nand->ecc.strength = 8;
915
+	}
930916 
931917 	if (AMBA_REV_BITS(host->pid) >= 8) {
932918 		switch (mtd->oobsize) {
....@@ -948,23 +934,25 @@
948934 		return 0;
949935 	}
950936 
951
-	switch (nand->ecc.mode) {
952
-	case NAND_ECC_HW:
937
+	switch (nand->ecc.engine_type) {
938
+	case NAND_ECC_ENGINE_TYPE_ON_HOST:
953939 		dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
954940 		nand->ecc.calculate = fsmc_read_hwecc_ecc1;
955941 		nand->ecc.correct = nand_correct_data;
942
+		nand->ecc.hwctl = fsmc_enable_hwecc;
956943 		nand->ecc.bytes = 3;
957944 		nand->ecc.strength = 1;
945
+		nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
958946 		break;
959947 
960
-	case NAND_ECC_SOFT:
961
-		if (nand->ecc.algo == NAND_ECC_BCH) {
948
+	case NAND_ECC_ENGINE_TYPE_SOFT:
949
+		if (nand->ecc.algo == NAND_ECC_ALGO_BCH) {
962950 			dev_info(host->dev,
963951 				 "Using 4-bit SW BCH ECC scheme\n");
964952 			break;
965953 		}
966954 
967
-	case NAND_ECC_ON_DIE:
955
+	case NAND_ECC_ENGINE_TYPE_ON_DIE:
968956 		break;
969957 
970958 	default:
....@@ -976,7 +964,7 @@
976964 	 * Don't set layout for BCH4 SW ECC. This will be
977965 	 * generated later in nand_bch_init() later.
978966 	 */
979
-	if (nand->ecc.mode == NAND_ECC_HW) {
967
+	if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
980968 		switch (mtd->oobsize) {
981969 		case 16:
982970 		case 64:
....@@ -997,7 +985,22 @@
997985 
998986 static const struct nand_controller_ops fsmc_nand_controller_ops = {
999987 	.attach_chip = fsmc_nand_attach_chip,
988
+	.exec_op = fsmc_exec_op,
989
+	.setup_interface = fsmc_setup_interface,
1000990 };
991
+
992
+/**
993
+ * fsmc_nand_disable() - Disables the NAND bank
994
+ * @host: The instance to disable
995
+ */
996
+static void fsmc_nand_disable(struct fsmc_nand_data *host)
997
+{
998
+	u32 val;
999
+
1000
+	val = readl(host->regs_va + FSMC_PC);
1001
+	val &= ~FSMC_ENABLE;
1002
+	writel(val, host->regs_va + FSMC_PC);
1003
+}
10011004 
10021005 /*
10031006  * fsmc_nand_probe - Probe function
....@@ -1066,10 +1069,13 @@
10661069 	 * AMBA PrimeCell bus. However it is not a PrimeCell.
10671070 	 */
10681071 	for (pid = 0, i = 0; i < 4; i++)
1069
-		pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
1072
+		pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) &
1073
+			255) << (i * 8);
1074
+
10701075 	host->pid = pid;
1071
-	dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
1072
-		 "revision %02x, config %02x\n",
1076
+
1077
+	dev_info(&pdev->dev,
1078
+		 "FSMC device partno %03x, manufacturer %02x, revision %02x, config %02x\n",
10731079 		 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
10741080 		 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
10751081 
....@@ -1080,21 +1086,10 @@
10801086 
10811087 	/* Link all private pointers */
10821088 	mtd = nand_to_mtd(&host->nand);
1083
-	nand_set_controller_data(nand, host);
10841089 	nand_set_flash_node(nand, pdev->dev.of_node);
10851090 
10861091 	mtd->dev.parent = &pdev->dev;
1087
-	nand->exec_op = fsmc_exec_op;
1088
-	nand->select_chip = fsmc_select_chip;
1089
-	nand->chip_delay = 30;
10901092 
1091
-	/*
1092
-	 * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
1093
-	 * can overwrite this value if the DT provides a different value.
1094
-	 */
1095
-	nand->ecc.mode = NAND_ECC_HW;
1096
-	nand->ecc.hwctl = fsmc_enable_hwecc;
1097
-	nand->ecc.size = 512;
10981093 	nand->badblockbits = 7;
10991094 
11001095 	if (host->mode == USE_DMA_ACCESS) {
....@@ -1114,23 +1109,18 @@
11141109 		}
11151110 	}
11161111 
1117
-	if (host->dev_timings)
1112
+	if (host->dev_timings) {
11181113 		fsmc_nand_setup(host, host->dev_timings);
1119
-	else
1120
-		nand->setup_data_interface = fsmc_setup_data_interface;
1121
-
1122
-	if (AMBA_REV_BITS(host->pid) >= 8) {
1123
-		nand->ecc.read_page = fsmc_read_page_hwecc;
1124
-		nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1125
-		nand->ecc.correct = fsmc_bch8_correct_data;
1126
-		nand->ecc.bytes = 13;
1127
-		nand->ecc.strength = 8;
1114
+		nand->options |= NAND_KEEP_TIMINGS;
11281115 	}
1116
+
1117
+	nand_controller_init(&host->base);
1118
+	host->base.ops = &fsmc_nand_controller_ops;
1119
+	nand->controller = &host->base;
11291120 
11301121 	/*
11311122 	 * Scan to find existence of the device
11321123 	 */
1133
-	nand->dummy_controller.ops = &fsmc_nand_controller_ops;
11341124 	ret = nand_scan(nand, 1);
11351125 	if (ret)
11361126 		goto release_dma_write_chan;
....@@ -1154,6 +1144,7 @@
11541144 	if (host->mode == USE_DMA_ACCESS)
11551145 		dma_release_channel(host->read_dma_chan);
11561146 disable_clk:
1147
+	fsmc_nand_disable(host);
11571148 	clk_disable_unprepare(host->clk);
11581149 
11591150 	return ret;
....@@ -1167,7 +1158,13 @@
11671158 	struct fsmc_nand_data *host = platform_get_drvdata(pdev);
11681159 
11691160 	if (host) {
1170
-		nand_release(&host->nand);
1161
+		struct nand_chip *chip = &host->nand;
1162
+		int ret;
1163
+
1164
+		ret = mtd_device_unregister(nand_to_mtd(chip));
1165
+		WARN_ON(ret);
1166
+		nand_cleanup(chip);
1167
+		fsmc_nand_disable(host);
11711168 
11721169 		if (host->mode == USE_DMA_ACCESS) {
11731170 			dma_release_channel(host->write_dma_chan);
....@@ -1183,19 +1180,29 @@
11831180 static int fsmc_nand_suspend(struct device *dev)
11841181 {
11851182 	struct fsmc_nand_data *host = dev_get_drvdata(dev);
1183
+
11861184 	if (host)
11871185 		clk_disable_unprepare(host->clk);
1186
+
11881187 	return 0;
11891188 }
11901189 
11911190 static int fsmc_nand_resume(struct device *dev)
11921191 {
11931192 	struct fsmc_nand_data *host = dev_get_drvdata(dev);
1193
+	int ret;
1194
+
11941195 	if (host) {
1195
-		clk_prepare_enable(host->clk);
1196
+		ret = clk_prepare_enable(host->clk);
1197
+		if (ret) {
1198
+			dev_err(dev, "failed to enable clk\n");
1199
+			return ret;
1200
+		}
11961201 		if (host->dev_timings)
11971202 			fsmc_nand_setup(host, host->dev_timings);
1203
+		nand_reset(&host->nand, 0);
11981204 	}
1205
+
11991206 	return 0;
12001207 }
12011208 #endif
....@@ -1220,6 +1227,6 @@
12201227 
12211228 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
12221229 
1223
-MODULE_LICENSE("GPL");
1230
+MODULE_LICENSE("GPL v2");
12241231 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
12251232 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");