hc
2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5
kernel/drivers/mmc/host/dw_mmc-exynos.c
....@@ -1,12 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23 * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
34 *
45 * Copyright (C) 2012, Samsung Electronics Co., Ltd.
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License as published by
8
- * the Free Software Foundation; either version 2 of the License, or
9
- * (at your option) any later version.
106 */
117
128 #include <linux/module.h>
....@@ -180,6 +176,7 @@
180176 #ifdef CONFIG_PM_SLEEP
181177 /**
182178 * dw_mci_exynos_suspend_noirq - Exynos-specific suspend code
179
+ * @dev: Device to suspend (this device)
183180 *
184181 * This ensures that device will be in runtime active state in
185182 * dw_mci_exynos_resume_noirq after calling pm_runtime_force_resume()
....@@ -192,6 +189,7 @@
192189
193190 /**
194191 * dw_mci_exynos_resume_noirq - Exynos-specific resume code
192
+ * @dev: Device to resume (this device)
195193 *
196194 * On exynos5420 there is a silicon errata that will sometimes leave the
197195 * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
....@@ -253,6 +251,8 @@
253251 if (timing == MMC_TIMING_MMC_HS400) {
254252 dqs |= DATA_STROBE_EN;
255253 strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
254
+ } else if (timing == MMC_TIMING_UHS_SDR104) {
255
+ dqs &= 0xffffff00;
256256 } else {
257257 dqs &= ~DATA_STROBE_EN;
258258 }
....@@ -311,6 +311,15 @@
311311 /* Should be double rate for DDR mode */
312312 if (ios->bus_width == MMC_BUS_WIDTH_8)
313313 wanted <<= 1;
314
+ break;
315
+ case MMC_TIMING_UHS_SDR104:
316
+ case MMC_TIMING_UHS_SDR50:
317
+ clksel = (priv->sdr_timing & 0xfff8ffff) |
318
+ (priv->ciu_div << 16);
319
+ break;
320
+ case MMC_TIMING_UHS_DDR50:
321
+ clksel = (priv->ddr_timing & 0xfff8ffff) |
322
+ (priv->ciu_div << 16);
314323 break;
315324 default:
316325 clksel = priv->sdr_timing;
....@@ -477,7 +486,7 @@
477486 struct dw_mci_exynos_priv_data *priv = host->priv;
478487 struct mmc_host *mmc = slot->mmc;
479488 u8 start_smpl, smpl, candiates = 0;
480
- s8 found = -1;
489
+ s8 found;
481490 int ret = 0;
482491
483492 start_smpl = dw_mci_exynos_get_clksmpl(host);
....@@ -597,6 +606,7 @@
597606 .remove = dw_mci_exynos_remove,
598607 .driver = {
599608 .name = "dwmmc_exynos",
609
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
600610 .of_match_table = dw_mci_exynos_match,
601611 .pm = &dw_mci_exynos_pmops,
602612 },