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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/misc/mei/hw-me.c
....@@ -1,17 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
2
- *
3
+ * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
34  * Intel Management Engine Interface (Intel MEI) Linux driver
4
- * Copyright (c) 2003-2012, Intel Corporation.
5
- *
6
- * This program is free software; you can redistribute it and/or modify it
7
- * under the terms and conditions of the GNU General Public License,
8
- * version 2, as published by the Free Software Foundation.
9
- *
10
- * This program is distributed in the hope it will be useful, but WITHOUT
11
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
- * more details.
14
- *
155  */
166 
177 #include <linux/pci.h>
....@@ -183,6 +173,27 @@
183173 }
184174 
185175 /**
176
+ * mei_me_trc_status - read trc status register
177
+ *
178
+ * @dev: mei device
179
+ * @trc: trc status register value
180
+ *
181
+ * Return: 0 on success, error otherwise
182
+ */
183
+static int mei_me_trc_status(struct mei_device *dev, u32 *trc)
184
+{
185
+	struct mei_me_hw *hw = to_me_hw(dev);
186
+
187
+	if (!hw->cfg->hw_trc_supported)
188
+		return -EOPNOTSUPP;
189
+
190
+	*trc = mei_me_reg_read(hw, ME_TRC);
191
+	trace_mei_reg_read(dev->dev, "ME_TRC", ME_TRC, *trc);
192
+
193
+	return 0;
194
+}
195
+
196
+/**
186197  * mei_me_fw_status - read fw status register from pci config space
187198  *
188199  * @dev: mei device
....@@ -193,20 +204,19 @@
193204 static int mei_me_fw_status(struct mei_device *dev,
194205 			    struct mei_fw_status *fw_status)
195206 {
196
-	struct pci_dev *pdev = to_pci_dev(dev->dev);
197207 	struct mei_me_hw *hw = to_me_hw(dev);
198208 	const struct mei_fw_status *fw_src = &hw->cfg->fw_status;
199209 	int ret;
200210 	int i;
201211 
202
-	if (!fw_status)
212
+	if (!fw_status || !hw->read_fws)
203213 		return -EINVAL;
204214 
205215 	fw_status->count = fw_src->count;
206216 	for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
207
-		ret = pci_read_config_dword(pdev, fw_src->status[i],
208
-					    &fw_status->status[i]);
209
-		trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X",
217
+		ret = hw->read_fws(dev, fw_src->status[i],
218
+				   &fw_status->status[i]);
219
+		trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_X",
210220 				       fw_src->status[i],
211221 				       fw_status->status[i]);
212222 		if (ret)
....@@ -220,19 +230,26 @@
220230  * mei_me_hw_config - configure hw dependent settings
221231  *
222232  * @dev: mei device
233
+ *
234
+ * Return:
235
+ *  * -EINVAL when read_fws is not set
236
+ *  * 0 on success
237
+ *
223238  */
224
-static void mei_me_hw_config(struct mei_device *dev)
239
+static int mei_me_hw_config(struct mei_device *dev)
225240 {
226
-	struct pci_dev *pdev = to_pci_dev(dev->dev);
227241 	struct mei_me_hw *hw = to_me_hw(dev);
228242 	u32 hcsr, reg;
243
+
244
+	if (WARN_ON(!hw->read_fws))
245
+		return -EINVAL;
229246 
230247 	/* Doesn't change in runtime */
231248 	hcsr = mei_hcsr_read(dev);
232249 	hw->hbuf_depth = (hcsr & H_CBD) >> 24;
233250 
234251 	reg = 0;
235
-	pci_read_config_dword(pdev, PCI_CFG_HFS_1, &reg);
252
+	hw->read_fws(dev, PCI_CFG_HFS_1, &reg);
236253 	trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
237254 	hw->d0i3_supported =
238255 		((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK);
....@@ -243,6 +260,8 @@
243260 		if (reg & H_D0I3C_I3)
244261 			hw->pg_state = MEI_PG_ON;
245262 	}
263
+
264
+	return 0;
246265 }
247266 
248267 /**
....@@ -279,7 +298,7 @@
279298 }
280299 
281300 /**
282
- * mei_me_intr_clear - clear and stop interrupts
301
+ * me_intr_clear - clear and stop interrupts
283302  *
284303  * @dev: the device structure
285304  * @hcsr: supplied hcsr register value
....@@ -333,9 +352,9 @@
333352  */
334353 static void mei_me_synchronize_irq(struct mei_device *dev)
335354 {
336
-	struct pci_dev *pdev = to_pci_dev(dev->dev);
355
+	struct mei_me_hw *hw = to_me_hw(dev);
337356 
338
-	synchronize_irq(pdev->irq);
357
+	synchronize_irq(hw->irq);
339358 }
340359 
341360 /**
....@@ -350,9 +369,6 @@
350369 	hcsr |= H_IG;
351370 	hcsr &= ~H_RST;
352371 	mei_hcsr_set(dev, hcsr);
353
-
354
-	/* complete this write before we set host ready on another CPU */
355
-	mmiowb();
356372 }
357373 
358374 /**
....@@ -1307,6 +1323,7 @@
13071323 
13081324 static const struct mei_hw_ops mei_me_hw_ops = {
13091325 
1326
+	.trc_status = mei_me_trc_status,
13101327 	.fw_status = mei_me_fw_status,
13111328 	.pg_state  = mei_me_pg_state,
13121329 
....@@ -1336,11 +1353,24 @@
13361353 	.read = mei_me_read_slots
13371354 };
13381355 
1339
-static bool mei_me_fw_type_nm(struct pci_dev *pdev)
1356
+/**
1357
+ * mei_me_fw_type_nm() - check for nm sku
1358
+ *
1359
+ * Read ME FW Status register to check for the Node Manager (NM) Firmware.
1360
+ * The NM FW is only signaled in PCI function 0.
1361
+ * __Note__: Deprecated by PCH8 and newer.
1362
+ *
1363
+ * @pdev: pci device
1364
+ *
1365
+ * Return: true in case of NM firmware
1366
+ */
1367
+static bool mei_me_fw_type_nm(const struct pci_dev *pdev)
13401368 {
13411369 	u32 reg;
1370
+	unsigned int devfn;
13421371 
1343
-	pci_read_config_dword(pdev, PCI_CFG_HFS_2, &reg);
1372
+	devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
1373
+	pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_2, &reg);
13441374 	trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg);
13451375 	/* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
13461376 	return (reg & 0x600) == 0x200;
....@@ -1349,23 +1379,61 @@
13491379 #define MEI_CFG_FW_NM                           \
13501380 	.quirk_probe = mei_me_fw_type_nm
13511381 
1352
-static bool mei_me_fw_type_sps(struct pci_dev *pdev)
1382
+/**
1383
+ * mei_me_fw_sku_sps_4() - check for sps 4.0 sku
1384
+ *
1385
+ * Read ME FW Status register to check for SPS Firmware.
1386
+ * The SPS FW is only signaled in the PCI function 0.
1387
+ * __Note__: Deprecated by SPS 5.0 and newer.
1388
+ *
1389
+ * @pdev: pci device
1390
+ *
1391
+ * Return: true in case of SPS firmware
1392
+ */
1393
+static bool mei_me_fw_type_sps_4(const struct pci_dev *pdev)
13531394 {
13541395 	u32 reg;
13551396 	unsigned int devfn;
13561397 
1357
-	/*
1358
-	 * Read ME FW Status register to check for SPS Firmware
1359
-	 * The SPS FW is only signaled in pci function 0
1360
-	 */
13611398 	devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
13621399 	pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_1, &reg);
13631400 	trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
1364
-	/* if bits [19:16] = 15, running SPS Firmware */
1365
-	return (reg & 0xf0000) == 0xf0000;
1401
+	return (reg & PCI_CFG_HFS_1_OPMODE_MSK) == PCI_CFG_HFS_1_OPMODE_SPS;
13661402 }
13671403 
1368
-#define MEI_CFG_FW_SPS                           \
1404
+#define MEI_CFG_FW_SPS_4                          \
1405
+	.quirk_probe = mei_me_fw_type_sps_4
1406
+
1407
+/**
1408
+ * mei_me_fw_sku_sps() - check for sps sku
1409
+ *
1410
+ * Read ME FW Status register to check for SPS Firmware.
1411
+ * The SPS FW is only signaled in pci function 0
1412
+ *
1413
+ * @pdev: pci device
1414
+ *
1415
+ * Return: true in case of SPS firmware
1416
+ */
1417
+static bool mei_me_fw_type_sps(const struct pci_dev *pdev)
1418
+{
1419
+	u32 reg;
1420
+	u32 fw_type;
1421
+	unsigned int devfn;
1422
+
1423
+	devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
1424
+	pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_3, &reg);
1425
+	trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_3", PCI_CFG_HFS_3, reg);
1426
+	fw_type = (reg & PCI_CFG_HFS_3_FW_SKU_MSK);
1427
+
1428
+	dev_dbg(&pdev->dev, "fw type is %d\n", fw_type);
1429
+
1430
+	return fw_type == PCI_CFG_HFS_3_FW_SKU_SPS;
1431
+}
1432
+
1433
+#define MEI_CFG_KIND_ITOUCH                     \
1434
+	.kind = "itouch"
1435
+
1436
+#define MEI_CFG_FW_SPS                          \
13691437 	.quirk_probe = mei_me_fw_type_sps
13701438 
13711439 #define MEI_CFG_FW_VER_SUPP                     \
....@@ -1396,6 +1464,9 @@
13961464 	.dma_size[DMA_DSCR_HOST] = SZ_128K, \
13971465 	.dma_size[DMA_DSCR_DEVICE] = SZ_128K, \
13981466 	.dma_size[DMA_DSCR_CTRL] = PAGE_SIZE
1467
+
1468
+#define MEI_CFG_TRC \
1469
+	.hw_trc_supported = 1
13991470 
14001471 /* ICH Legacy devices */
14011472 static const struct mei_cfg mei_me_ich_cfg = {
....@@ -1431,11 +1502,25 @@
14311502 	MEI_CFG_FW_VER_SUPP,
14321503 };
14331504 
1434
-/* PCH8 Lynx Point with quirk for SPS Firmware exclusion */
1435
-static const struct mei_cfg mei_me_pch8_sps_cfg = {
1505
+/* PCH8 Lynx Point and newer devices - iTouch */
1506
+static const struct mei_cfg mei_me_pch8_itouch_cfg = {
1507
+	MEI_CFG_KIND_ITOUCH,
14361508 	MEI_CFG_PCH8_HFS,
14371509 	MEI_CFG_FW_VER_SUPP,
1438
-	MEI_CFG_FW_SPS,
1510
+};
1511
+
1512
+/* PCH8 Lynx Point with quirk for SPS Firmware exclusion */
1513
+static const struct mei_cfg mei_me_pch8_sps_4_cfg = {
1514
+	MEI_CFG_PCH8_HFS,
1515
+	MEI_CFG_FW_VER_SUPP,
1516
+	MEI_CFG_FW_SPS_4,
1517
+};
1518
+
1519
+/* LBG with quirk for SPS (4.0) Firmware exclusion */
1520
+static const struct mei_cfg mei_me_pch12_sps_4_cfg = {
1521
+	MEI_CFG_PCH8_HFS,
1522
+	MEI_CFG_FW_VER_SUPP,
1523
+	MEI_CFG_FW_SPS_4,
14391524 };
14401525 
14411526 /* Cannon Lake and newer devices */
....@@ -1443,6 +1528,41 @@
14431528 	MEI_CFG_PCH8_HFS,
14441529 	MEI_CFG_FW_VER_SUPP,
14451530 	MEI_CFG_DMA_128,
1531
+};
1532
+
1533
+/* Cannon Lake with quirk for SPS 5.0 and newer Firmware exclusion */
1534
+static const struct mei_cfg mei_me_pch12_sps_cfg = {
1535
+	MEI_CFG_PCH8_HFS,
1536
+	MEI_CFG_FW_VER_SUPP,
1537
+	MEI_CFG_DMA_128,
1538
+	MEI_CFG_FW_SPS,
1539
+};
1540
+
1541
+/* Cannon Lake itouch with quirk for SPS 5.0 and newer Firmware exclusion
1542
+ * w/o DMA support.
1543
+ */
1544
+static const struct mei_cfg mei_me_pch12_itouch_sps_cfg = {
1545
+	MEI_CFG_KIND_ITOUCH,
1546
+	MEI_CFG_PCH8_HFS,
1547
+	MEI_CFG_FW_VER_SUPP,
1548
+	MEI_CFG_FW_SPS,
1549
+};
1550
+
1551
+/* Tiger Lake and newer devices */
1552
+static const struct mei_cfg mei_me_pch15_cfg = {
1553
+	MEI_CFG_PCH8_HFS,
1554
+	MEI_CFG_FW_VER_SUPP,
1555
+	MEI_CFG_DMA_128,
1556
+	MEI_CFG_TRC,
1557
+};
1558
+
1559
+/* Tiger Lake with quirk for SPS 5.0 and newer Firmware exclusion */
1560
+static const struct mei_cfg mei_me_pch15_sps_cfg = {
1561
+	MEI_CFG_PCH8_HFS,
1562
+	MEI_CFG_FW_VER_SUPP,
1563
+	MEI_CFG_DMA_128,
1564
+	MEI_CFG_TRC,
1565
+	MEI_CFG_FW_SPS,
14461566 };
14471567 
14481568 /*
....@@ -1457,8 +1577,14 @@
14571577 	[MEI_ME_PCH7_CFG] = &mei_me_pch7_cfg,
14581578 	[MEI_ME_PCH_CPT_PBG_CFG] = &mei_me_pch_cpt_pbg_cfg,
14591579 	[MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg,
1460
-	[MEI_ME_PCH8_SPS_CFG] = &mei_me_pch8_sps_cfg,
1580
+	[MEI_ME_PCH8_ITOUCH_CFG] = &mei_me_pch8_itouch_cfg,
1581
+	[MEI_ME_PCH8_SPS_4_CFG] = &mei_me_pch8_sps_4_cfg,
14611582 	[MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg,
1583
+	[MEI_ME_PCH12_SPS_4_CFG] = &mei_me_pch12_sps_4_cfg,
1584
+	[MEI_ME_PCH12_SPS_CFG] = &mei_me_pch12_sps_cfg,
1585
+	[MEI_ME_PCH12_SPS_ITOUCH_CFG] = &mei_me_pch12_itouch_sps_cfg,
1586
+	[MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg,
1587
+	[MEI_ME_PCH15_SPS_CFG] = &mei_me_pch15_sps_cfg,
14621588 };
14631589 
14641590 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
....@@ -1474,27 +1600,34 @@
14741600 /**
14751601  * mei_me_dev_init - allocates and initializes the mei device structure
14761602  *
1477
- * @pdev: The pci device structure
1603
+ * @parent: device associated with physical device (pci/platform)
14781604  * @cfg: per device generation config
14791605  *
14801606  * Return: The mei_device pointer on success, NULL on failure.
14811607  */
1482
-struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
1608
+struct mei_device *mei_me_dev_init(struct device *parent,
14831609 				   const struct mei_cfg *cfg)
14841610 {
14851611 	struct mei_device *dev;
14861612 	struct mei_me_hw *hw;
1613
+	int i;
14871614 
1488
-	dev = devm_kzalloc(&pdev->dev, sizeof(struct mei_device) +
1489
-			   sizeof(struct mei_me_hw), GFP_KERNEL);
1615
+	dev = devm_kzalloc(parent, sizeof(*dev) + sizeof(*hw), GFP_KERNEL);
14901616 	if (!dev)
14911617 		return NULL;
1618
+
14921619 	hw = to_me_hw(dev);
14931620 
1494
-	mei_device_init(dev, &pdev->dev, &mei_me_hw_ops);
1621
+	for (i = 0; i < DMA_DSCR_NUM; i++)
1622
+		dev->dr_dscr[i].size = cfg->dma_size[i];
1623
+
1624
+	mei_device_init(dev, parent, &mei_me_hw_ops);
14951625 	hw->cfg = cfg;
1626
+
14961627 	dev->fw_f_fw_ver_supported = cfg->fw_ver_supported;
14971628 
1629
+	dev->kind = cfg->kind;
1630
+
14981631 	return dev;
14991632 }
15001633