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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/memory/omap-gpmc.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * GPMC support functions
34  *
....@@ -7,10 +8,6 @@
78  *
89  * Copyright (C) 2009 Texas Instruments
910  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10
- *
11
- * This program is free software; you can redistribute it and/or modify
12
- * it under the terms of the GNU General Public License version 2 as
13
- * published by the Free Software Foundation.
1411  */
1512 #include <linux/irq.h>
1613 #include <linux/kernel.h>
....@@ -22,6 +19,7 @@
2219 #include <linux/io.h>
2320 #include <linux/gpio/driver.h>
2421 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
22
+#include <linux/gpio/machine.h>
2523 #include <linux/interrupt.h>
2624 #include <linux/irqdomain.h>
2725 #include <linux/platform_device.h>
....@@ -31,10 +29,9 @@
3129 #include <linux/of_platform.h>
3230 #include <linux/omap-gpmc.h>
3331 #include <linux/pm_runtime.h>
32
+#include <linux/sizes.h>
3433 
3534 #include <linux/platform_data/mtd-nand-omap2.h>
36
-
37
-#include <asm/mach-types.h>
3835 
3936 #define	DEVICE_NAME		"omap-gpmc"
4037 
....@@ -110,8 +107,8 @@
110107 #define ENABLE_PREFETCH		(0x1 << 7)
111108 #define DMA_MPU_MODE		2
112109 
113
-#define	GPMC_REVISION_MAJOR(l)		((l >> 4) & 0xf)
114
-#define	GPMC_REVISION_MINOR(l)		(l & 0xf)
110
+#define	GPMC_REVISION_MAJOR(l)		(((l) >> 4) & 0xf)
111
+#define	GPMC_REVISION_MINOR(l)		((l) & 0xf)
115112 
116113 #define	GPMC_HAS_WR_ACCESS		0x1
117114 #define	GPMC_HAS_WR_DATA_MUX_BUS	0x2
....@@ -142,27 +139,27 @@
142139 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
143140 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
144141 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
145
-#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
142
+#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
146143 /** CLKACTIVATIONTIME Max Ticks */
147144 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
148
-#define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
145
+#define GPMC_CONFIG1_PAGE_LEN(val)      (((val) & 3) << 23)
149146 /** ATTACHEDDEVICEPAGELENGTH Max Value */
150147 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
151148 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
152149 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
153
-#define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
150
+#define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
154151 /** WAITMONITORINGTIME Max Ticks */
155152 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
156
-#define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
157
-#define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
153
+#define GPMC_CONFIG1_WAIT_PIN_SEL(val)  (((val) & 3) << 16)
154
+#define GPMC_CONFIG1_DEVICESIZE(val)    (((val) & 3) << 12)
158155 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
159156 /** DEVICESIZE Max Value */
160157 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
161
-#define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
158
+#define GPMC_CONFIG1_DEVICETYPE(val)    (((val) & 3) << 10)
162159 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
163
-#define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
160
+#define GPMC_CONFIG1_MUXTYPE(val)       (((val) & 3) << 8)
164161 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
165
-#define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
162
+#define GPMC_CONFIG1_FCLK_DIV(val)      ((val) & 3)
166163 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
167164 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
168165 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
....@@ -246,8 +243,7 @@
246243 /* Define chip-selects as reserved by default until probe completes */
247244 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
248245 static unsigned int gpmc_nr_waitpins;
249
-static resource_size_t phys_base, mem_size;
250
-static unsigned gpmc_capability;
246
+static unsigned int gpmc_capability;
251247 static void __iomem *gpmc_base;
252248 
253249 static struct clk *gpmc_l3_clk;
....@@ -293,15 +289,14 @@
293289 
294290 /**
295291  * gpmc_get_clk_period - get period of selected clock domain in ps
296
- * @cs Chip Select Region.
297
- * @cd Clock Domain.
292
+ * @cs: Chip Select Region.
293
+ * @cd: Clock Domain.
298294  *
299295  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
300296  * prior to calling this function with GPMC_CD_CLK.
301297  */
302298 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
303299 {
304
-
305300 	unsigned long tick_ps = gpmc_get_fclk_period();
306301 	u32 l;
307302 	int div;
....@@ -315,13 +310,11 @@
315310 		tick_ps *= div;
316311 		break;
317312 	case GPMC_CD_FCLK:
318
-		/* FALL-THROUGH */
319313 	default:
320314 		break;
321315 	}
322316 
323317 	return tick_ps;
324
-
325318 }
326319 
327320 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
....@@ -413,7 +406,7 @@
413406  * @reg:     GPMC_CS_CONFIGn register offset.
414407  * @st_bit:  Start Bit
415408  * @end_bit: End Bit. Must be >= @st_bit.
416
- * @ma:x     Maximum parameter value (before optional @shift).
409
+ * @max:     Maximum parameter value (before optional @shift).
417410  *           If 0, maximum is as high as @st_bit and @end_bit allow.
418411  * @name:    DTS node name, w/o "gpmc,"
419412  * @cd:      Clock Domain of timing parameter.
....@@ -513,7 +506,7 @@
513506 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
514507 	GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
515508 	GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
516
-			 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
509
+			       GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
517510 	GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
518511 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
519512 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
....@@ -627,9 +620,8 @@
627620 
628621 	l = gpmc_cs_read_reg(cs, reg);
629622 #ifdef CONFIG_OMAP_GPMC_DEBUG
630
-	pr_info(
631
-		"GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
632
-	       cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
623
+	pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
624
+		cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
633625 			(l >> st_bit) & mask, time);
634626 #endif
635627 	l &= ~(mask << st_bit);
....@@ -638,14 +630,6 @@
638630 
639631 	return 0;
640632 }
641
-
642
-#define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd)  \
643
-	if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
644
-	    t->field, (cd), #field) < 0)                       \
645
-		return -1
646
-
647
-#define GPMC_SET_ONE(reg, st, end, field) \
648
-	GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
649633 
650634 /**
651635  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
....@@ -664,7 +648,6 @@
664648  */
665649 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
666650 {
667
-
668651 	int div = gpmc_ns_to_ticks(wait_monitoring);
669652 
670653 	div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
....@@ -676,7 +659,6 @@
676659 		div = 1;
677660 
678661 	return div;
679
-
680662 }
681663 
682664 /**
....@@ -707,12 +689,12 @@
707689 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
708690 			const struct gpmc_settings *s)
709691 {
710
-	int div;
692
+	int div, ret;
711693 	u32 l;
712694 
713695 	div = gpmc_calc_divider(t->sync_clk);
714696 	if (div < 0)
715
-		return div;
697
+		return -EINVAL;
716698 
717699 	/*
718700 	 * See if we need to change the divider for waitmonitoringtime.
....@@ -730,64 +712,120 @@
730712 	if (!s->sync_read && !s->sync_write &&
731713 	    (s->wait_on_read || s->wait_on_write)
732714 	   ) {
733
-
734715 		div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
735716 		if (div < 0) {
736717 			pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
737718 			       __func__,
738719 			       t->wait_monitoring
739720 			       );
740
-			return -1;
721
+			return -ENXIO;
741722 		}
742723 	}
743724 
744
-	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
745
-	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
746
-	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
725
+	ret = 0;
726
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
727
+				   GPMC_CD_FCLK, "cs_on");
728
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
729
+				   GPMC_CD_FCLK, "cs_rd_off");
730
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
731
+				   GPMC_CD_FCLK, "cs_wr_off");
732
+	if (ret)
733
+		return -ENXIO;
747734 
748
-	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
749
-	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
750
-	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
735
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
736
+				   GPMC_CD_FCLK, "adv_on");
737
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
738
+				   GPMC_CD_FCLK, "adv_rd_off");
739
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
740
+				   GPMC_CD_FCLK, "adv_wr_off");
741
+	if (ret)
742
+		return -ENXIO;
743
+
751744 	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
752
-		GPMC_SET_ONE(GPMC_CS_CONFIG3,  4,  6, adv_aad_mux_on);
753
-		GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
754
-		GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
745
+		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
746
+					   t->adv_aad_mux_on, GPMC_CD_FCLK,
747
+					   "adv_aad_mux_on");
748
+		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
749
+					   t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
750
+					   "adv_aad_mux_rd_off");
751
+		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
752
+					   t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
753
+					   "adv_aad_mux_wr_off");
754
+		if (ret)
755
+			return -ENXIO;
755756 	}
756757 
757
-	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
758
-	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
758
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
759
+				   GPMC_CD_FCLK, "oe_on");
760
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
761
+				   GPMC_CD_FCLK, "oe_off");
759762 	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
760
-		GPMC_SET_ONE(GPMC_CS_CONFIG4,  4,  6, oe_aad_mux_on);
761
-		GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
763
+		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
764
+					   t->oe_aad_mux_on, GPMC_CD_FCLK,
765
+					   "oe_aad_mux_on");
766
+		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
767
+					   t->oe_aad_mux_off, GPMC_CD_FCLK,
768
+					   "oe_aad_mux_off");
762769 	}
763
-	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
764
-	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
770
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
771
+				   GPMC_CD_FCLK, "we_on");
772
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
773
+				   GPMC_CD_FCLK, "we_off");
774
+	if (ret)
775
+		return -ENXIO;
765776 
766
-	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
767
-	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
768
-	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
777
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
778
+				   GPMC_CD_FCLK, "rd_cycle");
779
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
780
+				   GPMC_CD_FCLK, "wr_cycle");
781
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
782
+				   GPMC_CD_FCLK, "access");
783
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
784
+				   t->page_burst_access, GPMC_CD_FCLK,
785
+				   "page_burst_access");
786
+	if (ret)
787
+		return -ENXIO;
769788 
770
-	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
789
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
790
+				   t->bus_turnaround, GPMC_CD_FCLK,
791
+				   "bus_turnaround");
792
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
793
+				   t->cycle2cycle_delay, GPMC_CD_FCLK,
794
+				   "cycle2cycle_delay");
795
+	if (ret)
796
+		return -ENXIO;
771797 
772
-	GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
773
-	GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
774
-
775
-	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
776
-		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
777
-	if (gpmc_capability & GPMC_HAS_WR_ACCESS)
778
-		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
798
+	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
799
+		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
800
+					   t->wr_data_mux_bus, GPMC_CD_FCLK,
801
+					   "wr_data_mux_bus");
802
+		if (ret)
803
+			return -ENXIO;
804
+	}
805
+	if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
806
+		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
807
+					   t->wr_access, GPMC_CD_FCLK,
808
+					   "wr_access");
809
+		if (ret)
810
+			return -ENXIO;
811
+	}
779812 
780813 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
781814 	l &= ~0x03;
782815 	l |= (div - 1);
783816 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
784817 
785
-	GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
786
-			    GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
787
-			    wait_monitoring, GPMC_CD_CLK);
788
-	GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
789
-			    GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
790
-			    clk_activation, GPMC_CD_FCLK);
818
+	ret = 0;
819
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
820
+				   GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
821
+				   t->wait_monitoring, GPMC_CD_CLK,
822
+				   "wait_monitoring");
823
+	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
824
+				   GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
825
+				   t->clk_activation, GPMC_CD_FCLK,
826
+				   "clk_activation");
827
+	if (ret)
828
+		return -ENXIO;
791829 
792830 #ifdef CONFIG_OMAP_GPMC_DEBUG
793831 	pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
....@@ -878,20 +916,6 @@
878916 	return gpmc->flags & GPMC_CS_RESERVED;
879917 }
880918 
881
-static void gpmc_cs_set_name(int cs, const char *name)
882
-{
883
-	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
884
-
885
-	gpmc->name = name;
886
-}
887
-
888
-static const char *gpmc_cs_get_name(int cs)
889
-{
890
-	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
891
-
892
-	return gpmc->name;
893
-}
894
-
895919 static unsigned long gpmc_mem_align(unsigned long size)
896920 {
897921 	int order;
....@@ -935,49 +959,6 @@
935959 	spin_unlock(&gpmc_mem_lock);
936960 
937961 	return r;
938
-}
939
-
940
-/**
941
- * gpmc_cs_remap - remaps a chip-select physical base address
942
- * @cs:		chip-select to remap
943
- * @base:	physical base address to re-map chip-select to
944
- *
945
- * Re-maps a chip-select to a new physical base address specified by
946
- * "base". Returns 0 on success and appropriate negative error code
947
- * on failure.
948
- */
949
-static int gpmc_cs_remap(int cs, u32 base)
950
-{
951
-	int ret;
952
-	u32 old_base, size;
953
-
954
-	if (cs >= gpmc_cs_num) {
955
-		pr_err("%s: requested chip-select is disabled\n", __func__);
956
-		return -ENODEV;
957
-	}
958
-
959
-	/*
960
-	 * Make sure we ignore any device offsets from the GPMC partition
961
-	 * allocated for the chip select and that the new base confirms
962
-	 * to the GPMC 16MB minimum granularity.
963
-	 */ 
964
-	base &= ~(SZ_16M - 1);
965
-
966
-	gpmc_cs_get_memconf(cs, &old_base, &size);
967
-	if (base == old_base)
968
-		return 0;
969
-
970
-	ret = gpmc_cs_delete_mem(cs);
971
-	if (ret < 0)
972
-		return ret;
973
-
974
-	ret = gpmc_cs_insert_mem(cs, base, size);
975
-	if (ret < 0)
976
-		return ret;
977
-
978
-	ret = gpmc_cs_set_memconf(cs, base, size);
979
-
980
-	return ret;
981962 }
982963 
983964 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
....@@ -1033,8 +1014,7 @@
10331014 
10341015 	spin_lock(&gpmc_mem_lock);
10351016 	if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1036
-		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1037
-		BUG();
1017
+		WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs);
10381018 		spin_unlock(&gpmc_mem_lock);
10391019 		return;
10401020 	}
....@@ -1092,7 +1072,7 @@
10921072 
10931073 /**
10941074  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1095
- * @regs: the GPMC NAND register map exclusive for NAND use.
1075
+ * @reg: the GPMC NAND register map exclusive for NAND use.
10961076  * @cs: GPMC chip select number on which the NAND sits. The
10971077  *      register map returned will be specific to this chip select.
10981078  *
....@@ -1247,7 +1227,7 @@
12471227 }
12481228 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
12491229 
1250
-int gpmc_get_client_irq(unsigned irq_config)
1230
+int gpmc_get_client_irq(unsigned int irq_config)
12511231 {
12521232 	if (!gpmc_irq_domain) {
12531233 		pr_warn("%s called before GPMC IRQ domain available\n",
....@@ -1470,7 +1450,6 @@
14701450 			continue;
14711451 		gpmc_cs_delete_mem(cs);
14721452 	}
1473
-
14741453 }
14751454 
14761455 static void gpmc_mem_init(void)
....@@ -1639,17 +1618,14 @@
16391618 	/* oe_on */
16401619 	temp = dev_t->t_oeasu;
16411620 	if (mux)
1642
-		temp = max_t(u32, temp,
1643
-			gpmc_t->adv_rd_off + dev_t->t_aavdh);
1621
+		temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
16441622 	gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
16451623 
16461624 	/* access */
16471625 	temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1648
-				gpmc_t->oe_on + dev_t->t_oe);
1649
-	temp = max_t(u32, temp,
1650
-				gpmc_t->cs_on + dev_t->t_ce);
1651
-	temp = max_t(u32, temp,
1652
-				gpmc_t->adv_on + dev_t->t_aa);
1626
+		     gpmc_t->oe_on + dev_t->t_oe);
1627
+	temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
1628
+	temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
16531629 	gpmc_t->access = gpmc_round_ps_to_ticks(temp);
16541630 
16551631 	gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
....@@ -1758,10 +1734,11 @@
17581734 	return 0;
17591735 }
17601736 
1761
-/* TODO: remove this function once all peripherals are confirmed to
1737
+/*
1738
+ * TODO: remove this function once all peripherals are confirmed to
17621739  * work with generic timing. Simultaneously gpmc_cs_set_timings()
17631740  * has to be modified to handle timings in ps instead of ns
1764
-*/
1741
+ */
17651742 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
17661743 {
17671744 	t->cs_on /= 1000;
....@@ -1909,6 +1886,63 @@
19091886 	{ .compatible = "ti,am3352-gpmc" },	/* am335x devices */
19101887 	{ }
19111888 };
1889
+
1890
+static void gpmc_cs_set_name(int cs, const char *name)
1891
+{
1892
+	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1893
+
1894
+	gpmc->name = name;
1895
+}
1896
+
1897
+static const char *gpmc_cs_get_name(int cs)
1898
+{
1899
+	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1900
+
1901
+	return gpmc->name;
1902
+}
1903
+
1904
+/**
1905
+ * gpmc_cs_remap - remaps a chip-select physical base address
1906
+ * @cs:		chip-select to remap
1907
+ * @base:	physical base address to re-map chip-select to
1908
+ *
1909
+ * Re-maps a chip-select to a new physical base address specified by
1910
+ * "base". Returns 0 on success and appropriate negative error code
1911
+ * on failure.
1912
+ */
1913
+static int gpmc_cs_remap(int cs, u32 base)
1914
+{
1915
+	int ret;
1916
+	u32 old_base, size;
1917
+
1918
+	if (cs >= gpmc_cs_num) {
1919
+		pr_err("%s: requested chip-select is disabled\n", __func__);
1920
+		return -ENODEV;
1921
+	}
1922
+
1923
+	/*
1924
+	 * Make sure we ignore any device offsets from the GPMC partition
1925
+	 * allocated for the chip select and that the new base confirms
1926
+	 * to the GPMC 16MB minimum granularity.
1927
+	 */
1928
+	base &= ~(SZ_16M - 1);
1929
+
1930
+	gpmc_cs_get_memconf(cs, &old_base, &size);
1931
+	if (base == old_base)
1932
+		return 0;
1933
+
1934
+	ret = gpmc_cs_delete_mem(cs);
1935
+	if (ret < 0)
1936
+		return ret;
1937
+
1938
+	ret = gpmc_cs_insert_mem(cs, base, size);
1939
+	if (ret < 0)
1940
+		return ret;
1941
+
1942
+	ret = gpmc_cs_set_memconf(cs, base, size);
1943
+
1944
+	return ret;
1945
+}
19121946 
19131947 /**
19141948  * gpmc_read_settings_dt - read gpmc settings from device-tree
....@@ -2064,7 +2098,7 @@
20642098 	 * timings.
20652099 	 */
20662100 	name = gpmc_cs_get_name(cs);
2067
-	if (name && of_node_cmp(child->name, name) == 0)
2101
+	if (name && of_node_name_eq(child, name))
20682102 		goto no_timings;
20692103 
20702104 	ret = gpmc_cs_request(cs, resource_size(&res), &base);
....@@ -2072,7 +2106,7 @@
20722106 		dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
20732107 		return ret;
20742108 	}
2075
-	gpmc_cs_set_name(cs, child->name);
2109
+	gpmc_cs_set_name(cs, child->full_name);
20762110 
20772111 	gpmc_read_settings_dt(child, &gpmc_s);
20782112 	gpmc_read_timings_dt(child, &gpmc_t);
....@@ -2094,7 +2128,7 @@
20942128 	gpmc_cs_disable_mem(cs);
20952129 
20962130 	/*
2097
-	 * FIXME: gpmc_cs_request() will map the CS to an arbitary
2131
+	 * FIXME: gpmc_cs_request() will map the CS to an arbitrary
20982132 	 * location in the gpmc address space. When booting with
20992133 	 * device-tree we want the NOR flash to be mapped to the
21002134 	 * location specified in the device-tree blob. So remap the
....@@ -2117,7 +2151,7 @@
21172151 		goto err;
21182152 	}
21192153 
2120
-	if (of_node_cmp(child->name, "nand") == 0) {
2154
+	if (of_node_name_eq(child, "nand")) {
21212155 		/* Warn about older DT blobs with no compatible property */
21222156 		if (!of_property_read_bool(child, "compatible")) {
21232157 			dev_warn(&pdev->dev,
....@@ -2127,7 +2161,7 @@
21272161 		}
21282162 	}
21292163 
2130
-	if (of_node_cmp(child->name, "onenand") == 0) {
2164
+	if (of_node_name_eq(child, "onenand")) {
21312165 		/* Warn about older DT blobs with no compatible property */
21322166 		if (!of_property_read_bool(child, "compatible")) {
21332167 			dev_warn(&pdev->dev,
....@@ -2149,8 +2183,8 @@
21492183 			gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
21502184 			break;
21512185 		default:
2152
-			dev_err(&pdev->dev, "%s: invalid 'nand-bus-width'\n",
2153
-				child->name);
2186
+			dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2187
+				child);
21542188 			ret = -EINVAL;
21552189 			goto err;
21562190 		}
....@@ -2174,7 +2208,9 @@
21742208 		unsigned int wait_pin = gpmc_s.wait_pin;
21752209 
21762210 		waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2177
-							 wait_pin, "WAITPIN");
2211
+							 wait_pin, "WAITPIN",
2212
+							 GPIO_ACTIVE_HIGH,
2213
+							 GPIOD_IN);
21782214 		if (IS_ERR(waitpin_desc)) {
21792215 			dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
21802216 			ret = PTR_ERR(waitpin_desc);
....@@ -2190,8 +2226,8 @@
21902226 
21912227 	ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
21922228 	if (ret) {
2193
-		dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2194
-			child->name);
2229
+		dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2230
+			child);
21952231 		goto err_cs;
21962232 	}
21972233 
....@@ -2219,7 +2255,7 @@
22192255 
22202256 err_child_fail:
22212257 
2222
-	dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2258
+	dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
22232259 	ret = -ENODEV;
22242260 
22252261 err_cs:
....@@ -2269,14 +2305,10 @@
22692305 	struct device_node *child;
22702306 
22712307 	for_each_available_child_of_node(pdev->dev.of_node, child) {
2272
-
2273
-		if (!child->name)
2274
-			continue;
2275
-
22762308 		ret = gpmc_probe_generic_child(pdev, child);
22772309 		if (ret) {
2278
-			dev_err(&pdev->dev, "failed to probe DT child '%s': %d\n",
2279
-				child->name, ret);
2310
+			dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2311
+				child, ret);
22802312 		}
22812313 	}
22822314 }
....@@ -2367,11 +2399,8 @@
23672399 	platform_set_drvdata(pdev, gpmc);
23682400 
23692401 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2370
-	if (res == NULL)
2402
+	if (!res)
23712403 		return -ENOENT;
2372
-
2373
-	phys_base = res->start;
2374
-	mem_size = resource_size(res);
23752404 
23762405 	gpmc_base = devm_ioremap_resource(&pdev->dev, res);
23772406 	if (IS_ERR(gpmc_base))