修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/drivers/memory/fsl_ifc.c
..
..
@@ -1,23 +1,10 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Copyright 2011 Freescale Semiconductor, Inc
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  *
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  * Freescale Integrated Flash Controller
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  *
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  * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
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- *
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- * This program is free software; you can redistribute  it and/or modify it
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- * under  the terms of  the GNU General  Public License as published by the
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- * Free Software Foundation;  either version 2 of the  License, or (at your
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- * option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program; if not, write to the Free Software
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- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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  */
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 #include <linux/module.h>
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10
 #include <linux/kernel.h>
..
..
@@ -66,6 +53,7 @@
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53
 
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 	for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
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 		u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
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+
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 		if (cspr & CSPR_V && (cspr & CSPR_BA) ==
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 				convert_ifc_address(addr_base))
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 			return i;
..
..
@@ -165,8 +153,8 @@
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 	/* read for chip select error */
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 	cs_err = ifc_in32(&ifc->cm_evter_stat);
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 	if (cs_err) {
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-		dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
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-				"any memory bank 0x%08X\n", cs_err);
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+		dev_err(ctrl->dev, "transaction sent to IFC is not mapped to any memory bank 0x%08X\n",
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+			cs_err);
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 		/* clear the chip select error */
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 		ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
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160
 
..
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@@ -175,24 +163,24 @@
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 		err_addr = ifc_in32(&ifc->cm_erattr1);
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 		if (status & IFC_CM_ERATTR0_ERTYP_READ)
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-			dev_err(ctrl->dev, "Read transaction error"
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-				"CM_ERATTR0 0x%08X\n", status);
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+			dev_err(ctrl->dev, "Read transaction error CM_ERATTR0 0x%08X\n",
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+				status);
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 		else
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-			dev_err(ctrl->dev, "Write transaction error"
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-				"CM_ERATTR0 0x%08X\n", status);
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+			dev_err(ctrl->dev, "Write transaction error CM_ERATTR0 0x%08X\n",
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+				status);
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 		err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
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 					IFC_CM_ERATTR0_ERAID_SHIFT;
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-		dev_err(ctrl->dev, "AXI ID of the error"
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-					"transaction 0x%08X\n", err_axiid);
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+		dev_err(ctrl->dev, "AXI ID of the error transaction 0x%08X\n",
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+			err_axiid);
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 		err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
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 					IFC_CM_ERATTR0_ESRCID_SHIFT;
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-		dev_err(ctrl->dev, "SRC ID of the error"
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-					"transaction 0x%08X\n", err_srcid);
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+		dev_err(ctrl->dev, "SRC ID of the error transaction 0x%08X\n",
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+			err_srcid);
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-		dev_err(ctrl->dev, "Transaction Address corresponding to error"
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-					"ERADDR 0x%08X\n", err_addr);
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+		dev_err(ctrl->dev, "Transaction Address corresponding to error ERADDR 0x%08X\n",
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+			err_addr);
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 		ret = IRQ_HANDLED;
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 	}
..
..
@@ -211,7 +199,7 @@
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  * the resources needed for the controller only.  The
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  * resources for the NAND banks themselves are allocated
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  * in the chip probe function.
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-*/
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+ */
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 static int fsl_ifc_ctrl_probe(struct platform_device *dev)
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 {
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 	int ret = 0;
..
..
@@ -262,8 +250,7 @@
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 	/* get the Controller level irq */
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 	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
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 	if (fsl_ifc_ctrl_dev->irq == 0) {
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-		dev_err(&dev->dev, "failed to get irq resource "
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-							"for IFC\n");
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+		dev_err(&dev->dev, "failed to get irq resource for IFC\n");
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 		ret = -ENODEV;
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 		goto err;
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 	}