~hc/RK356X_SDK_RELEASE.git

..	..	@@ -26,6 +26,7 @@
26	26	#include <media/v4l2-ctrls.h>
27	27	#include <media/v4l2-subdev.h>
28	28	#include <linux/pinctrl/consumer.h>
	29	+#include "../platform/rockchip/isp/rkisp_tb_helper.h"
29	30
30	31	#define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
31	32
..	..	@@ -35,11 +36,15 @@
35	36
36	37	#define SC3336_LANES 2
37	38	#define SC3336_BITS_PER_SAMPLE 10
	39	+#define SC3336_LINK_FREQ_253 253125000
38	40	#define SC3336_LINK_FREQ_255 255000000
39	41
	42	+#define PIXEL_RATE_WITH_253M_10BIT (SC3336_LINK_FREQ_253 * 2 * \
	43	+ SC3336_LANES / SC3336_BITS_PER_SAMPLE)
40	44	#define PIXEL_RATE_WITH_255M_10BIT (SC3336_LINK_FREQ_255 * 2 * \
41	45	SC3336_LANES / SC3336_BITS_PER_SAMPLE)
42		-#define SC3336_XVCLK_FREQ 24000000
	46	+
	47	+#define SC3336_XVCLK_FREQ 27000000
43	48
44	49	#define CHIP_ID 0xcc41
45	50	#define SC3336_REG_CHIP_ID 0x3107
..	..	@@ -110,14 +115,6 @@
110	115	u8 val;
111	116	};
112	117
113		-enum sc3336_max_pad {
114		- PAD0,
115		- PAD1,
116		- PAD2,
117		- PAD3,
118		- PAD_MAX,
119		-};
120		-
121	118	struct sc3336_mode {
122	119	u32 bus_fmt;
123	120	u32 width;
..	..	@@ -128,6 +125,8 @@
128	125	u32 exp_def;
129	126	const struct regval *reg_list;
130	127	u32 hdr_mode;
	128	+ u32 xvclk_freq;
	129	+ u32 link_freq_idx;
131	130	u32 vc[PAD_MAX];
132	131	};
133	132
..	..	@@ -150,8 +149,11 @@
150	149	struct v4l2_ctrl *digi_gain;
151	150	struct v4l2_ctrl *hblank;
152	151	struct v4l2_ctrl *vblank;
	152	+ struct v4l2_ctrl *pixel_rate;
	153	+ struct v4l2_ctrl *link_freq;
153	154	struct v4l2_ctrl *test_pattern;
154	155	struct mutex mutex;
	156	+ struct v4l2_fract cur_fps;
155	157	bool streaming;
156	158	bool power_on;
157	159	const struct sc3336_mode *cur_mode;
..	..	@@ -160,6 +162,10 @@
160	162	const char *module_name;
161	163	const char *len_name;
162	164	u32 cur_vts;
	165	+ bool has_init_exp;
	166	+ bool is_thunderboot;
	167	+ bool is_first_streamoff;
	168	+ struct preisp_hdrae_exp_s init_hdrae_exp;
163	169	};
164	170
165	171	#define to_sc3336(sd) container_of(sd, struct sc3336, subdev)
..	..	@@ -172,11 +178,150 @@
172	178	};
173	179
174	180	/*
	181	+ * Xclk 27Mhz
	182	+ * max_framerate 25fps
	183	+ * mipi_datarate per lane 506.25Mbps, 2lane
	184	+ */
	185	+static const struct regval sc3336_linear_10_2304x1296_25fps_regs[] = {
	186	+ {0x0103, 0x01},
	187	+ {0x36e9, 0x80},
	188	+ {0x37f9, 0x80},
	189	+ {0x301f, 0x01},
	190	+ {0x30b8, 0x33},
	191	+ {0x320e, 0x06},
	192	+ {0x320f, 0x54},
	193	+ {0x3253, 0x10},
	194	+ {0x325f, 0x20},
	195	+ {0x3301, 0x04},
	196	+ {0x3306, 0x50},
	197	+ {0x3309, 0xa8},
	198	+ {0x330a, 0x00},
	199	+ {0x330b, 0xd8},
	200	+ {0x3314, 0x13},
	201	+ {0x331f, 0x99},
	202	+ {0x3333, 0x10},
	203	+ {0x3334, 0x40},
	204	+ {0x335e, 0x06},
	205	+ {0x335f, 0x0a},
	206	+ {0x3364, 0x5e},
	207	+ {0x337c, 0x02},
	208	+ {0x337d, 0x0e},
	209	+ {0x3390, 0x01},
	210	+ {0x3391, 0x03},
	211	+ {0x3392, 0x07},
	212	+ {0x3393, 0x04},
	213	+ {0x3394, 0x04},
	214	+ {0x3395, 0x04},
	215	+ {0x3396, 0x08},
	216	+ {0x3397, 0x0b},
	217	+ {0x3398, 0x1f},
	218	+ {0x3399, 0x04},
	219	+ {0x339a, 0x0a},
	220	+ {0x339b, 0x3a},
	221	+ {0x339c, 0xb4},
	222	+ {0x33a2, 0x04},
	223	+ {0x33ac, 0x08},
	224	+ {0x33ad, 0x1c},
	225	+ {0x33ae, 0x10},
	226	+ {0x33af, 0x30},
	227	+ {0x33b1, 0x80},
	228	+ {0x33b3, 0x48},
	229	+ {0x33f9, 0x60},
	230	+ {0x33fb, 0x74},
	231	+ {0x33fc, 0x4b},
	232	+ {0x33fd, 0x5f},
	233	+ {0x349f, 0x03},
	234	+ {0x34a6, 0x4b},
	235	+ {0x34a7, 0x5f},
	236	+ {0x34a8, 0x20},
	237	+ {0x34a9, 0x18},
	238	+ {0x34ab, 0xe8},
	239	+ {0x34ac, 0x01},
	240	+ {0x34ad, 0x00},
	241	+ {0x34f8, 0x5f},
	242	+ {0x34f9, 0x18},
	243	+ {0x3630, 0xc0},
	244	+ {0x3631, 0x84},
	245	+ {0x3632, 0x64},
	246	+ {0x3633, 0x32},
	247	+ {0x363b, 0x03},
	248	+ {0x363c, 0x08},
	249	+ {0x3641, 0x38},
	250	+ {0x3670, 0x4e},
	251	+ {0x3674, 0xc0},
	252	+ {0x3675, 0xc0},
	253	+ {0x3676, 0xc0},
	254	+ {0x3677, 0x84},
	255	+ {0x3678, 0x84},
	256	+ {0x3679, 0x84},
	257	+ {0x367c, 0x48},
	258	+ {0x367d, 0x49},
	259	+ {0x367e, 0x4b},
	260	+ {0x367f, 0x5f},
	261	+ {0x3690, 0x32},
	262	+ {0x3691, 0x32},
	263	+ {0x3692, 0x42},
	264	+ {0x369c, 0x4b},
	265	+ {0x369d, 0x5f},
	266	+ {0x36b0, 0x87},
	267	+ {0x36b1, 0x90},
	268	+ {0x36b2, 0xa1},
	269	+ {0x36b3, 0xd8},
	270	+ {0x36b4, 0x49},
	271	+ {0x36b5, 0x4b},
	272	+ {0x36b6, 0x4f},
	273	+ {0x370f, 0x01},
	274	+ {0x3722, 0x09},
	275	+ {0x3724, 0x41},
	276	+ {0x3725, 0xc1},
	277	+ {0x3771, 0x09},
	278	+ {0x3772, 0x09},
	279	+ {0x3773, 0x05},
	280	+ {0x377a, 0x48},
	281	+ {0x377b, 0x5f},
	282	+ {0x3904, 0x04},
	283	+ {0x3905, 0x8c},
	284	+ {0x391d, 0x04},
	285	+ {0x3921, 0x20},
	286	+ {0x3926, 0x21},
	287	+ {0x3933, 0x80},
	288	+ {0x3934, 0x0a},
	289	+ {0x3935, 0x00},
	290	+ {0x3936, 0x2a},
	291	+ {0x3937, 0x6a},
	292	+ {0x3938, 0x6a},
	293	+ {0x39dc, 0x02},
	294	+ {0x3e01, 0x53},
	295	+ {0x3e02, 0xe0},
	296	+ {0x3e09, 0x00},
	297	+ {0x440e, 0x02},
	298	+ {0x4509, 0x20},
	299	+ {0x5ae0, 0xfe},
	300	+ {0x5ae1, 0x40},
	301	+ {0x5ae2, 0x38},
	302	+ {0x5ae3, 0x30},
	303	+ {0x5ae4, 0x28},
	304	+ {0x5ae5, 0x38},
	305	+ {0x5ae6, 0x30},
	306	+ {0x5ae7, 0x28},
	307	+ {0x5ae8, 0x3f},
	308	+ {0x5ae9, 0x34},
	309	+ {0x5aea, 0x2c},
	310	+ {0x5aeb, 0x3f},
	311	+ {0x5aec, 0x34},
	312	+ {0x5aed, 0x2c},
	313	+ {0x36e9, 0x54},
	314	+ {0x37f9, 0x27},
	315	+ {0x3028, 0x05},
	316	+ {REG_NULL, 0x00},
	317	+};
	318	+
	319	+/*
175	320	* Xclk 24Mhz
176	321	* max_framerate 30fps
177	322	* mipi_datarate per lane 510Mbps, 2lane
178	323	*/
179		-static const struct regval sc3336_linear_10_2304x1296_regs[] = {
	324	+static const struct regval sc3336_linear_10_2304x1296_30fps_regs[] = {
180	325	{0x0103, 0x01},
181	326	{0x36e9, 0x80},
182	327	{0x37f9, 0x80},
..	..	@@ -321,20 +466,40 @@
321	466	.height = 1296,
322	467	.max_fps = {
323	468	.numerator = 10000,
	469	+ .denominator = 250000,
	470	+ },
	471	+ .exp_def = 0x0080,
	472	+ .hts_def = 0x05dc,
	473	+ .vts_def = 0x0654,
	474	+ .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
	475	+ .reg_list = sc3336_linear_10_2304x1296_25fps_regs,
	476	+ .hdr_mode = NO_HDR,
	477	+ .xvclk_freq = 27000000,
	478	+ .link_freq_idx = 0,
	479	+ .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
	480	+ },
	481	+ {
	482	+ .width = 2304,
	483	+ .height = 1296,
	484	+ .max_fps = {
	485	+ .numerator = 10000,
324	486	.denominator = 300000,
325	487	},
326	488	.exp_def = 0x0080,
327	489	.hts_def = 0x0578 * 2,
328	490	.vts_def = 0x0550,
329	491	.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
330		- .reg_list = sc3336_linear_10_2304x1296_regs,
	492	+ .reg_list = sc3336_linear_10_2304x1296_30fps_regs,
331	493	.hdr_mode = NO_HDR,
	494	+ .xvclk_freq = 24000000,
	495	+ .link_freq_idx = 1,
332	496	.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
333	497	}
334	498	};
335	499
336	500	static const s64 link_freq_menu_items[] = {
337		- SC3336_LINK_FREQ_255
	501	+ SC3336_LINK_FREQ_253,
	502	+ SC3336_LINK_FREQ_255,
338	503	};
339	504
340	505	static const char * const sc3336_test_pattern_menu[] = {
..	..	@@ -342,7 +507,7 @@
342	507	"Vertical Color Bar Type 1",
343	508	"Vertical Color Bar Type 2",
344	509	"Vertical Color Bar Type 3",
345		- "Vertical Color Bar Type 4"
	510	+ "Vertical Color Bar Type 4",
346	511	};
347	512
348	513	/* Write registers up to 4 at a time */
..	..	@@ -423,9 +588,9 @@
423	588
424	589	static int sc3336_set_gain_reg(struct sc3336 *sc3336, u32 gain)
425	590	{
426		- u32 coarse_again = 0, coarse_dgian = 0, fine_dgian = 0;
427		- u32 gain_factor;
428		- int ret = 0;
	591	+ struct i2c_client *client = sc3336->client;
	592	+ u32 coarse_again = 0, coarse_dgain = 0, fine_dgain = 0;
	593	+ int ret = 0, gain_factor;
429	594
430	595	if (gain < 128)
431	596	gain = 128;
..	..	@@ -435,55 +600,57 @@
435	600	gain_factor = gain * 1000 / 128;
436	601	if (gain_factor < 1520) {
437	602	coarse_again = 0x00;
438		- coarse_dgian = 0x00;
439		- fine_dgian = gain_factor * 128 / 1000;
	603	+ coarse_dgain = 0x00;
	604	+ fine_dgain = gain_factor * 128 / 1000;
440	605	} else if (gain_factor < 3040) {
441	606	coarse_again = 0x40;
442		- coarse_dgian = 0x00;
443		- fine_dgian = gain_factor * 128 / 1520;
	607	+ coarse_dgain = 0x00;
	608	+ fine_dgain = gain_factor * 128 / 1520;
444	609	} else if (gain_factor < 6080) {
445	610	coarse_again = 0x48;
446		- coarse_dgian = 0x00;
447		- fine_dgian = gain_factor * 128 / 3040;
	611	+ coarse_dgain = 0x00;
	612	+ fine_dgain = gain_factor * 128 / 3040;
448	613	} else if (gain_factor < 12160) {
449	614	coarse_again = 0x49;
450		- coarse_dgian = 0x00;
451		- fine_dgian = gain_factor * 128 / 6080;
	615	+ coarse_dgain = 0x00;
	616	+ fine_dgain = gain_factor * 128 / 6080;
452	617	} else if (gain_factor < 24320) {
453	618	coarse_again = 0x4b;
454		- coarse_dgian = 0x00;
455		- fine_dgian = gain_factor * 128 / 12160;
	619	+ coarse_dgain = 0x00;
	620	+ fine_dgain = gain_factor * 128 / 12160;
456	621	} else if (gain_factor < 48640) {
457	622	coarse_again = 0x4f;
458		- coarse_dgian = 0x00;
459		- fine_dgian = gain_factor * 128 / 24320;
	623	+ coarse_dgain = 0x00;
	624	+ fine_dgain = gain_factor * 128 / 24320;
460	625	} else if (gain_factor < 48640 * 2) {
461	626	//open dgain begin max digital gain 4X
462	627	coarse_again = 0x5f;
463		- coarse_dgian = 0x00;
464		- fine_dgian = gain_factor * 128 / 48640;
	628	+ coarse_dgain = 0x00;
	629	+ fine_dgain = gain_factor * 128 / 48640;
465	630	} else if (gain_factor < 48640 * 4) {
466	631	coarse_again = 0x5f;
467		- coarse_dgian = 0x01;
468		- fine_dgian = gain_factor * 128 / 48640 / 2;
	632	+ coarse_dgain = 0x01;
	633	+ fine_dgain = gain_factor * 128 / 48640 / 2;
469	634	} else if (gain_factor < 48640 * 8) {
470	635	coarse_again = 0x5f;
471		- coarse_dgian = 0x03;
472		- fine_dgian = gain_factor * 128 / 48640 / 4;
	636	+ coarse_dgain = 0x03;
	637	+ fine_dgain = gain_factor * 128 / 48640 / 4;
473	638	} else if (gain_factor < 48640 * 16) {
474	639	coarse_again = 0x5f;
475		- coarse_dgian = 0x07;
476		- fine_dgian = gain_factor * 128 / 48640 / 8;
	640	+ coarse_dgain = 0x07;
	641	+ fine_dgain = gain_factor * 128 / 48640 / 8;
477	642	}
	643	+ dev_dbg(&client->dev, "c_again: 0x%x, c_dgain: 0x%x, f_dgain: 0x%0x\n",
	644	+ coarse_again, coarse_dgain, fine_dgain);
478	645
479	646	ret = sc3336_write_reg(sc3336->client,
480	647	SC3336_REG_DIG_GAIN,
481	648	SC3336_REG_VALUE_08BIT,
482		- coarse_dgian);
	649	+ coarse_dgain);
483	650	ret \|= sc3336_write_reg(sc3336->client,
484	651	SC3336_REG_DIG_FINE_GAIN,
485	652	SC3336_REG_VALUE_08BIT,
486		- fine_dgian);
	653	+ fine_dgain);
487	654	ret \|= sc3336_write_reg(sc3336->client,
488	655	SC3336_REG_ANA_GAIN,
489	656	SC3336_REG_VALUE_08BIT,
..	..	@@ -526,6 +693,8 @@
526	693	struct sc3336 *sc3336 = to_sc3336(sd);
527	694	const struct sc3336_mode *mode;
528	695	s64 h_blank, vblank_def;
	696	+ u64 dst_link_freq = 0;
	697	+ u64 dst_pixel_rate = 0;
529	698
530	699	mutex_lock(&sc3336->mutex);
531	700
..	..	@@ -550,6 +719,14 @@
550	719	__v4l2_ctrl_modify_range(sc3336->vblank, vblank_def,
551	720	SC3336_VTS_MAX - mode->height,
552	721	1, vblank_def);
	722	+ dst_link_freq = mode->link_freq_idx;
	723	+ dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
	724	+ SC3336_BITS_PER_SAMPLE * 2 * SC3336_LANES;
	725	+ __v4l2_ctrl_s_ctrl_int64(sc3336->pixel_rate,
	726	+ dst_pixel_rate);
	727	+ __v4l2_ctrl_s_ctrl(sc3336->link_freq,
	728	+ dst_link_freq);
	729	+ sc3336->cur_fps = mode->max_fps;
553	730	}
554	731
555	732	mutex_unlock(&sc3336->mutex);
..	..	@@ -642,18 +819,20 @@
642	819	struct sc3336 *sc3336 = to_sc3336(sd);
643	820	const struct sc3336_mode *mode = sc3336->cur_mode;
644	821
645		- mutex_lock(&sc3336->mutex);
646		- fi->interval = mode->max_fps;
647		- mutex_unlock(&sc3336->mutex);
648		-
	822	+ if (sc3336->streaming)
	823	+ fi->interval = sc3336->cur_fps;
	824	+ else
	825	+ fi->interval = mode->max_fps;
649	826	return 0;
650	827	}
651	828
652	829	static int sc3336_g_mbus_config(struct v4l2_subdev *sd,
	830	+ unsigned int pad_id,
653	831	struct v4l2_mbus_config *config)
654	832	{
655	833	struct sc3336 *sc3336 = to_sc3336(sd);
656	834	const struct sc3336_mode *mode = sc3336->cur_mode;
	835	+
657	836	u32 val = 1 << (SC3336_LANES - 1) \|
658	837	V4L2_MBUS_CSI2_CHANNEL_0 \|
659	838	V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
..	..	@@ -663,7 +842,7 @@
663	842	if (mode->hdr_mode == HDR_X3)
664	843	val \|= V4L2_MBUS_CSI2_CHANNEL_2;
665	844
666		- config->type = V4L2_MBUS_CSI2;
	845	+ config->type = V4L2_MBUS_CSI2_DPHY;
667	846	config->flags = val;
668	847
669	848	return 0;
..	..	@@ -719,6 +898,7 @@
719	898	__v4l2_ctrl_modify_range(sc3336->hblank, w, w, 1, w);
720	899	__v4l2_ctrl_modify_range(sc3336->vblank, h,
721	900	SC3336_VTS_MAX - sc3336->cur_mode->height, 1, h);
	901	+ sc3336->cur_fps = sc3336->cur_mode->max_fps;
722	902	}
723	903	break;
724	904	case PREISP_CMD_SET_HDRAE_EXP:
..	..	@@ -830,25 +1010,39 @@
830	1010	{
831	1011	int ret;
832	1012
833		- ret = sc3336_write_array(sc3336->client, sc3336->cur_mode->reg_list);
834		- if (ret)
835		- return ret;
836		-
837		- /* In case these controls are set before streaming */
838		- ret = __v4l2_ctrl_handler_setup(&sc3336->ctrl_handler);
839		- if (ret)
840		- return ret;
841		-
842		- return sc3336_write_reg(sc3336->client, SC3336_REG_CTRL_MODE,
	1013	+ if (!sc3336->is_thunderboot) {
	1014	+ ret = sc3336_write_array(sc3336->client, sc3336->cur_mode->reg_list);
	1015	+ if (ret)
	1016	+ return ret;
	1017	+ /* In case these controls are set before streaming */
	1018	+ ret = __v4l2_ctrl_handler_setup(&sc3336->ctrl_handler);
	1019	+ if (ret)
	1020	+ return ret;
	1021	+ if (sc3336->has_init_exp && sc3336->cur_mode->hdr_mode != NO_HDR) {
	1022	+ ret = sc3336_ioctl(&sc3336->subdev, PREISP_CMD_SET_HDRAE_EXP,
	1023	+ &sc3336->init_hdrae_exp);
	1024	+ if (ret) {
	1025	+ dev_err(&sc3336->client->dev,
	1026	+ "init exp fail in hdr mode\n");
	1027	+ return ret;
	1028	+ }
	1029	+ }
	1030	+ }
	1031	+ ret = sc3336_write_reg(sc3336->client, SC3336_REG_CTRL_MODE,
843	1032	SC3336_REG_VALUE_08BIT, SC3336_MODE_STREAMING);
	1033	+ return ret;
844	1034	}
845	1035
846	1036	static int __sc3336_stop_stream(struct sc3336 *sc3336)
847	1037	{
	1038	+ sc3336->has_init_exp = false;
	1039	+ if (sc3336->is_thunderboot)
	1040	+ sc3336->is_first_streamoff = true;
848	1041	return sc3336_write_reg(sc3336->client, SC3336_REG_CTRL_MODE,
849	1042	SC3336_REG_VALUE_08BIT, SC3336_MODE_SW_STANDBY);
850	1043	}
851	1044
	1045	+static int __sc3336_power_on(struct sc3336 *sc3336);
852	1046	static int sc3336_s_stream(struct v4l2_subdev *sd, int on)
853	1047	{
854	1048	struct sc3336 *sc3336 = to_sc3336(sd);
..	..	@@ -859,14 +1053,16 @@
859	1053	on = !!on;
860	1054	if (on == sc3336->streaming)
861	1055	goto unlock_and_return;
862		-
863	1056	if (on) {
	1057	+ if (sc3336->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
	1058	+ sc3336->is_thunderboot = false;
	1059	+ __sc3336_power_on(sc3336);
	1060	+ }
864	1061	ret = pm_runtime_get_sync(&client->dev);
865	1062	if (ret < 0) {
866	1063	pm_runtime_put_noidle(&client->dev);
867	1064	goto unlock_and_return;
868	1065	}
869		-
870	1066	ret = __sc3336_start_stream(sc3336);
871	1067	if (ret) {
872	1068	v4l2_err(sd, "start stream failed while write regs\n");
..	..	@@ -879,10 +1075,8 @@
879	1075	}
880	1076
881	1077	sc3336->streaming = on;
882		-
883	1078	unlock_and_return:
884	1079	mutex_unlock(&sc3336->mutex);
885		-
886	1080	return ret;
887	1081	}
888	1082
..	..	@@ -905,11 +1099,13 @@
905	1099	goto unlock_and_return;
906	1100	}
907	1101
908		- ret = sc3336_write_array(sc3336->client, sc3336_global_regs);
909		- if (ret) {
910		- v4l2_err(sd, "could not set init registers\n");
911		- pm_runtime_put_noidle(&client->dev);
912		- goto unlock_and_return;
	1102	+ if (!sc3336->is_thunderboot) {
	1103	+ ret = sc3336_write_array(sc3336->client, sc3336_global_regs);
	1104	+ if (ret) {
	1105	+ v4l2_err(sd, "could not set init registers\n");
	1106	+ pm_runtime_put_noidle(&client->dev);
	1107	+ goto unlock_and_return;
	1108	+ }
913	1109	}
914	1110
915	1111	sc3336->power_on = true;
..	..	@@ -925,9 +1121,9 @@
925	1121	}
926	1122
927	1123	/* Calculate the delay in us by clock rate and clock cycles */
928		-static inline u32 sc3336_cal_delay(u32 cycles)
	1124	+static inline u32 sc3336_cal_delay(u32 cycles, struct sc3336 *sc3336)
929	1125	{
930		- return DIV_ROUND_UP(cycles, SC3336_XVCLK_FREQ / 1000 / 1000);
	1126	+ return DIV_ROUND_UP(cycles, sc3336->cur_mode->xvclk_freq / 1000 / 1000);
931	1127	}
932	1128
933	1129	static int __sc3336_power_on(struct sc3336 *sc3336)
..	..	@@ -942,16 +1138,21 @@
942	1138	if (ret < 0)
943	1139	dev_err(dev, "could not set pins\n");
944	1140	}
945		- ret = clk_set_rate(sc3336->xvclk, SC3336_XVCLK_FREQ);
	1141	+ ret = clk_set_rate(sc3336->xvclk, sc3336->cur_mode->xvclk_freq);
946	1142	if (ret < 0)
947		- dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
948		- if (clk_get_rate(sc3336->xvclk) != SC3336_XVCLK_FREQ)
949		- dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
	1143	+ dev_warn(dev, "Failed to set xvclk rate (%dHz)\n", sc3336->cur_mode->xvclk_freq);
	1144	+ if (clk_get_rate(sc3336->xvclk) != sc3336->cur_mode->xvclk_freq)
	1145	+ dev_warn(dev, "xvclk mismatched, modes are based on %dHz\n",
	1146	+ sc3336->cur_mode->xvclk_freq);
950	1147	ret = clk_prepare_enable(sc3336->xvclk);
951	1148	if (ret < 0) {
952	1149	dev_err(dev, "Failed to enable xvclk\n");
953	1150	return ret;
954	1151	}
	1152	+
	1153	+ if (sc3336->is_thunderboot)
	1154	+ return 0;
	1155	+
955	1156	if (!IS_ERR(sc3336->reset_gpio))
956	1157	gpiod_set_value_cansleep(sc3336->reset_gpio, 0);
957	1158
..	..	@@ -965,6 +1166,7 @@
965	1166	gpiod_set_value_cansleep(sc3336->reset_gpio, 1);
966	1167
967	1168	usleep_range(500, 1000);
	1169	+
968	1170	if (!IS_ERR(sc3336->pwdn_gpio))
969	1171	gpiod_set_value_cansleep(sc3336->pwdn_gpio, 1);
970	1172
..	..	@@ -974,7 +1176,7 @@
974	1176	usleep_range(12000, 16000);
975	1177
976	1178	/* 8192 cycles prior to first SCCB transaction */
977		- delay_us = sc3336_cal_delay(8192);
	1179	+ delay_us = sc3336_cal_delay(8192, sc3336);
978	1180	usleep_range(delay_us, delay_us * 2);
979	1181
980	1182	return 0;
..	..	@@ -990,6 +1192,16 @@
990	1192	int ret;
991	1193	struct device *dev = &sc3336->client->dev;
992	1194
	1195	+ clk_disable_unprepare(sc3336->xvclk);
	1196	+ if (sc3336->is_thunderboot) {
	1197	+ if (sc3336->is_first_streamoff) {
	1198	+ sc3336->is_thunderboot = false;
	1199	+ sc3336->is_first_streamoff = false;
	1200	+ } else {
	1201	+ return;
	1202	+ }
	1203	+ }
	1204	+
993	1205	if (!IS_ERR(sc3336->pwdn_gpio))
994	1206	gpiod_set_value_cansleep(sc3336->pwdn_gpio, 0);
995	1207	clk_disable_unprepare(sc3336->xvclk);
..	..	@@ -1004,7 +1216,7 @@
1004	1216	regulator_bulk_disable(SC3336_NUM_SUPPLIES, sc3336->supplies);
1005	1217	}
1006	1218
1007		-static int sc3336_runtime_resume(struct device *dev)
	1219	+static int __maybe_unused sc3336_runtime_resume(struct device *dev)
1008	1220	{
1009	1221	struct i2c_client *client = to_i2c_client(dev);
1010	1222	struct v4l2_subdev *sd = i2c_get_clientdata(client);
..	..	@@ -1013,7 +1225,7 @@
1013	1225	return __sc3336_power_on(sc3336);
1014	1226	}
1015	1227
1016		-static int sc3336_runtime_suspend(struct device *dev)
	1228	+static int __maybe_unused sc3336_runtime_suspend(struct device *dev)
1017	1229	{
1018	1230	struct i2c_client *client = to_i2c_client(dev);
1019	1231	struct v4l2_subdev *sd = i2c_get_clientdata(client);
..	..	@@ -1061,36 +1273,6 @@
1061	1273	return 0;
1062	1274	}
1063	1275
1064		-#define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1065		-#define DST_WIDTH 1920
1066		-#define DST_HEIGHT 1080
1067		-
1068		-/*
1069		- * The resolution of the driver configuration needs to be exactly
1070		- * the same as the current output resolution of the sensor,
1071		- * the input width of the isp needs to be 16 aligned,
1072		- * the input height of the isp needs to be 8 aligned.
1073		- * Can be cropped to standard resolution by this function,
1074		- * otherwise it will crop out strange resolution according
1075		- * to the alignment rules.
1076		- */
1077		-
1078		-static int sc3336_get_selection(struct v4l2_subdev *sd,
1079		- struct v4l2_subdev_pad_config *cfg,
1080		- struct v4l2_subdev_selection *sel)
1081		-{
1082		- struct sc3336 *sc3336 = to_sc3336(sd);
1083		-
1084		- if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1085		- sel->r.left = CROP_START(sc3336->cur_mode->width, DST_WIDTH);
1086		- sel->r.width = DST_WIDTH;
1087		- sel->r.top = CROP_START(sc3336->cur_mode->height, DST_HEIGHT);
1088		- sel->r.height = DST_HEIGHT;
1089		- return 0;
1090		- }
1091		- return -EINVAL;
1092		-}
1093		-
1094	1276	static const struct dev_pm_ops sc3336_pm_ops = {
1095	1277	SET_RUNTIME_PM_OPS(sc3336_runtime_suspend,
1096	1278	sc3336_runtime_resume, NULL)
..	..	@@ -1113,7 +1295,6 @@
1113	1295	static const struct v4l2_subdev_video_ops sc3336_video_ops = {
1114	1296	.s_stream = sc3336_s_stream,
1115	1297	.g_frame_interval = sc3336_g_frame_interval,
1116		- .g_mbus_config = sc3336_g_mbus_config,
1117	1298	};
1118	1299
1119	1300	static const struct v4l2_subdev_pad_ops sc3336_pad_ops = {
..	..	@@ -1122,7 +1303,7 @@
1122	1303	.enum_frame_interval = sc3336_enum_frame_interval,
1123	1304	.get_fmt = sc3336_get_fmt,
1124	1305	.set_fmt = sc3336_set_fmt,
1125		- .get_selection = sc3336_get_selection,
	1306	+ .get_mbus_config = sc3336_g_mbus_config,
1126	1307	};
1127	1308
1128	1309	static const struct v4l2_subdev_ops sc3336_subdev_ops = {
..	..	@@ -1130,6 +1311,14 @@
1130	1311	.video = &sc3336_video_ops,
1131	1312	.pad = &sc3336_pad_ops,
1132	1313	};
	1314	+
	1315	+static void sc3336_modify_fps_info(struct sc3336 *sc3336)
	1316	+{
	1317	+ const struct sc3336_mode *mode = sc3336->cur_mode;
	1318	+
	1319	+ sc3336->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
	1320	+ sc3336->cur_vts;
	1321	+}
1133	1322
1134	1323	static int sc3336_set_ctrl(struct v4l2_ctrl *ctrl)
1135	1324	{
..	..	@@ -1193,6 +1382,7 @@
1193	1382	(ctrl->val + sc3336->cur_mode->height)
1194	1383	& 0xff);
1195	1384	sc3336->cur_vts = ctrl->val + sc3336->cur_mode->height;
	1385	+ sc3336_modify_fps_info(sc3336);
1196	1386	break;
1197	1387	case V4L2_CID_TEST_PATTERN:
1198	1388	ret = sc3336_enable_test_pattern(sc3336, ctrl->val);
..	..	@@ -1230,10 +1420,11 @@
1230	1420	{
1231	1421	const struct sc3336_mode *mode;
1232	1422	struct v4l2_ctrl_handler *handler;
1233		- struct v4l2_ctrl *ctrl;
1234	1423	s64 exposure_max, vblank_def;
1235	1424	u32 h_blank;
1236	1425	int ret;
	1426	+ u64 dst_link_freq = 0;
	1427	+ u64 dst_pixel_rate = 0;
1237	1428
1238	1429	handler = &sc3336->ctrl_handler;
1239	1430	mode = sc3336->cur_mode;
..	..	@@ -1242,13 +1433,19 @@
1242	1433	return ret;
1243	1434	handler->lock = &sc3336->mutex;
1244	1435
1245		- ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1246		- 0, 0, link_freq_menu_items);
1247		- if (ctrl)
1248		- ctrl->flags \|= V4L2_CTRL_FLAG_READ_ONLY;
	1436	+ sc3336->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
	1437	+ V4L2_CID_LINK_FREQ,
	1438	+ ARRAY_SIZE(link_freq_menu_items) - 1, 0, link_freq_menu_items);
	1439	+ if (sc3336->link_freq)
	1440	+ sc3336->link_freq->flags \|= V4L2_CTRL_FLAG_READ_ONLY;
1249	1441
1250		- v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1251		- 0, PIXEL_RATE_WITH_255M_10BIT, 1, PIXEL_RATE_WITH_255M_10BIT);
	1442	+ dst_link_freq = mode->link_freq_idx;
	1443	+ dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
	1444	+ SC3336_BITS_PER_SAMPLE * 2 * SC3336_LANES;
	1445	+ sc3336->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
	1446	+ 0, PIXEL_RATE_WITH_255M_10BIT, 1, dst_pixel_rate);
	1447	+
	1448	+ __v4l2_ctrl_s_ctrl(sc3336->link_freq, dst_link_freq);
1252	1449
1253	1450	h_blank = mode->hts_def - mode->width;
1254	1451	sc3336->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
..	..	@@ -1286,6 +1483,8 @@
1286	1483	}
1287	1484
1288	1485	sc3336->subdev.ctrl_handler = handler;
	1486	+ sc3336->has_init_exp = false;
	1487	+ sc3336->cur_fps = mode->max_fps;
1289	1488
1290	1489	return 0;
1291	1490
..	..	@@ -1301,6 +1500,11 @@
1301	1500	struct device *dev = &sc3336->client->dev;
1302	1501	u32 id = 0;
1303	1502	int ret;
	1503	+
	1504	+ if (sc3336->is_thunderboot) {
	1505	+ dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
	1506	+ return 0;
	1507	+ }
1304	1508
1305	1509	ret = sc3336_read_reg(client, SC3336_REG_CHIP_ID,
1306	1510	SC3336_REG_VALUE_16BIT, &id);
..	..	@@ -1335,6 +1539,7 @@
1335	1539	struct v4l2_subdev *sd;
1336	1540	char facing[2];
1337	1541	int ret;
	1542	+ int i, hdr_mode = 0;
1338	1543
1339	1544	dev_info(dev, "driver version: %02x.%02x.%02x",
1340	1545	DRIVER_VERSION >> 16,
..	..	@@ -1358,8 +1563,17 @@
1358	1563	return -EINVAL;
1359	1564	}
1360	1565
	1566	+ sc3336->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
	1567	+
1361	1568	sc3336->client = client;
1362		- sc3336->cur_mode = &supported_modes[0];
	1569	+ for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
	1570	+ if (hdr_mode == supported_modes[i].hdr_mode) {
	1571	+ sc3336->cur_mode = &supported_modes[i];
	1572	+ break;
	1573	+ }
	1574	+ }
	1575	+ if (i == ARRAY_SIZE(supported_modes))
	1576	+ sc3336->cur_mode = &supported_modes[0];
1363	1577
1364	1578	sc3336->xvclk = devm_clk_get(dev, "xvclk");
1365	1579	if (IS_ERR(sc3336->xvclk)) {
..	..	@@ -1367,11 +1581,17 @@
1367	1581	return -EINVAL;
1368	1582	}
1369	1583
1370		- sc3336->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
	1584	+ if (!sc3336->is_thunderboot)
	1585	+ sc3336->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
	1586	+ else
	1587	+ sc3336->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1371	1588	if (IS_ERR(sc3336->reset_gpio))
1372	1589	dev_warn(dev, "Failed to get reset-gpios\n");
1373	1590
1374		- sc3336->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
	1591	+ if (!sc3336->is_thunderboot)
	1592	+ sc3336->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
	1593	+ else
	1594	+ sc3336->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
1375	1595	if (IS_ERR(sc3336->pwdn_gpio))
1376	1596	dev_warn(dev, "Failed to get pwdn-gpios\n");
1377	1597
..	..	@@ -1516,8 +1736,12 @@
1516	1736	i2c_del_driver(&sc3336_i2c_driver);
1517	1737	}
1518	1738
	1739	+#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
	1740	+subsys_initcall(sensor_mod_init);
	1741	+#else
1519	1742	device_initcall_sync(sensor_mod_init);
	1743	+#endif
1520	1744	module_exit(sensor_mod_exit);
1521	1745
1522	1746	MODULE_DESCRIPTION("smartsens sc3336 sensor driver");
1523		-MODULE_LICENSE("GPL");
	1747	+MODULE_LICENSE("GPL v2");