.. | .. |
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106 | 106 | #define MIRROR_BIT_MASK BIT(2) |
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107 | 107 | #define FLIP_BIT_MASK BIT(2) |
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108 | 108 | |
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109 | | -enum os05a20_max_pad { |
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110 | | - PAD0, |
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111 | | - PAD1, |
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112 | | - PAD2, |
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113 | | - PAD3, |
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114 | | - PAD_MAX, |
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115 | | -}; |
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116 | | - |
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117 | 109 | struct regval { |
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118 | 110 | u16 addr; |
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119 | 111 | u8 val; |
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.. | .. |
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682 | 674 | .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1, |
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683 | 675 | .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0 |
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684 | 676 | .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1, |
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685 | | - .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2 //Á½Õë¹Ì¶¨¶ÌÖ¡ |
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| 677 | + .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2 |
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686 | 678 | }, |
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687 | 679 | }; |
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688 | 680 | |
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.. | .. |
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928 | 920 | struct os05a20 *os05a20 = to_os05a20(sd); |
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929 | 921 | const struct os05a20_mode *mode = os05a20->cur_mode; |
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930 | 922 | |
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931 | | - mutex_lock(&os05a20->mutex); |
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932 | 923 | fi->interval = mode->max_fps; |
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933 | | - mutex_unlock(&os05a20->mutex); |
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934 | 924 | |
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935 | 925 | return 0; |
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936 | 926 | } |
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937 | 927 | |
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938 | | -static int os05a20_g_mbus_config(struct v4l2_subdev *sd, |
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| 928 | +static int os05a20_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id, |
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939 | 929 | struct v4l2_mbus_config *config) |
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940 | 930 | { |
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941 | 931 | struct os05a20 *os05a20 = to_os05a20(sd); |
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.. | .. |
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952 | 942 | V4L2_MBUS_CSI2_CONTINUOUS_CLOCK | |
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953 | 943 | V4L2_MBUS_CSI2_CHANNEL_1; |
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954 | 944 | |
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955 | | - config->type = V4L2_MBUS_CSI2; |
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| 945 | + config->type = V4L2_MBUS_CSI2_DPHY; |
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956 | 946 | config->flags = val; |
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957 | 947 | |
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958 | 948 | return 0; |
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.. | .. |
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1526 | 1516 | static const struct v4l2_subdev_video_ops os05a20_video_ops = { |
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1527 | 1517 | .s_stream = os05a20_s_stream, |
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1528 | 1518 | .g_frame_interval = os05a20_g_frame_interval, |
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1529 | | - .g_mbus_config = os05a20_g_mbus_config, |
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1530 | 1519 | }; |
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1531 | 1520 | |
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1532 | 1521 | static const struct v4l2_subdev_pad_ops os05a20_pad_ops = { |
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.. | .. |
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1535 | 1524 | .enum_frame_interval = os05a20_enum_frame_interval, |
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1536 | 1525 | .get_fmt = os05a20_get_fmt, |
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1537 | 1526 | .set_fmt = os05a20_set_fmt, |
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| 1527 | + .get_mbus_config = os05a20_g_mbus_config, |
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1538 | 1528 | }; |
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1539 | 1529 | |
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1540 | 1530 | static const struct v4l2_subdev_ops os05a20_subdev_ops = { |
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.. | .. |
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1573 | 1563 | switch (ctrl->id) { |
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1574 | 1564 | case V4L2_CID_EXPOSURE: |
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1575 | 1565 | if (os05a20->cur_mode->hdr_mode != NO_HDR) |
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1576 | | - return 0; |
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| 1566 | + goto ctrl_end; |
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1577 | 1567 | ret = os05a20_write_reg(os05a20->client, |
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1578 | 1568 | OS05A20_REG_EXP_LONG_H, |
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1579 | 1569 | OS05A20_REG_VALUE_16BIT, |
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.. | .. |
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1583 | 1573 | break; |
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1584 | 1574 | case V4L2_CID_ANALOGUE_GAIN: |
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1585 | 1575 | if (os05a20->cur_mode->hdr_mode != NO_HDR) |
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1586 | | - return 0; |
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| 1576 | + goto ctrl_end; |
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1587 | 1577 | if (ctrl->val > 1984) {// >15.5x |
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1588 | 1578 | dgain = ctrl->val * 10 / 155; |
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1589 | 1579 | again = 1984; |
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.. | .. |
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1642 | 1632 | break; |
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1643 | 1633 | } |
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1644 | 1634 | |
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| 1635 | +ctrl_end: |
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1645 | 1636 | pm_runtime_put(&client->dev); |
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1646 | 1637 | |
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1647 | 1638 | return ret; |
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