修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/drivers/gpu/drm/rockchip/ebc-dev/tcon/ebc_tcon.c
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@@ -163,37 +163,23 @@
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 static int tcon_enable(struct ebc_tcon *tcon, struct ebc_panel *panel)
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 {
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-	u32 width, height, vir_width, vir_height;
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-
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 	clk_prepare_enable(tcon->hclk);
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 	clk_prepare_enable(tcon->dclk);
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 	pm_runtime_get_sync(tcon->dev);
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-	if (panel->rearrange) {
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-		width = panel->width * 2;
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-		height = panel->height / 2;
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-		vir_width = panel->vir_width * 2;
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-		vir_height = panel->vir_height / 2;
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-	} else {
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-		width = panel->width;
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-		height = panel->height;
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-		vir_width = panel->vir_width;
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-		vir_height = panel->vir_height;
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-	}
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-
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 	/* panel timing and win info config */
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 	tcon_write(tcon, EBC_DSP_HTIMING0,
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-				DSP_HTOTAL(panel->lsl + panel->lbl + panel->ldl + panel->lel) | DSP_HS_END(panel->lsl));
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+				DSP_HTOTAL(panel->lsl + panel->lbl + panel->ldl + panel->lel) | DSP_HS_END(panel->lsl + 2));
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 	tcon_write(tcon, EBC_DSP_HTIMING1,
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 				DSP_HACT_END(panel->lsl + panel->lbl + panel->ldl) | DSP_HACT_ST(panel->lsl + panel->lbl - 1));
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 	tcon_write(tcon, EBC_DSP_VTIMING0,
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 				DSP_VTOTAL(panel->fsl + panel->fbl + panel->fdl + panel->fel) | DSP_VS_END(panel->fsl));
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 	tcon_write(tcon, EBC_DSP_VTIMING1,
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 				DSP_VACT_END(panel->fsl + panel->fbl + panel->fdl) | DSP_VACT_ST(panel->fsl + panel->fbl));
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-	tcon_write(tcon, EBC_DSP_ACT_INFO, DSP_HEIGHT(height) | DSP_WIDTH(width));
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-	tcon_write(tcon, EBC_WIN_VIR, WIN_VIR_HEIGHT(vir_height) | WIN_VIR_WIDTH(vir_width));
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-	tcon_write(tcon, EBC_WIN_ACT, WIN_ACT_HEIGHT(height) | WIN_ACT_WIDTH(width));
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-	tcon_write(tcon, EBC_WIN_DSP, WIN_DSP_HEIGHT(height) | WIN_DSP_WIDTH(width));
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+	tcon_write(tcon, EBC_DSP_ACT_INFO, DSP_HEIGHT(panel->height) | DSP_WIDTH(panel->width));
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+	tcon_write(tcon, EBC_WIN_VIR, WIN_VIR_HEIGHT(panel->vir_height) | WIN_VIR_WIDTH(panel->vir_width));
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+	tcon_write(tcon, EBC_WIN_ACT, WIN_ACT_HEIGHT(panel->height) | WIN_ACT_WIDTH(panel->width));
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+	tcon_write(tcon, EBC_WIN_DSP, WIN_DSP_HEIGHT(panel->height) | WIN_DSP_WIDTH(panel->width));
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 	tcon_write(tcon, EBC_WIN_DSP_ST, WIN_DSP_YST(panel->fsl + panel->fbl) | WIN_DSP_XST(panel->lsl + panel->lbl));
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 	/* win2 fifo is 512x128, win fifo is 256x128, we set fifo almost value (fifo_size - 16)
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@@ -223,7 +209,7 @@
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 				| EPD_SDSHR(1));
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 	tcon_write(tcon, EBC_DSP_START, DSP_SDCE_WIDTH(panel->ldl) | SW_BURST_CTRL);
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 	tcon_write(tcon, EBC_DSP_CTRL,
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-				DSP_SWAP_MODE(panel->panel_16bit ? 2 : 3) | DSP_VCOM_MODE(1) | DSP_SDCLK_DIV(0));
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+				DSP_SWAP_MODE(panel->panel_16bit ? 2 : 3) | DSP_VCOM_MODE(1) | DSP_SDCLK_DIV(panel->panel_16bit ? 7 : 3));
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 	tcon_cfg_done(tcon);
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 	enable_irq(tcon->irq);
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@@ -307,7 +293,7 @@
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 	intr_status = tcon_read(tcon, EBC_INT_STATUS);
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 	if (intr_status & DSP_END_INT) {
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-		tcon_update_bits(tcon, EBC_INT_STATUS, DSP_END_INT_CLR | LINE_FLAG_INT_CLR, DSP_END_INT_CLR | LINE_FLAG_INT_CLR);
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+		tcon_update_bits(tcon, EBC_INT_STATUS, DSP_END_INT_CLR, DSP_END_INT_CLR);
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 		if (tcon->dsp_end_callback)
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 			tcon->dsp_end_callback();