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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
....@@ -1,14 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 and
6
- * only version 2 as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
124  */
135 
146 #include <linux/platform_device.h>
....@@ -153,7 +145,7 @@
153145 {
154146 	const unsigned long bit_rate = clk_req->bitclk_rate;
155147 	const unsigned long esc_rate = clk_req->escclk_rate;
156
-	s32 ui, ui_x8, lpx;
148
+	s32 ui, ui_x8;
157149 	s32 tmax, tmin;
158150 	s32 pcnt0 = 50;
159151 	s32 pcnt1 = 50;
....@@ -183,7 +175,6 @@
183175 
184176 	ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
185177 	ui_x8 = ui << 3;
186
-	lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
187178 
188179 	temp = S_DIV_ROUND_UP(38 * coeff - val_ckln * ui, ui_x8);
189180 	tmin = max_t(s32, temp, 0);
....@@ -270,7 +261,7 @@
270261 {
271262 	const unsigned long bit_rate = clk_req->bitclk_rate;
272263 	const unsigned long esc_rate = clk_req->escclk_rate;
273
-	s32 ui, ui_x8, lpx;
264
+	s32 ui, ui_x8;
274265 	s32 tmax, tmin;
275266 	s32 pcnt0 = 50;
276267 	s32 pcnt1 = 50;
....@@ -292,7 +283,6 @@
292283 
293284 	ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
294285 	ui_x8 = ui << 3;
295
-	lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
296286 
297287 	temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
298288 	tmin = max_t(s32, temp, 0);
....@@ -355,7 +345,7 @@
355345 	} else {
356346 		timing->shared_timings.clk_pre =
357347 			linear_inter(tmax, tmin, pcnt2, 0, false);
358
-			timing->shared_timings.clk_pre_inc_by_2 = 0;
348
+		timing->shared_timings.clk_pre_inc_by_2 = 0;
359349 	}
360350 
361351 	timing->ta_go = 3;
....@@ -370,6 +360,102 @@
370360 		timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
371361 		timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
372362 		timing->hs_prep_dly_ckln);
363
+
364
+	return 0;
365
+}
366
+
367
+int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
368
+	struct msm_dsi_phy_clk_request *clk_req)
369
+{
370
+	const unsigned long bit_rate = clk_req->bitclk_rate;
371
+	const unsigned long esc_rate = clk_req->escclk_rate;
372
+	s32 ui, ui_x8;
373
+	s32 tmax, tmin;
374
+	s32 pcnt_clk_prep = 50;
375
+	s32 pcnt_clk_zero = 2;
376
+	s32 pcnt_clk_trail = 30;
377
+	s32 pcnt_hs_prep = 50;
378
+	s32 pcnt_hs_zero = 10;
379
+	s32 pcnt_hs_trail = 30;
380
+	s32 pcnt_hs_exit = 10;
381
+	s32 coeff = 1000; /* Precision, should avoid overflow */
382
+	s32 hb_en;
383
+	s32 temp;
384
+
385
+	if (!bit_rate || !esc_rate)
386
+		return -EINVAL;
387
+
388
+	hb_en = 0;
389
+
390
+	ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
391
+	ui_x8 = ui << 3;
392
+
393
+	/* TODO: verify these calculations against latest downstream driver
394
+	 * everything except clk_post/clk_pre uses calculations from v3 based
395
+	 * on the downstream driver having the same calculations for v3 and v4
396
+	 */
397
+
398
+	temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
399
+	tmin = max_t(s32, temp, 0);
400
+	temp = (95 * coeff) / ui_x8;
401
+	tmax = max_t(s32, temp, 0);
402
+	timing->clk_prepare = linear_inter(tmax, tmin, pcnt_clk_prep, 0, false);
403
+
404
+	temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
405
+	tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
406
+	tmax = (tmin > 255) ? 511 : 255;
407
+	timing->clk_zero = linear_inter(tmax, tmin, pcnt_clk_zero, 0, false);
408
+
409
+	tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
410
+	temp = 105 * coeff + 12 * ui - 20 * coeff;
411
+	tmax = (temp + 3 * ui) / ui_x8;
412
+	timing->clk_trail = linear_inter(tmax, tmin, pcnt_clk_trail, 0, false);
413
+
414
+	temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
415
+	tmin = max_t(s32, temp, 0);
416
+	temp = (85 * coeff + 6 * ui) / ui_x8;
417
+	tmax = max_t(s32, temp, 0);
418
+	timing->hs_prepare = linear_inter(tmax, tmin, pcnt_hs_prep, 0, false);
419
+
420
+	temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
421
+	tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
422
+	tmax = 255;
423
+	timing->hs_zero = linear_inter(tmax, tmin, pcnt_hs_zero, 0, false);
424
+
425
+	tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
426
+	temp = 105 * coeff + 12 * ui - 20 * coeff;
427
+	tmax = (temp / ui_x8) - 1;
428
+	timing->hs_trail = linear_inter(tmax, tmin, pcnt_hs_trail, 0, false);
429
+
430
+	temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
431
+	timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
432
+
433
+	tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
434
+	tmax = 255;
435
+	timing->hs_exit = linear_inter(tmax, tmin, pcnt_hs_exit, 0, false);
436
+
437
+	/* recommended min
438
+	 * = roundup((mipi_min_ns + t_hs_trail_ns)/(16*bit_clk_ns), 0) - 1
439
+	 */
440
+	temp = 60 * coeff + 52 * ui + + (timing->hs_trail + 1) * ui_x8;
441
+	tmin = DIV_ROUND_UP(temp, 16 * ui) - 1;
442
+	tmax = 255;
443
+	timing->shared_timings.clk_post = linear_inter(tmax, tmin, 5, 0, false);
444
+
445
+	/* recommended min
446
+	 * val1 = (tlpx_ns + clk_prepare_ns + clk_zero_ns + hs_rqst_ns)
447
+	 * val2 = (16 * bit_clk_ns)
448
+	 * final = roundup(val1/val2, 0) - 1
449
+	 */
450
+	temp = 52 * coeff + (timing->clk_prepare + timing->clk_zero + 1) * ui_x8 + 54 * coeff;
451
+	tmin = DIV_ROUND_UP(temp, 16 * ui) - 1;
452
+	tmax = 255;
453
+	timing->shared_timings.clk_pre = DIV_ROUND_UP((tmax - tmin) * 125, 10000) + tmin;
454
+
455
+	DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
456
+		timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
457
+		timing->clk_zero, timing->clk_trail, timing->clk_prepare, timing->hs_exit,
458
+		timing->hs_zero, timing->hs_prepare, timing->hs_trail, timing->hs_rqst);
373459 
374460 	return 0;
375461 }
....@@ -404,8 +490,12 @@
404490 
405491 	ret = devm_regulator_bulk_get(dev, num, s);
406492 	if (ret < 0) {
407
-		dev_err(dev, "%s: failed to init regulator, ret=%d\n",
408
-						__func__, ret);
493
+		if (ret != -EPROBE_DEFER) {
494
+			DRM_DEV_ERROR(dev,
495
+				      "%s: failed to init regulator, ret=%d\n",
496
+				      __func__, ret);
497
+		}
498
+
409499 		return ret;
410500 	}
411501 
....@@ -441,7 +531,7 @@
441531 			ret = regulator_set_load(s[i].consumer,
442532 							regs[i].enable_load);
443533 			if (ret < 0) {
444
-				dev_err(dev,
534
+				DRM_DEV_ERROR(dev,
445535 					"regulator %d set op mode failed, %d\n",
446536 					i, ret);
447537 				goto fail;
....@@ -451,7 +541,7 @@
451541 
452542 	ret = regulator_bulk_enable(num, s);
453543 	if (ret < 0) {
454
-		dev_err(dev, "regulator enable failed, %d\n", ret);
544
+		DRM_DEV_ERROR(dev, "regulator enable failed, %d\n", ret);
455545 		goto fail;
456546 	}
457547 
....@@ -472,7 +562,7 @@
472562 
473563 	ret = clk_prepare_enable(phy->ahb_clk);
474564 	if (ret) {
475
-		dev_err(dev, "%s: can't enable ahb clk, %d\n", __func__, ret);
565
+		DRM_DEV_ERROR(dev, "%s: can't enable ahb clk, %d\n", __func__, ret);
476566 		pm_runtime_put_sync(dev);
477567 	}
478568 
....@@ -489,6 +579,8 @@
489579 #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
490580 	{ .compatible = "qcom,dsi-phy-28nm-hpm",
491581 	  .data = &dsi_phy_28nm_hpm_cfgs },
582
+	{ .compatible = "qcom,dsi-phy-28nm-hpm-fam-b",
583
+	  .data = &dsi_phy_28nm_hpm_famb_cfgs },
492584 	{ .compatible = "qcom,dsi-phy-28nm-lp",
493585 	  .data = &dsi_phy_28nm_lp_cfgs },
494586 #endif
....@@ -503,10 +595,20 @@
503595 #ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
504596 	{ .compatible = "qcom,dsi-phy-14nm",
505597 	  .data = &dsi_phy_14nm_cfgs },
598
+	{ .compatible = "qcom,dsi-phy-14nm-660",
599
+	  .data = &dsi_phy_14nm_660_cfgs },
506600 #endif
507601 #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
508602 	{ .compatible = "qcom,dsi-phy-10nm",
509603 	  .data = &dsi_phy_10nm_cfgs },
604
+	{ .compatible = "qcom,dsi-phy-10nm-8998",
605
+	  .data = &dsi_phy_10nm_8998_cfgs },
606
+#endif
607
+#ifdef CONFIG_DRM_MSM_DSI_7NM_PHY
608
+	{ .compatible = "qcom,dsi-phy-7nm",
609
+	  .data = &dsi_phy_7nm_cfgs },
610
+	{ .compatible = "qcom,dsi-phy-7nm-8150",
611
+	  .data = &dsi_phy_7nm_8150_cfgs },
510612 #endif
511613 	{}
512614 };
....@@ -543,7 +645,7 @@
543645 	phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
544646 				"DSI_PHY_REG");
545647 	if (IS_ERR(phy->reg_base)) {
546
-		dev_err(&pdev->dev, "%s: failed to map phy regulator base\n",
648
+		DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n",
547649 			__func__);
548650 		ret = -ENOMEM;
549651 		goto fail;
....@@ -574,7 +676,7 @@
574676 	phy->id = dsi_phy_get_id(phy);
575677 	if (phy->id < 0) {
576678 		ret = phy->id;
577
-		dev_err(dev, "%s: couldn't identify PHY index, %d\n",
679
+		DRM_DEV_ERROR(dev, "%s: couldn't identify PHY index, %d\n",
578680 			__func__, ret);
579681 		goto fail;
580682 	}
....@@ -584,20 +686,18 @@
584686 
585687 	phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
586688 	if (IS_ERR(phy->base)) {
587
-		dev_err(dev, "%s: failed to map phy base\n", __func__);
689
+		DRM_DEV_ERROR(dev, "%s: failed to map phy base\n", __func__);
588690 		ret = -ENOMEM;
589691 		goto fail;
590692 	}
591693 
592694 	ret = dsi_phy_regulator_init(phy);
593
-	if (ret) {
594
-		dev_err(dev, "%s: failed to init regulator\n", __func__);
695
+	if (ret)
595696 		goto fail;
596
-	}
597697 
598698 	phy->ahb_clk = msm_clk_get(pdev, "iface");
599699 	if (IS_ERR(phy->ahb_clk)) {
600
-		dev_err(dev, "%s: Unable to get ahb clk\n", __func__);
700
+		DRM_DEV_ERROR(dev, "%s: Unable to get ahb clk\n", __func__);
601701 		ret = PTR_ERR(phy->ahb_clk);
602702 		goto fail;
603703 	}
....@@ -616,10 +716,12 @@
616716 		goto fail;
617717 
618718 	phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id);
619
-	if (IS_ERR_OR_NULL(phy->pll))
620
-		dev_info(dev,
719
+	if (IS_ERR_OR_NULL(phy->pll)) {
720
+		DRM_DEV_INFO(dev,
621721 			"%s: pll init failed: %ld, need separate pll clk driver\n",
622722 			__func__, PTR_ERR(phy->pll));
723
+		phy->pll = NULL;
724
+	}
623725 
624726 	dsi_phy_disable_resource(phy);
625727 
....@@ -677,21 +779,21 @@
677779 
678780 	ret = dsi_phy_enable_resource(phy);
679781 	if (ret) {
680
-		dev_err(dev, "%s: resource enable failed, %d\n",
782
+		DRM_DEV_ERROR(dev, "%s: resource enable failed, %d\n",
681783 			__func__, ret);
682784 		goto res_en_fail;
683785 	}
684786 
685787 	ret = dsi_phy_regulator_enable(phy);
686788 	if (ret) {
687
-		dev_err(dev, "%s: regulator enable failed, %d\n",
789
+		DRM_DEV_ERROR(dev, "%s: regulator enable failed, %d\n",
688790 			__func__, ret);
689791 		goto reg_en_fail;
690792 	}
691793 
692794 	ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req);
693795 	if (ret) {
694
-		dev_err(dev, "%s: phy enable failed, %d\n", __func__, ret);
796
+		DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret);
695797 		goto phy_en_fail;
696798 	}
697799 
....@@ -704,7 +806,7 @@
704806 	if (phy->usecase != MSM_DSI_PHY_SLAVE) {
705807 		ret = msm_dsi_pll_restore_state(phy->pll);
706808 		if (ret) {
707
-			dev_err(dev, "%s: failed to restore pll state, %d\n",
809
+			DRM_DEV_ERROR(dev, "%s: failed to restore pll state, %d\n",
708810 				__func__, ret);
709811 			goto pll_restor_fail;
710812 		}