forked from ~ljy/RK356X_SDK_RELEASE
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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/gpu/drm/i915/gvt/mmio.c
....@@ -39,6 +39,7 @@
3939 /**
4040  * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
4141  * @vgpu: a vGPU
42
+ * @gpa: guest physical address
4243  *
4344  * Returns:
4445  * Zero on success, negative error code if failed
....@@ -56,7 +57,7 @@
5657 	(reg >= gvt->device_info.gtt_start_offset \
5758 	 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
5859 
59
-static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
60
+static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
6061 		void *p_data, unsigned int bytes, bool read)
6162 {
6263 	struct intel_gvt *gvt = NULL;
....@@ -98,10 +99,11 @@
9899  * Returns:
99100  * Zero on success, negative error code if failed
100101  */
101
-int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
102
+int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
102103 		void *p_data, unsigned int bytes)
103104 {
104105 	struct intel_gvt *gvt = vgpu->gvt;
106
+	struct drm_i915_private *i915 = gvt->gt->i915;
105107 	unsigned int offset = 0;
106108 	int ret = -EINVAL;
107109 
....@@ -113,15 +115,17 @@
113115 
114116 	offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
115117 
116
-	if (WARN_ON(bytes > 8))
118
+	if (drm_WARN_ON(&i915->drm, bytes > 8))
117119 		goto err;
118120 
119121 	if (reg_is_gtt(gvt, offset)) {
120
-		if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
122
+		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) &&
123
+				!IS_ALIGNED(offset, 8)))
121124 			goto err;
122
-		if (WARN_ON(bytes != 4 && bytes != 8))
125
+		if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))
123126 			goto err;
124
-		if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
127
+		if (drm_WARN_ON(&i915->drm,
128
+				!reg_is_gtt(gvt, offset + bytes - 1)))
125129 			goto err;
126130 
127131 		ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,
....@@ -131,16 +135,16 @@
131135 		goto out;
132136 	}
133137 
134
-	if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
138
+	if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) {
135139 		ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
136140 		goto out;
137141 	}
138142 
139
-	if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1)))
143
+	if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1)))
140144 		goto err;
141145 
142146 	if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
143
-		if (WARN_ON(!IS_ALIGNED(offset, bytes)))
147
+		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes)))
144148 			goto err;
145149 	}
146150 
....@@ -170,10 +174,11 @@
170174  * Returns:
171175  * Zero on success, negative error code if failed
172176  */
173
-int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
177
+int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
174178 		void *p_data, unsigned int bytes)
175179 {
176180 	struct intel_gvt *gvt = vgpu->gvt;
181
+	struct drm_i915_private *i915 = gvt->gt->i915;
177182 	unsigned int offset = 0;
178183 	int ret = -EINVAL;
179184 
....@@ -186,15 +191,17 @@
186191 
187192 	offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
188193 
189
-	if (WARN_ON(bytes > 8))
194
+	if (drm_WARN_ON(&i915->drm, bytes > 8))
190195 		goto err;
191196 
192197 	if (reg_is_gtt(gvt, offset)) {
193
-		if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
198
+		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) &&
199
+				!IS_ALIGNED(offset, 8)))
194200 			goto err;
195
-		if (WARN_ON(bytes != 4 && bytes != 8))
201
+		if (drm_WARN_ON(&i915->drm, bytes != 4 && bytes != 8))
196202 			goto err;
197
-		if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
203
+		if (drm_WARN_ON(&i915->drm,
204
+				!reg_is_gtt(gvt, offset + bytes - 1)))
198205 			goto err;
199206 
200207 		ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,
....@@ -204,7 +211,7 @@
204211 		goto out;
205212 	}
206213 
207
-	if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
214
+	if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) {
208215 		ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
209216 		goto out;
210217 	}
....@@ -228,7 +235,7 @@
228235 /**
229236  * intel_vgpu_reset_mmio - reset virtual MMIO space
230237  * @vgpu: a vGPU
231
- *
238
+ * @dmlr: whether this is device model level reset
232239  */
233240 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
234241 {
....@@ -238,14 +245,16 @@
238245 
239246 	if (dmlr) {
240247 		memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
241
-		memcpy(vgpu->mmio.sreg, mmio, info->mmio_size);
242248 
243249 		vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
244250 
245251 		/* set the bit 0:2(Core C-State ) to C0 */
246252 		vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
247253 
248
-		if (IS_BROXTON(vgpu->gvt->dev_priv)) {
254
+		/* uc reset hw expect GS_MIA_IN_RESET */
255
+		vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
256
+
257
+		if (IS_BROXTON(vgpu->gvt->gt->i915)) {
249258 			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
250259 				    ~(BIT(0) | BIT(1));
251260 			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
....@@ -271,6 +280,11 @@
271280 			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
272281 				    BXT_PHY_CMNLANE_POWERDOWN_ACK |
273282 				    BXT_PHY_LANE_POWERDOWN_ACK;
283
+			vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
284
+				SKL_FUSE_DOWNLOAD_STATUS |
285
+				SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
286
+				SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
287
+				SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
274288 		}
275289 	} else {
276290 #define GVT_GEN8_MMIO_RESET_OFFSET		(0x44200)
....@@ -279,7 +293,6 @@
279293 		 * touched
280294 		 */
281295 		memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
282
-		memcpy(vgpu->mmio.sreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
283296 	}
284297 
285298 }
....@@ -295,11 +308,9 @@
295308 {
296309 	const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
297310 
298
-	vgpu->mmio.vreg = vzalloc(array_size(info->mmio_size, 2));
311
+	vgpu->mmio.vreg = vzalloc(info->mmio_size);
299312 	if (!vgpu->mmio.vreg)
300313 		return -ENOMEM;
301
-
302
-	vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size;
303314 
304315 	intel_vgpu_reset_mmio(vgpu, true);
305316 
....@@ -314,5 +325,5 @@
314325 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
315326 {
316327 	vfree(vgpu->mmio.vreg);
317
-	vgpu->mmio.vreg = vgpu->mmio.sreg = NULL;
328
+	vgpu->mmio.vreg = NULL;
318329 }