hc
2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5
kernel/drivers/gpu/drm/amd/display/include/dal_asic_id.h
....@@ -30,6 +30,34 @@
3030 * ASIC internal revision ID
3131 */
3232
33
+/* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */
34
+#define SI_TAHITI_P_A0 0x01
35
+#define SI_TAHITI_P_B0 0x05
36
+#define SI_TAHITI_P_B1 0x06
37
+#define SI_PITCAIRN_PM_A0 0x14
38
+#define SI_PITCAIRN_PM_A1 0x15
39
+#define SI_CAPEVERDE_M_A0 0x28
40
+#define SI_CAPEVERDE_M_A1 0x29
41
+#define SI_OLAND_M_A0 0x3C
42
+#define SI_HAINAN_V_A0 0x46
43
+
44
+#define SI_UNKNOWN 0xFF
45
+
46
+#define ASIC_REV_IS_TAHITI_P(rev) \
47
+ ((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0))
48
+
49
+#define ASIC_REV_IS_PITCAIRN_PM(rev) \
50
+ ((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0))
51
+
52
+#define ASIC_REV_IS_CAPEVERDE_M(rev) \
53
+ ((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0))
54
+
55
+#define ASIC_REV_IS_OLAND_M(rev) \
56
+ ((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0))
57
+
58
+#define ASIC_REV_IS_HAINAN_V(rev) \
59
+ ((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN))
60
+
3361 /* DCE80 (based on ci_id.h in Perforce) */
3462 #define CI_BONAIRE_M_A0 0x14
3563 #define CI_BONAIRE_M_A1 0x15
....@@ -131,24 +159,81 @@
131159 #define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
132160 #define RAVEN_A0 0x01
133161 #define RAVEN_B0 0x21
134
-#define RAVEN_UNKNOWN 0xFF
135
-
136
-#define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
162
+#define PICASSO_A0 0x41
163
+/* DCN1_01 */
164
+#define RAVEN2_A0 0x81
137165 #define RAVEN1_F0 0xF0
166
+#define RAVEN_UNKNOWN 0xFF
167
+#define RENOIR_A0 0x91
168
+#ifndef ASICREV_IS_RAVEN
169
+#define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
170
+#endif
171
+#define PRID_DALI_DE 0xDE
172
+#define PRID_DALI_DF 0xDF
173
+#define PRID_DALI_E3 0xE3
174
+#define PRID_DALI_E4 0xE4
175
+
176
+#define PRID_POLLOCK_94 0x94
177
+#define PRID_POLLOCK_95 0x95
178
+#define PRID_POLLOCK_E9 0xE9
179
+#define PRID_POLLOCK_EA 0xEA
180
+#define PRID_POLLOCK_EB 0xEB
181
+
182
+#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
183
+#ifndef ASICREV_IS_RAVEN2
184
+#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < RENOIR_A0))
185
+#endif
138186 #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
139187
140
-
141188 #define FAMILY_RV 142 /* DCN 1*/
189
+
190
+
191
+#define FAMILY_NV 143 /* DCN 2*/
192
+
193
+enum {
194
+ NV_NAVI10_P_A0 = 1,
195
+ NV_NAVI12_P_A0 = 10,
196
+ NV_NAVI14_M_A0 = 20,
197
+ NV_SIENNA_CICHLID_P_A0 = 40,
198
+ NV_UNKNOWN = 0xFF
199
+};
200
+
201
+#define ASICREV_IS_NAVI10_P(eChipRev) (eChipRev < NV_NAVI12_P_A0)
202
+#define ASICREV_IS_NAVI12_P(eChipRev) ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
203
+#define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
204
+#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0))
205
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
206
+#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0))
207
+#endif
208
+#define GREEN_SARDINE_A0 0xA1
209
+#ifndef ASICREV_IS_GREEN_SARDINE
210
+#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
211
+#endif
142212
143213 /*
144214 * ASIC chip ID
145215 */
216
+
217
+/* DCE60 */
218
+#define DEVICE_ID_SI_TAHITI_P_6780 0x6780
219
+#define DEVICE_ID_SI_PITCAIRN_PM_6800 0x6800
220
+#define DEVICE_ID_SI_PITCAIRN_PM_6808 0x6808
221
+#define DEVICE_ID_SI_CAPEVERDE_M_6820 0x6820
222
+#define DEVICE_ID_SI_CAPEVERDE_M_6828 0x6828
223
+#define DEVICE_ID_SI_OLAND_M_6600 0x6600
224
+#define DEVICE_ID_SI_OLAND_M_6608 0x6608
225
+#define DEVICE_ID_SI_HAINAN_V_6660 0x6660
226
+
146227 /* DCE80 */
147228 #define DEVICE_ID_KALINDI_9834 0x9834
148229 #define DEVICE_ID_TEMASH_9839 0x9839
149230 #define DEVICE_ID_TEMASH_983D 0x983D
150231
232
+/* RENOIR */
233
+#define DEVICE_ID_RENOIR_1636 0x1636
234
+
151235 /* Asic Family IDs for different asic family. */
236
+#define FAMILY_SI 110 /* Southern Islands: Tahiti (P), Pitcairn (PM), Cape Verde (M), Oland (M), Hainan (V) */
152237 #define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
153238 #define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
154239 #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
....@@ -158,4 +243,6 @@
158243
159244 #define FAMILY_UNKNOWN 0xFF
160245
246
+
247
+
161248 #endif /* __DAL_ASIC_ID_H__ */