.. | .. |
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30 | 30 | * ASIC internal revision ID |
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31 | 31 | */ |
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32 | 32 | |
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| 33 | +/* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */ |
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| 34 | +#define SI_TAHITI_P_A0 0x01 |
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| 35 | +#define SI_TAHITI_P_B0 0x05 |
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| 36 | +#define SI_TAHITI_P_B1 0x06 |
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| 37 | +#define SI_PITCAIRN_PM_A0 0x14 |
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| 38 | +#define SI_PITCAIRN_PM_A1 0x15 |
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| 39 | +#define SI_CAPEVERDE_M_A0 0x28 |
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| 40 | +#define SI_CAPEVERDE_M_A1 0x29 |
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| 41 | +#define SI_OLAND_M_A0 0x3C |
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| 42 | +#define SI_HAINAN_V_A0 0x46 |
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| 43 | + |
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| 44 | +#define SI_UNKNOWN 0xFF |
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| 45 | + |
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| 46 | +#define ASIC_REV_IS_TAHITI_P(rev) \ |
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| 47 | + ((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0)) |
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| 48 | + |
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| 49 | +#define ASIC_REV_IS_PITCAIRN_PM(rev) \ |
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| 50 | + ((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0)) |
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| 51 | + |
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| 52 | +#define ASIC_REV_IS_CAPEVERDE_M(rev) \ |
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| 53 | + ((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0)) |
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| 54 | + |
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| 55 | +#define ASIC_REV_IS_OLAND_M(rev) \ |
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| 56 | + ((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0)) |
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| 57 | + |
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| 58 | +#define ASIC_REV_IS_HAINAN_V(rev) \ |
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| 59 | + ((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN)) |
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| 60 | + |
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33 | 61 | /* DCE80 (based on ci_id.h in Perforce) */ |
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34 | 62 | #define CI_BONAIRE_M_A0 0x14 |
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35 | 63 | #define CI_BONAIRE_M_A1 0x15 |
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.. | .. |
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131 | 159 | #define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */ |
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132 | 160 | #define RAVEN_A0 0x01 |
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133 | 161 | #define RAVEN_B0 0x21 |
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134 | | -#define RAVEN_UNKNOWN 0xFF |
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135 | | - |
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136 | | -#define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN) |
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| 162 | +#define PICASSO_A0 0x41 |
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| 163 | +/* DCN1_01 */ |
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| 164 | +#define RAVEN2_A0 0x81 |
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137 | 165 | #define RAVEN1_F0 0xF0 |
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| 166 | +#define RAVEN_UNKNOWN 0xFF |
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| 167 | +#define RENOIR_A0 0x91 |
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| 168 | +#ifndef ASICREV_IS_RAVEN |
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| 169 | +#define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN) |
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| 170 | +#endif |
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| 171 | +#define PRID_DALI_DE 0xDE |
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| 172 | +#define PRID_DALI_DF 0xDF |
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| 173 | +#define PRID_DALI_E3 0xE3 |
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| 174 | +#define PRID_DALI_E4 0xE4 |
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| 175 | + |
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| 176 | +#define PRID_POLLOCK_94 0x94 |
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| 177 | +#define PRID_POLLOCK_95 0x95 |
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| 178 | +#define PRID_POLLOCK_E9 0xE9 |
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| 179 | +#define PRID_POLLOCK_EA 0xEA |
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| 180 | +#define PRID_POLLOCK_EB 0xEB |
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| 181 | + |
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| 182 | +#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0)) |
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| 183 | +#ifndef ASICREV_IS_RAVEN2 |
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| 184 | +#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < RENOIR_A0)) |
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| 185 | +#endif |
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138 | 186 | #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN)) |
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139 | 187 | |
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140 | | - |
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141 | 188 | #define FAMILY_RV 142 /* DCN 1*/ |
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| 189 | + |
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| 190 | + |
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| 191 | +#define FAMILY_NV 143 /* DCN 2*/ |
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| 192 | + |
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| 193 | +enum { |
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| 194 | + NV_NAVI10_P_A0 = 1, |
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| 195 | + NV_NAVI12_P_A0 = 10, |
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| 196 | + NV_NAVI14_M_A0 = 20, |
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| 197 | + NV_SIENNA_CICHLID_P_A0 = 40, |
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| 198 | + NV_UNKNOWN = 0xFF |
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| 199 | +}; |
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| 200 | + |
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| 201 | +#define ASICREV_IS_NAVI10_P(eChipRev) (eChipRev < NV_NAVI12_P_A0) |
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| 202 | +#define ASICREV_IS_NAVI12_P(eChipRev) ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0)) |
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| 203 | +#define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN)) |
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| 204 | +#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0)) |
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| 205 | +#if defined(CONFIG_DRM_AMD_DC_DCN3_0) |
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| 206 | +#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0)) |
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| 207 | +#endif |
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| 208 | +#define GREEN_SARDINE_A0 0xA1 |
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| 209 | +#ifndef ASICREV_IS_GREEN_SARDINE |
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| 210 | +#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF)) |
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| 211 | +#endif |
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142 | 212 | |
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143 | 213 | /* |
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144 | 214 | * ASIC chip ID |
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145 | 215 | */ |
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| 216 | + |
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| 217 | +/* DCE60 */ |
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| 218 | +#define DEVICE_ID_SI_TAHITI_P_6780 0x6780 |
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| 219 | +#define DEVICE_ID_SI_PITCAIRN_PM_6800 0x6800 |
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| 220 | +#define DEVICE_ID_SI_PITCAIRN_PM_6808 0x6808 |
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| 221 | +#define DEVICE_ID_SI_CAPEVERDE_M_6820 0x6820 |
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| 222 | +#define DEVICE_ID_SI_CAPEVERDE_M_6828 0x6828 |
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| 223 | +#define DEVICE_ID_SI_OLAND_M_6600 0x6600 |
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| 224 | +#define DEVICE_ID_SI_OLAND_M_6608 0x6608 |
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| 225 | +#define DEVICE_ID_SI_HAINAN_V_6660 0x6660 |
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| 226 | + |
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146 | 227 | /* DCE80 */ |
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147 | 228 | #define DEVICE_ID_KALINDI_9834 0x9834 |
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148 | 229 | #define DEVICE_ID_TEMASH_9839 0x9839 |
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149 | 230 | #define DEVICE_ID_TEMASH_983D 0x983D |
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150 | 231 | |
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| 232 | +/* RENOIR */ |
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| 233 | +#define DEVICE_ID_RENOIR_1636 0x1636 |
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| 234 | + |
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151 | 235 | /* Asic Family IDs for different asic family. */ |
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| 236 | +#define FAMILY_SI 110 /* Southern Islands: Tahiti (P), Pitcairn (PM), Cape Verde (M), Oland (M), Hainan (V) */ |
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152 | 237 | #define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */ |
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153 | 238 | #define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */ |
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154 | 239 | #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */ |
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.. | .. |
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158 | 243 | |
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159 | 244 | #define FAMILY_UNKNOWN 0xFF |
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160 | 245 | |
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| 246 | + |
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| 247 | + |
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161 | 248 | #endif /* __DAL_ASIC_ID_H__ */ |
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