修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
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@@ -39,11 +39,12 @@
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 	SRII(MPCC_BG_G_Y, MPCC, inst),\
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 	SRII(MPCC_BG_R_CR, MPCC, inst),\
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 	SRII(MPCC_BG_B_CB, MPCC, inst),\
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-	SRII(MPCC_BG_B_CB, MPCC, inst),\
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-	SRII(MPCC_SM_CONTROL, MPCC, inst)
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+	SRII(MPCC_SM_CONTROL, MPCC, inst),\
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+	SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
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 #define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \
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-	SRII(MUX, MPC_OUT, inst)
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+	SRII(MUX, MPC_OUT, inst),\
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+	VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst)
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 #define MPC_COMMON_REG_VARIABLE_LIST \
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 	uint32_t MPCC_TOP_SEL[MAX_MPCC]; \
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@@ -55,7 +56,9 @@
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 	uint32_t MPCC_BG_R_CR[MAX_MPCC]; \
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 	uint32_t MPCC_BG_B_CB[MAX_MPCC]; \
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 	uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \
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-	uint32_t MUX[MAX_OPP];
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+	uint32_t MUX[MAX_OPP]; \
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+	uint32_t MPCC_UPDATE_LOCK_SEL[MAX_MPCC]; \
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+	uint32_t CUR[MAX_OPP];
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 #define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
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 	SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
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@@ -78,7 +81,8 @@
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 	SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\
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 	SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\
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 	SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\
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-	SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh)
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+	SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\
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+	SF(MPCC0_MPCC_UPDATE_LOCK_SEL, MPCC_UPDATE_LOCK_SEL, mask_sh)
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 #define MPC_REG_FIELD_LIST(type) \
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 	type MPCC_TOP_SEL;\
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@@ -101,7 +105,9 @@
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 	type MPCC_SM_FIELD_ALT;\
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 	type MPCC_SM_FORCE_NEXT_FRAME_POL;\
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 	type MPCC_SM_FORCE_NEXT_TOP_POL;\
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-	type MPC_OUT_MUX;
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+	type MPC_OUT_MUX;\
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+	type MPCC_UPDATE_LOCK_SEL;\
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+	type CUR_VUPDATE_LOCK_SET;
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 struct dcn_mpc_registers {
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 	MPC_COMMON_REG_VARIABLE_LIST
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@@ -149,6 +155,10 @@
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 void mpc1_mpc_init(
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 	struct mpc *mpc);
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+void mpc1_mpc_init_single_inst(
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+	struct mpc *mpc,
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+	unsigned int mpcc_id);
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+
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 void mpc1_assert_idle_mpcc(
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 	struct mpc *mpc,
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 	int id);
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@@ -188,4 +198,6 @@
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 		int mpcc_inst,
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 		struct mpcc_state *s);
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+void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);
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+
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 #endif