修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
..
..
@@ -27,23 +27,179 @@
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 #define __DC_HWSS_DCN10_H__
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 #include "core_types.h"
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+#include "hw_sequencer_private.h"
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 struct dc;
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 void dcn10_hw_sequencer_construct(struct dc *dc);
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-extern void fill_display_configs(
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-	const struct dc_state *context,
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-	struct dm_pp_display_configuration *pp_display_cfg);
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-bool is_rgb_cspace(enum dc_color_space output_color_space);
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-
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-void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
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-
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-void dcn10_verify_allow_pstate_change_high(struct dc *dc);
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-
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+int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
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+void dcn10_calc_vupdate_position(
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+		struct dc *dc,
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+		struct pipe_ctx *pipe_ctx,
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+		uint32_t *start_line,
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+		uint32_t *end_line);
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+void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
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+enum dc_status dcn10_enable_stream_timing(
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+		struct pipe_ctx *pipe_ctx,
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+		struct dc_state *context,
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+		struct dc *dc);
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+void dcn10_optimize_bandwidth(
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+		struct dc *dc,
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+		struct dc_state *context);
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+void dcn10_prepare_bandwidth(
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+		struct dc *dc,
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+		struct dc_state *context);
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+void dcn10_pipe_control_lock(
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+	struct dc *dc,
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+	struct pipe_ctx *pipe,
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+	bool lock);
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+void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock);
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+void dcn10_blank_pixel_data(
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+		struct dc *dc,
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+		struct pipe_ctx *pipe_ctx,
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+		bool blank);
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+void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
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+		struct dc_link_settings *link_settings);
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+void dcn10_program_output_csc(struct dc *dc,
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+		struct pipe_ctx *pipe_ctx,
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+		enum dc_color_space colorspace,
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+		uint16_t *matrix,
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+		int opp_id);
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+bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
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+				const struct dc_stream_state *stream);
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+bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
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+			const struct dc_plane_state *plane_state);
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+void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
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+void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
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+void dcn10_reset_hw_ctx_wrap(
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+		struct dc *dc,
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+		struct dc_state *context);
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+void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
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+void dcn10_lock_all_pipes(
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+		struct dc *dc,
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+		struct dc_state *context,
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+		bool lock);
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+void dcn10_apply_ctx_for_surface(
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+		struct dc *dc,
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+		const struct dc_stream_state *stream,
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+		int num_planes,
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+		struct dc_state *context);
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+void dcn10_post_unlock_program_front_end(
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+		struct dc *dc,
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+		struct dc_state *context);
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+void dcn10_hubp_pg_control(
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+		struct dce_hwseq *hws,
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+		unsigned int hubp_inst,
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+		bool power_on);
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+void dcn10_dpp_pg_control(
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+		struct dce_hwseq *hws,
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+		unsigned int dpp_inst,
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+		bool power_on);
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+void dcn10_enable_power_gating_plane(
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+	struct dce_hwseq *hws,
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+	bool enable);
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+void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
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+void dcn10_disable_vga(
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+	struct dce_hwseq *hws);
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 void dcn10_program_pipe(
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 		struct dc *dc,
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 		struct pipe_ctx *pipe_ctx,
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 		struct dc_state *context);
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+void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx);
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+void dcn10_init_hw(struct dc *dc);
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+void dcn10_init_pipes(struct dc *dc, struct dc_state *context);
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+void dcn10_power_down_on_boot(struct dc *dc);
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+enum dc_status dce110_apply_ctx_to_hw(
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+		struct dc *dc,
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+		struct dc_state *context);
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+void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx);
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+void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data);
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+void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx);
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+void dce110_power_down(struct dc *dc);
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+void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context);
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+void dcn10_enable_timing_synchronization(
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+		struct dc *dc,
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+		int group_index,
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+		int group_size,
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+		struct pipe_ctx *grouped_pipes[]);
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+void dcn10_enable_per_frame_crtc_position_reset(
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+		struct dc *dc,
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+		int group_size,
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+		struct pipe_ctx *grouped_pipes[]);
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+void dce110_update_info_frame(struct pipe_ctx *pipe_ctx);
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+void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx,
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+		const uint8_t *custom_sdp_message,
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+		unsigned int sdp_message_size);
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+void dce110_blank_stream(struct pipe_ctx *pipe_ctx);
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+void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx);
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+void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx);
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+bool dcn10_dummy_display_power_gating(
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+		struct dc *dc,
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+		uint8_t controller_id,
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+		struct dc_bios *dcb,
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+		enum pipe_gating_control power_gating);
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+void dcn10_set_drr(struct pipe_ctx **pipe_ctx,
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+		int num_pipes, unsigned int vmin, unsigned int vmax,
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+		unsigned int vmid, unsigned int vmid_frame_number);
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+void dcn10_get_position(struct pipe_ctx **pipe_ctx,
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+		int num_pipes,
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+		struct crtc_position *position);
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+void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx,
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+		int num_pipes, const struct dc_static_screen_params *params);
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+void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc);
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+void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
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+void dcn10_log_hw_state(struct dc *dc,
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+		struct dc_log_buffer_ctx *log_ctx);
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+void dcn10_get_hw_state(struct dc *dc,
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+		char *pBuf,
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+		unsigned int bufSize,
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+		unsigned int mask);
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+void dcn10_clear_status_bits(struct dc *dc, unsigned int mask);
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+void dcn10_wait_for_mpcc_disconnect(
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+		struct dc *dc,
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+		struct resource_pool *res_pool,
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+		struct pipe_ctx *pipe_ctx);
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+void dce110_edp_backlight_control(
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+		struct dc_link *link,
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+		bool enable);
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+void dce110_edp_power_control(
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+		struct dc_link *link,
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+		bool power_up);
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+void dce110_edp_wait_for_hpd_ready(
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+		struct dc_link *link,
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+		bool power_up);
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+void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx);
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+void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
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+void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx);
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+void dcn10_setup_periodic_interrupt(
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+		struct dc *dc,
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+		struct pipe_ctx *pipe_ctx);
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+enum dc_status dcn10_set_clock(struct dc *dc,
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+		enum dc_clock_type clock_type,
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+		uint32_t clk_khz,
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+		uint32_t stepping);
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+void dcn10_get_clock(struct dc *dc,
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+		enum dc_clock_type clock_type,
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+		struct dc_clock_config *clock_cfg);
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+bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
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+void dcn10_bios_golden_init(struct dc *dc);
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+void dcn10_plane_atomic_power_down(struct dc *dc,
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+		struct dpp *dpp,
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+		struct hubp *hubp);
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+void dcn10_get_surface_visual_confirm_color(
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+		const struct pipe_ctx *pipe_ctx,
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+		struct tg_color *color);
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+void dcn10_get_hdr_visual_confirm_color(
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+		struct pipe_ctx *pipe_ctx,
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+		struct tg_color *color);
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+bool dcn10_disconnect_pipes(
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+		struct dc *dc,
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+		struct dc_state *context);
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+
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+void dcn10_wait_for_pending_cleared(struct dc *dc,
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+		struct dc_state *context);
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+void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx);
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+void dcn10_verify_allow_pstate_change_high(struct dc *dc);
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 #endif /* __DC_HWSS_DCN10_H__ */