forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
....@@ -63,7 +63,7 @@
6363 		}
6464 
6565 		hubp->mpcc_id = 0xf;
66
-		hubp->opp_id = 0xf;
66
+		hubp->opp_id = OPP_ID_INVALID;
6767 	}
6868 }
6969 
....@@ -99,6 +99,14 @@
9999 	return hubp_underflow;
100100 }
101101 
102
+
103
+void hubp1_clear_underflow(struct hubp *hubp)
104
+{
105
+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
106
+
107
+	REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
108
+}
109
+
102110 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
103111 {
104112 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
....@@ -107,7 +115,7 @@
107115 	REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);
108116 }
109117 
110
-static void hubp1_vready_workaround(struct hubp *hubp,
118
+void hubp1_vready_workaround(struct hubp *hubp,
111119 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
112120 {
113121 	uint32_t value = 0;
....@@ -155,7 +163,7 @@
155163 void hubp1_program_size(
156164 	struct hubp *hubp,
157165 	enum surface_pixel_format format,
158
-	const union plane_size *plane_size,
166
+	const struct plane_size *plane_size,
159167 	struct dc_plane_dcc_param *dcc)
160168 {
161169 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
....@@ -165,16 +173,16 @@
165173 	 * 444 or 420 luma
166174 	 */
167175 	if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) {
168
-		ASSERT(plane_size->video.chroma_pitch != 0);
176
+		ASSERT(plane_size->chroma_pitch != 0);
169177 		/* Chroma pitch zero can cause system hang! */
170178 
171
-		pitch = plane_size->video.luma_pitch - 1;
172
-		meta_pitch = dcc->video.meta_pitch_l - 1;
173
-		pitch_c = plane_size->video.chroma_pitch - 1;
174
-		meta_pitch_c = dcc->video.meta_pitch_c - 1;
179
+		pitch = plane_size->surface_pitch - 1;
180
+		meta_pitch = dcc->meta_pitch - 1;
181
+		pitch_c = plane_size->chroma_pitch - 1;
182
+		meta_pitch_c = dcc->meta_pitch_c - 1;
175183 	} else {
176
-		pitch = plane_size->grph.surface_pitch - 1;
177
-		meta_pitch = dcc->grph.meta_pitch - 1;
184
+		pitch = plane_size->surface_pitch - 1;
185
+		meta_pitch = dcc->meta_pitch - 1;
178186 		pitch_c = 0;
179187 		meta_pitch_c = 0;
180188 	}
....@@ -298,6 +306,38 @@
298306 		REG_UPDATE(DCSURF_SURFACE_CONFIG,
299307 				SURFACE_PIXEL_FORMAT, 12);
300308 		break;
309
+	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
310
+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
311
+				SURFACE_PIXEL_FORMAT, 112);
312
+		break;
313
+	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
314
+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
315
+				SURFACE_PIXEL_FORMAT, 113);
316
+		break;
317
+	case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
318
+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
319
+				SURFACE_PIXEL_FORMAT, 114);
320
+		break;
321
+	case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
322
+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
323
+				SURFACE_PIXEL_FORMAT, 118);
324
+		break;
325
+	case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
326
+		REG_UPDATE(DCSURF_SURFACE_CONFIG,
327
+				SURFACE_PIXEL_FORMAT, 119);
328
+		break;
329
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
330
+	case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
331
+		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
332
+				SURFACE_PIXEL_FORMAT, 116,
333
+				ALPHA_PLANE_EN, 0);
334
+		break;
335
+	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
336
+		REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
337
+				SURFACE_PIXEL_FORMAT, 116,
338
+				ALPHA_PLANE_EN, 1);
339
+		break;
340
+#endif
301341 	default:
302342 		BREAK_TO_DEBUGGER();
303343 		break;
....@@ -313,9 +353,23 @@
313353 {
314354 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
315355 
316
-	/* program flip type */
317
-	REG_SET(DCSURF_FLIP_CONTROL, 0,
356
+
357
+	//program flip type
358
+	REG_UPDATE(DCSURF_FLIP_CONTROL,
318359 			SURFACE_FLIP_TYPE, flip_immediate);
360
+
361
+
362
+	if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {
363
+		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1);
364
+		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
365
+
366
+	} else {
367
+		// turn off stereo if not in stereo
368
+		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
369
+		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
370
+	}
371
+
372
+
319373 
320374 	/* HW automatically latch rest of address register on write to
321375 	 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
....@@ -465,7 +519,7 @@
465519 }
466520 
467521 void hubp1_dcc_control(struct hubp *hubp, bool enable,
468
-		bool independent_64b_blks)
522
+		enum hubp_ind_block_size independent_64b_blks)
469523 {
470524 	uint32_t dcc_en = enable ? 1 : 0;
471525 	uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
....@@ -482,12 +536,13 @@
482536 	struct hubp *hubp,
483537 	enum surface_pixel_format format,
484538 	union dc_tiling_info *tiling_info,
485
-	union plane_size *plane_size,
539
+	struct plane_size *plane_size,
486540 	enum dc_rotation_angle rotation,
487541 	struct dc_plane_dcc_param *dcc,
488
-	bool horizontal_mirror)
542
+	bool horizontal_mirror,
543
+	unsigned int compat_level)
489544 {
490
-	hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
545
+	hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
491546 	hubp1_program_tiling(hubp, tiling_info, format);
492547 	hubp1_program_size(hubp, format, plane_size, dcc);
493548 	hubp1_program_rotation(hubp, rotation, horizontal_mirror);
....@@ -550,28 +605,12 @@
550605 		REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
551606 		DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
552607 
553
-	if (REG(PREFETCH_SETTINS))
554
-		REG_SET_2(PREFETCH_SETTINS, 0,
555
-			DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
556
-			VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
557
-	else
558
-		REG_SET_2(PREFETCH_SETTINGS, 0,
559
-			DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
560
-			VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
561
-
562
-	REG_SET_2(VBLANK_PARAMETERS_0, 0,
563
-		DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
564
-		DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
565
-
566608 	REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
567609 		REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
568610 
569611 	/* DLG - Per luma/chroma */
570612 	REG_SET(VBLANK_PARAMETERS_1, 0,
571613 		REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
572
-
573
-	REG_SET(VBLANK_PARAMETERS_3, 0,
574
-		REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
575614 
576615 	if (REG(NOM_PARAMETERS_0))
577616 		REG_SET(NOM_PARAMETERS_0, 0,
....@@ -587,26 +626,12 @@
587626 	REG_SET(NOM_PARAMETERS_5, 0,
588627 		REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
589628 
590
-	REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
591
-		REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
592
-		REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
593
-
594629 	REG_SET_2(PER_LINE_DELIVERY, 0,
595630 		REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
596631 		REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
597632 
598
-	if (REG(PREFETCH_SETTINS_C))
599
-		REG_SET(PREFETCH_SETTINS_C, 0,
600
-			VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
601
-	else
602
-		REG_SET(PREFETCH_SETTINGS_C, 0,
603
-			VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
604
-
605633 	REG_SET(VBLANK_PARAMETERS_2, 0,
606634 		REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
607
-
608
-	REG_SET(VBLANK_PARAMETERS_4, 0,
609
-		REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
610635 
611636 	if (REG(NOM_PARAMETERS_2))
612637 		REG_SET(NOM_PARAMETERS_2, 0,
....@@ -627,10 +652,6 @@
627652 		QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
628653 		QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
629654 
630
-	REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
631
-		MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
632
-		QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
633
-
634655 	/* TTU - per luma/chroma */
635656 	/* Assumed surf0 is luma and 1 is chroma */
636657 
....@@ -639,25 +660,15 @@
639660 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
640661 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
641662 
642
-	REG_SET(DCN_SURF0_TTU_CNTL1, 0,
643
-		REFCYC_PER_REQ_DELIVERY_PRE,
644
-		ttu_attr->refcyc_per_req_delivery_pre_l);
645
-
646663 	REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
647664 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
648665 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
649666 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
650667 
651
-	REG_SET(DCN_SURF1_TTU_CNTL1, 0,
652
-		REFCYC_PER_REQ_DELIVERY_PRE,
653
-		ttu_attr->refcyc_per_req_delivery_pre_c);
654
-
655668 	REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
656669 		REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
657670 		QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
658671 		QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
659
-	REG_SET(DCN_CUR0_TTU_CNTL1, 0,
660
-		REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
661672 }
662673 
663674 static void hubp1_setup(
....@@ -675,11 +686,56 @@
675686 	hubp1_vready_workaround(hubp, pipe_dest);
676687 }
677688 
689
+static void hubp1_setup_interdependent(
690
+		struct hubp *hubp,
691
+		struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
692
+		struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
693
+{
694
+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
695
+
696
+	REG_SET_2(PREFETCH_SETTINS, 0,
697
+		DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
698
+		VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
699
+
700
+	REG_SET(PREFETCH_SETTINS_C, 0,
701
+		VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
702
+
703
+	REG_SET_2(VBLANK_PARAMETERS_0, 0,
704
+		DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
705
+		DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
706
+
707
+	REG_SET(VBLANK_PARAMETERS_3, 0,
708
+		REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
709
+
710
+	REG_SET(VBLANK_PARAMETERS_4, 0,
711
+		REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
712
+
713
+	REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
714
+		REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
715
+		REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
716
+
717
+	REG_SET(DCN_SURF0_TTU_CNTL1, 0,
718
+		REFCYC_PER_REQ_DELIVERY_PRE,
719
+		ttu_attr->refcyc_per_req_delivery_pre_l);
720
+	REG_SET(DCN_SURF1_TTU_CNTL1, 0,
721
+		REFCYC_PER_REQ_DELIVERY_PRE,
722
+		ttu_attr->refcyc_per_req_delivery_pre_c);
723
+	REG_SET(DCN_CUR0_TTU_CNTL1, 0,
724
+		REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
725
+
726
+	REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
727
+		MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
728
+		QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
729
+}
730
+
678731 bool hubp1_is_flip_pending(struct hubp *hubp)
679732 {
680733 	uint32_t flip_pending = 0;
681734 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
682735 	struct dc_plane_address earliest_inuse_address;
736
+
737
+	if (hubp && hubp->power_gated)
738
+		return false;
683739 
684740 	REG_GET(DCSURF_FLIP_CONTROL,
685741 			SURFACE_FLIP_PENDING, &flip_pending);
....@@ -798,9 +854,17 @@
798854 	REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
799855 		  PRI_VIEWPORT_X_START_C, viewport_c->x,
800856 		  PRI_VIEWPORT_Y_START_C, viewport_c->y);
857
+
858
+	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,
859
+		  SEC_VIEWPORT_WIDTH_C, viewport_c->width,
860
+		  SEC_VIEWPORT_HEIGHT_C, viewport_c->height);
861
+
862
+	REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,
863
+		  SEC_VIEWPORT_X_START_C, viewport_c->x,
864
+		  SEC_VIEWPORT_Y_START_C, viewport_c->y);
801865 }
802866 
803
-void hubp1_read_state(struct hubp *hubp)
867
+void hubp1_read_state_common(struct hubp *hubp)
804868 {
805869 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
806870 	struct dcn_hubp_state *s = &hubp1->state;
....@@ -816,24 +880,6 @@
816880 			PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
817881 			MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
818882 			CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
819
-	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
820
-		CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
821
-		MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
822
-		META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
823
-		MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
824
-		DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
825
-		MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
826
-		SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
827
-		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
828
-	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
829
-		CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
830
-		MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
831
-		META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
832
-		MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
833
-		DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
834
-		MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
835
-		SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
836
-		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
837883 
838884 	/* DLG - Per hubp */
839885 	REG_GET_2(BLANK_OFFSET_0,
....@@ -959,6 +1005,9 @@
9591005 	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
9601006 			SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
9611007 
1008
+	REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
1009
+			SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
1010
+
9621011 	REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
9631012 			PRI_VIEWPORT_WIDTH, &s->viewport_width,
9641013 			PRI_VIEWPORT_HEIGHT, &s->viewport_height);
....@@ -978,14 +1027,47 @@
9781027 			HUBP_TTU_DISABLE, &s->ttu_disable,
9791028 			HUBP_UNDERFLOW_STATUS, &s->underflow_status);
9801029 
1030
+	REG_GET(HUBP_CLK_CNTL,
1031
+			HUBP_CLOCK_ENABLE, &s->clock_en);
1032
+
9811033 	REG_GET(DCN_GLOBAL_TTU_CNTL,
9821034 			MIN_TTU_VBLANK, &s->min_ttu_vblank);
9831035 
9841036 	REG_GET_2(DCN_TTU_QOS_WM,
9851037 			QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
9861038 			QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
1039
+
9871040 }
9881041 
1042
+void hubp1_read_state(struct hubp *hubp)
1043
+{
1044
+	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1045
+	struct dcn_hubp_state *s = &hubp1->state;
1046
+	struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1047
+
1048
+	hubp1_read_state_common(hubp);
1049
+
1050
+	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1051
+		CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1052
+		MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
1053
+		META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
1054
+		MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
1055
+		DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
1056
+		MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
1057
+		SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
1058
+		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
1059
+
1060
+	REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1061
+		CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
1062
+		MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
1063
+		META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
1064
+		MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
1065
+		DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
1066
+		MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
1067
+		SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
1068
+		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
1069
+
1070
+}
9891071 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch)
9901072 {
9911073 	enum cursor_pitch hw_pitch;
....@@ -1069,8 +1151,11 @@
10691151 {
10701152 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
10711153 	int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
1154
+	int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
10721155 	int x_hotspot = pos->x_hotspot;
10731156 	int y_hotspot = pos->y_hotspot;
1157
+	int cursor_height = (int)hubp->curs_attr.height;
1158
+	int cursor_width = (int)hubp->curs_attr.width;
10741159 	uint32_t dst_x_offset;
10751160 	uint32_t cur_en = pos->enable ? 1 : 0;
10761161 
....@@ -1084,10 +1169,16 @@
10841169 	if (hubp->curs_attr.address.quad_part == 0)
10851170 		return;
10861171 
1172
+	// Rotated cursor width/height and hotspots tweaks for offset calculation
10871173 	if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
1088
-		src_x_offset = pos->y - pos->y_hotspot - param->viewport.x;
1089
-		y_hotspot = pos->x_hotspot;
1090
-		x_hotspot = pos->y_hotspot;
1174
+		swap(cursor_height, cursor_width);
1175
+		if (param->rotation == ROTATION_ANGLE_90) {
1176
+			src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
1177
+			src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
1178
+		}
1179
+	} else if (param->rotation == ROTATION_ANGLE_180) {
1180
+		src_x_offset = pos->x - param->viewport.x;
1181
+		src_y_offset = pos->y - param->viewport.y;
10911182 	}
10921183 
10931184 	if (param->mirror) {
....@@ -1109,8 +1200,14 @@
11091200 	if (src_x_offset >= (int)param->viewport.width)
11101201 		cur_en = 0;  /* not visible beyond right edge*/
11111202 
1112
-	if (src_x_offset + (int)hubp->curs_attr.width <= 0)
1203
+	if (src_x_offset + cursor_width <= 0)
11131204 		cur_en = 0;  /* not visible beyond left edge*/
1205
+
1206
+	if (src_y_offset >= (int)param->viewport.height)
1207
+		cur_en = 0;  /* not visible beyond bottom edge*/
1208
+
1209
+	if (src_y_offset + cursor_height <= 0)
1210
+		cur_en = 0;  /* not visible beyond top edge*/
11141211 
11151212 	if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
11161213 		hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
....@@ -1146,6 +1243,10 @@
11461243 	REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
11471244 }
11481245 
1246
+void hubp1_init(struct hubp *hubp)
1247
+{
1248
+	//do nothing
1249
+}
11491250 static const struct hubp_funcs dcn10_hubp_funcs = {
11501251 	.hubp_program_surface_flip_and_addr =
11511252 			hubp1_program_surface_flip_and_addr,
....@@ -1153,6 +1254,7 @@
11531254 			hubp1_program_surface_config,
11541255 	.hubp_is_flip_pending = hubp1_is_flip_pending,
11551256 	.hubp_setup = hubp1_setup,
1257
+	.hubp_setup_interdependent = hubp1_setup_interdependent,
11561258 	.hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings,
11571259 	.hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings,
11581260 	.set_blank = hubp1_set_blank,
....@@ -1165,9 +1267,13 @@
11651267 	.hubp_clk_cntl = hubp1_clk_cntl,
11661268 	.hubp_vtg_sel = hubp1_vtg_sel,
11671269 	.hubp_read_state = hubp1_read_state,
1270
+	.hubp_clear_underflow = hubp1_clear_underflow,
11681271 	.hubp_disable_control =  hubp1_disable_control,
11691272 	.hubp_get_underflow_status = hubp1_get_underflow_status,
1273
+	.hubp_init = hubp1_init,
11701274 
1275
+	.dmdata_set_attributes = NULL,
1276
+	.dmdata_load = NULL,
11711277 };
11721278 
11731279 /*****************************************/
....@@ -1188,7 +1294,7 @@
11881294 	hubp1->hubp_shift = hubp_shift;
11891295 	hubp1->hubp_mask = hubp_mask;
11901296 	hubp1->base.inst = inst;
1191
-	hubp1->base.opp_id = 0xf;
1297
+	hubp1->base.opp_id = OPP_ID_INVALID;
11921298 	hubp1->base.mpcc_id = 0xf;
11931299 }
11941300