forked from ~ljy/RK356X_SDK_RELEASE
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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
....@@ -23,25 +23,28 @@
2323  *
2424  */
2525 
26
+#include <linux/delay.h>
27
+
2628 #include "dm_services.h"
2729 #include "dcn10_hubp.h"
2830 #include "dcn10_hubbub.h"
2931 #include "reg_helper.h"
3032 
3133 #define CTX \
32
-	hubbub->ctx
34
+	hubbub1->base.ctx
3335 #define DC_LOGGER \
34
-	hubbub->ctx->logger
36
+	hubbub1->base.ctx->logger
3537 #define REG(reg)\
36
-	hubbub->regs->reg
38
+	hubbub1->regs->reg
3739 
3840 #undef FN
3941 #define FN(reg_name, field_name) \
40
-	hubbub->shifts->field_name, hubbub->masks->field_name
42
+	hubbub1->shifts->field_name, hubbub1->masks->field_name
4143 
4244 void hubbub1_wm_read_state(struct hubbub *hubbub,
4345 		struct dcn_hubbub_wm *wm)
4446 {
47
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
4548 	struct dcn_hubbub_wm_set *s;
4649 
4750 	memset(wm, 0, sizeof(struct dcn_hubbub_wm));
....@@ -87,9 +90,36 @@
8790 	s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
8891 }
8992 
93
+void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow)
94
+{
95
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
96
+	/*
97
+	 * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 1 means do not allow stutter
98
+	 * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0 means allow stutter
99
+	 */
100
+
101
+	REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
102
+			DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
103
+			DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, !allow);
104
+}
105
+
106
+bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
107
+{
108
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
109
+	uint32_t enable = 0;
110
+
111
+	REG_GET(DCHUBBUB_ARB_DRAM_STATE_CNTL,
112
+			DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, &enable);
113
+
114
+	return enable ? true : false;
115
+}
116
+
117
+
90118 bool hubbub1_verify_allow_pstate_change_high(
91119 	struct hubbub *hubbub)
92120 {
121
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
122
+
93123 	/* pstate latency is ~20us so if we wait over 40us and pstate allow
94124 	 * still not asserted, we are probably stuck and going to hang
95125 	 *
....@@ -97,8 +127,8 @@
97127 	 * pstate takes around ~100us on linux. Unknown currently as to
98128 	 * why it takes that long on linux
99129 	 */
100
-	static unsigned int pstate_wait_timeout_us = 200;
101
-	static unsigned int pstate_wait_expected_timeout_us = 40;
130
+	const unsigned int pstate_wait_timeout_us = 200;
131
+	const unsigned int pstate_wait_expected_timeout_us = 40;
102132 	static unsigned int max_sampled_pstate_wait_us; /* data collection */
103133 	static bool forced_pstate_allow; /* help with revert wa */
104134 
....@@ -116,32 +146,45 @@
116146 		forced_pstate_allow = false;
117147 	}
118148 
119
-	/* RV1:
120
-	 * dchubbubdebugind, at: 0x7
121
-	 * description "3-0:   Pipe0 cursor0 QOS
122
-	 * 7-4:   Pipe1 cursor0 QOS
123
-	 * 11-8:  Pipe2 cursor0 QOS
124
-	 * 15-12: Pipe3 cursor0 QOS
125
-	 * 16:    Pipe0 Plane0 Allow Pstate Change
126
-	 * 17:    Pipe1 Plane0 Allow Pstate Change
127
-	 * 18:    Pipe2 Plane0 Allow Pstate Change
128
-	 * 19:    Pipe3 Plane0 Allow Pstate Change
129
-	 * 20:    Pipe0 Plane1 Allow Pstate Change
130
-	 * 21:    Pipe1 Plane1 Allow Pstate Change
131
-	 * 22:    Pipe2 Plane1 Allow Pstate Change
132
-	 * 23:    Pipe3 Plane1 Allow Pstate Change
133
-	 * 24:    Pipe0 cursor0 Allow Pstate Change
134
-	 * 25:    Pipe1 cursor0 Allow Pstate Change
135
-	 * 26:    Pipe2 cursor0 Allow Pstate Change
136
-	 * 27:    Pipe3 cursor0 Allow Pstate Change
149
+	/* The following table only applies to DCN1 and DCN2,
150
+	 * for newer DCNs, need to consult with HW IP folks to read RTL
151
+	 * HUBBUB:DCHUBBUB_TEST_ARB_DEBUG10 DCHUBBUBDEBUGIND:0xB
152
+	 * description
153
+	 * 0:     Pipe0 Plane0 Allow Pstate Change
154
+	 * 1:     Pipe0 Plane1 Allow Pstate Change
155
+	 * 2:     Pipe0 Cursor0 Allow Pstate Change
156
+	 * 3:     Pipe0 Cursor1 Allow Pstate Change
157
+	 * 4:     Pipe1 Plane0 Allow Pstate Change
158
+	 * 5:     Pipe1 Plane1 Allow Pstate Change
159
+	 * 6:     Pipe1 Cursor0 Allow Pstate Change
160
+	 * 7:     Pipe1 Cursor1 Allow Pstate Change
161
+	 * 8:     Pipe2 Plane0 Allow Pstate Change
162
+	 * 9:     Pipe2 Plane1 Allow Pstate Change
163
+	 * 10:    Pipe2 Cursor0 Allow Pstate Change
164
+	 * 11:    Pipe2 Cursor1 Allow Pstate Change
165
+	 * 12:    Pipe3 Plane0 Allow Pstate Change
166
+	 * 13:    Pipe3 Plane1 Allow Pstate Change
167
+	 * 14:    Pipe3 Cursor0 Allow Pstate Change
168
+	 * 15:    Pipe3 Cursor1 Allow Pstate Change
169
+	 * 16:    Pipe4 Plane0 Allow Pstate Change
170
+	 * 17:    Pipe4 Plane1 Allow Pstate Change
171
+	 * 18:    Pipe4 Cursor0 Allow Pstate Change
172
+	 * 19:    Pipe4 Cursor1 Allow Pstate Change
173
+	 * 20:    Pipe5 Plane0 Allow Pstate Change
174
+	 * 21:    Pipe5 Plane1 Allow Pstate Change
175
+	 * 22:    Pipe5 Cursor0 Allow Pstate Change
176
+	 * 23:    Pipe5 Cursor1 Allow Pstate Change
177
+	 * 24:    Pipe6 Plane0 Allow Pstate Change
178
+	 * 25:    Pipe6 Plane1 Allow Pstate Change
179
+	 * 26:    Pipe6 Cursor0 Allow Pstate Change
180
+	 * 27:    Pipe6 Cursor1 Allow Pstate Change
137181 	 * 28:    WB0 Allow Pstate Change
138182 	 * 29:    WB1 Allow Pstate Change
139183 	 * 30:    Arbiter's allow_pstate_change
140184 	 * 31:    SOC pstate change request
141185 	 */
142186 
143
-
144
-	REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub->debug_test_index_pstate);
187
+	REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub1->debug_test_index_pstate);
145188 
146189 	for (i = 0; i < pstate_wait_timeout_us; i++) {
147190 		debug_data = REG_READ(DCHUBBUB_TEST_DEBUG_DATA);
....@@ -192,297 +235,395 @@
192235 
193236 void hubbub1_wm_change_req_wa(struct hubbub *hubbub)
194237 {
195
-	REG_UPDATE_SEQ(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
196
-			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0, 1);
238
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
239
+
240
+	REG_UPDATE_SEQ_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
241
+			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 0,
242
+			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
197243 }
198244 
199
-void hubbub1_program_watermarks(
245
+bool hubbub1_program_urgent_watermarks(
200246 		struct hubbub *hubbub,
201247 		struct dcn_watermark_set *watermarks,
202248 		unsigned int refclk_mhz,
203249 		bool safe_to_lower)
204250 {
205
-	uint32_t force_en = hubbub->ctx->dc->debug.disable_stutter ? 1 : 0;
206
-	/*
207
-	 * Need to clamp to max of the register values (i.e. no wrap)
208
-	 * for dcn1, all wm registers are 21-bit wide
209
-	 */
251
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
210252 	uint32_t prog_wm_value;
211
-
253
+	bool wm_pending = false;
212254 
213255 	/* Repeat for water mark set A, B, C and D. */
214256 	/* clock state A */
215
-	if (safe_to_lower || watermarks->a.urgent_ns > hubbub->watermarks.a.urgent_ns) {
216
-		hubbub->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
257
+	if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) {
258
+		hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
217259 		prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
218260 				refclk_mhz, 0x1fffff);
219
-		REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
261
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
262
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
220263 
221264 		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n"
222265 			"HW register value = 0x%x\n",
223266 			watermarks->a.urgent_ns, prog_wm_value);
224
-	}
267
+	} else if (watermarks->a.urgent_ns < hubbub1->watermarks.a.urgent_ns)
268
+		wm_pending = true;
225269 
226
-	if (safe_to_lower || watermarks->a.pte_meta_urgent_ns > hubbub->watermarks.a.pte_meta_urgent_ns) {
227
-		hubbub->watermarks.a.pte_meta_urgent_ns = watermarks->a.pte_meta_urgent_ns;
270
+	if (safe_to_lower || watermarks->a.pte_meta_urgent_ns > hubbub1->watermarks.a.pte_meta_urgent_ns) {
271
+		hubbub1->watermarks.a.pte_meta_urgent_ns = watermarks->a.pte_meta_urgent_ns;
228272 		prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,
229273 				refclk_mhz, 0x1fffff);
230274 		REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
231275 		DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_A calculated =%d\n"
232276 			"HW register value = 0x%x\n",
233277 			watermarks->a.pte_meta_urgent_ns, prog_wm_value);
234
-	}
235
-
236
-	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
237
-		if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
238
-				> hubbub->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) {
239
-			hubbub->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
240
-					watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns;
241
-			prog_wm_value = convert_and_clamp(
242
-					watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
243
-					refclk_mhz, 0x1fffff);
244
-			REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
245
-			DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
246
-				"HW register value = 0x%x\n",
247
-				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
248
-		}
249
-
250
-		if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns
251
-				> hubbub->watermarks.a.cstate_pstate.cstate_exit_ns) {
252
-			hubbub->watermarks.a.cstate_pstate.cstate_exit_ns =
253
-					watermarks->a.cstate_pstate.cstate_exit_ns;
254
-			prog_wm_value = convert_and_clamp(
255
-					watermarks->a.cstate_pstate.cstate_exit_ns,
256
-					refclk_mhz, 0x1fffff);
257
-			REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
258
-			DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"
259
-				"HW register value = 0x%x\n",
260
-				watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
261
-		}
262
-	}
263
-
264
-	if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns
265
-			> hubbub->watermarks.a.cstate_pstate.pstate_change_ns) {
266
-		hubbub->watermarks.a.cstate_pstate.pstate_change_ns =
267
-				watermarks->a.cstate_pstate.pstate_change_ns;
268
-		prog_wm_value = convert_and_clamp(
269
-				watermarks->a.cstate_pstate.pstate_change_ns,
270
-				refclk_mhz, 0x1fffff);
271
-		REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
272
-		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
273
-			"HW register value = 0x%x\n\n",
274
-			watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
275
-	}
278
+	} else if (watermarks->a.pte_meta_urgent_ns < hubbub1->watermarks.a.pte_meta_urgent_ns)
279
+		wm_pending = true;
276280 
277281 	/* clock state B */
278
-	if (safe_to_lower || watermarks->b.urgent_ns > hubbub->watermarks.b.urgent_ns) {
279
-		hubbub->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
282
+	if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) {
283
+		hubbub1->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
280284 		prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns,
281285 				refclk_mhz, 0x1fffff);
282
-		REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
286
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
287
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
283288 
284289 		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n"
285290 			"HW register value = 0x%x\n",
286291 			watermarks->b.urgent_ns, prog_wm_value);
287
-	}
292
+	} else if (watermarks->b.urgent_ns < hubbub1->watermarks.b.urgent_ns)
293
+		wm_pending = true;
288294 
289
-	if (safe_to_lower || watermarks->b.pte_meta_urgent_ns > hubbub->watermarks.b.pte_meta_urgent_ns) {
290
-		hubbub->watermarks.b.pte_meta_urgent_ns = watermarks->b.pte_meta_urgent_ns;
295
+	if (safe_to_lower || watermarks->b.pte_meta_urgent_ns > hubbub1->watermarks.b.pte_meta_urgent_ns) {
296
+		hubbub1->watermarks.b.pte_meta_urgent_ns = watermarks->b.pte_meta_urgent_ns;
291297 		prog_wm_value = convert_and_clamp(watermarks->b.pte_meta_urgent_ns,
292298 				refclk_mhz, 0x1fffff);
293299 		REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
294300 		DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_B calculated =%d\n"
295301 			"HW register value = 0x%x\n",
296302 			watermarks->b.pte_meta_urgent_ns, prog_wm_value);
297
-	}
298
-
299
-	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
300
-		if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
301
-				> hubbub->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) {
302
-			hubbub->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
303
-					watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns;
304
-			prog_wm_value = convert_and_clamp(
305
-					watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
306
-					refclk_mhz, 0x1fffff);
307
-			REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
308
-			DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n"
309
-				"HW register value = 0x%x\n",
310
-				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
311
-		}
312
-
313
-		if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns
314
-				> hubbub->watermarks.b.cstate_pstate.cstate_exit_ns) {
315
-			hubbub->watermarks.b.cstate_pstate.cstate_exit_ns =
316
-					watermarks->b.cstate_pstate.cstate_exit_ns;
317
-			prog_wm_value = convert_and_clamp(
318
-					watermarks->b.cstate_pstate.cstate_exit_ns,
319
-					refclk_mhz, 0x1fffff);
320
-			REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
321
-			DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"
322
-				"HW register value = 0x%x\n",
323
-				watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
324
-		}
325
-	}
326
-
327
-	if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns
328
-			> hubbub->watermarks.b.cstate_pstate.pstate_change_ns) {
329
-		hubbub->watermarks.b.cstate_pstate.pstate_change_ns =
330
-				watermarks->b.cstate_pstate.pstate_change_ns;
331
-		prog_wm_value = convert_and_clamp(
332
-				watermarks->b.cstate_pstate.pstate_change_ns,
333
-				refclk_mhz, 0x1fffff);
334
-		REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
335
-		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n"
336
-			"HW register value = 0x%x\n\n",
337
-			watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
338
-	}
303
+	} else if (watermarks->b.pte_meta_urgent_ns < hubbub1->watermarks.b.pte_meta_urgent_ns)
304
+		wm_pending = true;
339305 
340306 	/* clock state C */
341
-	if (safe_to_lower || watermarks->c.urgent_ns > hubbub->watermarks.c.urgent_ns) {
342
-		hubbub->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
307
+	if (safe_to_lower || watermarks->c.urgent_ns > hubbub1->watermarks.c.urgent_ns) {
308
+		hubbub1->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
343309 		prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns,
344310 				refclk_mhz, 0x1fffff);
345
-		REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
311
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
312
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
346313 
347314 		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n"
348315 			"HW register value = 0x%x\n",
349316 			watermarks->c.urgent_ns, prog_wm_value);
350
-	}
317
+	} else if (watermarks->c.urgent_ns < hubbub1->watermarks.c.urgent_ns)
318
+		wm_pending = true;
351319 
352
-	if (safe_to_lower || watermarks->c.pte_meta_urgent_ns > hubbub->watermarks.c.pte_meta_urgent_ns) {
353
-		hubbub->watermarks.c.pte_meta_urgent_ns = watermarks->c.pte_meta_urgent_ns;
320
+	if (safe_to_lower || watermarks->c.pte_meta_urgent_ns > hubbub1->watermarks.c.pte_meta_urgent_ns) {
321
+		hubbub1->watermarks.c.pte_meta_urgent_ns = watermarks->c.pte_meta_urgent_ns;
354322 		prog_wm_value = convert_and_clamp(watermarks->c.pte_meta_urgent_ns,
355323 				refclk_mhz, 0x1fffff);
356324 		REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
357325 		DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_C calculated =%d\n"
358326 			"HW register value = 0x%x\n",
359327 			watermarks->c.pte_meta_urgent_ns, prog_wm_value);
360
-	}
361
-
362
-	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
363
-		if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
364
-				> hubbub->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) {
365
-			hubbub->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
366
-					watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns;
367
-			prog_wm_value = convert_and_clamp(
368
-					watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
369
-					refclk_mhz, 0x1fffff);
370
-			REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
371
-			DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n"
372
-				"HW register value = 0x%x\n",
373
-				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
374
-		}
375
-
376
-		if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns
377
-				> hubbub->watermarks.c.cstate_pstate.cstate_exit_ns) {
378
-			hubbub->watermarks.c.cstate_pstate.cstate_exit_ns =
379
-					watermarks->c.cstate_pstate.cstate_exit_ns;
380
-			prog_wm_value = convert_and_clamp(
381
-					watermarks->c.cstate_pstate.cstate_exit_ns,
382
-					refclk_mhz, 0x1fffff);
383
-			REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
384
-			DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n"
385
-				"HW register value = 0x%x\n",
386
-				watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
387
-		}
388
-	}
389
-
390
-	if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns
391
-			> hubbub->watermarks.c.cstate_pstate.pstate_change_ns) {
392
-		hubbub->watermarks.c.cstate_pstate.pstate_change_ns =
393
-				watermarks->c.cstate_pstate.pstate_change_ns;
394
-		prog_wm_value = convert_and_clamp(
395
-				watermarks->c.cstate_pstate.pstate_change_ns,
396
-				refclk_mhz, 0x1fffff);
397
-		REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
398
-		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n"
399
-			"HW register value = 0x%x\n\n",
400
-			watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
401
-	}
328
+	} else if (watermarks->c.pte_meta_urgent_ns < hubbub1->watermarks.c.pte_meta_urgent_ns)
329
+		wm_pending = true;
402330 
403331 	/* clock state D */
404
-	if (safe_to_lower || watermarks->d.urgent_ns > hubbub->watermarks.d.urgent_ns) {
405
-		hubbub->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
332
+	if (safe_to_lower || watermarks->d.urgent_ns > hubbub1->watermarks.d.urgent_ns) {
333
+		hubbub1->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
406334 		prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns,
407335 				refclk_mhz, 0x1fffff);
408
-		REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
336
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,
337
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
409338 
410339 		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n"
411340 			"HW register value = 0x%x\n",
412341 			watermarks->d.urgent_ns, prog_wm_value);
413
-	}
342
+	} else if (watermarks->d.urgent_ns < hubbub1->watermarks.d.urgent_ns)
343
+		wm_pending = true;
414344 
415
-	if (safe_to_lower || watermarks->d.pte_meta_urgent_ns > hubbub->watermarks.d.pte_meta_urgent_ns) {
416
-		hubbub->watermarks.d.pte_meta_urgent_ns = watermarks->d.pte_meta_urgent_ns;
345
+	if (safe_to_lower || watermarks->d.pte_meta_urgent_ns > hubbub1->watermarks.d.pte_meta_urgent_ns) {
346
+		hubbub1->watermarks.d.pte_meta_urgent_ns = watermarks->d.pte_meta_urgent_ns;
417347 		prog_wm_value = convert_and_clamp(watermarks->d.pte_meta_urgent_ns,
418348 				refclk_mhz, 0x1fffff);
419349 		REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
420350 		DC_LOG_BANDWIDTH_CALCS("PTE_META_URGENCY_WATERMARK_D calculated =%d\n"
421351 			"HW register value = 0x%x\n",
422352 			watermarks->d.pte_meta_urgent_ns, prog_wm_value);
423
-	}
353
+	} else if (watermarks->d.pte_meta_urgent_ns < hubbub1->watermarks.d.pte_meta_urgent_ns)
354
+		wm_pending = true;
424355 
425
-	if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
426
-		if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
427
-				> hubbub->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) {
428
-			hubbub->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
429
-					watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns;
430
-			prog_wm_value = convert_and_clamp(
431
-					watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
432
-					refclk_mhz, 0x1fffff);
433
-			REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
434
-			DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n"
435
-				"HW register value = 0x%x\n",
436
-				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
437
-		}
356
+	return wm_pending;
357
+}
438358 
439
-		if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns
440
-				> hubbub->watermarks.d.cstate_pstate.cstate_exit_ns) {
441
-			hubbub->watermarks.d.cstate_pstate.cstate_exit_ns =
442
-					watermarks->d.cstate_pstate.cstate_exit_ns;
443
-			prog_wm_value = convert_and_clamp(
444
-					watermarks->d.cstate_pstate.cstate_exit_ns,
445
-					refclk_mhz, 0x1fffff);
446
-			REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
447
-			DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n"
448
-				"HW register value = 0x%x\n",
449
-				watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
450
-		}
451
-	}
359
+bool hubbub1_program_stutter_watermarks(
360
+		struct hubbub *hubbub,
361
+		struct dcn_watermark_set *watermarks,
362
+		unsigned int refclk_mhz,
363
+		bool safe_to_lower)
364
+{
365
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
366
+	uint32_t prog_wm_value;
367
+	bool wm_pending = false;
452368 
369
+	/* clock state A */
370
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
371
+			> hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) {
372
+		hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
373
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns;
374
+		prog_wm_value = convert_and_clamp(
375
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
376
+				refclk_mhz, 0x1fffff);
377
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,
378
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
379
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
380
+			"HW register value = 0x%x\n",
381
+			watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
382
+	} else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
383
+			< hubbub1->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns)
384
+		wm_pending = true;
385
+
386
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns
387
+			> hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns) {
388
+		hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns =
389
+				watermarks->a.cstate_pstate.cstate_exit_ns;
390
+		prog_wm_value = convert_and_clamp(
391
+				watermarks->a.cstate_pstate.cstate_exit_ns,
392
+				refclk_mhz, 0x1fffff);
393
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,
394
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
395
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"
396
+			"HW register value = 0x%x\n",
397
+			watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
398
+	} else if (watermarks->a.cstate_pstate.cstate_exit_ns
399
+			< hubbub1->watermarks.a.cstate_pstate.cstate_exit_ns)
400
+		wm_pending = true;
401
+
402
+	/* clock state B */
403
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
404
+			> hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) {
405
+		hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
406
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns;
407
+		prog_wm_value = convert_and_clamp(
408
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
409
+				refclk_mhz, 0x1fffff);
410
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,
411
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
412
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n"
413
+			"HW register value = 0x%x\n",
414
+			watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
415
+	} else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
416
+			< hubbub1->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns)
417
+		wm_pending = true;
418
+
419
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns
420
+			> hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns) {
421
+		hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns =
422
+				watermarks->b.cstate_pstate.cstate_exit_ns;
423
+		prog_wm_value = convert_and_clamp(
424
+				watermarks->b.cstate_pstate.cstate_exit_ns,
425
+				refclk_mhz, 0x1fffff);
426
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,
427
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
428
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"
429
+			"HW register value = 0x%x\n",
430
+			watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
431
+	} else if (watermarks->b.cstate_pstate.cstate_exit_ns
432
+			< hubbub1->watermarks.b.cstate_pstate.cstate_exit_ns)
433
+		wm_pending = true;
434
+
435
+	/* clock state C */
436
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
437
+			> hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) {
438
+		hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
439
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns;
440
+		prog_wm_value = convert_and_clamp(
441
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
442
+				refclk_mhz, 0x1fffff);
443
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,
444
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
445
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n"
446
+			"HW register value = 0x%x\n",
447
+			watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
448
+	} else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
449
+			< hubbub1->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns)
450
+		wm_pending = true;
451
+
452
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns
453
+			> hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns) {
454
+		hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns =
455
+				watermarks->c.cstate_pstate.cstate_exit_ns;
456
+		prog_wm_value = convert_and_clamp(
457
+				watermarks->c.cstate_pstate.cstate_exit_ns,
458
+				refclk_mhz, 0x1fffff);
459
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0,
460
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
461
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n"
462
+			"HW register value = 0x%x\n",
463
+			watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
464
+	} else if (watermarks->c.cstate_pstate.cstate_exit_ns
465
+			< hubbub1->watermarks.c.cstate_pstate.cstate_exit_ns)
466
+		wm_pending = true;
467
+
468
+	/* clock state D */
469
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
470
+			> hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) {
471
+		hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
472
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns;
473
+		prog_wm_value = convert_and_clamp(
474
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
475
+				refclk_mhz, 0x1fffff);
476
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0,
477
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
478
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n"
479
+			"HW register value = 0x%x\n",
480
+			watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
481
+	} else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
482
+			< hubbub1->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns)
483
+		wm_pending = true;
484
+
485
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns
486
+			> hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns) {
487
+		hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns =
488
+				watermarks->d.cstate_pstate.cstate_exit_ns;
489
+		prog_wm_value = convert_and_clamp(
490
+				watermarks->d.cstate_pstate.cstate_exit_ns,
491
+				refclk_mhz, 0x1fffff);
492
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0,
493
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
494
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n"
495
+			"HW register value = 0x%x\n",
496
+			watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
497
+	} else if (watermarks->d.cstate_pstate.cstate_exit_ns
498
+			< hubbub1->watermarks.d.cstate_pstate.cstate_exit_ns)
499
+		wm_pending = true;
500
+
501
+	return wm_pending;
502
+}
503
+
504
+bool hubbub1_program_pstate_watermarks(
505
+		struct hubbub *hubbub,
506
+		struct dcn_watermark_set *watermarks,
507
+		unsigned int refclk_mhz,
508
+		bool safe_to_lower)
509
+{
510
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
511
+	uint32_t prog_wm_value;
512
+	bool wm_pending = false;
513
+
514
+	/* clock state A */
515
+	if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns
516
+			> hubbub1->watermarks.a.cstate_pstate.pstate_change_ns) {
517
+		hubbub1->watermarks.a.cstate_pstate.pstate_change_ns =
518
+				watermarks->a.cstate_pstate.pstate_change_ns;
519
+		prog_wm_value = convert_and_clamp(
520
+				watermarks->a.cstate_pstate.pstate_change_ns,
521
+				refclk_mhz, 0x1fffff);
522
+		REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0,
523
+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
524
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
525
+			"HW register value = 0x%x\n\n",
526
+			watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
527
+	} else if (watermarks->a.cstate_pstate.pstate_change_ns
528
+			< hubbub1->watermarks.a.cstate_pstate.pstate_change_ns)
529
+		wm_pending = true;
530
+
531
+	/* clock state B */
532
+	if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns
533
+			> hubbub1->watermarks.b.cstate_pstate.pstate_change_ns) {
534
+		hubbub1->watermarks.b.cstate_pstate.pstate_change_ns =
535
+				watermarks->b.cstate_pstate.pstate_change_ns;
536
+		prog_wm_value = convert_and_clamp(
537
+				watermarks->b.cstate_pstate.pstate_change_ns,
538
+				refclk_mhz, 0x1fffff);
539
+		REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0,
540
+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
541
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n"
542
+			"HW register value = 0x%x\n\n",
543
+			watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
544
+	} else if (watermarks->b.cstate_pstate.pstate_change_ns
545
+			< hubbub1->watermarks.b.cstate_pstate.pstate_change_ns)
546
+		wm_pending = true;
547
+
548
+	/* clock state C */
549
+	if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns
550
+			> hubbub1->watermarks.c.cstate_pstate.pstate_change_ns) {
551
+		hubbub1->watermarks.c.cstate_pstate.pstate_change_ns =
552
+				watermarks->c.cstate_pstate.pstate_change_ns;
553
+		prog_wm_value = convert_and_clamp(
554
+				watermarks->c.cstate_pstate.pstate_change_ns,
555
+				refclk_mhz, 0x1fffff);
556
+		REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0,
557
+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
558
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n"
559
+			"HW register value = 0x%x\n\n",
560
+			watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
561
+	} else if (watermarks->c.cstate_pstate.pstate_change_ns
562
+			< hubbub1->watermarks.c.cstate_pstate.pstate_change_ns)
563
+		wm_pending = true;
564
+
565
+	/* clock state D */
453566 	if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns
454
-			> hubbub->watermarks.d.cstate_pstate.pstate_change_ns) {
455
-		hubbub->watermarks.d.cstate_pstate.pstate_change_ns =
567
+			> hubbub1->watermarks.d.cstate_pstate.pstate_change_ns) {
568
+		hubbub1->watermarks.d.cstate_pstate.pstate_change_ns =
456569 				watermarks->d.cstate_pstate.pstate_change_ns;
457570 		prog_wm_value = convert_and_clamp(
458571 				watermarks->d.cstate_pstate.pstate_change_ns,
459572 				refclk_mhz, 0x1fffff);
460
-		REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
573
+		REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0,
574
+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
461575 		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
462576 			"HW register value = 0x%x\n\n",
463577 			watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
464
-	}
578
+	} else if (watermarks->d.cstate_pstate.pstate_change_ns
579
+			< hubbub1->watermarks.d.cstate_pstate.pstate_change_ns)
580
+		wm_pending = true;
581
+
582
+	return wm_pending;
583
+}
584
+
585
+bool hubbub1_program_watermarks(
586
+		struct hubbub *hubbub,
587
+		struct dcn_watermark_set *watermarks,
588
+		unsigned int refclk_mhz,
589
+		bool safe_to_lower)
590
+{
591
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
592
+	bool wm_pending = false;
593
+	/*
594
+	 * Need to clamp to max of the register values (i.e. no wrap)
595
+	 * for dcn1, all wm registers are 21-bit wide
596
+	 */
597
+	if (hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
598
+		wm_pending = true;
599
+
600
+	if (hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
601
+		wm_pending = true;
602
+
603
+	if (hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
604
+		wm_pending = true;
465605 
466606 	REG_UPDATE(DCHUBBUB_ARB_SAT_LEVEL,
467607 			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
468608 	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
469609 			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
470610 
471
-	REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
472
-			DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
473
-			DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
611
+	hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
474612 
475613 #if 0
476614 	REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
477615 			DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, 1,
478616 			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, 1);
479617 #endif
618
+	return wm_pending;
480619 }
481620 
482621 void hubbub1_update_dchub(
483622 	struct hubbub *hubbub,
484623 	struct dchub_init_data *dh_data)
485624 {
625
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
626
+
486627 	if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {
487628 		ASSERT(false);
488629 		/*should not come here*/
....@@ -542,6 +683,8 @@
542683 
543684 void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub)
544685 {
686
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
687
+
545688 	uint32_t watermark_change_req;
546689 
547690 	REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,
....@@ -558,6 +701,8 @@
558701 
559702 void hubbub1_soft_reset(struct hubbub *hubbub, bool reset)
560703 {
704
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
705
+
561706 	uint32_t reset_en = reset ? 1 : 0;
562707 
563708 	REG_UPDATE(DCHUBBUB_SOFT_RESET,
....@@ -700,7 +845,9 @@
700845 		const struct dc_dcc_surface_param *input,
701846 		struct dc_surface_dcc_cap *output)
702847 {
703
-	struct dc *dc = hubbub->ctx->dc;
848
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
849
+	struct dc *dc = hubbub1->base.ctx->dc;
850
+
704851 	/* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
705852 	enum dcc_control dcc_control;
706853 	unsigned int bpe;
....@@ -712,10 +859,10 @@
712859 	if (dc->debug.disable_dcc == DCC_DISABLE)
713860 		return false;
714861 
715
-	if (!hubbub->funcs->dcc_support_pixel_format(input->format, &bpe))
862
+	if (!hubbub1->base.funcs->dcc_support_pixel_format(input->format, &bpe))
716863 		return false;
717864 
718
-	if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
865
+	if (!hubbub1->base.funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
719866 			&segment_order_horz, &segment_order_vert))
720867 		return false;
721868 
....@@ -772,6 +919,9 @@
772919 		output->grph.rgb.max_compressed_blk_size = 64;
773920 		output->grph.rgb.independent_64b_blks = true;
774921 		break;
922
+	default:
923
+		ASSERT(false);
924
+		break;
775925 	}
776926 
777927 	output->capable = true;
....@@ -785,6 +935,10 @@
785935 	.dcc_support_swizzle = hubbub1_dcc_support_swizzle,
786936 	.dcc_support_pixel_format = hubbub1_dcc_support_pixel_format,
787937 	.get_dcc_compression_cap = hubbub1_get_dcc_compression_cap,
938
+	.wm_read_state = hubbub1_wm_read_state,
939
+	.program_watermarks = hubbub1_program_watermarks,
940
+	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
941
+	.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
788942 };
789943 
790944 void hubbub1_construct(struct hubbub *hubbub,
....@@ -793,14 +947,18 @@
793947 	const struct dcn_hubbub_shift *hubbub_shift,
794948 	const struct dcn_hubbub_mask *hubbub_mask)
795949 {
796
-	hubbub->ctx = ctx;
950
+	struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
797951 
798
-	hubbub->funcs = &hubbub1_funcs;
952
+	hubbub1->base.ctx = ctx;
799953 
800
-	hubbub->regs = hubbub_regs;
801
-	hubbub->shifts = hubbub_shift;
802
-	hubbub->masks = hubbub_mask;
954
+	hubbub1->base.funcs = &hubbub1_funcs;
803955 
804
-	hubbub->debug_test_index_pstate = 0x7;
956
+	hubbub1->regs = hubbub_regs;
957
+	hubbub1->shifts = hubbub_shift;
958
+	hubbub1->masks = hubbub_mask;
959
+
960
+	hubbub1->debug_test_index_pstate = 0x7;
961
+	if (ctx->dce_version == DCN_VERSION_1_01)
962
+		hubbub1->debug_test_index_pstate = 0xB;
805963 }
806964