修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h
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@@ -81,6 +81,17 @@
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 	OPP_COMMON_REG_LIST_BASE(id), \
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 	SRI(CONTROL, FMT_MEMORY, id)
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+#define OPP_DCE_60_REG_LIST(id) \
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+	SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
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+	SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
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+	SRI(FMT_CONTROL, FMT, id), \
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+	SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
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+	SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
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+	SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
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+	SRI(FMT_CLAMP_CNTL, FMT, id)
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+#endif
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+
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 #define OPP_SF(reg_name, field_name, post_fix)\
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 	.field_name = reg_name ## __ ## field_name ## post_fix
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@@ -192,6 +203,35 @@
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 	OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\
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 	OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh)
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+#define OPP_COMMON_MASK_SH_LIST_DCE_60(mask_sh)\
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+	OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\
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+	OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
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+	OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\
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+	OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\
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+	OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\
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+	OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\
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+	OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\
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+	OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\
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+	OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh)
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+#endif
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+
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 #define OPP_REG_FIELD_LIST(type) \
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 	type FMT_DYNAMIC_EXP_EN; \
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 	type FMT_DYNAMIC_EXP_MODE; \
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@@ -279,6 +319,15 @@
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 	const struct dce_opp_shift *opp_shift,
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 	const struct dce_opp_mask *opp_mask);
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+#if defined(CONFIG_DRM_AMD_DC_SI)
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+void dce60_opp_construct(struct dce110_opp *opp110,
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+	struct dc_context *ctx,
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+	uint32_t inst,
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+	const struct dce_opp_registers *regs,
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+	const struct dce_opp_shift *opp_shift,
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+	const struct dce_opp_mask *opp_mask);
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+#endif
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+
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 void dce110_opp_destroy(struct output_pixel_processor **opp);
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