forked from ~ljy/RK356X_SDK_RELEASE
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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
....@@ -30,11 +30,6 @@
3030 #include "abm.h"
3131 
3232 #define ABM_COMMON_REG_LIST_DCE_BASE() \
33
-	SR(BL_PWM_PERIOD_CNTL), \
34
-	SR(BL_PWM_CNTL), \
35
-	SR(BL_PWM_CNTL2), \
36
-	SR(BL_PWM_GRP1_REG_LOCK), \
37
-	SR(LVTMA_PWRSEQ_REF_DIV), \
3833 	SR(MASTER_COMM_CNTL_REG), \
3934 	SR(MASTER_COMM_CMD_REG), \
4035 	SR(MASTER_COMM_DATA_REG1)
....@@ -51,6 +46,8 @@
5146 	SR(BL1_PWM_USER_LEVEL), \
5247 	SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
5348 	SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
49
+	SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
50
+	SR(DC_ABM1_ACE_THRES_12), \
5451 	SR(BIOS_SCRATCH_2)
5552 
5653 #define ABM_DCN10_REG_LIST(id)\
....@@ -65,21 +62,48 @@
6562 	SRI(BL1_PWM_USER_LEVEL, ABM, id), \
6663 	SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
6764 	SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
65
+	SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
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+	SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
6867 	NBIO_SR(BIOS_SCRATCH_2)
68
+
69
+#define ABM_DCN20_REG_LIST() \
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+	ABM_COMMON_REG_LIST_DCE_BASE(), \
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+	SR(DC_ABM1_HG_SAMPLE_RATE), \
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+	SR(DC_ABM1_LS_SAMPLE_RATE), \
73
+	SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
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+	SR(DC_ABM1_HG_MISC_CTRL), \
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+	SR(DC_ABM1_IPCSC_COEFF_SEL), \
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+	SR(BL1_PWM_CURRENT_ABM_LEVEL), \
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+	SR(BL1_PWM_TARGET_ABM_LEVEL), \
78
+	SR(BL1_PWM_USER_LEVEL), \
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+	SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
80
+	SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
81
+	SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
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+	SR(DC_ABM1_ACE_THRES_12), \
83
+	NBIO_SR(BIOS_SCRATCH_2)
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+
85
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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+#define ABM_DCN30_REG_LIST(id)\
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+	ABM_COMMON_REG_LIST_DCE_BASE(), \
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+	SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
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+	SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
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+	SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
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+	SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
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+	SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
93
+	SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
94
+	SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
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+	SRI(BL1_PWM_USER_LEVEL, ABM, id), \
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+	SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
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+	SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
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+	SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
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+	SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
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+	NBIO_SR(BIOS_SCRATCH_2)
101
+#endif
69102 
70103 #define ABM_SF(reg_name, field_name, post_fix)\
71104 	.field_name = reg_name ## __ ## field_name ## post_fix
72105 
73106 #define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
74
-	ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
75
-	ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
76
-	ABM_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
77
-	ABM_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
78
-	ABM_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \
79
-	ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
80
-	ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
81
-	ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh), \
82
-	ABM_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
83107 	ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
84108 	ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
85109 	ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
....@@ -147,6 +171,12 @@
147171 	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
148172 			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
149173 
174
+#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
175
+
176
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
177
+#define ABM_MASK_SH_LIST_DCN301(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
178
+#endif
179
+
150180 #define ABM_REG_FIELD_LIST(type) \
151181 	type ABM1_HG_NUM_OF_BINS_SEL; \
152182 	type ABM1_HG_VMAX_SEL; \
....@@ -162,19 +192,10 @@
162192 	type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
163193 	type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
164194 	type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
165
-	type BL_PWM_PERIOD; \
166
-	type BL_PWM_PERIOD_BITCNT; \
167
-	type BL_ACTIVE_INT_FRAC_CNT; \
168
-	type BL_PWM_FRACTIONAL_EN; \
169195 	type MASTER_COMM_INTERRUPT; \
170196 	type MASTER_COMM_CMD_REG_BYTE0; \
171197 	type MASTER_COMM_CMD_REG_BYTE1; \
172
-	type MASTER_COMM_CMD_REG_BYTE2; \
173
-	type BL_PWM_REF_DIV; \
174
-	type BL_PWM_EN; \
175
-	type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
176
-	type BL_PWM_GRP1_REG_LOCK; \
177
-	type BL_PWM_GRP1_REG_UPDATE_PENDING
198
+	type MASTER_COMM_CMD_REG_BYTE2
178199 
179200 struct dce_abm_shift {
180201 	ABM_REG_FIELD_LIST(uint8_t);
....@@ -185,10 +206,6 @@
185206 };
186207 
187208 struct dce_abm_registers {
188
-	uint32_t BL_PWM_PERIOD_CNTL;
189
-	uint32_t BL_PWM_CNTL;
190
-	uint32_t BL_PWM_CNTL2;
191
-	uint32_t LVTMA_PWRSEQ_REF_DIV;
192209 	uint32_t DC_ABM1_HG_SAMPLE_RATE;
193210 	uint32_t DC_ABM1_LS_SAMPLE_RATE;
194211 	uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
....@@ -199,11 +216,12 @@
199216 	uint32_t BL1_PWM_USER_LEVEL;
200217 	uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
201218 	uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
219
+	uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0;
220
+	uint32_t DC_ABM1_ACE_THRES_12;
202221 	uint32_t MASTER_COMM_CNTL_REG;
203222 	uint32_t MASTER_COMM_CMD_REG;
204223 	uint32_t MASTER_COMM_DATA_REG1;
205224 	uint32_t BIOS_SCRATCH_2;
206
-	uint32_t BL_PWM_GRP1_REG_LOCK;
207225 };
208226 
209227 struct dce_abm {