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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
....@@ -23,6 +23,8 @@
2323  *
2424  */
2525 
26
+#include <linux/slab.h>
27
+
2628 #include "dce_abm.h"
2729 #include "dm_services.h"
2830 #include "reg_helper.h"
....@@ -53,156 +55,16 @@
5355 
5456 #define MCP_DISABLE_ABM_IMMEDIATELY 255
5557 
56
-
57
-static unsigned int get_current_backlight_16_bit(struct dce_abm *abm_dce)
58
+static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id, uint32_t panel_inst)
5859 {
59
-	uint64_t current_backlight;
60
-	uint32_t round_result;
61
-	uint32_t pwm_period_cntl, bl_period, bl_int_count;
62
-	uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
63
-	uint32_t bl_period_mask, bl_pwm_mask;
64
-
65
-	pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
66
-	REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
67
-	REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
68
-
69
-	bl_pwm_cntl = REG_READ(BL_PWM_CNTL);
70
-	REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));
71
-	REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
72
-
73
-	if (bl_int_count == 0)
74
-		bl_int_count = 16;
75
-
76
-	bl_period_mask = (1 << bl_int_count) - 1;
77
-	bl_period &= bl_period_mask;
78
-
79
-	bl_pwm_mask = bl_period_mask << (16 - bl_int_count);
80
-
81
-	if (fractional_duty_cycle_en == 0)
82
-		bl_pwm &= bl_pwm_mask;
83
-	else
84
-		bl_pwm &= 0xFFFF;
85
-
86
-	current_backlight = bl_pwm << (1 + bl_int_count);
87
-
88
-	if (bl_period == 0)
89
-		bl_period = 0xFFFF;
90
-
91
-	current_backlight = div_u64(current_backlight, bl_period);
92
-	current_backlight = (current_backlight + 1) >> 1;
93
-
94
-	current_backlight = (uint64_t)(current_backlight) * bl_period;
95
-
96
-	round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);
97
-
98
-	round_result = (round_result >> (bl_int_count-1)) & 1;
99
-
100
-	current_backlight >>= bl_int_count;
101
-	current_backlight += round_result;
102
-
103
-	return (uint32_t)(current_backlight);
104
-}
105
-
106
-static void driver_set_backlight_level(struct dce_abm *abm_dce, uint32_t level)
107
-{
108
-	uint32_t backlight_24bit;
109
-	uint32_t backlight_17bit;
110
-	uint32_t backlight_16bit;
111
-	uint32_t masked_pwm_period;
112
-	uint8_t rounding_bit;
113
-	uint8_t bit_count;
114
-	uint64_t active_duty_cycle;
115
-	uint32_t pwm_period_bitcnt;
116
-
117
-	/*
118
-	 * 1. Convert 8-bit value to 17 bit U1.16 format
119
-	 * (1 integer, 16 fractional bits)
120
-	 */
121
-
122
-	/* 1.1 multiply 8 bit value by 0x10101 to get a 24 bit value,
123
-	 * effectively multiplying value by 256/255
124
-	 * eg. for a level of 0xEF, backlight_24bit = 0xEF * 0x10101 = 0xEFEFEF
125
-	 */
126
-	backlight_24bit = level * 0x10101;
127
-
128
-	/* 1.2 The upper 16 bits of the 24 bit value is the fraction, lower 8
129
-	 * used for rounding, take most significant bit of fraction for
130
-	 * rounding, e.g. for 0xEFEFEF, rounding bit is 1
131
-	 */
132
-	rounding_bit = (backlight_24bit >> 7) & 1;
133
-
134
-	/* 1.3 Add the upper 16 bits of the 24 bit value with the rounding bit
135
-	 * resulting in a 17 bit value e.g. 0xEFF0 = (0xEFEFEF >> 8) + 1
136
-	 */
137
-	backlight_17bit = (backlight_24bit >> 8) + rounding_bit;
138
-
139
-	/*
140
-	 * 2. Find  16 bit backlight active duty cycle, where 0 <= backlight
141
-	 * active duty cycle <= backlight period
142
-	 */
143
-
144
-	/* 2.1 Apply bitmask for backlight period value based on value of BITCNT
145
-	 */
146
-	REG_GET_2(BL_PWM_PERIOD_CNTL,
147
-			BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt,
148
-			BL_PWM_PERIOD, &masked_pwm_period);
149
-
150
-	if (pwm_period_bitcnt == 0)
151
-		bit_count = 16;
152
-	else
153
-		bit_count = pwm_period_bitcnt;
154
-
155
-	/* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
156
-	masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1);
157
-
158
-	/* 2.2 Calculate integer active duty cycle required upper 16 bits
159
-	 * contain integer component, lower 16 bits contain fractional component
160
-	 * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24
161
-	 */
162
-	active_duty_cycle = backlight_17bit * masked_pwm_period;
163
-
164
-	/* 2.3 Calculate 16 bit active duty cycle from integer and fractional
165
-	 * components shift by bitCount then mask 16 bits and add rounding bit
166
-	 * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
167
-	 */
168
-	backlight_16bit = active_duty_cycle >> bit_count;
169
-	backlight_16bit &= 0xFFFF;
170
-	backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
171
-
172
-	/*
173
-	 * 3. Program register with updated value
174
-	 */
175
-
176
-	/* 3.1 Lock group 2 backlight registers */
177
-
178
-	REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,
179
-			BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1,
180
-			BL_PWM_GRP1_REG_LOCK, 1);
181
-
182
-	// 3.2 Write new active duty cycle
183
-	REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);
184
-
185
-	/* 3.3 Unlock group 2 backlight registers */
186
-	REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
187
-			BL_PWM_GRP1_REG_LOCK, 0);
188
-
189
-	/* 5.4.4 Wait for pending bit to be cleared */
190
-	REG_WAIT(BL_PWM_GRP1_REG_LOCK,
191
-			BL_PWM_GRP1_REG_UPDATE_PENDING, 0,
192
-			1, 10000);
193
-}
194
-
195
-static void dmcu_set_backlight_level(
196
-	struct dce_abm *abm_dce,
197
-	uint32_t level,
198
-	uint32_t frame_ramp,
199
-	uint32_t controller_id)
200
-{
201
-	unsigned int backlight_16_bit = (level * 0x10101) >> 8;
202
-	unsigned int backlight_17_bit = backlight_16_bit +
203
-				(((backlight_16_bit & 0x80) >> 7) & 1);
60
+	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
20461 	uint32_t rampingBoundary = 0xFFFF;
205
-	uint32_t s2;
62
+
63
+	if (abm->dmcu_is_running == false)
64
+		return true;
65
+
66
+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
67
+			1, 80000);
20668 
20769 	/* set ramping boundary */
20870 	REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);
....@@ -215,12 +77,37 @@
21577 	/* notifyDMCUMsg */
21678 	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
21779 
80
+	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
81
+			1, 80000);
82
+
83
+	return true;
84
+}
85
+
86
+static void dmcu_set_backlight_level(
87
+	struct dce_abm *abm_dce,
88
+	uint32_t backlight_pwm_u16_16,
89
+	uint32_t frame_ramp,
90
+	uint32_t controller_id,
91
+	uint32_t panel_id)
92
+{
93
+	unsigned int backlight_8_bit = 0;
94
+	uint32_t s2;
95
+
96
+	if (backlight_pwm_u16_16 & 0x10000)
97
+		// Check for max backlight condition
98
+		backlight_8_bit = 0xFF;
99
+	else
100
+		// Take MSB of fractional part since backlight is not max
101
+		backlight_8_bit = (backlight_pwm_u16_16 >> 8) & 0xFF;
102
+
103
+	dce_abm_set_pipe(&abm_dce->base, controller_id, panel_id);
104
+
218105 	/* waitDMCUReadyForCmd */
219106 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,
220107 			0, 1, 80000);
221108 
222109 	/* setDMCUParam_BL */
223
-	REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_17_bit);
110
+	REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_pwm_u16_16);
224111 
225112 	/* write ramp */
226113 	if (controller_id == 0)
....@@ -237,9 +124,9 @@
237124 	s2 = REG_READ(BIOS_SCRATCH_2);
238125 
239126 	s2 &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
240
-	level &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >>
127
+	backlight_8_bit &= (ATOM_S2_CURRENT_BL_LEVEL_MASK >>
241128 				ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
242
-	s2 |= (level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
129
+	s2 |= (backlight_8_bit << ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
243130 
244131 	REG_WRITE(BIOS_SCRATCH_2, s2);
245132 
....@@ -248,10 +135,9 @@
248135 			0, 1, 80000);
249136 }
250137 
251
-static void dce_abm_init(struct abm *abm)
138
+static void dce_abm_init(struct abm *abm, uint32_t backlight)
252139 {
253140 	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
254
-	unsigned int backlight = get_current_backlight_16_bit(abm_dce);
255141 
256142 	REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103);
257143 	REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);
....@@ -288,17 +174,34 @@
288174 			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1);
289175 }
290176 
291
-static unsigned int dce_abm_get_current_backlight_8_bit(struct abm *abm)
177
+static unsigned int dce_abm_get_current_backlight(struct abm *abm)
292178 {
293179 	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
294180 	unsigned int backlight = REG_READ(BL1_PWM_CURRENT_ABM_LEVEL);
295181 
296
-	return (backlight >> 8);
182
+	/* return backlight in hardware format which is unsigned 17 bits, with
183
+	 * 1 bit integer and 16 bit fractional
184
+	 */
185
+	return backlight;
186
+}
187
+
188
+static unsigned int dce_abm_get_target_backlight(struct abm *abm)
189
+{
190
+	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
191
+	unsigned int backlight = REG_READ(BL1_PWM_TARGET_ABM_LEVEL);
192
+
193
+	/* return backlight in hardware format which is unsigned 17 bits, with
194
+	 * 1 bit integer and 16 bit fractional
195
+	 */
196
+	return backlight;
297197 }
298198 
299199 static bool dce_abm_set_level(struct abm *abm, uint32_t level)
300200 {
301201 	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
202
+
203
+	if (abm->dmcu_is_running == false)
204
+		return true;
302205 
303206 	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
304207 			1, 80000);
....@@ -314,112 +217,33 @@
314217 	return true;
315218 }
316219 
317
-static bool dce_abm_immediate_disable(struct abm *abm)
220
+static bool dce_abm_immediate_disable(struct abm *abm, uint32_t panel_inst)
318221 {
319
-	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
222
+	if (abm->dmcu_is_running == false)
223
+		return true;
320224 
321
-	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
322
-			1, 80000);
323
-
324
-	/* setDMCUParam_ABMLevel */
325
-	REG_UPDATE_2(MASTER_COMM_CMD_REG,
326
-			MASTER_COMM_CMD_REG_BYTE0, MCP_ABM_LEVEL_SET,
327
-			MASTER_COMM_CMD_REG_BYTE2, MCP_DISABLE_ABM_IMMEDIATELY);
328
-
329
-	/* notifyDMCUMsg */
330
-	REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1);
331
-
332
-	abm->stored_backlight_registers.BL_PWM_CNTL =
333
-		REG_READ(BL_PWM_CNTL);
334
-	abm->stored_backlight_registers.BL_PWM_CNTL2 =
335
-		REG_READ(BL_PWM_CNTL2);
336
-	abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
337
-		REG_READ(BL_PWM_PERIOD_CNTL);
338
-
339
-	REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
340
-		&abm->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
341
-	return true;
342
-}
343
-
344
-static bool dce_abm_init_backlight(struct abm *abm)
345
-{
346
-	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
347
-	uint32_t value;
348
-
349
-	/* It must not be 0, so we have to restore them
350
-	 * Bios bug w/a - period resets to zero,
351
-	 * restoring to cache values which is always correct
352
-	 */
353
-	REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
354
-	if (value == 0 || value == 1) {
355
-		if (abm->stored_backlight_registers.BL_PWM_CNTL != 0) {
356
-			REG_WRITE(BL_PWM_CNTL,
357
-				abm->stored_backlight_registers.BL_PWM_CNTL);
358
-			REG_WRITE(BL_PWM_CNTL2,
359
-				abm->stored_backlight_registers.BL_PWM_CNTL2);
360
-			REG_WRITE(BL_PWM_PERIOD_CNTL,
361
-				abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
362
-			REG_UPDATE(LVTMA_PWRSEQ_REF_DIV,
363
-				BL_PWM_REF_DIV,
364
-				abm->stored_backlight_registers.
365
-				LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
366
-		} else {
367
-			/* TODO: Note: This should not really happen since VBIOS
368
-			 * should have initialized PWM registers on boot.
369
-			 */
370
-			REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
371
-			REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
372
-		}
373
-	} else {
374
-		abm->stored_backlight_registers.BL_PWM_CNTL =
375
-				REG_READ(BL_PWM_CNTL);
376
-		abm->stored_backlight_registers.BL_PWM_CNTL2 =
377
-				REG_READ(BL_PWM_CNTL2);
378
-		abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
379
-				REG_READ(BL_PWM_PERIOD_CNTL);
380
-
381
-		REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
382
-				&abm->stored_backlight_registers.
383
-				LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
384
-	}
385
-
386
-	/* Have driver take backlight control
387
-	 * TakeBacklightControl(true)
388
-	 */
389
-	value = REG_READ(BIOS_SCRATCH_2);
390
-	value |= ATOM_S2_VRI_BRIGHT_ENABLE;
391
-	REG_WRITE(BIOS_SCRATCH_2, value);
392
-
393
-	/* Enable the backlight output */
394
-	REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
395
-
396
-	/* Unlock group 2 backlight registers */
397
-	REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
398
-			BL_PWM_GRP1_REG_LOCK, 0);
225
+	dce_abm_set_pipe(abm, MCP_DISABLE_ABM_IMMEDIATELY, panel_inst);
399226 
400227 	return true;
401228 }
402229 
403
-static bool dce_abm_set_backlight_level(
230
+static bool dce_abm_set_backlight_level_pwm(
404231 		struct abm *abm,
405
-		unsigned int backlight_level,
232
+		unsigned int backlight_pwm_u16_16,
406233 		unsigned int frame_ramp,
407234 		unsigned int controller_id,
408
-		bool use_smooth_brightness)
235
+		unsigned int panel_inst)
409236 {
410237 	struct dce_abm *abm_dce = TO_DCE_ABM(abm);
411238 
412239 	DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
413
-			backlight_level, backlight_level);
240
+			backlight_pwm_u16_16, backlight_pwm_u16_16);
414241 
415
-	/* If DMCU is in reset state, DMCU is uninitialized */
416
-	if (use_smooth_brightness)
417
-		dmcu_set_backlight_level(abm_dce,
418
-				backlight_level,
419
-				frame_ramp,
420
-				controller_id);
421
-	else
422
-		driver_set_backlight_level(abm_dce, backlight_level);
242
+	dmcu_set_backlight_level(abm_dce,
243
+			backlight_pwm_u16_16,
244
+			frame_ramp,
245
+			controller_id,
246
+			panel_inst);
423247 
424248 	return true;
425249 }
....@@ -427,10 +251,12 @@
427251 static const struct abm_funcs dce_funcs = {
428252 	.abm_init = dce_abm_init,
429253 	.set_abm_level = dce_abm_set_level,
430
-	.init_backlight = dce_abm_init_backlight,
431
-	.set_backlight_level = dce_abm_set_backlight_level,
432
-	.get_current_backlight_8_bit = dce_abm_get_current_backlight_8_bit,
433
-	.set_abm_immediate_disable = dce_abm_immediate_disable
254
+	.set_pipe = dce_abm_set_pipe,
255
+	.set_backlight_level_pwm = dce_abm_set_backlight_level_pwm,
256
+	.get_current_backlight = dce_abm_get_current_backlight,
257
+	.get_target_backlight = dce_abm_get_target_backlight,
258
+	.init_abm_config = NULL,
259
+	.set_abm_immediate_disable = dce_abm_immediate_disable,
434260 };
435261 
436262 static void dce_abm_construct(
....@@ -444,10 +270,7 @@
444270 
445271 	base->ctx = ctx;
446272 	base->funcs = &dce_funcs;
447
-	base->stored_backlight_registers.BL_PWM_CNTL = 0;
448
-	base->stored_backlight_registers.BL_PWM_CNTL2 = 0;
449
-	base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0;
450
-	base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0;
273
+	base->dmcu_is_running = false;
451274 
452275 	abm_dce->regs = regs;
453276 	abm_dce->abm_shift = abm_shift;
....@@ -460,7 +283,7 @@
460283 	const struct dce_abm_shift *abm_shift,
461284 	const struct dce_abm_mask *abm_mask)
462285 {
463
-	struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL);
286
+	struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_ATOMIC);
464287 
465288 	if (abm_dce == NULL) {
466289 		BREAK_TO_DEBUGGER();
....@@ -477,8 +300,6 @@
477300 void dce_abm_destroy(struct abm **abm)
478301 {
479302 	struct dce_abm *abm_dce = TO_DCE_ABM(*abm);
480
-
481
-	abm_dce->base.funcs->set_abm_immediate_disable(*abm);
482303 
483304 	kfree(abm_dce);
484305 	*abm = NULL;