.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * linux/arch/arm/plat-pxa/gpio.c |
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3 | 4 | * |
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.. | .. |
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6 | 7 | * Author: Nicolas Pitre |
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7 | 8 | * Created: Jun 15, 2001 |
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8 | 9 | * Copyright: MontaVista Software Inc. |
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9 | | - * |
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10 | | - * This program is free software; you can redistribute it and/or modify |
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11 | | - * it under the terms of the GNU General Public License version 2 as |
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12 | | - * published by the Free Software Foundation. |
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13 | 10 | */ |
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14 | 11 | #include <linux/module.h> |
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15 | 12 | #include <linux/clk.h> |
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.. | .. |
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246 | 243 | switch (gpio_type) { |
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247 | 244 | case PXA3XX_GPIO: |
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248 | 245 | case MMP2_GPIO: |
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| 246 | + case MMP_GPIO: |
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249 | 247 | return false; |
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250 | 248 | |
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251 | 249 | default: |
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.. | .. |
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364 | 362 | pchip->chip.set = pxa_gpio_set; |
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365 | 363 | pchip->chip.to_irq = pxa_gpio_to_irq; |
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366 | 364 | pchip->chip.ngpio = ngpio; |
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367 | | - |
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368 | | - if (pxa_gpio_has_pinctrl()) { |
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369 | | - pchip->chip.request = gpiochip_generic_request; |
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370 | | - pchip->chip.free = gpiochip_generic_free; |
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371 | | - } |
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| 365 | + pchip->chip.request = gpiochip_generic_request; |
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| 366 | + pchip->chip.free = gpiochip_generic_free; |
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372 | 367 | |
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373 | 368 | #ifdef CONFIG_OF_GPIO |
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374 | 369 | pchip->chip.of_node = np; |
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.. | .. |
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577 | 572 | return 0; |
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578 | 573 | } |
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579 | 574 | |
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580 | | -const struct irq_domain_ops pxa_irq_domain_ops = { |
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| 575 | +static const struct irq_domain_ops pxa_irq_domain_ops = { |
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581 | 576 | .map = pxa_irq_domain_map, |
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582 | 577 | .xlate = irq_domain_xlate_twocell, |
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583 | 578 | }; |
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.. | .. |
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622 | 617 | { |
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623 | 618 | struct pxa_gpio_chip *pchip; |
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624 | 619 | struct pxa_gpio_bank *c; |
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625 | | - struct resource *res; |
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626 | 620 | struct clk *clk; |
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627 | 621 | struct pxa_gpio_platform_data *info; |
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628 | 622 | void __iomem *gpio_reg_base; |
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.. | .. |
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656 | 650 | if (!pchip->irqdomain) |
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657 | 651 | return -ENOMEM; |
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658 | 652 | |
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659 | | - irq0 = platform_get_irq_byname(pdev, "gpio0"); |
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660 | | - irq1 = platform_get_irq_byname(pdev, "gpio1"); |
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| 653 | + irq0 = platform_get_irq_byname_optional(pdev, "gpio0"); |
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| 654 | + irq1 = platform_get_irq_byname_optional(pdev, "gpio1"); |
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661 | 655 | irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); |
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662 | 656 | if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) |
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663 | 657 | || (irq_mux <= 0)) |
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.. | .. |
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665 | 659 | |
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666 | 660 | pchip->irq0 = irq0; |
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667 | 661 | pchip->irq1 = irq1; |
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668 | | - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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669 | | - if (!res) |
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670 | | - return -EINVAL; |
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671 | | - gpio_reg_base = devm_ioremap(&pdev->dev, res->start, |
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672 | | - resource_size(res)); |
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673 | | - if (!gpio_reg_base) |
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674 | | - return -EINVAL; |
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| 662 | + |
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| 663 | + gpio_reg_base = devm_platform_ioremap_resource(pdev, 0); |
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| 664 | + if (IS_ERR(gpio_reg_base)) |
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| 665 | + return PTR_ERR(gpio_reg_base); |
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675 | 666 | |
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676 | 667 | clk = clk_get(&pdev->dev, NULL); |
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677 | 668 | if (IS_ERR(clk)) { |
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.. | .. |
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816 | 807 | #define pxa_gpio_resume NULL |
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817 | 808 | #endif |
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818 | 809 | |
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819 | | -struct syscore_ops pxa_gpio_syscore_ops = { |
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| 810 | +static struct syscore_ops pxa_gpio_syscore_ops = { |
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820 | 811 | .suspend = pxa_gpio_suspend, |
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821 | 812 | .resume = pxa_gpio_resume, |
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822 | 813 | }; |
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