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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/drivers/dma/stm32-mdma.c
....@@ -1,24 +1,13 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  *
34  * Copyright (C) STMicroelectronics SA 2017
45  * Author(s): M'boumba Cedric Madianga <cedric.madianga@gmail.com>
56  *            Pierre-Yves Mordret <pierre-yves.mordret@st.com>
67  *
7
- * License terms: GPL V2.0.
8
- *
9
- * This program is free software; you can redistribute it and/or modify it
10
- * under the terms of the GNU General Public License version 2 as published by
11
- * the Free Software Foundation.
12
- *
13
- * This program is distributed in the hope that it will be useful, but
14
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
16
- * details.
17
- *
188  * Driver for STM32 MDMA controller
199  *
2010  * Inspired by stm32-dma.c and dma-jz4780.c
21
- *
2211  */
2312 
2413 #include <linux/clk.h>
....@@ -37,6 +26,7 @@
3726 #include <linux/of_device.h>
3827 #include <linux/of_dma.h>
3928 #include <linux/platform_device.h>
29
+#include <linux/pm_runtime.h>
4030 #include <linux/reset.h>
4131 #include <linux/slab.h>
4232 
....@@ -50,7 +40,6 @@
5040 					 STM32_MDMA_SHIFT(mask))
5141 
5242 #define STM32_MDMA_GISR0		0x0000 /* MDMA Int Status Reg 1 */
53
-#define STM32_MDMA_GISR1		0x0004 /* MDMA Int Status Reg 2 */
5443 
5544 /* MDMA Channel x interrupt/status register */
5645 #define STM32_MDMA_CISR(x)		(0x40 + 0x40 * (x)) /* x = 0..62 */
....@@ -206,7 +195,7 @@
206195 
207196 #define STM32_MDMA_MAX_BUF_LEN		128
208197 #define STM32_MDMA_MAX_BLOCK_LEN	65536
209
-#define STM32_MDMA_MAX_CHANNELS		63
198
+#define STM32_MDMA_MAX_CHANNELS		32
210199 #define STM32_MDMA_MAX_REQUESTS		256
211200 #define STM32_MDMA_MAX_BURST		128
212201 #define STM32_MDMA_VERY_HIGH_PRIORITY	0x11
....@@ -283,7 +272,6 @@
283272 	void __iomem *base;
284273 	struct clk *clk;
285274 	int irq;
286
-	struct reset_control *rst;
287275 	u32 nr_channels;
288276 	u32 nr_requests;
289277 	u32 nr_ahb_addr_masks;
....@@ -1356,90 +1344,84 @@
13561344 static irqreturn_t stm32_mdma_irq_handler(int irq, void *devid)
13571345 {
13581346 	struct stm32_mdma_device *dmadev = devid;
1359
-	struct stm32_mdma_chan *chan = devid;
1360
-	u32 reg, id, ien, status, flag;
1347
+	struct stm32_mdma_chan *chan;
1348
+	u32 reg, id, ccr, ien, status;
13611349 
13621350 	/* Find out which channel generates the interrupt */
13631351 	status = readl_relaxed(dmadev->base + STM32_MDMA_GISR0);
1364
-	if (status) {
1365
-		id = __ffs(status);
1366
-	} else {
1367
-		status = readl_relaxed(dmadev->base + STM32_MDMA_GISR1);
1368
-		if (!status) {
1369
-			dev_dbg(mdma2dev(dmadev), "spurious it\n");
1370
-			return IRQ_NONE;
1371
-		}
1372
-		id = __ffs(status);
1373
-		/*
1374
-		 * As GISR0 provides status for channel id from 0 to 31,
1375
-		 * so GISR1 provides status for channel id from 32 to 62
1376
-		 */
1377
-		id += 32;
1352
+	if (!status) {
1353
+		dev_dbg(mdma2dev(dmadev), "spurious it\n");
1354
+		return IRQ_NONE;
13781355 	}
1356
+	id = __ffs(status);
13791357 
13801358 	chan = &dmadev->chan[id];
13811359 	if (!chan) {
1382
-		dev_dbg(mdma2dev(dmadev), "MDMA channel not initialized\n");
1383
-		goto exit;
1360
+		dev_warn(mdma2dev(dmadev), "MDMA channel not initialized\n");
1361
+		return IRQ_NONE;
13841362 	}
13851363 
13861364 	/* Handle interrupt for the channel */
13871365 	spin_lock(&chan->vchan.lock);
1388
-	status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(chan->id));
1389
-	ien = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id));
1390
-	ien &= STM32_MDMA_CCR_IRQ_MASK;
1391
-	ien >>= 1;
1366
+	status = stm32_mdma_read(dmadev, STM32_MDMA_CISR(id));
1367
+	/* Mask Channel ReQuest Active bit which can be set in case of MEM2MEM */
1368
+	status &= ~STM32_MDMA_CISR_CRQA;
1369
+	ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(id));
1370
+	ien = (ccr & STM32_MDMA_CCR_IRQ_MASK) >> 1;
13921371 
13931372 	if (!(status & ien)) {
13941373 		spin_unlock(&chan->vchan.lock);
1395
-		dev_dbg(chan2dev(chan),
1396
-			"spurious it (status=0x%04x, ien=0x%04x)\n",
1397
-			status, ien);
1374
+		dev_warn(chan2dev(chan),
1375
+			 "spurious it (status=0x%04x, ien=0x%04x)\n",
1376
+			 status, ien);
13981377 		return IRQ_NONE;
13991378 	}
14001379 
1401
-	flag = __ffs(status & ien);
1402
-	reg = STM32_MDMA_CIFCR(chan->id);
1380
+	reg = STM32_MDMA_CIFCR(id);
14031381 
1404
-	switch (1 << flag) {
1405
-	case STM32_MDMA_CISR_TEIF:
1406
-		id = chan->id;
1407
-		status = readl_relaxed(dmadev->base + STM32_MDMA_CESR(id));
1408
-		dev_err(chan2dev(chan), "Transfer Err: stat=0x%08x\n", status);
1382
+	if (status & STM32_MDMA_CISR_TEIF) {
1383
+		dev_err(chan2dev(chan), "Transfer Err: stat=0x%08x\n",
1384
+			readl_relaxed(dmadev->base + STM32_MDMA_CESR(id)));
14091385 		stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CTEIF);
1410
-		break;
1386
+		status &= ~STM32_MDMA_CISR_TEIF;
1387
+	}
14111388 
1412
-	case STM32_MDMA_CISR_CTCIF:
1389
+	if (status & STM32_MDMA_CISR_CTCIF) {
14131390 		stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CCTCIF);
1391
+		status &= ~STM32_MDMA_CISR_CTCIF;
14141392 		stm32_mdma_xfer_end(chan);
1415
-		break;
1393
+	}
14161394 
1417
-	case STM32_MDMA_CISR_BRTIF:
1395
+	if (status & STM32_MDMA_CISR_BRTIF) {
14181396 		stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CBRTIF);
1419
-		break;
1397
+		status &= ~STM32_MDMA_CISR_BRTIF;
1398
+	}
14201399 
1421
-	case STM32_MDMA_CISR_BTIF:
1400
+	if (status & STM32_MDMA_CISR_BTIF) {
14221401 		stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CBTIF);
1402
+		status &= ~STM32_MDMA_CISR_BTIF;
14231403 		chan->curr_hwdesc++;
14241404 		if (chan->desc && chan->desc->cyclic) {
14251405 			if (chan->curr_hwdesc == chan->desc->count)
14261406 				chan->curr_hwdesc = 0;
14271407 			vchan_cyclic_callback(&chan->desc->vdesc);
14281408 		}
1429
-		break;
1409
+	}
14301410 
1431
-	case STM32_MDMA_CISR_TCIF:
1411
+	if (status & STM32_MDMA_CISR_TCIF) {
14321412 		stm32_mdma_set_bits(dmadev, reg, STM32_MDMA_CIFCR_CLTCIF);
1433
-		break;
1413
+		status &= ~STM32_MDMA_CISR_TCIF;
1414
+	}
14341415 
1435
-	default:
1436
-		dev_err(chan2dev(chan), "it %d unhandled (status=0x%04x)\n",
1437
-			1 << flag, status);
1416
+	if (status) {
1417
+		stm32_mdma_set_bits(dmadev, reg, status);
1418
+		dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
1419
+		if (!(ccr & STM32_MDMA_CCR_EN))
1420
+			dev_err(chan2dev(chan), "chan disabled by HW\n");
14381421 	}
14391422 
14401423 	spin_unlock(&chan->vchan.lock);
14411424 
1442
-exit:
14431425 	return IRQ_HANDLED;
14441426 }
14451427 
....@@ -1459,15 +1441,13 @@
14591441 		return -ENOMEM;
14601442 	}
14611443 
1462
-	ret = clk_prepare_enable(dmadev->clk);
1463
-	if (ret < 0) {
1464
-		dev_err(chan2dev(chan), "clk_prepare_enable failed: %d\n", ret);
1444
+	ret = pm_runtime_resume_and_get(dmadev->ddev.dev);
1445
+	if (ret < 0)
14651446 		return ret;
1466
-	}
14671447 
14681448 	ret = stm32_mdma_disable_chan(chan);
14691449 	if (ret < 0)
1470
-		clk_disable_unprepare(dmadev->clk);
1450
+		pm_runtime_put(dmadev->ddev.dev);
14711451 
14721452 	return ret;
14731453 }
....@@ -1487,7 +1467,7 @@
14871467 		spin_unlock_irqrestore(&chan->vchan.lock, flags);
14881468 	}
14891469 
1490
-	clk_disable_unprepare(dmadev->clk);
1470
+	pm_runtime_put(dmadev->ddev.dev);
14911471 	vchan_free_chan_resources(to_virt_chan(c));
14921472 	dmam_pool_destroy(chan->desc_pool);
14931473 	chan->desc_pool = NULL;
....@@ -1547,6 +1527,7 @@
15471527 	struct dma_device *dd;
15481528 	struct device_node *of_node;
15491529 	struct resource *res;
1530
+	struct reset_control *rst;
15501531 	u32 nr_channels, nr_requests;
15511532 	int i, count, ret;
15521533 
....@@ -1570,8 +1551,7 @@
15701551 			 nr_requests);
15711552 	}
15721553 
1573
-	count = device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
1574
-					       NULL, 0);
1554
+	count = device_property_count_u32(&pdev->dev, "st,ahb-addr-masks");
15751555 	if (count < 0)
15761556 		count = 0;
15771557 
....@@ -1593,18 +1573,25 @@
15931573 		return PTR_ERR(dmadev->base);
15941574 
15951575 	dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1596
-	if (IS_ERR(dmadev->clk)) {
1597
-		ret = PTR_ERR(dmadev->clk);
1598
-		if (ret == -EPROBE_DEFER)
1599
-			dev_info(&pdev->dev, "Missing controller clock\n");
1576
+	if (IS_ERR(dmadev->clk))
1577
+		return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk),
1578
+				     "Missing clock controller\n");
1579
+
1580
+	ret = clk_prepare_enable(dmadev->clk);
1581
+	if (ret < 0) {
1582
+		dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
16001583 		return ret;
16011584 	}
16021585 
1603
-	dmadev->rst = devm_reset_control_get(&pdev->dev, NULL);
1604
-	if (!IS_ERR(dmadev->rst)) {
1605
-		reset_control_assert(dmadev->rst);
1586
+	rst = devm_reset_control_get(&pdev->dev, NULL);
1587
+	if (IS_ERR(rst)) {
1588
+		ret = PTR_ERR(rst);
1589
+		if (ret == -EPROBE_DEFER)
1590
+			goto err_clk;
1591
+	} else {
1592
+		reset_control_assert(rst);
16061593 		udelay(2);
1607
-		reset_control_deassert(dmadev->rst);
1594
+		reset_control_deassert(rst);
16081595 	}
16091596 
16101597 	dd = &dmadev->ddev;
....@@ -1624,6 +1611,8 @@
16241611 	dd->device_resume = stm32_mdma_resume;
16251612 	dd->device_terminate_all = stm32_mdma_terminate_all;
16261613 	dd->device_synchronize = stm32_mdma_synchronize;
1614
+	dd->descriptor_reuse = true;
1615
+
16271616 	dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
16281617 		BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
16291618 		BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
....@@ -1648,45 +1637,113 @@
16481637 
16491638 	dmadev->irq = platform_get_irq(pdev, 0);
16501639 	if (dmadev->irq < 0) {
1651
-		dev_err(&pdev->dev, "failed to get IRQ\n");
1652
-		return dmadev->irq;
1640
+		ret = dmadev->irq;
1641
+		goto err_clk;
16531642 	}
16541643 
16551644 	ret = devm_request_irq(&pdev->dev, dmadev->irq, stm32_mdma_irq_handler,
16561645 			       0, dev_name(&pdev->dev), dmadev);
16571646 	if (ret) {
16581647 		dev_err(&pdev->dev, "failed to request IRQ\n");
1659
-		return ret;
1648
+		goto err_clk;
16601649 	}
16611650 
1662
-	ret = dma_async_device_register(dd);
1651
+	ret = dmaenginem_async_device_register(dd);
16631652 	if (ret)
1664
-		return ret;
1653
+		goto err_clk;
16651654 
16661655 	ret = of_dma_controller_register(of_node, stm32_mdma_of_xlate, dmadev);
16671656 	if (ret < 0) {
16681657 		dev_err(&pdev->dev,
16691658 			"STM32 MDMA DMA OF registration failed %d\n", ret);
1670
-		goto err_unregister;
1659
+		goto err_clk;
16711660 	}
16721661 
16731662 	platform_set_drvdata(pdev, dmadev);
1663
+	pm_runtime_set_active(&pdev->dev);
1664
+	pm_runtime_enable(&pdev->dev);
1665
+	pm_runtime_get_noresume(&pdev->dev);
1666
+	pm_runtime_put(&pdev->dev);
16741667 
16751668 	dev_info(&pdev->dev, "STM32 MDMA driver registered\n");
16761669 
16771670 	return 0;
16781671 
1679
-err_unregister:
1680
-	dma_async_device_unregister(dd);
1672
+err_clk:
1673
+	clk_disable_unprepare(dmadev->clk);
16811674 
16821675 	return ret;
16831676 }
1677
+
1678
+#ifdef CONFIG_PM
1679
+static int stm32_mdma_runtime_suspend(struct device *dev)
1680
+{
1681
+	struct stm32_mdma_device *dmadev = dev_get_drvdata(dev);
1682
+
1683
+	clk_disable_unprepare(dmadev->clk);
1684
+
1685
+	return 0;
1686
+}
1687
+
1688
+static int stm32_mdma_runtime_resume(struct device *dev)
1689
+{
1690
+	struct stm32_mdma_device *dmadev = dev_get_drvdata(dev);
1691
+	int ret;
1692
+
1693
+	ret = clk_prepare_enable(dmadev->clk);
1694
+	if (ret) {
1695
+		dev_err(dev, "failed to prepare_enable clock\n");
1696
+		return ret;
1697
+	}
1698
+
1699
+	return 0;
1700
+}
1701
+#endif
1702
+
1703
+#ifdef CONFIG_PM_SLEEP
1704
+static int stm32_mdma_pm_suspend(struct device *dev)
1705
+{
1706
+	struct stm32_mdma_device *dmadev = dev_get_drvdata(dev);
1707
+	u32 ccr, id;
1708
+	int ret;
1709
+
1710
+	ret = pm_runtime_resume_and_get(dev);
1711
+	if (ret < 0)
1712
+		return ret;
1713
+
1714
+	for (id = 0; id < dmadev->nr_channels; id++) {
1715
+		ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(id));
1716
+		if (ccr & STM32_MDMA_CCR_EN) {
1717
+			dev_warn(dev, "Suspend is prevented by Chan %i\n", id);
1718
+			return -EBUSY;
1719
+		}
1720
+	}
1721
+
1722
+	pm_runtime_put_sync(dev);
1723
+
1724
+	pm_runtime_force_suspend(dev);
1725
+
1726
+	return 0;
1727
+}
1728
+
1729
+static int stm32_mdma_pm_resume(struct device *dev)
1730
+{
1731
+	return pm_runtime_force_resume(dev);
1732
+}
1733
+#endif
1734
+
1735
+static const struct dev_pm_ops stm32_mdma_pm_ops = {
1736
+	SET_SYSTEM_SLEEP_PM_OPS(stm32_mdma_pm_suspend, stm32_mdma_pm_resume)
1737
+	SET_RUNTIME_PM_OPS(stm32_mdma_runtime_suspend,
1738
+			   stm32_mdma_runtime_resume, NULL)
1739
+};
16841740 
16851741 static struct platform_driver stm32_mdma_driver = {
16861742 	.probe = stm32_mdma_probe,
16871743 	.driver = {
16881744 		.name = "stm32-mdma",
16891745 		.of_match_table = stm32_mdma_of_match,
1746
+		.pm = &stm32_mdma_pm_ops,
16901747 	},
16911748 };
16921749