hc
2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5
kernel/drivers/clk/qcom/apcs-msm8916.c
....@@ -19,9 +19,9 @@
1919
2020 static const u32 gpll0_a53cc_map[] = { 4, 5 };
2121
22
-static const char * const gpll0_a53cc[] = {
23
- "gpll0_vote",
24
- "a53pll",
22
+static const struct clk_parent_data pdata[] = {
23
+ { .fw_name = "aux", .name = "gpll0_vote", },
24
+ { .fw_name = "pll", .name = "a53pll", },
2525 };
2626
2727 /*
....@@ -62,8 +62,8 @@
6262 return -ENOMEM;
6363
6464 init.name = "a53mux";
65
- init.parent_names = gpll0_a53cc;
66
- init.num_parents = ARRAY_SIZE(gpll0_a53cc);
65
+ init.parent_data = pdata;
66
+ init.num_parents = ARRAY_SIZE(pdata);
6767 init.ops = &clk_regmap_mux_div_ops;
6868 init.flags = CLK_SET_RATE_PARENT;
6969
....@@ -79,7 +79,8 @@
7979 a53cc->pclk = devm_clk_get(parent, NULL);
8080 if (IS_ERR(a53cc->pclk)) {
8181 ret = PTR_ERR(a53cc->pclk);
82
- dev_err(dev, "failed to get clk: %d\n", ret);
82
+ if (ret != -EPROBE_DEFER)
83
+ dev_err(dev, "failed to get clk: %d\n", ret);
8384 return ret;
8485 }
8586
....@@ -96,8 +97,8 @@
9697 goto err;
9798 }
9899
99
- ret = of_clk_add_hw_provider(parent->of_node, of_clk_hw_simple_get,
100
- &a53cc->clkr.hw);
100
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
101
+ &a53cc->clkr.hw);
101102 if (ret) {
102103 dev_err(dev, "failed to add clock provider: %d\n", ret);
103104 goto err;
....@@ -115,10 +116,8 @@
115116 static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev)
116117 {
117118 struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev);
118
- struct device *parent = pdev->dev.parent;
119119
120120 clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb);
121
- of_clk_del_provider(parent->of_node);
122121
123122 return 0;
124123 }