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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/arch/ia64/include/asm/pgtable.h
....@@ -279,16 +279,16 @@
279279 #define pud_bad(pud)			(!ia64_phys_addr_valid(pud_val(pud)))
280280 #define pud_present(pud)		(pud_val(pud) != 0UL)
281281 #define pud_clear(pudp)			(pud_val(*(pudp)) = 0UL)
282
-#define pud_page_vaddr(pud)		((unsigned long) __va(pud_val(pud) & _PFN_MASK))
282
+#define pud_pgtable(pud)		((pmd_t *) __va(pud_val(pud) & _PFN_MASK))
283283 #define pud_page(pud)			virt_to_page((pud_val(pud) + PAGE_OFFSET))
284284 
285285 #if CONFIG_PGTABLE_LEVELS == 4
286
-#define pgd_none(pgd)			(!pgd_val(pgd))
287
-#define pgd_bad(pgd)			(!ia64_phys_addr_valid(pgd_val(pgd)))
288
-#define pgd_present(pgd)		(pgd_val(pgd) != 0UL)
289
-#define pgd_clear(pgdp)			(pgd_val(*(pgdp)) = 0UL)
290
-#define pgd_page_vaddr(pgd)		((unsigned long) __va(pgd_val(pgd) & _PFN_MASK))
291
-#define pgd_page(pgd)			virt_to_page((pgd_val(pgd) + PAGE_OFFSET))
286
+#define p4d_none(p4d)			(!p4d_val(p4d))
287
+#define p4d_bad(p4d)			(!ia64_phys_addr_valid(p4d_val(p4d)))
288
+#define p4d_present(p4d)		(p4d_val(p4d) != 0UL)
289
+#define p4d_clear(p4dp)			(p4d_val(*(p4dp)) = 0UL)
290
+#define p4d_pgtable(p4d)		((pud_t *) __va(p4d_val(p4d) & _PFN_MASK))
291
+#define p4d_page(p4d)			virt_to_page((p4d_val(p4d) + PAGE_OFFSET))
292292 #endif
293293 
294294 /*
....@@ -298,7 +298,6 @@
298298 #define pte_exec(pte)		((pte_val(pte) & _PAGE_AR_RX) != 0)
299299 #define pte_dirty(pte)		((pte_val(pte) & _PAGE_D) != 0)
300300 #define pte_young(pte)		((pte_val(pte) & _PAGE_A) != 0)
301
-#define pte_special(pte)	0
302301 
303302 /*
304303  * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
....@@ -311,7 +310,6 @@
311310 #define pte_mkclean(pte)	(__pte(pte_val(pte) & ~_PAGE_D))
312311 #define pte_mkdirty(pte)	(__pte(pte_val(pte) | _PAGE_D))
313312 #define pte_mkhuge(pte)		(__pte(pte_val(pte)))
314
-#define pte_mkspecial(pte)	(pte)
315313 
316314 /*
317315  * Because ia64's Icache and Dcache is not coherent (on a cpu), we need to
....@@ -366,17 +364,14 @@
366364 
367365 	return (region << (PAGE_SHIFT - 6)) | l1index;
368366 }
367
+#define pgd_index pgd_index
369368 
370
-/* The offset in the 1-level directory is given by the 3 region bits
371
-   (61..63) and the level-1 bits.  */
372
-static inline pgd_t*
373
-pgd_offset (const struct mm_struct *mm, unsigned long address)
374
-{
375
-	return mm->pgd + pgd_index(address);
376
-}
377
-
378
-/* In the kernel's mapped region we completely ignore the region number
379
-   (since we know it's in region number 5). */
369
+/*
370
+ * In the kernel's mapped region we know everything is in region number 5, so
371
+ * as an optimisation its PGD already points to the area for that region.
372
+ * However, this also means that we cannot use pgd_index() and we must
373
+ * never add the region here.
374
+ */
380375 #define pgd_offset_k(addr) \
381376 	(init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
382377 
....@@ -384,25 +379,6 @@
384379    resides in the kernel-mapped segment, hence we use pgd_offset_k()
385380    here.  */
386381 #define pgd_offset_gate(mm, addr)	pgd_offset_k(addr)
387
-
388
-#if CONFIG_PGTABLE_LEVELS == 4
389
-/* Find an entry in the second-level page table.. */
390
-#define pud_offset(dir,addr) \
391
-	((pud_t *) pgd_page_vaddr(*(dir)) + (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
392
-#endif
393
-
394
-/* Find an entry in the third-level page table.. */
395
-#define pmd_offset(dir,addr) \
396
-	((pmd_t *) pud_page_vaddr(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
397
-
398
-/*
399
- * Find an entry in the third-level page table.  This looks more complicated than it
400
- * should be because some platforms place page tables in high memory.
401
- */
402
-#define pte_index(addr)	 	(((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
403
-#define pte_offset_kernel(dir,addr)	((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
404
-#define pte_offset_map(dir,addr)	pte_offset_kernel(dir, addr)
405
-#define pte_unmap(pte)			do { } while (0)
406382 
407383 /* atomic versions of the some PTE manipulations: */
408384 
....@@ -544,9 +520,9 @@
544520 
545521 #  ifdef CONFIG_VIRTUAL_MEM_MAP
546522   /* arch mem_map init routine is needed due to holes in a virtual mem_map */
547
-#   define __HAVE_ARCH_MEMMAP_INIT
548
-    extern void memmap_init (unsigned long size, int nid, unsigned long zone,
549
-			     unsigned long start_pfn);
523
+void memmap_init(void);
524
+void arch_memmap_init(unsigned long size, int nid, unsigned long zone,
525
+		      unsigned long start_pfn);
550526 #  endif /* CONFIG_VIRTUAL_MEM_MAP */
551527 # endif /* !__ASSEMBLY__ */
552528 
....@@ -567,11 +543,6 @@
567543 #define KERNEL_TR_PAGE_SHIFT	_PAGE_SIZE_64M
568544 #define KERNEL_TR_PAGE_SIZE	(1 << KERNEL_TR_PAGE_SHIFT)
569545 
570
-/*
571
- * No page table caches to initialise
572
- */
573
-#define pgtable_cache_init()	do { } while (0)
574
-
575546 /* These tell get_user_pages() that the first gate page is accessible from user-level.  */
576547 #define FIXADDR_USER_START	GATE_ADDR
577548 #ifdef HAVE_BUGGY_SEGREL
....@@ -588,10 +559,8 @@
588559 
589560 
590561 #if CONFIG_PGTABLE_LEVELS == 3
591
-#define __ARCH_USE_5LEVEL_HACK
592562 #include <asm-generic/pgtable-nopud.h>
593563 #endif
594
-#include <asm-generic/5level-fixup.h>
595
-#include <asm-generic/pgtable.h>
564
+#include <asm-generic/pgtable-nop4d.h>
596565 
597566 #endif /* _ASM_IA64_PGTABLE_H */