hc
2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5
kernel/arch/arm64/include/uapi/asm/sigcontext.h
....@@ -77,6 +77,15 @@
7777 __uint128_t vregs[32];
7878 };
7979
80
+/*
81
+ * Note: similarly to all other integer fields, each V-register is stored in an
82
+ * endianness-dependent format, with the byte at offset i from the start of the
83
+ * in-memory representation of the register value containing
84
+ *
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+ * bits [(7 + 8 * i) : (8 * i)] of the register on little-endian hosts; or
86
+ * bits [(127 - 8 * i) : (120 - 8 * i)] on big-endian hosts.
87
+ */
88
+
8089 /* ESR_EL1 context */
8190 #define ESR_MAGIC 0x45535201
8291
....@@ -130,29 +139,30 @@
130139
131140 #endif /* !__ASSEMBLY__ */
132141
142
+#include <asm/sve_context.h>
143
+
133144 /*
134145 * The SVE architecture leaves space for future expansion of the
135146 * vector length beyond its initial architectural limit of 2048 bits
136147 * (16 quadwords).
137148 *
138
- * See linux/Documentation/arm64/sve.txt for a description of the VL/VQ
149
+ * See linux/Documentation/arm64/sve.rst for a description of the VL/VQ
139150 * terminology.
140151 */
141
-#define SVE_VQ_BYTES 16 /* number of bytes per quadword */
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+#define SVE_VQ_BYTES __SVE_VQ_BYTES /* bytes per quadword */
142153
143
-#define SVE_VQ_MIN 1
144
-#define SVE_VQ_MAX 512
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+#define SVE_VQ_MIN __SVE_VQ_MIN
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+#define SVE_VQ_MAX __SVE_VQ_MAX
145156
146
-#define SVE_VL_MIN (SVE_VQ_MIN * SVE_VQ_BYTES)
147
-#define SVE_VL_MAX (SVE_VQ_MAX * SVE_VQ_BYTES)
157
+#define SVE_VL_MIN __SVE_VL_MIN
158
+#define SVE_VL_MAX __SVE_VL_MAX
148159
149
-#define SVE_NUM_ZREGS 32
150
-#define SVE_NUM_PREGS 16
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+#define SVE_NUM_ZREGS __SVE_NUM_ZREGS
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+#define SVE_NUM_PREGS __SVE_NUM_PREGS
151162
152
-#define sve_vl_valid(vl) \
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- ((vl) % SVE_VQ_BYTES == 0 && (vl) >= SVE_VL_MIN && (vl) <= SVE_VL_MAX)
154
-#define sve_vq_from_vl(vl) ((vl) / SVE_VQ_BYTES)
155
-#define sve_vl_from_vq(vq) ((vq) * SVE_VQ_BYTES)
163
+#define sve_vl_valid(vl) __sve_vl_valid(vl)
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+#define sve_vq_from_vl(vl) __sve_vq_from_vl(vl)
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+#define sve_vl_from_vq(vq) __sve_vl_from_vq(vq)
156166
157167 /*
158168 * If the SVE registers are currently live for the thread at signal delivery,
....@@ -169,7 +179,7 @@
169179 * The same convention applies when returning from a signal: a caller
170180 * will need to remove or resize the sve_context block if it wants to
171181 * make the SVE registers live when they were previously non-live or
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- * vice-versa. This may require the the caller to allocate fresh
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+ * vice-versa. This may require the caller to allocate fresh
173183 * memory and/or move other context blocks in the signal frame.
174184 *
175185 * Changing the vector length during signal return is not permitted:
....@@ -203,36 +213,40 @@
203213 * FFR uint16_t[vq] first-fault status register
204214 *
205215 * Additional data might be appended in the future.
216
+ *
217
+ * Unlike vregs[] in fpsimd_context, each SVE scalable register (Z-, P- or FFR)
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+ * is encoded in memory in an endianness-invariant format, with the byte at
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+ * offset i from the start of the in-memory representation containing bits
220
+ * [(7 + 8 * i) : (8 * i)] of the register value.
206221 */
207222
208
-#define SVE_SIG_ZREG_SIZE(vq) ((__u32)(vq) * SVE_VQ_BYTES)
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-#define SVE_SIG_PREG_SIZE(vq) ((__u32)(vq) * (SVE_VQ_BYTES / 8))
210
-#define SVE_SIG_FFR_SIZE(vq) SVE_SIG_PREG_SIZE(vq)
223
+#define SVE_SIG_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
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+#define SVE_SIG_PREG_SIZE(vq) __SVE_PREG_SIZE(vq)
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+#define SVE_SIG_FFR_SIZE(vq) __SVE_FFR_SIZE(vq)
211226
212227 #define SVE_SIG_REGS_OFFSET \
213
- ((sizeof(struct sve_context) + (SVE_VQ_BYTES - 1)) \
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- / SVE_VQ_BYTES * SVE_VQ_BYTES)
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+ ((sizeof(struct sve_context) + (__SVE_VQ_BYTES - 1)) \
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+ / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
215230
216
-#define SVE_SIG_ZREGS_OFFSET SVE_SIG_REGS_OFFSET
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+#define SVE_SIG_ZREGS_OFFSET \
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+ (SVE_SIG_REGS_OFFSET + __SVE_ZREGS_OFFSET)
217233 #define SVE_SIG_ZREG_OFFSET(vq, n) \
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- (SVE_SIG_ZREGS_OFFSET + SVE_SIG_ZREG_SIZE(vq) * (n))
219
-#define SVE_SIG_ZREGS_SIZE(vq) \
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- (SVE_SIG_ZREG_OFFSET(vq, SVE_NUM_ZREGS) - SVE_SIG_ZREGS_OFFSET)
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+ (SVE_SIG_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
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+#define SVE_SIG_ZREGS_SIZE(vq) __SVE_ZREGS_SIZE(vq)
221236
222237 #define SVE_SIG_PREGS_OFFSET(vq) \
223
- (SVE_SIG_ZREGS_OFFSET + SVE_SIG_ZREGS_SIZE(vq))
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+ (SVE_SIG_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
224239 #define SVE_SIG_PREG_OFFSET(vq, n) \
225
- (SVE_SIG_PREGS_OFFSET(vq) + SVE_SIG_PREG_SIZE(vq) * (n))
226
-#define SVE_SIG_PREGS_SIZE(vq) \
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- (SVE_SIG_PREG_OFFSET(vq, SVE_NUM_PREGS) - SVE_SIG_PREGS_OFFSET(vq))
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+ (SVE_SIG_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
241
+#define SVE_SIG_PREGS_SIZE(vq) __SVE_PREGS_SIZE(vq)
228242
229243 #define SVE_SIG_FFR_OFFSET(vq) \
230
- (SVE_SIG_PREGS_OFFSET(vq) + SVE_SIG_PREGS_SIZE(vq))
244
+ (SVE_SIG_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
231245
232246 #define SVE_SIG_REGS_SIZE(vq) \
233
- (SVE_SIG_FFR_OFFSET(vq) + SVE_SIG_FFR_SIZE(vq) - SVE_SIG_REGS_OFFSET)
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+ (__SVE_FFR_OFFSET(vq) + __SVE_FFR_SIZE(vq))
234248
235
-#define SVE_SIG_CONTEXT_SIZE(vq) (SVE_SIG_REGS_OFFSET + SVE_SIG_REGS_SIZE(vq))
236
-
249
+#define SVE_SIG_CONTEXT_SIZE(vq) \
250
+ (SVE_SIG_REGS_OFFSET + SVE_SIG_REGS_SIZE(vq))
237251
238252 #endif /* _UAPI__ASM_SIGCONTEXT_H */