.. | .. |
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77 | 77 | __uint128_t vregs[32]; |
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78 | 78 | }; |
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79 | 79 | |
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| 80 | +/* |
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| 81 | + * Note: similarly to all other integer fields, each V-register is stored in an |
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| 82 | + * endianness-dependent format, with the byte at offset i from the start of the |
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| 83 | + * in-memory representation of the register value containing |
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| 84 | + * |
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| 85 | + * bits [(7 + 8 * i) : (8 * i)] of the register on little-endian hosts; or |
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| 86 | + * bits [(127 - 8 * i) : (120 - 8 * i)] on big-endian hosts. |
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| 87 | + */ |
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| 88 | + |
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80 | 89 | /* ESR_EL1 context */ |
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81 | 90 | #define ESR_MAGIC 0x45535201 |
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82 | 91 | |
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.. | .. |
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130 | 139 | |
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131 | 140 | #endif /* !__ASSEMBLY__ */ |
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132 | 141 | |
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| 142 | +#include <asm/sve_context.h> |
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| 143 | + |
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133 | 144 | /* |
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134 | 145 | * The SVE architecture leaves space for future expansion of the |
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135 | 146 | * vector length beyond its initial architectural limit of 2048 bits |
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136 | 147 | * (16 quadwords). |
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137 | 148 | * |
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138 | | - * See linux/Documentation/arm64/sve.txt for a description of the VL/VQ |
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| 149 | + * See linux/Documentation/arm64/sve.rst for a description of the VL/VQ |
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139 | 150 | * terminology. |
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140 | 151 | */ |
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141 | | -#define SVE_VQ_BYTES 16 /* number of bytes per quadword */ |
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| 152 | +#define SVE_VQ_BYTES __SVE_VQ_BYTES /* bytes per quadword */ |
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142 | 153 | |
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143 | | -#define SVE_VQ_MIN 1 |
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144 | | -#define SVE_VQ_MAX 512 |
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| 154 | +#define SVE_VQ_MIN __SVE_VQ_MIN |
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| 155 | +#define SVE_VQ_MAX __SVE_VQ_MAX |
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145 | 156 | |
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146 | | -#define SVE_VL_MIN (SVE_VQ_MIN * SVE_VQ_BYTES) |
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147 | | -#define SVE_VL_MAX (SVE_VQ_MAX * SVE_VQ_BYTES) |
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| 157 | +#define SVE_VL_MIN __SVE_VL_MIN |
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| 158 | +#define SVE_VL_MAX __SVE_VL_MAX |
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148 | 159 | |
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149 | | -#define SVE_NUM_ZREGS 32 |
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150 | | -#define SVE_NUM_PREGS 16 |
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| 160 | +#define SVE_NUM_ZREGS __SVE_NUM_ZREGS |
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| 161 | +#define SVE_NUM_PREGS __SVE_NUM_PREGS |
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151 | 162 | |
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152 | | -#define sve_vl_valid(vl) \ |
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153 | | - ((vl) % SVE_VQ_BYTES == 0 && (vl) >= SVE_VL_MIN && (vl) <= SVE_VL_MAX) |
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154 | | -#define sve_vq_from_vl(vl) ((vl) / SVE_VQ_BYTES) |
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155 | | -#define sve_vl_from_vq(vq) ((vq) * SVE_VQ_BYTES) |
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| 163 | +#define sve_vl_valid(vl) __sve_vl_valid(vl) |
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| 164 | +#define sve_vq_from_vl(vl) __sve_vq_from_vl(vl) |
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| 165 | +#define sve_vl_from_vq(vq) __sve_vl_from_vq(vq) |
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156 | 166 | |
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157 | 167 | /* |
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158 | 168 | * If the SVE registers are currently live for the thread at signal delivery, |
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.. | .. |
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169 | 179 | * The same convention applies when returning from a signal: a caller |
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170 | 180 | * will need to remove or resize the sve_context block if it wants to |
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171 | 181 | * make the SVE registers live when they were previously non-live or |
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172 | | - * vice-versa. This may require the the caller to allocate fresh |
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| 182 | + * vice-versa. This may require the caller to allocate fresh |
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173 | 183 | * memory and/or move other context blocks in the signal frame. |
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174 | 184 | * |
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175 | 185 | * Changing the vector length during signal return is not permitted: |
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.. | .. |
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203 | 213 | * FFR uint16_t[vq] first-fault status register |
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204 | 214 | * |
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205 | 215 | * Additional data might be appended in the future. |
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| 216 | + * |
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| 217 | + * Unlike vregs[] in fpsimd_context, each SVE scalable register (Z-, P- or FFR) |
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| 218 | + * is encoded in memory in an endianness-invariant format, with the byte at |
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| 219 | + * offset i from the start of the in-memory representation containing bits |
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| 220 | + * [(7 + 8 * i) : (8 * i)] of the register value. |
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206 | 221 | */ |
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207 | 222 | |
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208 | | -#define SVE_SIG_ZREG_SIZE(vq) ((__u32)(vq) * SVE_VQ_BYTES) |
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209 | | -#define SVE_SIG_PREG_SIZE(vq) ((__u32)(vq) * (SVE_VQ_BYTES / 8)) |
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210 | | -#define SVE_SIG_FFR_SIZE(vq) SVE_SIG_PREG_SIZE(vq) |
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| 223 | +#define SVE_SIG_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq) |
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| 224 | +#define SVE_SIG_PREG_SIZE(vq) __SVE_PREG_SIZE(vq) |
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| 225 | +#define SVE_SIG_FFR_SIZE(vq) __SVE_FFR_SIZE(vq) |
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211 | 226 | |
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212 | 227 | #define SVE_SIG_REGS_OFFSET \ |
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213 | | - ((sizeof(struct sve_context) + (SVE_VQ_BYTES - 1)) \ |
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214 | | - / SVE_VQ_BYTES * SVE_VQ_BYTES) |
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| 228 | + ((sizeof(struct sve_context) + (__SVE_VQ_BYTES - 1)) \ |
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| 229 | + / __SVE_VQ_BYTES * __SVE_VQ_BYTES) |
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215 | 230 | |
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216 | | -#define SVE_SIG_ZREGS_OFFSET SVE_SIG_REGS_OFFSET |
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| 231 | +#define SVE_SIG_ZREGS_OFFSET \ |
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| 232 | + (SVE_SIG_REGS_OFFSET + __SVE_ZREGS_OFFSET) |
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217 | 233 | #define SVE_SIG_ZREG_OFFSET(vq, n) \ |
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218 | | - (SVE_SIG_ZREGS_OFFSET + SVE_SIG_ZREG_SIZE(vq) * (n)) |
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219 | | -#define SVE_SIG_ZREGS_SIZE(vq) \ |
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220 | | - (SVE_SIG_ZREG_OFFSET(vq, SVE_NUM_ZREGS) - SVE_SIG_ZREGS_OFFSET) |
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| 234 | + (SVE_SIG_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n)) |
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| 235 | +#define SVE_SIG_ZREGS_SIZE(vq) __SVE_ZREGS_SIZE(vq) |
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221 | 236 | |
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222 | 237 | #define SVE_SIG_PREGS_OFFSET(vq) \ |
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223 | | - (SVE_SIG_ZREGS_OFFSET + SVE_SIG_ZREGS_SIZE(vq)) |
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| 238 | + (SVE_SIG_REGS_OFFSET + __SVE_PREGS_OFFSET(vq)) |
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224 | 239 | #define SVE_SIG_PREG_OFFSET(vq, n) \ |
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225 | | - (SVE_SIG_PREGS_OFFSET(vq) + SVE_SIG_PREG_SIZE(vq) * (n)) |
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226 | | -#define SVE_SIG_PREGS_SIZE(vq) \ |
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227 | | - (SVE_SIG_PREG_OFFSET(vq, SVE_NUM_PREGS) - SVE_SIG_PREGS_OFFSET(vq)) |
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| 240 | + (SVE_SIG_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n)) |
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| 241 | +#define SVE_SIG_PREGS_SIZE(vq) __SVE_PREGS_SIZE(vq) |
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228 | 242 | |
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229 | 243 | #define SVE_SIG_FFR_OFFSET(vq) \ |
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230 | | - (SVE_SIG_PREGS_OFFSET(vq) + SVE_SIG_PREGS_SIZE(vq)) |
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| 244 | + (SVE_SIG_REGS_OFFSET + __SVE_FFR_OFFSET(vq)) |
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231 | 245 | |
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232 | 246 | #define SVE_SIG_REGS_SIZE(vq) \ |
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233 | | - (SVE_SIG_FFR_OFFSET(vq) + SVE_SIG_FFR_SIZE(vq) - SVE_SIG_REGS_OFFSET) |
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| 247 | + (__SVE_FFR_OFFSET(vq) + __SVE_FFR_SIZE(vq)) |
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234 | 248 | |
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235 | | -#define SVE_SIG_CONTEXT_SIZE(vq) (SVE_SIG_REGS_OFFSET + SVE_SIG_REGS_SIZE(vq)) |
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236 | | - |
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| 249 | +#define SVE_SIG_CONTEXT_SIZE(vq) \ |
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| 250 | + (SVE_SIG_REGS_OFFSET + SVE_SIG_REGS_SIZE(vq)) |
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237 | 251 | |
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238 | 252 | #endif /* _UAPI__ASM_SIGCONTEXT_H */ |
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