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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/arch/arm64/boot/dts/qcom/msm8994.dtsi
....@@ -1,25 +1,11 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
2
- *
3
- * This program is free software; you can redistribute it and/or modify
4
- * it under the terms of the GNU General Public License version 2 and
5
- * only version 2 as published by the Free Software Foundation.
6
- *
7
- * This program is distributed in the hope that it will be useful,
8
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
9
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10
- * GNU General Public License for more details.
113  */
124 
135 #include <dt-bindings/interrupt-controller/arm-gic.h>
146 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
157 
168 / {
17
-	model = "Qualcomm Technologies, Inc. MSM 8994";
18
-	compatible = "qcom,msm8994";
19
-	// msm-id and pmic-id are required by bootloader for
20
-	// proper selection of dt blob
21
-	qcom,msm-id = <207 0x20000>;
22
-	qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
239 	interrupt-parent = <&intc>;
2410 
2511 	#address-cells = <2>;
....@@ -27,35 +13,196 @@
2713 
2814 	chosen { };
2915 
16
+	clocks {
17
+		xo_board: xo-board {
18
+			compatible = "fixed-clock";
19
+			#clock-cells = <0>;
20
+			clock-frequency = <19200000>;
21
+			clock-output-names = "xo_board";
22
+		};
23
+
24
+		sleep_clk: sleep-clk {
25
+			compatible = "fixed-clock";
26
+			#clock-cells = <0>;
27
+			clock-frequency = <32768>;
28
+			clock-output-names = "sleep_clk";
29
+		};
30
+	};
31
+
3032 	cpus {
31
-		#address-cells = <1>;
33
+		#address-cells = <2>;
3234 		#size-cells = <0>;
35
+
36
+		CPU0: cpu@0 {
37
+			device_type = "cpu";
38
+			compatible = "arm,cortex-a53";
39
+			reg = <0x0 0x0>;
40
+			enable-method = "psci";
41
+			next-level-cache = <&L2_0>;
42
+			L2_0: l2-cache {
43
+				compatible = "cache";
44
+				cache-level = <2>;
45
+			};
46
+		};
47
+
48
+		CPU1: cpu@1 {
49
+			device_type = "cpu";
50
+			compatible = "arm,cortex-a53";
51
+			reg = <0x0 0x1>;
52
+			enable-method = "psci";
53
+			next-level-cache = <&L2_0>;
54
+		};
55
+
56
+		CPU2: cpu@2 {
57
+			device_type = "cpu";
58
+			compatible = "arm,cortex-a53";
59
+			reg = <0x0 0x2>;
60
+			enable-method = "psci";
61
+			next-level-cache = <&L2_0>;
62
+		};
63
+
64
+		CPU3: cpu@3 {
65
+			device_type = "cpu";
66
+			compatible = "arm,cortex-a53";
67
+			reg = <0x0 0x3>;
68
+			enable-method = "psci";
69
+			next-level-cache = <&L2_0>;
70
+		};
71
+
72
+		CPU4: cpu@100 {
73
+			device_type = "cpu";
74
+			compatible = "arm,cortex-a57";
75
+			reg = <0x0 0x100>;
76
+			enable-method = "psci";
77
+			next-level-cache = <&L2_1>;
78
+			L2_1: l2-cache {
79
+				compatible = "cache";
80
+				cache-level = <2>;
81
+			};
82
+		};
83
+
84
+		CPU5: cpu@101 {
85
+			device_type = "cpu";
86
+			compatible = "arm,cortex-a57";
87
+			reg = <0x0 0x101>;
88
+			enable-method = "psci";
89
+			next-level-cache = <&L2_1>;
90
+		};
91
+
92
+		CPU6: cpu@102 {
93
+			device_type = "cpu";
94
+			compatible = "arm,cortex-a57";
95
+			reg = <0x0 0x102>;
96
+			enable-method = "psci";
97
+			next-level-cache = <&L2_1>;
98
+		};
99
+
100
+		CPU7: cpu@103 {
101
+			device_type = "cpu";
102
+			compatible = "arm,cortex-a57";
103
+			reg = <0x0 0x103>;
104
+			enable-method = "psci";
105
+			next-level-cache = <&L2_1>;
106
+		};
107
+
33108 		cpu-map {
34109 			cluster0 {
35110 				core0 {
36111 					cpu = <&CPU0>;
37112 				};
38
-			};
39
-		};
40113 
41
-		CPU0: cpu@0 {
42
-			device_type = "cpu";
43
-			compatible = "arm,cortex-a53", "arm,armv8";
44
-			reg = <0x0>;
45
-			next-level-cache = <&L2_0>;
46
-			L2_0: l2-cache {
47
-			      compatible = "cache";
48
-			      cache-level = <2>;
114
+				core1 {
115
+					cpu = <&CPU1>;
116
+				};
117
+
118
+				core2 {
119
+					cpu = <&CPU2>;
120
+				};
121
+
122
+				core3 {
123
+					cpu = <&CPU3>;
124
+				};
125
+			};
126
+
127
+			cluster1 {
128
+				core0 {
129
+					cpu = <&CPU4>;
130
+				};
131
+
132
+				core1 {
133
+					cpu = <&CPU5>;
134
+				};
135
+
136
+				core2 {
137
+					cpu = <&CPU6>;
138
+				};
139
+
140
+				core3 {
141
+					cpu = <&CPU7>;
142
+				};
49143 			};
50144 		};
51145 	};
52146 
53
-	timer {
54
-		compatible = "arm,armv8-timer";
55
-		interrupts = <1 2 0xff08>,
56
-			     <1 3 0xff08>,
57
-			     <1 4 0xff08>,
58
-			     <1 1 0xff08>;
147
+	firmware {
148
+		scm {
149
+			compatible = "qcom,scm-msm8994", "qcom,scm";
150
+		};
151
+	};
152
+
153
+	memory {
154
+		device_type = "memory";
155
+		/* We expect the bootloader to fill in the reg */
156
+		reg = <0 0 0 0>;
157
+	};
158
+
159
+	pmu {
160
+		compatible = "arm,cortex-a53-pmu";
161
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
162
+	};
163
+
164
+	psci {
165
+		compatible = "arm,psci-0.2";
166
+		method = "hvc";
167
+	};
168
+
169
+	reserved-memory {
170
+		#address-cells = <2>;
171
+		#size-cells = <2>;
172
+		ranges;
173
+
174
+		smem_mem: smem_region@6a00000 {
175
+			reg = <0x0 0x6a00000 0x0 0x200000>;
176
+			no-map;
177
+		};
178
+	};
179
+
180
+	smd {
181
+		compatible = "qcom,smd";
182
+		rpm {
183
+			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
184
+			qcom,ipc = <&apcs 8 0>;
185
+			qcom,smd-edge = <15>;
186
+			qcom,local-pid = <0>;
187
+			qcom,remote-pid = <6>;
188
+
189
+			rpm_requests: rpm-requests {
190
+				compatible = "qcom,rpm-msm8994";
191
+				qcom,smd-channels = "rpm_requests";
192
+
193
+				rpmcc: rpmcc {
194
+					compatible = "qcom,rpmcc-msm8994";
195
+					#clock-cells = <1>;
196
+				};
197
+			};
198
+		};
199
+	};
200
+
201
+	smem {
202
+		compatible = "qcom,smem";
203
+		memory-region = <&smem_mem>;
204
+		qcom,rpm-msg-ram = <&rpm_msg_ram>;
205
+		hwlocks = <&tcsr_mutex 3>;
59206 	};
60207 
61208 	soc: soc {
....@@ -70,7 +217,13 @@
70217 			interrupt-controller;
71218 			#interrupt-cells = <3>;
72219 			reg = <0xf9000000 0x1000>,
73
-				  <0xf9002000 0x1000>;
220
+			      <0xf9002000 0x1000>;
221
+		};
222
+
223
+		apcs: mailbox@f900d000 {
224
+			compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
225
+			reg = <0xf900d000 0x2000>;
226
+			#mbox-cells = <1>;
74227 		};
75228 
76229 		timer@f9020000 {
....@@ -131,29 +284,225 @@
131284 			};
132285 		};
133286 
134
-		restart@fc4ab000 {
135
-			compatible = "qcom,pshold";
136
-			reg = <0xfc4ab000 0x4>;
287
+		sdhc1: sdhci@f9824900 {
288
+			compatible = "qcom,sdhci-msm-v4";
289
+			reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
290
+			reg-names = "hc_mem", "core_mem";
291
+
292
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
293
+				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
294
+			interrupt-names = "hc_irq", "pwr_irq";
295
+
296
+			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
297
+			         <&gcc GCC_SDCC1_AHB_CLK>,
298
+				 <&xo_board>;
299
+			clock-names = "core", "iface", "xo";
300
+
301
+			pinctrl-names = "default", "sleep";
302
+			pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
303
+			pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
304
+
305
+			bus-width = <8>;
306
+			non-removable;
307
+			status = "disabled";
137308 		};
138309 
139
-		msmgpio: pinctrl@fd510000 {
140
-			compatible = "qcom,msm8994-pinctrl";
141
-			reg = <0xfd510000 0x4000>;
142
-			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
143
-			gpio-controller;
144
-			#gpio-cells = <2>;
145
-			interrupt-controller;
146
-			#interrupt-cells = <2>;
310
+		blsp1_dma: dma@f9904000 {
311
+			compatible = "qcom,bam-v1.7.0";
312
+			reg = <0xf9904000 0x19000>;
313
+			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
314
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
315
+			clock-names = "bam_clk";
316
+			#dma-cells = <1>;
317
+			qcom,ee = <0>;
318
+			qcom,controlled-remotely;
319
+			num-channels = <24>;
320
+			qcom,num-ees = <4>;
147321 		};
148322 
149323 		blsp1_uart2: serial@f991e000 {
150324 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
151325 			reg = <0xf991e000 0x1000>;
152326 			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
153
-			status = "disabled";
154327 			clock-names = "core", "iface";
155
-			clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
156
-				 <&clock_gcc GCC_BLSP1_AHB_CLK>;
328
+			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
329
+				 <&gcc GCC_BLSP1_AHB_CLK>;
330
+			pinctrl-names = "default", "sleep";
331
+			pinctrl-0 = <&blsp1_uart2_default>;
332
+			pinctrl-1 = <&blsp1_uart2_sleep>;
333
+			status = "disabled";
334
+		};
335
+
336
+		blsp_i2c1: i2c@f9923000 {
337
+			compatible = "qcom,i2c-qup-v2.2.1";
338
+			reg = <0xf9923000 0x500>;
339
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
340
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
341
+						<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
342
+			clock-names = "iface", "core";
343
+			clock-frequency = <400000>;
344
+			pinctrl-names = "default", "sleep";
345
+			pinctrl-0 = <&i2c1_default>;
346
+			pinctrl-1 = <&i2c1_sleep>;
347
+			#address-cells = <1>;
348
+			#size-cells = <0>;
349
+			status = "disabled";
350
+		};
351
+
352
+		blsp_spi0: spi@f9923000 {
353
+			compatible = "qcom,spi-qup-v2.2.1";
354
+			reg = <0xf9923000 0x500>;
355
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
356
+			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
357
+				 <&gcc GCC_BLSP1_AHB_CLK>;
358
+			clock-names = "core", "iface";
359
+			spi-max-frequency = <19200000>;
360
+			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
361
+			dma-names = "tx", "rx";
362
+			pinctrl-names = "default", "sleep";
363
+			pinctrl-0 = <&blsp1_spi0_default>;
364
+			pinctrl-1 = <&blsp1_spi0_sleep>;
365
+			#address-cells = <1>;
366
+			#size-cells = <0>;
367
+			status = "disabled";
368
+		};
369
+
370
+		blsp_i2c2: i2c@f9924000 {
371
+			compatible = "qcom,i2c-qup-v2.2.1";
372
+			reg = <0xf9924000 0x500>;
373
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
374
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
375
+						<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
376
+			clock-names = "iface", "core";
377
+			clock-frequency = <355000>;
378
+			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
379
+			dma-names = "tx", "rx";
380
+			pinctrl-names = "default", "sleep";
381
+			pinctrl-0 = <&i2c2_default>;
382
+			pinctrl-1 = <&i2c2_sleep>;
383
+			#address-cells = <1>;
384
+			#size-cells = <0>;
385
+			status = "disabled";
386
+		};
387
+
388
+		/* I2C3 doesn't exist */
389
+
390
+		blsp_i2c4: i2c@f9926000 {
391
+			compatible = "qcom,i2c-qup-v2.2.1";
392
+			reg = <0xf9926000 0x500>;
393
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
394
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
395
+						<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
396
+			clock-names = "iface", "core";
397
+			clock-frequency = <355000>;
398
+			pinctrl-names = "default", "sleep";
399
+			pinctrl-0 = <&i2c4_default>;
400
+			pinctrl-1 = <&i2c4_sleep>;
401
+			#address-cells = <1>;
402
+			#size-cells = <0>;
403
+			status = "disabled";
404
+		};
405
+
406
+		blsp2_dma: dma@f9944000 {
407
+			compatible = "qcom,bam-v1.7.0";
408
+			reg = <0xf9944000 0x19000>;
409
+			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
410
+			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
411
+			clock-names = "bam_clk";
412
+			#dma-cells = <1>;
413
+			qcom,ee = <0>;
414
+			qcom,controlled-remotely;
415
+			num-channels = <24>;
416
+			qcom,num-ees = <4>;
417
+		};
418
+
419
+		/* According to downstream kernels, i2c6
420
+		 * comes before i2c5 address-wise...
421
+		 */
422
+
423
+		blsp_i2c6: i2c@f9928000 {
424
+			compatible = "qcom,i2c-qup-v2.2.1";
425
+			reg = <0xf9928000 0x500>;
426
+			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
427
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
428
+						<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
429
+			clock-names = "iface", "core";
430
+			clock-frequency = <355000>;
431
+			dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
432
+			dma-names = "tx", "rx";
433
+			pinctrl-names = "default", "sleep";
434
+			pinctrl-0 = <&i2c6_default>;
435
+			pinctrl-1 = <&i2c6_sleep>;
436
+			#address-cells = <1>;
437
+			#size-cells = <0>;
438
+			status = "disabled";
439
+		};
440
+
441
+		blsp2_uart2: serial@f995e000 {
442
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
443
+			reg = <0xf995e000 0x1000>;
444
+			interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_FALLING>;
445
+			clock-names = "core", "iface";
446
+			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
447
+					<&gcc GCC_BLSP2_AHB_CLK>;
448
+			dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
449
+			dma-names = "tx", "rx";
450
+			pinctrl-names = "default", "sleep";
451
+			pinctrl-0 = <&blsp2_uart2_default>;
452
+			pinctrl-1 = <&blsp2_uart2_sleep>;
453
+			status = "disabled";
454
+		};
455
+
456
+		blsp_i2c5: i2c@f9967000 {
457
+			compatible = "qcom,i2c-qup-v2.2.1";
458
+			reg = <0xf9967000 0x500>;
459
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
460
+			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
461
+						<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
462
+			clock-names = "iface", "core";
463
+			clock-frequency = <355000>;
464
+			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
465
+			dma-names = "tx", "rx";
466
+			pinctrl-names = "default", "sleep";
467
+			pinctrl-0 = <&i2c5_default>;
468
+			pinctrl-1 = <&i2c5_sleep>;
469
+			#address-cells = <1>;
470
+			#size-cells = <0>;
471
+			status = "disabled";
472
+		};
473
+
474
+		gcc: clock-controller@fc400000 {
475
+			compatible = "qcom,gcc-msm8994";
476
+			#clock-cells = <1>;
477
+			#reset-cells = <1>;
478
+			#power-domain-cells = <1>;
479
+			reg = <0xfc400000 0x2000>;
480
+		};
481
+
482
+		rpm_msg_ram: memory@fc428000 {
483
+			compatible = "qcom,rpm-msg-ram";
484
+			reg = <0xfc428000 0x4000>;
485
+		};
486
+
487
+		restart@fc4ab000 {
488
+			compatible = "qcom,pshold";
489
+			reg = <0xfc4ab000 0x4>;
490
+		};
491
+
492
+		spmi_bus: spmi@fc4cf000 {
493
+			compatible = "qcom,spmi-pmic-arb";
494
+			reg = <0xfc4cf000 0x1000>,
495
+			      <0xfc4cb000 0x1000>,
496
+			      <0xfc4ca000 0x1000>;
497
+			reg-names = "core", "intr", "cnfg";
498
+			interrupt-names = "periph_irq";
499
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
500
+			qcom,ee = <0>;
501
+			qcom,channel = <0>;
502
+			#address-cells = <2>;
503
+			#size-cells = <0>;
504
+			interrupt-controller;
505
+			#interrupt-cells = <4>;
157506 		};
158507 
159508 		tcsr_mutex_regs: syscon@fd484000 {
....@@ -161,41 +510,181 @@
161510 			reg = <0xfd484000 0x2000>;
162511 		};
163512 
164
-		clock_gcc: clock-controller@fc400000 {
165
-			compatible = "qcom,gcc-msm8994";
166
-			#clock-cells = <1>;
167
-			#reset-cells = <1>;
168
-			#power-domain-cells = <1>;
169
-			reg = <0xfc400000 0x2000>;
170
-		};
171
-	};
513
+		tlmm: pinctrl@fd510000 {
514
+			compatible = "qcom,msm8994-pinctrl";
515
+			reg = <0xfd510000 0x4000>;
516
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
517
+			gpio-controller;
518
+			gpio-ranges = <&tlmm 0 0 146>;
519
+			#gpio-cells = <2>;
520
+			interrupt-controller;
521
+			#interrupt-cells = <2>;
172522 
173
-	memory {
174
-		device_type = "memory";
175
-		// We expect the bootloader to fill in the reg
176
-		reg = <0 0 0 0>;
177
-	};
523
+			blsp1_uart2_default: blsp1-uart2-default {
524
+				function = "blsp_uart2";
525
+				pins = "gpio4", "gpio5";
526
+				drive-strength = <16>;
527
+				bias-disable;
528
+			};
178529 
179
-	xo_board: xo_board {
180
-		compatible = "fixed-clock";
181
-		#clock-cells = <0>;
182
-		clock-frequency = <19200000>;
183
-	};
530
+			blsp1_uart2_sleep: blsp1-uart2-sleep {
531
+				function = "gpio";
532
+				pins = "gpio4", "gpio5";
533
+				drive-strength = <2>;
534
+				bias-pull-down;
535
+			};
184536 
185
-	sleep_clk: sleep_clk {
186
-		compatible = "fixed-clock";
187
-		#clock-cells = <0>;
188
-		clock-frequency = <32768>;
189
-	};
537
+			blsp2_uart2_default: blsp2-uart2-default {
538
+				function = "blsp_uart8";
539
+				pins = "gpio45", "gpio46";
540
+				drive-strength = <2>;
541
+				bias-disable;
542
+			};
190543 
191
-	reserved-memory {
192
-		#address-cells = <2>;
193
-		#size-cells = <2>;
194
-		ranges;
544
+			blsp2_uart2_sleep: blsp2-uart2-sleep {
545
+				function = "gpio";
546
+				pins = "gpio45", "gpio46";
547
+				drive-strength = <2>;
548
+				bias-pull-down;
549
+			};
195550 
196
-		smem_mem: smem_region@6a00000 {
197
-			reg = <0x0 0x6a00000 0x0 0x200000>;
198
-			no-map;
551
+			i2c1_default: i2c1-default {
552
+				function = "blsp_i2c1";
553
+				pins = "gpio2", "gpio3";
554
+				drive-strength = <2>;
555
+				bias-disable;
556
+			};
557
+
558
+			i2c1_sleep: i2c1-sleep {
559
+				function = "gpio";
560
+				pins = "gpio2", "gpio3";
561
+				drive-strength = <2>;
562
+				bias-disable;
563
+			};
564
+
565
+			i2c2_default: i2c2-default {
566
+				function = "blsp_i2c2";
567
+				pins = "gpio6", "gpio7";
568
+				drive-strength = <2>;
569
+				bias-disable;
570
+			};
571
+
572
+			i2c2_sleep: i2c2-sleep {
573
+				function = "gpio";
574
+				pins = "gpio6", "gpio7";
575
+				drive-strength = <2>;
576
+				bias-disable;
577
+			};
578
+
579
+			i2c4_default: i2c4-default {
580
+				function = "blsp_i2c4";
581
+				pins = "gpio19", "gpio20";
582
+				drive-strength = <2>;
583
+				bias-disable;
584
+			};
585
+
586
+			i2c4_sleep: i2c4-sleep {
587
+				function = "gpio";
588
+				pins = "gpio19", "gpio20";
589
+				drive-strength = <2>;
590
+				bias-pull-down;
591
+				input-enable;
592
+			};
593
+
594
+			i2c5_default: i2c5-default {
595
+				function = "blsp_i2c5";
596
+				pins = "gpio23", "gpio24";
597
+				drive-strength = <2>;
598
+				bias-disable;
599
+			};
600
+
601
+			i2c5_sleep: i2c5-sleep {
602
+				function = "gpio";
603
+				pins = "gpio23", "gpio24";
604
+				drive-strength = <2>;
605
+				bias-disable;
606
+			};
607
+
608
+			i2c6_default: i2c6-default {
609
+				function = "blsp_i2c6";
610
+				pins = "gpio28", "gpio27";
611
+				drive-strength = <2>;
612
+				bias-disable;
613
+			};
614
+
615
+			i2c6_sleep: i2c6-sleep {
616
+				function = "gpio";
617
+				pins = "gpio28", "gpio27";
618
+				drive-strength = <2>;
619
+				bias-disable;
620
+			};
621
+
622
+			blsp1_spi0_default: blsp1-spi0-default {
623
+				default {
624
+					function = "blsp_spi1";
625
+					pins = "gpio0", "gpio1", "gpio3";
626
+					drive-strength = <10>;
627
+					bias-pull-down;
628
+				};
629
+				cs {
630
+					function = "gpio";
631
+					pins = "gpio8";
632
+					drive-strength = <2>;
633
+					bias-disable;
634
+				};
635
+			};
636
+
637
+			blsp1_spi0_sleep: blsp1-spi0-sleep {
638
+				pins = "gpio0", "gpio1", "gpio3";
639
+				drive-strength = <2>;
640
+				bias-disable;
641
+			};
642
+
643
+			sdc1_clk_on: clk-on {
644
+				pins = "sdc1_clk";
645
+				bias-disable;
646
+				drive-strength = <16>;
647
+			};
648
+
649
+			sdc1_clk_off: clk-off {
650
+				pins = "sdc1_clk";
651
+				bias-disable;
652
+				drive-strength = <2>;
653
+			};
654
+
655
+			sdc1_cmd_on: cmd-on {
656
+				pins = "sdc1_cmd";
657
+				bias-pull-up;
658
+				drive-strength = <8>;
659
+			};
660
+
661
+			sdc1_cmd_off: cmd-off {
662
+				pins = "sdc1_cmd";
663
+				bias-pull-up;
664
+				drive-strength = <2>;
665
+			};
666
+
667
+			sdc1_data_on: data-on {
668
+				pins = "sdc1_data";
669
+				bias-pull-up;
670
+				drive-strength = <8>;
671
+			};
672
+
673
+			sdc1_data_off: data-off {
674
+				pins = "sdc1_data";
675
+				bias-pull-up;
676
+				drive-strength = <2>;
677
+			};
678
+
679
+			sdc1_rclk_on: rclk-on {
680
+				pins = "sdc1_rclk";
681
+				bias-pull-down;
682
+			};
683
+
684
+			sdc1_rclk_off: rclk-off {
685
+				pins = "sdc1_rclk";
686
+				bias-pull-down;
687
+			};
199688 		};
200689 	};
201690 
....@@ -205,12 +694,22 @@
205694 		#hwlock-cells = <1>;
206695 	};
207696 
208
-	qcom,smem@6a00000 {
209
-		compatible = "qcom,smem";
210
-		memory-region = <&smem_mem>;
211
-		hwlocks = <&tcsr_mutex 3>;
697
+	timer {
698
+		compatible = "arm,armv8-timer";
699
+		interrupts = <GIC_PPI 2 0xff08>,
700
+			     <GIC_PPI 3 0xff08>,
701
+			     <GIC_PPI 4 0xff08>,
702
+			     <GIC_PPI 1 0xff08>;
703
+	};
704
+
705
+	vreg_vph_pwr: vreg-vph-pwr {
706
+		compatible = "regulator-fixed";
707
+		regulator-name = "vph-pwr";
708
+
709
+		regulator-min-microvolt = <3600000>;
710
+		regulator-max-microvolt = <3600000>;
711
+
712
+		regulator-always-on;
212713 	};
213714 };
214715 
215
-
216
-#include "msm8994-pins.dtsi"