~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,26 +1,17 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3		- *
4		- * This program is free software; you can redistribute it and/or modify
5		- * it under the terms of the GNU General Public License version 2 and
6		- * only version 2 as published by the Free Software Foundation.
7		- *
8		- * This program is distributed in the hope that it will be useful,
9		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11		- * GNU General Public License for more details.
12	4	*/
13	5
14		-#include <dt-bindings/interrupt-controller/arm-gic.h>
	6	+#include <dt-bindings/arm/coresight-cti-dt.h>
15	7	#include <dt-bindings/clock/qcom,gcc-msm8916.h>
16		-#include <dt-bindings/reset/qcom,gcc-msm8916.h>
17	8	#include <dt-bindings/clock/qcom,rpmcc.h>
	9	+#include <dt-bindings/interconnect/qcom,msm8916.h>
	10	+#include <dt-bindings/interrupt-controller/arm-gic.h>
	11	+#include <dt-bindings/reset/qcom,gcc-msm8916.h>
18	12	#include <dt-bindings/thermal/thermal.h>
19	13
20	14	/ {
21		- model = "Qualcomm Technologies, Inc. MSM8916";
22		- compatible = "qcom,msm8916";
23		-
24	15	interrupt-parent = <&intc>;
25	16
26	17	#address-cells = <2>;
..	..	@@ -103,66 +94,87 @@
103	94	};
104	95	};
105	96
	97	+ clocks {
	98	+ xo_board: xo-board {
	99	+ compatible = "fixed-clock";
	100	+ #clock-cells = <0>;
	101	+ clock-frequency = <19200000>;
	102	+ };
	103	+
	104	+ sleep_clk: sleep-clk {
	105	+ compatible = "fixed-clock";
	106	+ #clock-cells = <0>;
	107	+ clock-frequency = <32768>;
	108	+ };
	109	+ };
	110	+
106	111	cpus {
107	112	#address-cells = <1>;
108	113	#size-cells = <0>;
109	114
110	115	CPU0: cpu@0 {
111	116	device_type = "cpu";
112		- compatible = "arm,cortex-a53", "arm,armv8";
	117	+ compatible = "arm,cortex-a53";
113	118	reg = <0x0>;
114	119	next-level-cache = <&L2_0>;
115	120	enable-method = "psci";
116		- cpu-idle-states = <&CPU_SPC>;
117	121	clocks = <&apcs>;
118	122	operating-points-v2 = <&cpu_opp_table>;
119	123	#cooling-cells = <2>;
	124	+ power-domains = <&CPU_PD0>;
	125	+ power-domain-names = "psci";
120	126	};
121	127
122	128	CPU1: cpu@1 {
123	129	device_type = "cpu";
124		- compatible = "arm,cortex-a53", "arm,armv8";
	130	+ compatible = "arm,cortex-a53";
125	131	reg = <0x1>;
126	132	next-level-cache = <&L2_0>;
127	133	enable-method = "psci";
128		- cpu-idle-states = <&CPU_SPC>;
129	134	clocks = <&apcs>;
130	135	operating-points-v2 = <&cpu_opp_table>;
131	136	#cooling-cells = <2>;
	137	+ power-domains = <&CPU_PD1>;
	138	+ power-domain-names = "psci";
132	139	};
133	140
134	141	CPU2: cpu@2 {
135	142	device_type = "cpu";
136		- compatible = "arm,cortex-a53", "arm,armv8";
	143	+ compatible = "arm,cortex-a53";
137	144	reg = <0x2>;
138	145	next-level-cache = <&L2_0>;
139	146	enable-method = "psci";
140		- cpu-idle-states = <&CPU_SPC>;
141	147	clocks = <&apcs>;
142	148	operating-points-v2 = <&cpu_opp_table>;
143	149	#cooling-cells = <2>;
	150	+ power-domains = <&CPU_PD2>;
	151	+ power-domain-names = "psci";
144	152	};
145	153
146	154	CPU3: cpu@3 {
147	155	device_type = "cpu";
148		- compatible = "arm,cortex-a53", "arm,armv8";
	156	+ compatible = "arm,cortex-a53";
149	157	reg = <0x3>;
150	158	next-level-cache = <&L2_0>;
151	159	enable-method = "psci";
152		- cpu-idle-states = <&CPU_SPC>;
153	160	clocks = <&apcs>;
154	161	operating-points-v2 = <&cpu_opp_table>;
155	162	#cooling-cells = <2>;
	163	+ power-domains = <&CPU_PD3>;
	164	+ power-domain-names = "psci";
156	165	};
157	166
158	167	L2_0: l2-cache {
159		- compatible = "cache";
160		- cache-level = <2>;
	168	+ compatible = "cache";
	169	+ cache-level = <2>;
161	170	};
162	171
163	172	idle-states {
164		- CPU_SPC: spc {
	173	+ entry-method = "psci";
	174	+
	175	+ CPU_SLEEP_0: cpu-sleep-0 {
165	176	compatible = "arm,idle-state";
	177	+ idle-state-name = "standalone-power-collapse";
166	178	arm,psci-suspend-param = <0x40000002>;
167	179	entry-latency-us = <130>;
168	180	exit-latency-us = <150>;
..	..	@@ -170,76 +182,28 @@
170	182	local-timer-stop;
171	183	};
172	184	};
173		- };
174	185
175		- psci {
176		- compatible = "arm,psci-1.0";
177		- method = "smc";
178		- };
	186	+ domain-idle-states {
179	187
180		- pmu {
181		- compatible = "arm,cortex-a53-pmu";
182		- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)\| IRQ_TYPE_LEVEL_HIGH)>;
183		- };
184		-
185		- thermal-zones {
186		- cpu-thermal0 {
187		- polling-delay-passive = <250>;
188		- polling-delay = <1000>;
189		-
190		- thermal-sensors = <&tsens 4>;
191		-
192		- trips {
193		- cpu_alert0: trip0 {
194		- temperature = <75000>;
195		- hysteresis = <2000>;
196		- type = "passive";
197		- };
198		- cpu_crit0: trip1 {
199		- temperature = <110000>;
200		- hysteresis = <2000>;
201		- type = "critical";
202		- };
	188	+ CLUSTER_RET: cluster-retention {
	189	+ compatible = "domain-idle-state";
	190	+ arm,psci-suspend-param = <0x41000012>;
	191	+ entry-latency-us = <500>;
	192	+ exit-latency-us = <500>;
	193	+ min-residency-us = <2000>;
203	194	};
204	195
205		- cooling-maps {
206		- map0 {
207		- trip = <&cpu_alert0>;
208		- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
209		- };
	196	+ CLUSTER_PWRDN: cluster-gdhs {
	197	+ compatible = "domain-idle-state";
	198	+ arm,psci-suspend-param = <0x41000032>;
	199	+ entry-latency-us = <2000>;
	200	+ exit-latency-us = <2000>;
	201	+ min-residency-us = <6000>;
210	202	};
211	203	};
212		-
213		- cpu-thermal1 {
214		- polling-delay-passive = <250>;
215		- polling-delay = <1000>;
216		-
217		- thermal-sensors = <&tsens 3>;
218		-
219		- trips {
220		- cpu_alert1: trip0 {
221		- temperature = <75000>;
222		- hysteresis = <2000>;
223		- type = "passive";
224		- };
225		- cpu_crit1: trip1 {
226		- temperature = <110000>;
227		- hysteresis = <2000>;
228		- type = "critical";
229		- };
230		- };
231		-
232		- cooling-maps {
233		- map0 {
234		- trip = <&cpu_alert1>;
235		- cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
236		- };
237		- };
238		- };
239		-
240	204	};
241	205
242		- cpu_opp_table: cpu_opp_table {
	206	+ cpu_opp_table: cpu-opp-table {
243	207	compatible = "operating-points-v2";
244	208	opp-shared;
245	209
..	..	@@ -257,36 +221,75 @@
257	221	};
258	222	};
259	223
260		- gpu_opp_table: opp_table {
261		- compatible = "operating-points-v2";
	224	+ firmware {
	225	+ scm: scm {
	226	+ compatible = "qcom,scm-msm8916", "qcom,scm";
	227	+ clocks = <&gcc GCC_CRYPTO_CLK>,
	228	+ <&gcc GCC_CRYPTO_AXI_CLK>,
	229	+ <&gcc GCC_CRYPTO_AHB_CLK>;
	230	+ clock-names = "core", "bus", "iface";
	231	+ #reset-cells = <1>;
262	232
263		- opp-400000000 {
264		- opp-hz = /bits/ 64 <400000000>;
265		- };
266		- opp-19200000 {
267		- opp-hz = /bits/ 64 <19200000>;
	233	+ qcom,dload-mode = <&tcsr 0x6100>;
268	234	};
269	235	};
270	236
271		- timer {
272		- compatible = "arm,armv8-timer";
273		- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
274		- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
275		- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
276		- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	237	+ pmu {
	238	+ compatible = "arm,cortex-a53-pmu";
	239	+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
277	240	};
278	241
279		- clocks {
280		- xo_board: xo_board {
281		- compatible = "fixed-clock";
282		- #clock-cells = <0>;
283		- clock-frequency = <19200000>;
	242	+ psci {
	243	+ compatible = "arm,psci-1.0";
	244	+ method = "smc";
	245	+
	246	+ CPU_PD0: power-domain-cpu0 {
	247	+ #power-domain-cells = <0>;
	248	+ power-domains = <&CLUSTER_PD>;
	249	+ domain-idle-states = <&CPU_SLEEP_0>;
284	250	};
285	251
286		- sleep_clk: sleep_clk {
287		- compatible = "fixed-clock";
288		- #clock-cells = <0>;
289		- clock-frequency = <32768>;
	252	+ CPU_PD1: power-domain-cpu1 {
	253	+ #power-domain-cells = <0>;
	254	+ power-domains = <&CLUSTER_PD>;
	255	+ domain-idle-states = <&CPU_SLEEP_0>;
	256	+ };
	257	+
	258	+ CPU_PD2: power-domain-cpu2 {
	259	+ #power-domain-cells = <0>;
	260	+ power-domains = <&CLUSTER_PD>;
	261	+ domain-idle-states = <&CPU_SLEEP_0>;
	262	+ };
	263	+
	264	+ CPU_PD3: power-domain-cpu3 {
	265	+ #power-domain-cells = <0>;
	266	+ power-domains = <&CLUSTER_PD>;
	267	+ domain-idle-states = <&CPU_SLEEP_0>;
	268	+ };
	269	+
	270	+ CLUSTER_PD: power-domain-cluster {
	271	+ #power-domain-cells = <0>;
	272	+ domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
	273	+ };
	274	+ };
	275	+
	276	+ smd {
	277	+ compatible = "qcom,smd";
	278	+
	279	+ rpm {
	280	+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
	281	+ qcom,ipc = <&apcs 8 0>;
	282	+ qcom,smd-edge = <15>;
	283	+
	284	+ rpm_requests: rpm-requests {
	285	+ compatible = "qcom,rpm-msm8916";
	286	+ qcom,smd-channels = "rpm_requests";
	287	+
	288	+ rpmcc: clock-controller {
	289	+ compatible = "qcom,rpmcc-msm8916";
	290	+ #clock-cells = <1>;
	291	+ };
	292	+ };
290	293	};
291	294	};
292	295
..	..	@@ -299,14 +302,85 @@
299	302	hwlocks = <&tcsr_mutex 3>;
300	303	};
301	304
302		- firmware {
303		- scm: scm {
304		- compatible = "qcom,scm";
305		- clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
306		- clock-names = "core", "bus", "iface";
307		- #reset-cells = <1>;
	305	+ smp2p-hexagon {
	306	+ compatible = "qcom,smp2p";
	307	+ qcom,smem = <435>, <428>;
308	308
309		- qcom,dload-mode = <&tcsr 0x6100>;
	309	+ interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
	310	+
	311	+ qcom,ipc = <&apcs 8 14>;
	312	+
	313	+ qcom,local-pid = <0>;
	314	+ qcom,remote-pid = <1>;
	315	+
	316	+ hexagon_smp2p_out: master-kernel {
	317	+ qcom,entry-name = "master-kernel";
	318	+
	319	+ #qcom,smem-state-cells = <1>;
	320	+ };
	321	+
	322	+ hexagon_smp2p_in: slave-kernel {
	323	+ qcom,entry-name = "slave-kernel";
	324	+
	325	+ interrupt-controller;
	326	+ #interrupt-cells = <2>;
	327	+ };
	328	+ };
	329	+
	330	+ smp2p-wcnss {
	331	+ compatible = "qcom,smp2p";
	332	+ qcom,smem = <451>, <431>;
	333	+
	334	+ interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
	335	+
	336	+ qcom,ipc = <&apcs 8 18>;
	337	+
	338	+ qcom,local-pid = <0>;
	339	+ qcom,remote-pid = <4>;
	340	+
	341	+ wcnss_smp2p_out: master-kernel {
	342	+ qcom,entry-name = "master-kernel";
	343	+
	344	+ #qcom,smem-state-cells = <1>;
	345	+ };
	346	+
	347	+ wcnss_smp2p_in: slave-kernel {
	348	+ qcom,entry-name = "slave-kernel";
	349	+
	350	+ interrupt-controller;
	351	+ #interrupt-cells = <2>;
	352	+ };
	353	+ };
	354	+
	355	+ smsm {
	356	+ compatible = "qcom,smsm";
	357	+
	358	+ #address-cells = <1>;
	359	+ #size-cells = <0>;
	360	+
	361	+ qcom,ipc-1 = <&apcs 8 13>;
	362	+ qcom,ipc-3 = <&apcs 8 19>;
	363	+
	364	+ apps_smsm: apps@0 {
	365	+ reg = <0>;
	366	+
	367	+ #qcom,smem-state-cells = <1>;
	368	+ };
	369	+
	370	+ hexagon_smsm: hexagon@1 {
	371	+ reg = <1>;
	372	+ interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
	373	+
	374	+ interrupt-controller;
	375	+ #interrupt-cells = <2>;
	376	+ };
	377	+
	378	+ wcnss_smsm: wcnss@6 {
	379	+ reg = <6>;
	380	+ interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
	381	+
	382	+ interrupt-controller;
	383	+ #interrupt-cells = <2>;
310	384	};
311	385	};
312	386
..	..	@@ -316,16 +390,474 @@
316	390	ranges = <0 0 0 0xffffffff>;
317	391	compatible = "simple-bus";
318	392
	393	+ rng@22000 {
	394	+ compatible = "qcom,prng";
	395	+ reg = <0x00022000 0x200>;
	396	+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
	397	+ clock-names = "core";
	398	+ };
	399	+
319	400	restart@4ab000 {
320	401	compatible = "qcom,pshold";
321		- reg = <0x4ab000 0x4>;
	402	+ reg = <0x004ab000 0x4>;
	403	+ };
	404	+
	405	+ qfprom: qfprom@5c000 {
	406	+ compatible = "qcom,qfprom";
	407	+ reg = <0x0005c000 0x1000>;
	408	+ #address-cells = <1>;
	409	+ #size-cells = <1>;
	410	+ tsens_caldata: caldata@d0 {
	411	+ reg = <0xd0 0x8>;
	412	+ };
	413	+ tsens_calsel: calsel@ec {
	414	+ reg = <0xec 0x4>;
	415	+ };
	416	+ };
	417	+
	418	+ rpm_msg_ram: memory@60000 {
	419	+ compatible = "qcom,rpm-msg-ram";
	420	+ reg = <0x00060000 0x8000>;
	421	+ };
	422	+
	423	+ bimc: interconnect@400000 {
	424	+ compatible = "qcom,msm8916-bimc";
	425	+ reg = <0x00400000 0x62000>;
	426	+ #interconnect-cells = <1>;
	427	+ clock-names = "bus", "bus_a";
	428	+ clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
	429	+ <&rpmcc RPM_SMD_BIMC_A_CLK>;
	430	+ };
	431	+
	432	+ tsens: thermal-sensor@4a9000 {
	433	+ compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
	434	+ reg = <0x004a9000 0x1000>, /* TM */
	435	+ <0x004a8000 0x1000>; /* SROT */
	436	+ nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
	437	+ nvmem-cell-names = "calib", "calib_sel";
	438	+ #qcom,sensors = <5>;
	439	+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
	440	+ interrupt-names = "uplow";
	441	+ #thermal-sensor-cells = <1>;
	442	+ };
	443	+
	444	+ pcnoc: interconnect@500000 {
	445	+ compatible = "qcom,msm8916-pcnoc";
	446	+ reg = <0x00500000 0x11000>;
	447	+ #interconnect-cells = <1>;
	448	+ clock-names = "bus", "bus_a";
	449	+ clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
	450	+ <&rpmcc RPM_SMD_PCNOC_A_CLK>;
	451	+ };
	452	+
	453	+ snoc: interconnect@580000 {
	454	+ compatible = "qcom,msm8916-snoc";
	455	+ reg = <0x00580000 0x14000>;
	456	+ #interconnect-cells = <1>;
	457	+ clock-names = "bus", "bus_a";
	458	+ clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
	459	+ <&rpmcc RPM_SMD_SNOC_A_CLK>;
	460	+ };
	461	+
	462	+ /* System CTIs */
	463	+ /* CTI 0 - TMC connections */
	464	+ cti0: cti@810000 {
	465	+ compatible = "arm,coresight-cti", "arm,primecell";
	466	+ reg = <0x00810000 0x1000>;
	467	+
	468	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	469	+ clock-names = "apb_pclk";
	470	+
	471	+ status = "disabled";
	472	+ };
	473	+
	474	+ /* CTI 1 - TPIU connections */
	475	+ cti1: cti@811000 {
	476	+ compatible = "arm,coresight-cti", "arm,primecell";
	477	+ reg = <0x00811000 0x1000>;
	478	+
	479	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	480	+ clock-names = "apb_pclk";
	481	+
	482	+ status = "disabled";
	483	+ };
	484	+
	485	+ /* CTIs 2-11 - no information - not instantiated */
	486	+
	487	+ tpiu: tpiu@820000 {
	488	+ compatible = "arm,coresight-tpiu", "arm,primecell";
	489	+ reg = <0x00820000 0x1000>;
	490	+
	491	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	492	+ clock-names = "apb_pclk", "atclk";
	493	+
	494	+ status = "disabled";
	495	+
	496	+ in-ports {
	497	+ port {
	498	+ tpiu_in: endpoint {
	499	+ remote-endpoint = <&replicator_out1>;
	500	+ };
	501	+ };
	502	+ };
	503	+ };
	504	+
	505	+ funnel0: funnel@821000 {
	506	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	507	+ reg = <0x00821000 0x1000>;
	508	+
	509	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	510	+ clock-names = "apb_pclk", "atclk";
	511	+
	512	+ status = "disabled";
	513	+
	514	+ in-ports {
	515	+ #address-cells = <1>;
	516	+ #size-cells = <0>;
	517	+
	518	+ /*
	519	+ * Not described input ports:
	520	+ * 0 - connected to Resource and Power Manger CPU ETM
	521	+ * 1 - not-connected
	522	+ * 2 - connected to Modem CPU ETM
	523	+ * 3 - not-connected
	524	+ * 5 - not-connected
	525	+ * 6 - connected trought funnel to Wireless CPU ETM
	526	+ * 7 - connected to STM component
	527	+ */
	528	+
	529	+ port@4 {
	530	+ reg = <4>;
	531	+ funnel0_in4: endpoint {
	532	+ remote-endpoint = <&funnel1_out>;
	533	+ };
	534	+ };
	535	+ };
	536	+
	537	+ out-ports {
	538	+ port {
	539	+ funnel0_out: endpoint {
	540	+ remote-endpoint = <&etf_in>;
	541	+ };
	542	+ };
	543	+ };
	544	+ };
	545	+
	546	+ replicator: replicator@824000 {
	547	+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
	548	+ reg = <0x00824000 0x1000>;
	549	+
	550	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	551	+ clock-names = "apb_pclk", "atclk";
	552	+
	553	+ status = "disabled";
	554	+
	555	+ out-ports {
	556	+ #address-cells = <1>;
	557	+ #size-cells = <0>;
	558	+
	559	+ port@0 {
	560	+ reg = <0>;
	561	+ replicator_out0: endpoint {
	562	+ remote-endpoint = <&etr_in>;
	563	+ };
	564	+ };
	565	+ port@1 {
	566	+ reg = <1>;
	567	+ replicator_out1: endpoint {
	568	+ remote-endpoint = <&tpiu_in>;
	569	+ };
	570	+ };
	571	+ };
	572	+
	573	+ in-ports {
	574	+ port {
	575	+ replicator_in: endpoint {
	576	+ remote-endpoint = <&etf_out>;
	577	+ };
	578	+ };
	579	+ };
	580	+ };
	581	+
	582	+ etf: etf@825000 {
	583	+ compatible = "arm,coresight-tmc", "arm,primecell";
	584	+ reg = <0x00825000 0x1000>;
	585	+
	586	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	587	+ clock-names = "apb_pclk", "atclk";
	588	+
	589	+ status = "disabled";
	590	+
	591	+ in-ports {
	592	+ port {
	593	+ etf_in: endpoint {
	594	+ remote-endpoint = <&funnel0_out>;
	595	+ };
	596	+ };
	597	+ };
	598	+
	599	+ out-ports {
	600	+ port {
	601	+ etf_out: endpoint {
	602	+ remote-endpoint = <&replicator_in>;
	603	+ };
	604	+ };
	605	+ };
	606	+ };
	607	+
	608	+ etr: etr@826000 {
	609	+ compatible = "arm,coresight-tmc", "arm,primecell";
	610	+ reg = <0x00826000 0x1000>;
	611	+
	612	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	613	+ clock-names = "apb_pclk", "atclk";
	614	+
	615	+ status = "disabled";
	616	+
	617	+ in-ports {
	618	+ port {
	619	+ etr_in: endpoint {
	620	+ remote-endpoint = <&replicator_out0>;
	621	+ };
	622	+ };
	623	+ };
	624	+ };
	625	+
	626	+ funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */
	627	+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
	628	+ reg = <0x00841000 0x1000>;
	629	+
	630	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	631	+ clock-names = "apb_pclk", "atclk";
	632	+
	633	+ status = "disabled";
	634	+
	635	+ in-ports {
	636	+ #address-cells = <1>;
	637	+ #size-cells = <0>;
	638	+
	639	+ port@0 {
	640	+ reg = <0>;
	641	+ funnel1_in0: endpoint {
	642	+ remote-endpoint = <&etm0_out>;
	643	+ };
	644	+ };
	645	+ port@1 {
	646	+ reg = <1>;
	647	+ funnel1_in1: endpoint {
	648	+ remote-endpoint = <&etm1_out>;
	649	+ };
	650	+ };
	651	+ port@2 {
	652	+ reg = <2>;
	653	+ funnel1_in2: endpoint {
	654	+ remote-endpoint = <&etm2_out>;
	655	+ };
	656	+ };
	657	+ port@3 {
	658	+ reg = <3>;
	659	+ funnel1_in3: endpoint {
	660	+ remote-endpoint = <&etm3_out>;
	661	+ };
	662	+ };
	663	+ };
	664	+
	665	+ out-ports {
	666	+ port {
	667	+ funnel1_out: endpoint {
	668	+ remote-endpoint = <&funnel0_in4>;
	669	+ };
	670	+ };
	671	+ };
	672	+ };
	673	+
	674	+ debug0: debug@850000 {
	675	+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
	676	+ reg = <0x00850000 0x1000>;
	677	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	678	+ clock-names = "apb_pclk";
	679	+ cpu = <&CPU0>;
	680	+ status = "disabled";
	681	+ };
	682	+
	683	+ debug1: debug@852000 {
	684	+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
	685	+ reg = <0x00852000 0x1000>;
	686	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	687	+ clock-names = "apb_pclk";
	688	+ cpu = <&CPU1>;
	689	+ status = "disabled";
	690	+ };
	691	+
	692	+ debug2: debug@854000 {
	693	+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
	694	+ reg = <0x00854000 0x1000>;
	695	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	696	+ clock-names = "apb_pclk";
	697	+ cpu = <&CPU2>;
	698	+ status = "disabled";
	699	+ };
	700	+
	701	+ debug3: debug@856000 {
	702	+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
	703	+ reg = <0x00856000 0x1000>;
	704	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	705	+ clock-names = "apb_pclk";
	706	+ cpu = <&CPU3>;
	707	+ status = "disabled";
	708	+ };
	709	+
	710	+ /* Core CTIs; CTIs 12-15 */
	711	+ /* CTI - CPU-0 */
	712	+ cti12: cti@858000 {
	713	+ compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
	714	+ "arm,primecell";
	715	+ reg = <0x00858000 0x1000>;
	716	+
	717	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	718	+ clock-names = "apb_pclk";
	719	+
	720	+ cpu = <&CPU0>;
	721	+ arm,cs-dev-assoc = <&etm0>;
	722	+
	723	+ status = "disabled";
	724	+ };
	725	+
	726	+ /* CTI - CPU-1 */
	727	+ cti13: cti@859000 {
	728	+ compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
	729	+ "arm,primecell";
	730	+ reg = <0x00859000 0x1000>;
	731	+
	732	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	733	+ clock-names = "apb_pclk";
	734	+
	735	+ cpu = <&CPU1>;
	736	+ arm,cs-dev-assoc = <&etm1>;
	737	+
	738	+ status = "disabled";
	739	+ };
	740	+
	741	+ /* CTI - CPU-2 */
	742	+ cti14: cti@85a000 {
	743	+ compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
	744	+ "arm,primecell";
	745	+ reg = <0x0085a000 0x1000>;
	746	+
	747	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	748	+ clock-names = "apb_pclk";
	749	+
	750	+ cpu = <&CPU2>;
	751	+ arm,cs-dev-assoc = <&etm2>;
	752	+
	753	+ status = "disabled";
	754	+ };
	755	+
	756	+ /* CTI - CPU-3 */
	757	+ cti15: cti@85b000 {
	758	+ compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
	759	+ "arm,primecell";
	760	+ reg = <0x0085b000 0x1000>;
	761	+
	762	+ clocks = <&rpmcc RPM_QDSS_CLK>;
	763	+ clock-names = "apb_pclk";
	764	+
	765	+ cpu = <&CPU3>;
	766	+ arm,cs-dev-assoc = <&etm3>;
	767	+
	768	+ status = "disabled";
	769	+ };
	770	+
	771	+ etm0: etm@85c000 {
	772	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	773	+ reg = <0x0085c000 0x1000>;
	774	+
	775	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	776	+ clock-names = "apb_pclk", "atclk";
	777	+ arm,coresight-loses-context-with-cpu;
	778	+
	779	+ cpu = <&CPU0>;
	780	+
	781	+ status = "disabled";
	782	+
	783	+ out-ports {
	784	+ port {
	785	+ etm0_out: endpoint {
	786	+ remote-endpoint = <&funnel1_in0>;
	787	+ };
	788	+ };
	789	+ };
	790	+ };
	791	+
	792	+ etm1: etm@85d000 {
	793	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	794	+ reg = <0x0085d000 0x1000>;
	795	+
	796	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	797	+ clock-names = "apb_pclk", "atclk";
	798	+ arm,coresight-loses-context-with-cpu;
	799	+
	800	+ cpu = <&CPU1>;
	801	+
	802	+ status = "disabled";
	803	+
	804	+ out-ports {
	805	+ port {
	806	+ etm1_out: endpoint {
	807	+ remote-endpoint = <&funnel1_in1>;
	808	+ };
	809	+ };
	810	+ };
	811	+ };
	812	+
	813	+ etm2: etm@85e000 {
	814	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	815	+ reg = <0x0085e000 0x1000>;
	816	+
	817	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	818	+ clock-names = "apb_pclk", "atclk";
	819	+ arm,coresight-loses-context-with-cpu;
	820	+
	821	+ cpu = <&CPU2>;
	822	+
	823	+ status = "disabled";
	824	+
	825	+ out-ports {
	826	+ port {
	827	+ etm2_out: endpoint {
	828	+ remote-endpoint = <&funnel1_in2>;
	829	+ };
	830	+ };
	831	+ };
	832	+ };
	833	+
	834	+ etm3: etm@85f000 {
	835	+ compatible = "arm,coresight-etm4x", "arm,primecell";
	836	+ reg = <0x0085f000 0x1000>;
	837	+
	838	+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
	839	+ clock-names = "apb_pclk", "atclk";
	840	+ arm,coresight-loses-context-with-cpu;
	841	+
	842	+ cpu = <&CPU3>;
	843	+
	844	+ status = "disabled";
	845	+
	846	+ out-ports {
	847	+ port {
	848	+ etm3_out: endpoint {
	849	+ remote-endpoint = <&funnel1_in3>;
	850	+ };
	851	+ };
	852	+ };
322	853	};
323	854
324	855	msmgpio: pinctrl@1000000 {
325	856	compatible = "qcom,msm8916-pinctrl";
326		- reg = <0x1000000 0x300000>;
	857	+ reg = <0x01000000 0x300000>;
327	858	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
328	859	gpio-controller;
	860	+ gpio-ranges = <&msmgpio 0 0 122>;
329	861	#gpio-cells = <2>;
330	862	interrupt-controller;
331	863	#interrupt-cells = <2>;
..	..	@@ -336,63 +868,532 @@
336	868	#clock-cells = <1>;
337	869	#reset-cells = <1>;
338	870	#power-domain-cells = <1>;
339		- reg = <0x1800000 0x80000>;
	871	+ reg = <0x01800000 0x80000>;
340	872	};
341	873
342		- tcsr_mutex_regs: syscon@1905000 {
343		- compatible = "syscon";
344		- reg = <0x1905000 0x20000>;
	874	+ tcsr_mutex: hwlock@1905000 {
	875	+ compatible = "qcom,tcsr-mutex";
	876	+ reg = <0x01905000 0x20000>;
	877	+ #hwlock-cells = <1>;
345	878	};
346	879
347	880	tcsr: syscon@1937000 {
348	881	compatible = "qcom,tcsr-msm8916", "syscon";
349		- reg = <0x1937000 0x30000>;
	882	+ reg = <0x01937000 0x30000>;
350	883	};
351	884
352		- tcsr_mutex: hwlock {
353		- compatible = "qcom,tcsr-mutex";
354		- syscon = <&tcsr_mutex_regs 0 0x1000>;
355		- #hwlock-cells = <1>;
	885	+ mdss: mdss@1a00000 {
	886	+ compatible = "qcom,mdss";
	887	+ reg = <0x01a00000 0x1000>,
	888	+ <0x01ac8000 0x3000>;
	889	+ reg-names = "mdss_phys", "vbif_phys";
	890	+
	891	+ power-domains = <&gcc MDSS_GDSC>;
	892	+
	893	+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
	894	+ <&gcc GCC_MDSS_AXI_CLK>,
	895	+ <&gcc GCC_MDSS_VSYNC_CLK>;
	896	+ clock-names = "iface",
	897	+ "bus",
	898	+ "vsync";
	899	+
	900	+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
	901	+
	902	+ interrupt-controller;
	903	+ #interrupt-cells = <1>;
	904	+
	905	+ #address-cells = <1>;
	906	+ #size-cells = <1>;
	907	+ ranges;
	908	+
	909	+ mdp: mdp@1a01000 {
	910	+ compatible = "qcom,mdp5";
	911	+ reg = <0x01a01000 0x89000>;
	912	+ reg-names = "mdp_phys";
	913	+
	914	+ interrupt-parent = <&mdss>;
	915	+ interrupts = <0>;
	916	+
	917	+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
	918	+ <&gcc GCC_MDSS_AXI_CLK>,
	919	+ <&gcc GCC_MDSS_MDP_CLK>,
	920	+ <&gcc GCC_MDSS_VSYNC_CLK>;
	921	+ clock-names = "iface",
	922	+ "bus",
	923	+ "core",
	924	+ "vsync";
	925	+
	926	+ iommus = <&apps_iommu 4>;
	927	+
	928	+ ports {
	929	+ #address-cells = <1>;
	930	+ #size-cells = <0>;
	931	+
	932	+ port@0 {
	933	+ reg = <0>;
	934	+ mdp5_intf1_out: endpoint {
	935	+ remote-endpoint = <&dsi0_in>;
	936	+ };
	937	+ };
	938	+ };
	939	+ };
	940	+
	941	+ dsi0: dsi@1a98000 {
	942	+ compatible = "qcom,mdss-dsi-ctrl";
	943	+ reg = <0x01a98000 0x25c>;
	944	+ reg-names = "dsi_ctrl";
	945	+
	946	+ interrupt-parent = <&mdss>;
	947	+ interrupts = <4>;
	948	+
	949	+ assigned-clocks = <&gcc BYTE0_CLK_SRC>,
	950	+ <&gcc PCLK0_CLK_SRC>;
	951	+ assigned-clock-parents = <&dsi_phy0 0>,
	952	+ <&dsi_phy0 1>;
	953	+
	954	+ clocks = <&gcc GCC_MDSS_MDP_CLK>,
	955	+ <&gcc GCC_MDSS_AHB_CLK>,
	956	+ <&gcc GCC_MDSS_AXI_CLK>,
	957	+ <&gcc GCC_MDSS_BYTE0_CLK>,
	958	+ <&gcc GCC_MDSS_PCLK0_CLK>,
	959	+ <&gcc GCC_MDSS_ESC0_CLK>;
	960	+ clock-names = "mdp_core",
	961	+ "iface",
	962	+ "bus",
	963	+ "byte",
	964	+ "pixel",
	965	+ "core";
	966	+ phys = <&dsi_phy0>;
	967	+ phy-names = "dsi-phy";
	968	+
	969	+ #address-cells = <1>;
	970	+ #size-cells = <0>;
	971	+
	972	+ ports {
	973	+ #address-cells = <1>;
	974	+ #size-cells = <0>;
	975	+
	976	+ port@0 {
	977	+ reg = <0>;
	978	+ dsi0_in: endpoint {
	979	+ remote-endpoint = <&mdp5_intf1_out>;
	980	+ };
	981	+ };
	982	+
	983	+ port@1 {
	984	+ reg = <1>;
	985	+ dsi0_out: endpoint {
	986	+ };
	987	+ };
	988	+ };
	989	+ };
	990	+
	991	+ dsi_phy0: dsi-phy@1a98300 {
	992	+ compatible = "qcom,dsi-phy-28nm-lp";
	993	+ reg = <0x01a98300 0xd4>,
	994	+ <0x01a98500 0x280>,
	995	+ <0x01a98780 0x30>;
	996	+ reg-names = "dsi_pll",
	997	+ "dsi_phy",
	998	+ "dsi_phy_regulator";
	999	+
	1000	+ #clock-cells = <1>;
	1001	+ #phy-cells = <0>;
	1002	+
	1003	+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
	1004	+ <&xo_board>;
	1005	+ clock-names = "iface", "ref";
	1006	+ };
356	1007	};
357	1008
358		- rpm_msg_ram: memory@60000 {
359		- compatible = "qcom,rpm-msg-ram";
360		- reg = <0x60000 0x8000>;
	1009	+ camss: camss@1b0ac00 {
	1010	+ compatible = "qcom,msm8916-camss";
	1011	+ reg = <0x01b0ac00 0x200>,
	1012	+ <0x01b00030 0x4>,
	1013	+ <0x01b0b000 0x200>,
	1014	+ <0x01b00038 0x4>,
	1015	+ <0x01b08000 0x100>,
	1016	+ <0x01b08400 0x100>,
	1017	+ <0x01b0a000 0x500>,
	1018	+ <0x01b00020 0x10>,
	1019	+ <0x01b10000 0x1000>;
	1020	+ reg-names = "csiphy0",
	1021	+ "csiphy0_clk_mux",
	1022	+ "csiphy1",
	1023	+ "csiphy1_clk_mux",
	1024	+ "csid0",
	1025	+ "csid1",
	1026	+ "ispif",
	1027	+ "csi_clk_mux",
	1028	+ "vfe0";
	1029	+ interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
	1030	+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
	1031	+ <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
	1032	+ <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
	1033	+ <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
	1034	+ <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
	1035	+ interrupt-names = "csiphy0",
	1036	+ "csiphy1",
	1037	+ "csid0",
	1038	+ "csid1",
	1039	+ "ispif",
	1040	+ "vfe0";
	1041	+ power-domains = <&gcc VFE_GDSC>;
	1042	+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
	1043	+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
	1044	+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
	1045	+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
	1046	+ <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
	1047	+ <&gcc GCC_CAMSS_CSI0_CLK>,
	1048	+ <&gcc GCC_CAMSS_CSI0PHY_CLK>,
	1049	+ <&gcc GCC_CAMSS_CSI0PIX_CLK>,
	1050	+ <&gcc GCC_CAMSS_CSI0RDI_CLK>,
	1051	+ <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
	1052	+ <&gcc GCC_CAMSS_CSI1_CLK>,
	1053	+ <&gcc GCC_CAMSS_CSI1PHY_CLK>,
	1054	+ <&gcc GCC_CAMSS_CSI1PIX_CLK>,
	1055	+ <&gcc GCC_CAMSS_CSI1RDI_CLK>,
	1056	+ <&gcc GCC_CAMSS_AHB_CLK>,
	1057	+ <&gcc GCC_CAMSS_VFE0_CLK>,
	1058	+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
	1059	+ <&gcc GCC_CAMSS_VFE_AHB_CLK>,
	1060	+ <&gcc GCC_CAMSS_VFE_AXI_CLK>;
	1061	+ clock-names = "top_ahb",
	1062	+ "ispif_ahb",
	1063	+ "csiphy0_timer",
	1064	+ "csiphy1_timer",
	1065	+ "csi0_ahb",
	1066	+ "csi0",
	1067	+ "csi0_phy",
	1068	+ "csi0_pix",
	1069	+ "csi0_rdi",
	1070	+ "csi1_ahb",
	1071	+ "csi1",
	1072	+ "csi1_phy",
	1073	+ "csi1_pix",
	1074	+ "csi1_rdi",
	1075	+ "ahb",
	1076	+ "vfe0",
	1077	+ "csi_vfe0",
	1078	+ "vfe_ahb",
	1079	+ "vfe_axi";
	1080	+ iommus = <&apps_iommu 3>;
	1081	+ status = "disabled";
	1082	+ ports {
	1083	+ #address-cells = <1>;
	1084	+ #size-cells = <0>;
	1085	+ };
361	1086	};
362	1087
363		- blsp1_uart1: serial@78af000 {
364		- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
365		- reg = <0x78af000 0x200>;
366		- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
367		- clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
368		- clock-names = "core", "iface";
369		- dmas = <&blsp_dma 1>, <&blsp_dma 0>;
370		- dma-names = "rx", "tx";
	1088	+ cci: cci@1b0c000 {
	1089	+ compatible = "qcom,msm8916-cci";
	1090	+ #address-cells = <1>;
	1091	+ #size-cells = <0>;
	1092	+ reg = <0x01b0c000 0x1000>;
	1093	+ interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
	1094	+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
	1095	+ <&gcc GCC_CAMSS_CCI_AHB_CLK>,
	1096	+ <&gcc GCC_CAMSS_CCI_CLK>,
	1097	+ <&gcc GCC_CAMSS_AHB_CLK>;
	1098	+ clock-names = "camss_top_ahb", "cci_ahb",
	1099	+ "cci", "camss_ahb";
	1100	+ assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
	1101	+ <&gcc GCC_CAMSS_CCI_CLK>;
	1102	+ assigned-clock-rates = <80000000>, <19200000>;
	1103	+ pinctrl-names = "default";
	1104	+ pinctrl-0 = <&cci0_default>;
	1105	+ status = "disabled";
	1106	+
	1107	+ cci_i2c0: i2c-bus@0 {
	1108	+ reg = <0>;
	1109	+ clock-frequency = <400000>;
	1110	+ #address-cells = <1>;
	1111	+ #size-cells = <0>;
	1112	+ };
	1113	+ };
	1114	+
	1115	+ gpu@1c00000 {
	1116	+ compatible = "qcom,adreno-306.0", "qcom,adreno";
	1117	+ reg = <0x01c00000 0x20000>;
	1118	+ reg-names = "kgsl_3d0_reg_memory";
	1119	+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	1120	+ interrupt-names = "kgsl_3d0_irq";
	1121	+ clock-names =
	1122	+ "core",
	1123	+ "iface",
	1124	+ "mem",
	1125	+ "mem_iface",
	1126	+ "alt_mem_iface",
	1127	+ "gfx3d";
	1128	+ clocks =
	1129	+ <&gcc GCC_OXILI_GFX3D_CLK>,
	1130	+ <&gcc GCC_OXILI_AHB_CLK>,
	1131	+ <&gcc GCC_OXILI_GMEM_CLK>,
	1132	+ <&gcc GCC_BIMC_GFX_CLK>,
	1133	+ <&gcc GCC_BIMC_GPU_CLK>,
	1134	+ <&gcc GFX3D_CLK_SRC>;
	1135	+ power-domains = <&gcc OXILI_GDSC>;
	1136	+ operating-points-v2 = <&gpu_opp_table>;
	1137	+ iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
	1138	+
	1139	+ gpu_opp_table: opp-table {
	1140	+ compatible = "operating-points-v2";
	1141	+
	1142	+ opp-400000000 {
	1143	+ opp-hz = /bits/ 64 <400000000>;
	1144	+ };
	1145	+ opp-19200000 {
	1146	+ opp-hz = /bits/ 64 <19200000>;
	1147	+ };
	1148	+ };
	1149	+ };
	1150	+
	1151	+ venus: video-codec@1d00000 {
	1152	+ compatible = "qcom,msm8916-venus";
	1153	+ reg = <0x01d00000 0xff000>;
	1154	+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	1155	+ power-domains = <&gcc VENUS_GDSC>;
	1156	+ clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
	1157	+ <&gcc GCC_VENUS0_AHB_CLK>,
	1158	+ <&gcc GCC_VENUS0_AXI_CLK>;
	1159	+ clock-names = "core", "iface", "bus";
	1160	+ iommus = <&apps_iommu 5>;
	1161	+ memory-region = <&venus_mem>;
	1162	+ status = "okay";
	1163	+
	1164	+ video-decoder {
	1165	+ compatible = "venus-decoder";
	1166	+ };
	1167	+
	1168	+ video-encoder {
	1169	+ compatible = "venus-encoder";
	1170	+ };
	1171	+ };
	1172	+
	1173	+ apps_iommu: iommu@1ef0000 {
	1174	+ #address-cells = <1>;
	1175	+ #size-cells = <1>;
	1176	+ #iommu-cells = <1>;
	1177	+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
	1178	+ ranges = <0 0x01e20000 0x40000>;
	1179	+ reg = <0x01ef0000 0x3000>;
	1180	+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
	1181	+ <&gcc GCC_APSS_TCU_CLK>;
	1182	+ clock-names = "iface", "bus";
	1183	+ qcom,iommu-secure-id = <17>;
	1184	+
	1185	+ // vfe:
	1186	+ iommu-ctx@3000 {
	1187	+ compatible = "qcom,msm-iommu-v1-sec";
	1188	+ reg = <0x3000 0x1000>;
	1189	+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	1190	+ };
	1191	+
	1192	+ // mdp_0:
	1193	+ iommu-ctx@4000 {
	1194	+ compatible = "qcom,msm-iommu-v1-ns";
	1195	+ reg = <0x4000 0x1000>;
	1196	+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	1197	+ };
	1198	+
	1199	+ // venus_ns:
	1200	+ iommu-ctx@5000 {
	1201	+ compatible = "qcom,msm-iommu-v1-sec";
	1202	+ reg = <0x5000 0x1000>;
	1203	+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	1204	+ };
	1205	+ };
	1206	+
	1207	+ gpu_iommu: iommu@1f08000 {
	1208	+ #address-cells = <1>;
	1209	+ #size-cells = <1>;
	1210	+ #iommu-cells = <1>;
	1211	+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
	1212	+ ranges = <0 0x01f08000 0x10000>;
	1213	+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
	1214	+ <&gcc GCC_GFX_TCU_CLK>;
	1215	+ clock-names = "iface", "bus";
	1216	+ qcom,iommu-secure-id = <18>;
	1217	+
	1218	+ // gfx3d_user:
	1219	+ iommu-ctx@1000 {
	1220	+ compatible = "qcom,msm-iommu-v1-ns";
	1221	+ reg = <0x1000 0x1000>;
	1222	+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
	1223	+ };
	1224	+
	1225	+ // gfx3d_priv:
	1226	+ iommu-ctx@2000 {
	1227	+ compatible = "qcom,msm-iommu-v1-ns";
	1228	+ reg = <0x2000 0x1000>;
	1229	+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
	1230	+ };
	1231	+ };
	1232	+
	1233	+ spmi_bus: spmi@200f000 {
	1234	+ compatible = "qcom,spmi-pmic-arb";
	1235	+ reg = <0x0200f000 0x001000>,
	1236	+ <0x02400000 0x400000>,
	1237	+ <0x02c00000 0x400000>,
	1238	+ <0x03800000 0x200000>,
	1239	+ <0x0200a000 0x002100>;
	1240	+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
	1241	+ interrupt-names = "periph_irq";
	1242	+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
	1243	+ qcom,ee = <0>;
	1244	+ qcom,channel = <0>;
	1245	+ #address-cells = <2>;
	1246	+ #size-cells = <0>;
	1247	+ interrupt-controller;
	1248	+ #interrupt-cells = <4>;
	1249	+ };
	1250	+
	1251	+ mpss: remoteproc@4080000 {
	1252	+ compatible = "qcom,msm8916-mss-pil";
	1253	+ reg = <0x04080000 0x100>,
	1254	+ <0x04020000 0x040>;
	1255	+
	1256	+ reg-names = "qdsp6", "rmb";
	1257	+
	1258	+ interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
	1259	+ <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
	1260	+ <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
	1261	+ <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
	1262	+ <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
	1263	+ interrupt-names = "wdog", "fatal", "ready",
	1264	+ "handover", "stop-ack";
	1265	+
	1266	+ clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
	1267	+ <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
	1268	+ <&gcc GCC_BOOT_ROM_AHB_CLK>,
	1269	+ <&xo_board>;
	1270	+ clock-names = "iface", "bus", "mem", "xo";
	1271	+
	1272	+ qcom,smem-states = <&hexagon_smp2p_out 0>;
	1273	+ qcom,smem-state-names = "stop";
	1274	+
	1275	+ resets = <&scm 0>;
	1276	+ reset-names = "mss_restart";
	1277	+
	1278	+ qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
	1279	+
	1280	+ status = "disabled";
	1281	+
	1282	+ mba {
	1283	+ memory-region = <&mba_mem>;
	1284	+ };
	1285	+
	1286	+ mpss {
	1287	+ memory-region = <&mpss_mem>;
	1288	+ };
	1289	+
	1290	+ smd-edge {
	1291	+ interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
	1292	+
	1293	+ qcom,smd-edge = <0>;
	1294	+ qcom,ipc = <&apcs 8 12>;
	1295	+ qcom,remote-pid = <1>;
	1296	+
	1297	+ label = "hexagon";
	1298	+
	1299	+ fastrpc {
	1300	+ compatible = "qcom,fastrpc";
	1301	+ qcom,smd-channels = "fastrpcsmd-apps-dsp";
	1302	+ label = "adsp";
	1303	+
	1304	+ #address-cells = <1>;
	1305	+ #size-cells = <0>;
	1306	+
	1307	+ cb@1 {
	1308	+ compatible = "qcom,fastrpc-compute-cb";
	1309	+ reg = <1>;
	1310	+ };
	1311	+ };
	1312	+ };
	1313	+ };
	1314	+
	1315	+ sound: sound@7702000 {
	1316	+ status = "disabled";
	1317	+ compatible = "qcom,apq8016-sbc-sndcard";
	1318	+ reg = <0x07702000 0x4>, <0x07702004 0x4>;
	1319	+ reg-names = "mic-iomux", "spkr-iomux";
	1320	+ };
	1321	+
	1322	+ lpass: audio-controller@7708000 {
	1323	+ status = "disabled";
	1324	+ compatible = "qcom,lpass-cpu-apq8016";
	1325	+
	1326	+ /*
	1327	+ * Note: Unlike the name would suggest, the SEC_I2S_CLK
	1328	+ * is actually only used by Tertiary MI2S while
	1329	+ * Primary/Secondary MI2S both use the PRI_I2S_CLK.
	1330	+ */
	1331	+ clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
	1332	+ <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
	1333	+ <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
	1334	+ <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
	1335	+ <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
	1336	+ <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
	1337	+ <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
	1338	+
	1339	+ clock-names = "ahbix-clk",
	1340	+ "pcnoc-mport-clk",
	1341	+ "pcnoc-sway-clk",
	1342	+ "mi2s-bit-clk0",
	1343	+ "mi2s-bit-clk1",
	1344	+ "mi2s-bit-clk2",
	1345	+ "mi2s-bit-clk3";
	1346	+ #sound-dai-cells = <1>;
	1347	+
	1348	+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
	1349	+ interrupt-names = "lpass-irq-lpaif";
	1350	+ reg = <0x07708000 0x10000>;
	1351	+ reg-names = "lpass-lpaif";
	1352	+
	1353	+ #address-cells = <1>;
	1354	+ #size-cells = <0>;
	1355	+ };
	1356	+
	1357	+ lpass_codec: audio-codec@771c000 {
	1358	+ compatible = "qcom,msm8916-wcd-digital-codec";
	1359	+ reg = <0x0771c000 0x400>;
	1360	+ clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
	1361	+ <&gcc GCC_CODEC_DIGCODEC_CLK>;
	1362	+ clock-names = "ahbix-clk", "mclk";
	1363	+ #sound-dai-cells = <1>;
	1364	+ };
	1365	+
	1366	+ sdhc_1: sdhci@7824000 {
	1367	+ compatible = "qcom,sdhci-msm-v4";
	1368	+ reg = <0x07824900 0x11c>, <0x07824000 0x800>;
	1369	+ reg-names = "hc_mem", "core_mem";
	1370	+
	1371	+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
	1372	+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
	1373	+ interrupt-names = "hc_irq", "pwr_irq";
	1374	+ clocks = <&gcc GCC_SDCC1_APPS_CLK>,
	1375	+ <&gcc GCC_SDCC1_AHB_CLK>,
	1376	+ <&xo_board>;
	1377	+ clock-names = "core", "iface", "xo";
	1378	+ mmc-ddr-1_8v;
	1379	+ bus-width = <8>;
	1380	+ non-removable;
371	1381	status = "disabled";
372	1382	};
373	1383
374		- a53pll: clock@b016000 {
375		- compatible = "qcom,msm8916-a53pll";
376		- reg = <0xb016000 0x40>;
377		- #clock-cells = <0>;
378		- };
	1384	+ sdhc_2: sdhci@7864000 {
	1385	+ compatible = "qcom,sdhci-msm-v4";
	1386	+ reg = <0x07864900 0x11c>, <0x07864000 0x800>;
	1387	+ reg-names = "hc_mem", "core_mem";
379	1388
380		- apcs: mailbox@b011000 {
381		- compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
382		- reg = <0xb011000 0x1000>;
383		- #mbox-cells = <1>;
384		- clocks = <&a53pll>;
385		- #clock-cells = <0>;
386		- };
387		-
388		- blsp1_uart2: serial@78b0000 {
389		- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
390		- reg = <0x78b0000 0x200>;
391		- interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
392		- clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
393		- clock-names = "core", "iface";
394		- dmas = <&blsp_dma 3>, <&blsp_dma 2>;
395		- dma-names = "rx", "tx";
	1389	+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
	1390	+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
	1391	+ interrupt-names = "hc_irq", "pwr_irq";
	1392	+ clocks = <&gcc GCC_SDCC2_APPS_CLK>,
	1393	+ <&gcc GCC_SDCC2_AHB_CLK>,
	1394	+ <&xo_board>;
	1395	+ clock-names = "core", "iface", "xo";
	1396	+ bus-width = <4>;
396	1397	status = "disabled";
397	1398	};
398	1399
..	..	@@ -404,6 +1405,49 @@
404	1405	clock-names = "bam_clk";
405	1406	#dma-cells = <1>;
406	1407	qcom,ee = <0>;
	1408	+ status = "disabled";
	1409	+ };
	1410	+
	1411	+ blsp1_uart1: serial@78af000 {
	1412	+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	1413	+ reg = <0x078af000 0x200>;
	1414	+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	1415	+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	1416	+ clock-names = "core", "iface";
	1417	+ dmas = <&blsp_dma 1>, <&blsp_dma 0>;
	1418	+ dma-names = "rx", "tx";
	1419	+ pinctrl-names = "default", "sleep";
	1420	+ pinctrl-0 = <&blsp1_uart1_default>;
	1421	+ pinctrl-1 = <&blsp1_uart1_sleep>;
	1422	+ status = "disabled";
	1423	+ };
	1424	+
	1425	+ blsp1_uart2: serial@78b0000 {
	1426	+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	1427	+ reg = <0x078b0000 0x200>;
	1428	+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	1429	+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	1430	+ clock-names = "core", "iface";
	1431	+ dmas = <&blsp_dma 3>, <&blsp_dma 2>;
	1432	+ dma-names = "rx", "tx";
	1433	+ pinctrl-names = "default", "sleep";
	1434	+ pinctrl-0 = <&blsp1_uart2_default>;
	1435	+ pinctrl-1 = <&blsp1_uart2_sleep>;
	1436	+ status = "disabled";
	1437	+ };
	1438	+
	1439	+ blsp_i2c1: i2c@78b5000 {
	1440	+ compatible = "qcom,i2c-qup-v2.2.1";
	1441	+ reg = <0x078b5000 0x500>;
	1442	+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	1443	+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	1444	+ <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
	1445	+ clock-names = "iface", "core";
	1446	+ pinctrl-names = "default", "sleep";
	1447	+ pinctrl-0 = <&i2c1_default>;
	1448	+ pinctrl-1 = <&i2c1_sleep>;
	1449	+ #address-cells = <1>;
	1450	+ #size-cells = <0>;
407	1451	status = "disabled";
408	1452	};
409	1453
..	..	@@ -419,6 +1463,21 @@
419	1463	pinctrl-names = "default", "sleep";
420	1464	pinctrl-0 = <&spi1_default>;
421	1465	pinctrl-1 = <&spi1_sleep>;
	1466	+ #address-cells = <1>;
	1467	+ #size-cells = <0>;
	1468	+ status = "disabled";
	1469	+ };
	1470	+
	1471	+ blsp_i2c2: i2c@78b6000 {
	1472	+ compatible = "qcom,i2c-qup-v2.2.1";
	1473	+ reg = <0x078b6000 0x500>;
	1474	+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	1475	+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	1476	+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
	1477	+ clock-names = "iface", "core";
	1478	+ pinctrl-names = "default", "sleep";
	1479	+ pinctrl-0 = <&i2c2_default>;
	1480	+ pinctrl-1 = <&i2c2_sleep>;
422	1481	#address-cells = <1>;
423	1482	#size-cells = <0>;
424	1483	status = "disabled";
..	..	@@ -458,6 +1517,21 @@
458	1517	status = "disabled";
459	1518	};
460	1519
	1520	+ blsp_i2c4: i2c@78b8000 {
	1521	+ compatible = "qcom,i2c-qup-v2.2.1";
	1522	+ reg = <0x078b8000 0x500>;
	1523	+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	1524	+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	1525	+ <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
	1526	+ clock-names = "iface", "core";
	1527	+ pinctrl-names = "default", "sleep";
	1528	+ pinctrl-0 = <&i2c4_default>;
	1529	+ pinctrl-1 = <&i2c4_sleep>;
	1530	+ #address-cells = <1>;
	1531	+ #size-cells = <0>;
	1532	+ status = "disabled";
	1533	+ };
	1534	+
461	1535	blsp_spi4: spi@78b8000 {
462	1536	compatible = "qcom,spi-qup-v2.2.1";
463	1537	reg = <0x078b8000 0x500>;
..	..	@@ -470,6 +1544,21 @@
470	1544	pinctrl-names = "default", "sleep";
471	1545	pinctrl-0 = <&spi4_default>;
472	1546	pinctrl-1 = <&spi4_sleep>;
	1547	+ #address-cells = <1>;
	1548	+ #size-cells = <0>;
	1549	+ status = "disabled";
	1550	+ };
	1551	+
	1552	+ blsp_i2c5: i2c@78b9000 {
	1553	+ compatible = "qcom,i2c-qup-v2.2.1";
	1554	+ reg = <0x078b9000 0x500>;
	1555	+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
	1556	+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	1557	+ <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
	1558	+ clock-names = "iface", "core";
	1559	+ pinctrl-names = "default", "sleep";
	1560	+ pinctrl-0 = <&i2c5_default>;
	1561	+ pinctrl-1 = <&i2c5_sleep>;
473	1562	#address-cells = <1>;
474	1563	#size-cells = <0>;
475	1564	status = "disabled";
..	..	@@ -492,6 +1581,21 @@
492	1581	status = "disabled";
493	1582	};
494	1583
	1584	+ blsp_i2c6: i2c@78ba000 {
	1585	+ compatible = "qcom,i2c-qup-v2.2.1";
	1586	+ reg = <0x078ba000 0x500>;
	1587	+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	1588	+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	1589	+ <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
	1590	+ clock-names = "iface", "core";
	1591	+ pinctrl-names = "default", "sleep";
	1592	+ pinctrl-0 = <&i2c6_default>;
	1593	+ pinctrl-1 = <&i2c6_sleep>;
	1594	+ #address-cells = <1>;
	1595	+ #size-cells = <0>;
	1596	+ status = "disabled";
	1597	+ };
	1598	+
495	1599	blsp_spi6: spi@78ba000 {
496	1600	compatible = "qcom,spi-qup-v2.2.1";
497	1601	reg = <0x078ba000 0x500>;
..	..	@@ -509,122 +1613,10 @@
509	1613	status = "disabled";
510	1614	};
511	1615
512		- blsp_i2c2: i2c@78b6000 {
513		- compatible = "qcom,i2c-qup-v2.2.1";
514		- reg = <0x078b6000 0x500>;
515		- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
516		- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
517		- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
518		- clock-names = "iface", "core";
519		- pinctrl-names = "default", "sleep";
520		- pinctrl-0 = <&i2c2_default>;
521		- pinctrl-1 = <&i2c2_sleep>;
522		- #address-cells = <1>;
523		- #size-cells = <0>;
524		- status = "disabled";
525		- };
526		-
527		- blsp_i2c4: i2c@78b8000 {
528		- compatible = "qcom,i2c-qup-v2.2.1";
529		- reg = <0x078b8000 0x500>;
530		- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
531		- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
532		- <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
533		- clock-names = "iface", "core";
534		- pinctrl-names = "default", "sleep";
535		- pinctrl-0 = <&i2c4_default>;
536		- pinctrl-1 = <&i2c4_sleep>;
537		- #address-cells = <1>;
538		- #size-cells = <0>;
539		- status = "disabled";
540		- };
541		-
542		- blsp_i2c6: i2c@78ba000 {
543		- compatible = "qcom,i2c-qup-v2.2.1";
544		- reg = <0x078ba000 0x500>;
545		- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
546		- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
547		- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
548		- clock-names = "iface", "core";
549		- pinctrl-names = "default", "sleep";
550		- pinctrl-0 = <&i2c6_default>;
551		- pinctrl-1 = <&i2c6_sleep>;
552		- #address-cells = <1>;
553		- #size-cells = <0>;
554		- status = "disabled";
555		- };
556		-
557		- lpass: lpass@7708000 {
558		- status = "disabled";
559		- compatible = "qcom,lpass-cpu-apq8016";
560		- clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
561		- <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
562		- <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
563		- <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
564		- <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
565		- <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
566		- <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
567		-
568		- clock-names = "ahbix-clk",
569		- "pcnoc-mport-clk",
570		- "pcnoc-sway-clk",
571		- "mi2s-bit-clk0",
572		- "mi2s-bit-clk1",
573		- "mi2s-bit-clk2",
574		- "mi2s-bit-clk3";
575		- #sound-dai-cells = <1>;
576		-
577		- interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
578		- interrupt-names = "lpass-irq-lpaif";
579		- reg = <0x07708000 0x10000>;
580		- reg-names = "lpass-lpaif";
581		- };
582		-
583		- lpass_codec: codec{
584		- compatible = "qcom,msm8916-wcd-digital-codec";
585		- reg = <0x0771c000 0x400>;
586		- clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
587		- <&gcc GCC_CODEC_DIGCODEC_CLK>;
588		- clock-names = "ahbix-clk", "mclk";
589		- #sound-dai-cells = <1>;
590		- };
591		-
592		- sdhc_1: sdhci@7824000 {
593		- compatible = "qcom,sdhci-msm-v4";
594		- reg = <0x07824900 0x11c>, <0x07824000 0x800>;
595		- reg-names = "hc_mem", "core_mem";
596		-
597		- interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
598		- interrupt-names = "hc_irq", "pwr_irq";
599		- clocks = <&gcc GCC_SDCC1_APPS_CLK>,
600		- <&gcc GCC_SDCC1_AHB_CLK>,
601		- <&xo_board>;
602		- clock-names = "core", "iface", "xo";
603		- mmc-ddr-1_8v;
604		- bus-width = <8>;
605		- non-removable;
606		- status = "disabled";
607		- };
608		-
609		- sdhc_2: sdhci@7864000 {
610		- compatible = "qcom,sdhci-msm-v4";
611		- reg = <0x07864900 0x11c>, <0x07864000 0x800>;
612		- reg-names = "hc_mem", "core_mem";
613		-
614		- interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
615		- interrupt-names = "hc_irq", "pwr_irq";
616		- clocks = <&gcc GCC_SDCC2_APPS_CLK>,
617		- <&gcc GCC_SDCC2_AHB_CLK>,
618		- <&xo_board>;
619		- clock-names = "core", "iface", "xo";
620		- bus-width = <4>;
621		- status = "disabled";
622		- };
623		-
624		- otg: usb@78d9000 {
	1616	+ usb: usb@78d9000 {
625	1617	compatible = "qcom,ci-hdrc";
626		- reg = <0x78d9000 0x200>,
627		- <0x78d9200 0x200>;
	1618	+ reg = <0x078d9000 0x200>,
	1619	+ <0x078d9200 0x200>;
628	1620	interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
629	1621	<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
630	1622	clocks = <&gcc GCC_USB_HS_AHB_CLK>,
..	..	@@ -636,6 +1628,9 @@
636	1628	reset-names = "core";
637	1629	phy_type = "ulpi";
638	1630	dr_mode = "otg";
	1631	+ hnp-disable;
	1632	+ srp-disable;
	1633	+ adp-disable;
639	1634	ahb-burst-config = <0>;
640	1635	phy-names = "usb-phy";
641	1636	phys = <&usb_hs_phy>;
..	..	@@ -649,7 +1644,7 @@
649	1644	#phy-cells = <0>;
650	1645	clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
651	1646	clock-names = "ref", "sleep";
652		- resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
	1647	+ resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
653	1648	reset-names = "phy", "por";
654	1649	qcom,init-seq = /bits/ 8 <0x0 0x44
655	1650	0x1 0x6b 0x2 0x24 0x3 0x13>;
..	..	@@ -657,387 +1652,19 @@
657	1652	};
658	1653	};
659	1654
660		- intc: interrupt-controller@b000000 {
661		- compatible = "qcom,msm-qgic2";
662		- interrupt-controller;
663		- #interrupt-cells = <3>;
664		- reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
665		- };
666		-
667		- timer@b020000 {
668		- #address-cells = <1>;
669		- #size-cells = <1>;
670		- ranges;
671		- compatible = "arm,armv7-timer-mem";
672		- reg = <0xb020000 0x1000>;
673		- clock-frequency = <19200000>;
674		-
675		- frame@b021000 {
676		- frame-number = <0>;
677		- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
678		- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
679		- reg = <0xb021000 0x1000>,
680		- <0xb022000 0x1000>;
681		- };
682		-
683		- frame@b023000 {
684		- frame-number = <1>;
685		- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
686		- reg = <0xb023000 0x1000>;
687		- status = "disabled";
688		- };
689		-
690		- frame@b024000 {
691		- frame-number = <2>;
692		- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
693		- reg = <0xb024000 0x1000>;
694		- status = "disabled";
695		- };
696		-
697		- frame@b025000 {
698		- frame-number = <3>;
699		- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
700		- reg = <0xb025000 0x1000>;
701		- status = "disabled";
702		- };
703		-
704		- frame@b026000 {
705		- frame-number = <4>;
706		- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
707		- reg = <0xb026000 0x1000>;
708		- status = "disabled";
709		- };
710		-
711		- frame@b027000 {
712		- frame-number = <5>;
713		- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
714		- reg = <0xb027000 0x1000>;
715		- status = "disabled";
716		- };
717		-
718		- frame@b028000 {
719		- frame-number = <6>;
720		- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
721		- reg = <0xb028000 0x1000>;
722		- status = "disabled";
723		- };
724		- };
725		-
726		- spmi_bus: spmi@200f000 {
727		- compatible = "qcom,spmi-pmic-arb";
728		- reg = <0x200f000 0x001000>,
729		- <0x2400000 0x400000>,
730		- <0x2c00000 0x400000>,
731		- <0x3800000 0x200000>,
732		- <0x200a000 0x002100>;
733		- reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
734		- interrupt-names = "periph_irq";
735		- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
736		- qcom,ee = <0>;
737		- qcom,channel = <0>;
738		- #address-cells = <2>;
739		- #size-cells = <0>;
740		- interrupt-controller;
741		- #interrupt-cells = <4>;
742		- };
743		-
744		- rng@22000 {
745		- compatible = "qcom,prng";
746		- reg = <0x00022000 0x200>;
747		- clocks = <&gcc GCC_PRNG_AHB_CLK>;
748		- clock-names = "core";
749		- };
750		-
751		- qfprom: qfprom@5c000 {
752		- compatible = "qcom,qfprom";
753		- reg = <0x5c000 0x1000>;
754		- #address-cells = <1>;
755		- #size-cells = <1>;
756		- tsens_caldata: caldata@d0 {
757		- reg = <0xd0 0x8>;
758		- };
759		- tsens_calsel: calsel@ec {
760		- reg = <0xec 0x4>;
761		- };
762		- };
763		-
764		- tsens: thermal-sensor@4a8000 {
765		- compatible = "qcom,msm8916-tsens";
766		- reg = <0x4a8000 0x2000>;
767		- nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
768		- nvmem-cell-names = "calib", "calib_sel";
769		- #thermal-sensor-cells = <1>;
770		- };
771		-
772		- apps_iommu: iommu@1ef0000 {
773		- #address-cells = <1>;
774		- #size-cells = <1>;
775		- #iommu-cells = <1>;
776		- compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
777		- ranges = <0 0x1e20000 0x40000>;
778		- reg = <0x1ef0000 0x3000>;
779		- clocks = <&gcc GCC_SMMU_CFG_CLK>,
780		- <&gcc GCC_APSS_TCU_CLK>;
781		- clock-names = "iface", "bus";
782		- qcom,iommu-secure-id = <17>;
783		-
784		- // mdp_0:
785		- iommu-ctx@4000 {
786		- compatible = "qcom,msm-iommu-v1-ns";
787		- reg = <0x4000 0x1000>;
788		- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
789		- };
790		-
791		- // venus_ns:
792		- iommu-ctx@5000 {
793		- compatible = "qcom,msm-iommu-v1-sec";
794		- reg = <0x5000 0x1000>;
795		- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
796		- };
797		- };
798		-
799		- gpu_iommu: iommu@1f08000 {
800		- #address-cells = <1>;
801		- #size-cells = <1>;
802		- #iommu-cells = <1>;
803		- compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
804		- ranges = <0 0x1f08000 0x10000>;
805		- clocks = <&gcc GCC_SMMU_CFG_CLK>,
806		- <&gcc GCC_GFX_TCU_CLK>;
807		- clock-names = "iface", "bus";
808		- qcom,iommu-secure-id = <18>;
809		-
810		- // gfx3d_user:
811		- iommu-ctx@1000 {
812		- compatible = "qcom,msm-iommu-v1-ns";
813		- reg = <0x1000 0x1000>;
814		- interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
815		- };
816		-
817		- // gfx3d_priv:
818		- iommu-ctx@2000 {
819		- compatible = "qcom,msm-iommu-v1-ns";
820		- reg = <0x2000 0x1000>;
821		- interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
822		- };
823		- };
824		-
825		- gpu@1c00000 {
826		- compatible = "qcom,adreno-306.0", "qcom,adreno";
827		- reg = <0x01c00000 0x20000>;
828		- reg-names = "kgsl_3d0_reg_memory";
829		- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
830		- interrupt-names = "kgsl_3d0_irq";
831		- clock-names =
832		- "core",
833		- "iface",
834		- "mem",
835		- "mem_iface",
836		- "alt_mem_iface",
837		- "gfx3d";
838		- clocks =
839		- <&gcc GCC_OXILI_GFX3D_CLK>,
840		- <&gcc GCC_OXILI_AHB_CLK>,
841		- <&gcc GCC_OXILI_GMEM_CLK>,
842		- <&gcc GCC_BIMC_GFX_CLK>,
843		- <&gcc GCC_BIMC_GPU_CLK>,
844		- <&gcc GFX3D_CLK_SRC>;
845		- power-domains = <&gcc OXILI_GDSC>;
846		- operating-points-v2 = <&gpu_opp_table>;
847		- iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
848		- };
849		-
850		- mdss: mdss@1a00000 {
851		- compatible = "qcom,mdss";
852		- reg = <0x1a00000 0x1000>,
853		- <0x1ac8000 0x3000>;
854		- reg-names = "mdss_phys", "vbif_phys";
855		-
856		- power-domains = <&gcc MDSS_GDSC>;
857		-
858		- clocks = <&gcc GCC_MDSS_AHB_CLK>,
859		- <&gcc GCC_MDSS_AXI_CLK>,
860		- <&gcc GCC_MDSS_VSYNC_CLK>;
861		- clock-names = "iface",
862		- "bus",
863		- "vsync";
864		-
865		- interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
866		-
867		- interrupt-controller;
868		- #interrupt-cells = <1>;
869		-
870		- #address-cells = <1>;
871		- #size-cells = <1>;
872		- ranges;
873		-
874		- mdp: mdp@1a01000 {
875		- compatible = "qcom,mdp5";
876		- reg = <0x1a01000 0x89000>;
877		- reg-names = "mdp_phys";
878		-
879		- interrupt-parent = <&mdss>;
880		- interrupts = <0>;
881		-
882		- clocks = <&gcc GCC_MDSS_AHB_CLK>,
883		- <&gcc GCC_MDSS_AXI_CLK>,
884		- <&gcc GCC_MDSS_MDP_CLK>,
885		- <&gcc GCC_MDSS_VSYNC_CLK>;
886		- clock-names = "iface",
887		- "bus",
888		- "core",
889		- "vsync";
890		-
891		- iommus = <&apps_iommu 4>;
892		-
893		- ports {
894		- #address-cells = <1>;
895		- #size-cells = <0>;
896		-
897		- port@0 {
898		- reg = <0>;
899		- mdp5_intf1_out: endpoint {
900		- remote-endpoint = <&dsi0_in>;
901		- };
902		- };
903		- };
904		- };
905		-
906		- dsi0: dsi@1a98000 {
907		- compatible = "qcom,mdss-dsi-ctrl";
908		- reg = <0x1a98000 0x25c>;
909		- reg-names = "dsi_ctrl";
910		-
911		- interrupt-parent = <&mdss>;
912		- interrupts = <4>;
913		-
914		- assigned-clocks = <&gcc BYTE0_CLK_SRC>,
915		- <&gcc PCLK0_CLK_SRC>;
916		- assigned-clock-parents = <&dsi_phy0 0>,
917		- <&dsi_phy0 1>;
918		-
919		- clocks = <&gcc GCC_MDSS_MDP_CLK>,
920		- <&gcc GCC_MDSS_AHB_CLK>,
921		- <&gcc GCC_MDSS_AXI_CLK>,
922		- <&gcc GCC_MDSS_BYTE0_CLK>,
923		- <&gcc GCC_MDSS_PCLK0_CLK>,
924		- <&gcc GCC_MDSS_ESC0_CLK>;
925		- clock-names = "mdp_core",
926		- "iface",
927		- "bus",
928		- "byte",
929		- "pixel",
930		- "core";
931		- phys = <&dsi_phy0>;
932		- phy-names = "dsi-phy";
933		-
934		- ports {
935		- #address-cells = <1>;
936		- #size-cells = <0>;
937		-
938		- port@0 {
939		- reg = <0>;
940		- dsi0_in: endpoint {
941		- remote-endpoint = <&mdp5_intf1_out>;
942		- };
943		- };
944		-
945		- port@1 {
946		- reg = <1>;
947		- dsi0_out: endpoint {
948		- };
949		- };
950		- };
951		- };
952		-
953		- dsi_phy0: dsi-phy@1a98300 {
954		- compatible = "qcom,dsi-phy-28nm-lp";
955		- reg = <0x1a98300 0xd4>,
956		- <0x1a98500 0x280>,
957		- <0x1a98780 0x30>;
958		- reg-names = "dsi_pll",
959		- "dsi_phy",
960		- "dsi_phy_regulator";
961		-
962		- #clock-cells = <1>;
963		- #phy-cells = <0>;
964		-
965		- clocks = <&gcc GCC_MDSS_AHB_CLK>;
966		- clock-names = "iface";
967		- };
968		- };
969		-
970		-
971		- hexagon@4080000 {
972		- compatible = "qcom,q6v5-pil";
973		- reg = <0x04080000 0x100>,
974		- <0x04020000 0x040>;
975		-
976		- reg-names = "qdsp6", "rmb";
977		-
978		- interrupts-extended = <&intc 0 24 1>,
979		- <&hexagon_smp2p_in 0 0>,
980		- <&hexagon_smp2p_in 1 0>,
981		- <&hexagon_smp2p_in 2 0>,
982		- <&hexagon_smp2p_in 3 0>;
983		- interrupt-names = "wdog", "fatal", "ready",
984		- "handover", "stop-ack";
985		-
986		- clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
987		- <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
988		- <&gcc GCC_BOOT_ROM_AHB_CLK>,
989		- <&xo_board>;
990		- clock-names = "iface", "bus", "mem", "xo";
991		-
992		- qcom,smem-states = <&hexagon_smp2p_out 0>;
993		- qcom,smem-state-names = "stop";
994		-
995		- resets = <&scm 0>;
996		- reset-names = "mss_restart";
997		-
998		- cx-supply = <&pm8916_s1>;
999		- mx-supply = <&pm8916_l3>;
1000		- pll-supply = <&pm8916_l7>;
1001		-
1002		- qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1003		-
1004		- status = "disabled";
1005		-
1006		- mba {
1007		- memory-region = <&mba_mem>;
1008		- };
1009		-
1010		- mpss {
1011		- memory-region = <&mpss_mem>;
1012		- };
1013		-
1014		- smd-edge {
1015		- interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1016		-
1017		- qcom,smd-edge = <0>;
1018		- qcom,ipc = <&apcs 8 12>;
1019		- qcom,remote-pid = <1>;
1020		-
1021		- label = "hexagon";
1022		- };
1023		- };
1024		-
1025		- pronto: wcnss@a21b000 {
	1655	+ pronto: remoteproc@a21b000 {
1026	1656	compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1027	1657	reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1028	1658	reg-names = "ccu", "dxe", "pmu";
1029	1659
1030	1660	memory-region = <&wcnss_mem>;
1031	1661
1032		- interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
	1662	+ interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1033	1663	<&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1034	1664	<&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1035	1665	<&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1036	1666	<&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1037	1667	interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1038		-
1039		- vddmx-supply = <&pm8916_l3>;
1040		- vddpx-supply = <&pm8916_l7>;
1041	1668
1042	1669	qcom,state = <&wcnss_smp2p_out 0>;
1043	1670	qcom,state-names = "stop";
..	..	@@ -1052,15 +1679,10 @@
1052	1679
1053	1680	clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1054	1681	clock-names = "xo";
1055		-
1056		- vddxo-supply = <&pm8916_l7>;
1057		- vddrfa-supply = <&pm8916_s3>;
1058		- vddpa-supply = <&pm8916_l9>;
1059		- vdddig-supply = <&pm8916_l5>;
1060	1682	};
1061	1683
1062	1684	smd-edge {
1063		- interrupts = <0 142 1>;
	1685	+ interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1064	1686
1065	1687	qcom,ipc = <&apcs 8 17>;
1066	1688	qcom,smd-edge = <6>;
..	..	@@ -1081,8 +1703,8 @@
1081	1703	wifi {
1082	1704	compatible = "qcom,wcnss-wlan";
1083	1705
1084		- interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
1085		- <0 146 IRQ_TYPE_LEVEL_HIGH>;
	1706	+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
	1707	+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1086	1708	interrupt-names = "tx", "rx";
1087	1709
1088	1710	qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
..	..	@@ -1092,428 +1714,207 @@
1092	1714	};
1093	1715	};
1094	1716
1095		- tpiu@820000 {
1096		- compatible = "arm,coresight-tpiu", "arm,primecell";
1097		- reg = <0x820000 0x1000>;
1098		-
1099		- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1100		- clock-names = "apb_pclk", "atclk";
1101		-
1102		- port {
1103		- tpiu_in: endpoint {
1104		- slave-mode;
1105		- remote-endpoint = <&replicator_out1>;
1106		- };
1107		- };
	1717	+ intc: interrupt-controller@b000000 {
	1718	+ compatible = "qcom,msm-qgic2";
	1719	+ interrupt-controller;
	1720	+ #interrupt-cells = <3>;
	1721	+ reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1108	1722	};
1109	1723
1110		- funnel@821000 {
1111		- compatible = "arm,coresight-funnel", "arm,primecell";
1112		- reg = <0x821000 0x1000>;
1113		-
1114		- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1115		- clock-names = "apb_pclk", "atclk";
1116		-
1117		- ports {
1118		- #address-cells = <1>;
1119		- #size-cells = <0>;
1120		-
1121		- /*
1122		- * Not described input ports:
1123		- * 0 - connected to Resource and Power Manger CPU ETM
1124		- * 1 - not-connected
1125		- * 2 - connected to Modem CPU ETM
1126		- * 3 - not-connected
1127		- * 5 - not-connected
1128		- * 6 - connected trought funnel to Wireless CPU ETM
1129		- * 7 - connected to STM component
1130		- */
1131		-
1132		- port@4 {
1133		- reg = <4>;
1134		- funnel0_in4: endpoint {
1135		- slave-mode;
1136		- remote-endpoint = <&funnel1_out>;
1137		- };
1138		- };
1139		- port@8 {
1140		- reg = <0>;
1141		- funnel0_out: endpoint {
1142		- remote-endpoint = <&etf_in>;
1143		- };
1144		- };
1145		- };
	1724	+ apcs: mailbox@b011000 {
	1725	+ compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
	1726	+ reg = <0x0b011000 0x1000>;
	1727	+ #mbox-cells = <1>;
	1728	+ clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
	1729	+ clock-names = "pll", "aux";
	1730	+ #clock-cells = <0>;
1146	1731	};
1147	1732
1148		- replicator@824000 {
1149		- compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1150		- reg = <0x824000 0x1000>;
1151		-
1152		- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1153		- clock-names = "apb_pclk", "atclk";
1154		-
1155		- ports {
1156		- #address-cells = <1>;
1157		- #size-cells = <0>;
1158		-
1159		- port@0 {
1160		- reg = <0>;
1161		- replicator_out0: endpoint {
1162		- remote-endpoint = <&etr_in>;
1163		- };
1164		- };
1165		- port@1 {
1166		- reg = <1>;
1167		- replicator_out1: endpoint {
1168		- remote-endpoint = <&tpiu_in>;
1169		- };
1170		- };
1171		- port@2 {
1172		- reg = <0>;
1173		- replicator_in: endpoint {
1174		- slave-mode;
1175		- remote-endpoint = <&etf_out>;
1176		- };
1177		- };
1178		- };
	1733	+ a53pll: clock@b016000 {
	1734	+ compatible = "qcom,msm8916-a53pll";
	1735	+ reg = <0x0b016000 0x40>;
	1736	+ #clock-cells = <0>;
1179	1737	};
1180	1738
1181		- etf@825000 {
1182		- compatible = "arm,coresight-tmc", "arm,primecell";
1183		- reg = <0x825000 0x1000>;
	1739	+ timer@b020000 {
	1740	+ #address-cells = <1>;
	1741	+ #size-cells = <1>;
	1742	+ ranges;
	1743	+ compatible = "arm,armv7-timer-mem";
	1744	+ reg = <0x0b020000 0x1000>;
	1745	+ clock-frequency = <19200000>;
1184	1746
1185		- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1186		- clock-names = "apb_pclk", "atclk";
1187		-
1188		- ports {
1189		- #address-cells = <1>;
1190		- #size-cells = <0>;
1191		-
1192		- port@0 {
1193		- reg = <0>;
1194		- etf_in: endpoint {
1195		- slave-mode;
1196		- remote-endpoint = <&funnel0_out>;
1197		- };
1198		- };
1199		- port@1 {
1200		- reg = <0>;
1201		- etf_out: endpoint {
1202		- remote-endpoint = <&replicator_in>;
1203		- };
1204		- };
1205		- };
1206		- };
1207		-
1208		- etr@826000 {
1209		- compatible = "arm,coresight-tmc", "arm,primecell";
1210		- reg = <0x826000 0x1000>;
1211		-
1212		- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1213		- clock-names = "apb_pclk", "atclk";
1214		-
1215		- port {
1216		- etr_in: endpoint {
1217		- slave-mode;
1218		- remote-endpoint = <&replicator_out0>;
1219		- };
1220		- };
1221		- };
1222		-
1223		- funnel@841000 { /* APSS funnel only 4 inputs are used */
1224		- compatible = "arm,coresight-funnel", "arm,primecell";
1225		- reg = <0x841000 0x1000>;
1226		-
1227		- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1228		- clock-names = "apb_pclk", "atclk";
1229		-
1230		- ports {
1231		- #address-cells = <1>;
1232		- #size-cells = <0>;
1233		-
1234		- port@0 {
1235		- reg = <0>;
1236		- funnel1_in0: endpoint {
1237		- slave-mode;
1238		- remote-endpoint = <&etm0_out>;
1239		- };
1240		- };
1241		- port@1 {
1242		- reg = <1>;
1243		- funnel1_in1: endpoint {
1244		- slave-mode;
1245		- remote-endpoint = <&etm1_out>;
1246		- };
1247		- };
1248		- port@2 {
1249		- reg = <2>;
1250		- funnel1_in2: endpoint {
1251		- slave-mode;
1252		- remote-endpoint = <&etm2_out>;
1253		- };
1254		- };
1255		- port@3 {
1256		- reg = <3>;
1257		- funnel1_in3: endpoint {
1258		- slave-mode;
1259		- remote-endpoint = <&etm3_out>;
1260		- };
1261		- };
1262		- port@4 {
1263		- reg = <0>;
1264		- funnel1_out: endpoint {
1265		- remote-endpoint = <&funnel0_in4>;
1266		- };
1267		- };
1268		- };
1269		- };
1270		-
1271		- debug@850000 {
1272		- compatible = "arm,coresight-cpu-debug","arm,primecell";
1273		- reg = <0x850000 0x1000>;
1274		- clocks = <&rpmcc RPM_QDSS_CLK>;
1275		- clock-names = "apb_pclk";
1276		- cpu = <&CPU0>;
1277		- };
1278		-
1279		- debug@852000 {
1280		- compatible = "arm,coresight-cpu-debug","arm,primecell";
1281		- reg = <0x852000 0x1000>;
1282		- clocks = <&rpmcc RPM_QDSS_CLK>;
1283		- clock-names = "apb_pclk";
1284		- cpu = <&CPU1>;
1285		- };
1286		-
1287		- debug@854000 {
1288		- compatible = "arm,coresight-cpu-debug","arm,primecell";
1289		- reg = <0x854000 0x1000>;
1290		- clocks = <&rpmcc RPM_QDSS_CLK>;
1291		- clock-names = "apb_pclk";
1292		- cpu = <&CPU2>;
1293		- };
1294		-
1295		- debug@856000 {
1296		- compatible = "arm,coresight-cpu-debug","arm,primecell";
1297		- reg = <0x856000 0x1000>;
1298		- clocks = <&rpmcc RPM_QDSS_CLK>;
1299		- clock-names = "apb_pclk";
1300		- cpu = <&CPU3>;
1301		- };
1302		-
1303		- etm@85c000 {
1304		- compatible = "arm,coresight-etm4x", "arm,primecell";
1305		- reg = <0x85c000 0x1000>;
1306		-
1307		- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1308		- clock-names = "apb_pclk", "atclk";
1309		-
1310		- cpu = <&CPU0>;
1311		-
1312		- port {
1313		- etm0_out: endpoint {
1314		- remote-endpoint = <&funnel1_in0>;
1315		- };
1316		- };
1317		- };
1318		-
1319		- etm@85d000 {
1320		- compatible = "arm,coresight-etm4x", "arm,primecell";
1321		- reg = <0x85d000 0x1000>;
1322		-
1323		- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1324		- clock-names = "apb_pclk", "atclk";
1325		-
1326		- cpu = <&CPU1>;
1327		-
1328		- port {
1329		- etm1_out: endpoint {
1330		- remote-endpoint = <&funnel1_in1>;
1331		- };
1332		- };
1333		- };
1334		-
1335		- etm@85e000 {
1336		- compatible = "arm,coresight-etm4x", "arm,primecell";
1337		- reg = <0x85e000 0x1000>;
1338		-
1339		- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1340		- clock-names = "apb_pclk", "atclk";
1341		-
1342		- cpu = <&CPU2>;
1343		-
1344		- port {
1345		- etm2_out: endpoint {
1346		- remote-endpoint = <&funnel1_in2>;
1347		- };
1348		- };
1349		- };
1350		-
1351		- etm@85f000 {
1352		- compatible = "arm,coresight-etm4x", "arm,primecell";
1353		- reg = <0x85f000 0x1000>;
1354		-
1355		- clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1356		- clock-names = "apb_pclk", "atclk";
1357		-
1358		- cpu = <&CPU3>;
1359		-
1360		- port {
1361		- etm3_out: endpoint {
1362		- remote-endpoint = <&funnel1_in3>;
1363		- };
1364		- };
1365		- };
1366		-
1367		- venus: video-codec@1d00000 {
1368		- compatible = "qcom,msm8916-venus";
1369		- reg = <0x01d00000 0xff000>;
1370		- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1371		- power-domains = <&gcc VENUS_GDSC>;
1372		- clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1373		- <&gcc GCC_VENUS0_AHB_CLK>,
1374		- <&gcc GCC_VENUS0_AXI_CLK>;
1375		- clock-names = "core", "iface", "bus";
1376		- iommus = <&apps_iommu 5>;
1377		- memory-region = <&venus_mem>;
1378		- status = "okay";
1379		-
1380		- video-decoder {
1381		- compatible = "venus-decoder";
	1747	+ frame@b021000 {
	1748	+ frame-number = <0>;
	1749	+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	1750	+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	1751	+ reg = <0x0b021000 0x1000>,
	1752	+ <0x0b022000 0x1000>;
1382	1753	};
1383	1754
1384		- video-encoder {
1385		- compatible = "venus-encoder";
	1755	+ frame@b023000 {
	1756	+ frame-number = <1>;
	1757	+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	1758	+ reg = <0x0b023000 0x1000>;
	1759	+ status = "disabled";
	1760	+ };
	1761	+
	1762	+ frame@b024000 {
	1763	+ frame-number = <2>;
	1764	+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	1765	+ reg = <0x0b024000 0x1000>;
	1766	+ status = "disabled";
	1767	+ };
	1768	+
	1769	+ frame@b025000 {
	1770	+ frame-number = <3>;
	1771	+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	1772	+ reg = <0x0b025000 0x1000>;
	1773	+ status = "disabled";
	1774	+ };
	1775	+
	1776	+ frame@b026000 {
	1777	+ frame-number = <4>;
	1778	+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	1779	+ reg = <0x0b026000 0x1000>;
	1780	+ status = "disabled";
	1781	+ };
	1782	+
	1783	+ frame@b027000 {
	1784	+ frame-number = <5>;
	1785	+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	1786	+ reg = <0x0b027000 0x1000>;
	1787	+ status = "disabled";
	1788	+ };
	1789	+
	1790	+ frame@b028000 {
	1791	+ frame-number = <6>;
	1792	+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	1793	+ reg = <0x0b028000 0x1000>;
	1794	+ status = "disabled";
1386	1795	};
1387	1796	};
1388	1797	};
1389	1798
1390		- smd {
1391		- compatible = "qcom,smd";
	1799	+ thermal-zones {
	1800	+ cpu0-1-thermal {
	1801	+ polling-delay-passive = <250>;
	1802	+ polling-delay = <1000>;
1392	1803
1393		- rpm {
1394		- interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1395		- qcom,ipc = <&apcs 8 0>;
1396		- qcom,smd-edge = <15>;
	1804	+ thermal-sensors = <&tsens 5>;
1397	1805
1398		- rpm_requests {
1399		- compatible = "qcom,rpm-msm8916";
1400		- qcom,smd-channels = "rpm_requests";
1401		-
1402		- rpmcc: qcom,rpmcc {
1403		- compatible = "qcom,rpmcc-msm8916";
1404		- #clock-cells = <1>;
	1806	+ trips {
	1807	+ cpu0_1_alert0: trip-point0 {
	1808	+ temperature = <75000>;
	1809	+ hysteresis = <2000>;
	1810	+ type = "passive";
1405	1811	};
	1812	+ cpu0_1_crit: cpu_crit {
	1813	+ temperature = <110000>;
	1814	+ hysteresis = <2000>;
	1815	+ type = "critical";
	1816	+ };
	1817	+ };
1406	1818
1407		- smd_rpm_regulators: pm8916-regulators {
1408		- compatible = "qcom,rpm-pm8916-regulators";
1409		-
1410		- pm8916_s1: s1 {};
1411		- pm8916_s3: s3 {};
1412		- pm8916_s4: s4 {};
1413		-
1414		- pm8916_l1: l1 {};
1415		- pm8916_l2: l2 {};
1416		- pm8916_l3: l3 {};
1417		- pm8916_l4: l4 {};
1418		- pm8916_l5: l5 {};
1419		- pm8916_l6: l6 {};
1420		- pm8916_l7: l7 {};
1421		- pm8916_l8: l8 {};
1422		- pm8916_l9: l9 {};
1423		- pm8916_l10: l10 {};
1424		- pm8916_l11: l11 {};
1425		- pm8916_l12: l12 {};
1426		- pm8916_l13: l13 {};
1427		- pm8916_l14: l14 {};
1428		- pm8916_l15: l15 {};
1429		- pm8916_l16: l16 {};
1430		- pm8916_l17: l17 {};
1431		- pm8916_l18: l18 {};
	1819	+ cooling-maps {
	1820	+ map0 {
	1821	+ trip = <&cpu0_1_alert0>;
	1822	+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	1823	+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	1824	+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	1825	+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1432	1826	};
1433	1827	};
1434	1828	};
	1829	+
	1830	+ cpu2-3-thermal {
	1831	+ polling-delay-passive = <250>;
	1832	+ polling-delay = <1000>;
	1833	+
	1834	+ thermal-sensors = <&tsens 4>;
	1835	+
	1836	+ trips {
	1837	+ cpu2_3_alert0: trip-point0 {
	1838	+ temperature = <75000>;
	1839	+ hysteresis = <2000>;
	1840	+ type = "passive";
	1841	+ };
	1842	+ cpu2_3_crit: cpu_crit {
	1843	+ temperature = <110000>;
	1844	+ hysteresis = <2000>;
	1845	+ type = "critical";
	1846	+ };
	1847	+ };
	1848	+
	1849	+ cooling-maps {
	1850	+ map0 {
	1851	+ trip = <&cpu2_3_alert0>;
	1852	+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	1853	+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	1854	+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
	1855	+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	1856	+ };
	1857	+ };
	1858	+ };
	1859	+
	1860	+ gpu-thermal {
	1861	+ polling-delay-passive = <250>;
	1862	+ polling-delay = <1000>;
	1863	+
	1864	+ thermal-sensors = <&tsens 2>;
	1865	+
	1866	+ trips {
	1867	+ gpu_alert0: trip-point0 {
	1868	+ temperature = <75000>;
	1869	+ hysteresis = <2000>;
	1870	+ type = "passive";
	1871	+ };
	1872	+ gpu_crit: gpu_crit {
	1873	+ temperature = <95000>;
	1874	+ hysteresis = <2000>;
	1875	+ type = "critical";
	1876	+ };
	1877	+ };
	1878	+ };
	1879	+
	1880	+ camera-thermal {
	1881	+ polling-delay-passive = <250>;
	1882	+ polling-delay = <1000>;
	1883	+
	1884	+ thermal-sensors = <&tsens 1>;
	1885	+
	1886	+ trips {
	1887	+ cam_alert0: trip-point0 {
	1888	+ temperature = <75000>;
	1889	+ hysteresis = <2000>;
	1890	+ type = "hot";
	1891	+ };
	1892	+ };
	1893	+ };
	1894	+
	1895	+ modem-thermal {
	1896	+ polling-delay-passive = <250>;
	1897	+ polling-delay = <1000>;
	1898	+
	1899	+ thermal-sensors = <&tsens 0>;
	1900	+
	1901	+ trips {
	1902	+ modem_alert0: trip-point0 {
	1903	+ temperature = <85000>;
	1904	+ hysteresis = <2000>;
	1905	+ type = "hot";
	1906	+ };
	1907	+ };
	1908	+ };
	1909	+
1435	1910	};
1436	1911
1437		- hexagon-smp2p {
1438		- compatible = "qcom,smp2p";
1439		- qcom,smem = <435>, <428>;
1440		-
1441		- interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1442		-
1443		- qcom,ipc = <&apcs 8 14>;
1444		-
1445		- qcom,local-pid = <0>;
1446		- qcom,remote-pid = <1>;
1447		-
1448		- hexagon_smp2p_out: master-kernel {
1449		- qcom,entry-name = "master-kernel";
1450		-
1451		- #qcom,smem-state-cells = <1>;
1452		- };
1453		-
1454		- hexagon_smp2p_in: slave-kernel {
1455		- qcom,entry-name = "slave-kernel";
1456		-
1457		- interrupt-controller;
1458		- #interrupt-cells = <2>;
1459		- };
1460		- };
1461		-
1462		- wcnss-smp2p {
1463		- compatible = "qcom,smp2p";
1464		- qcom,smem = <451>, <431>;
1465		-
1466		- interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1467		-
1468		- qcom,ipc = <&apcs 8 18>;
1469		-
1470		- qcom,local-pid = <0>;
1471		- qcom,remote-pid = <4>;
1472		-
1473		- wcnss_smp2p_out: master-kernel {
1474		- qcom,entry-name = "master-kernel";
1475		-
1476		- #qcom,smem-state-cells = <1>;
1477		- };
1478		-
1479		- wcnss_smp2p_in: slave-kernel {
1480		- qcom,entry-name = "slave-kernel";
1481		-
1482		- interrupt-controller;
1483		- #interrupt-cells = <2>;
1484		- };
1485		- };
1486		-
1487		- smsm {
1488		- compatible = "qcom,smsm";
1489		-
1490		- #address-cells = <1>;
1491		- #size-cells = <0>;
1492		-
1493		- qcom,ipc-1 = <&apcs 8 13>;
1494		- qcom,ipc-3 = <&apcs 8 19>;
1495		-
1496		- apps_smsm: apps@0 {
1497		- reg = <0>;
1498		-
1499		- #qcom,smem-state-cells = <1>;
1500		- };
1501		-
1502		- hexagon_smsm: hexagon@1 {
1503		- reg = <1>;
1504		- interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1505		-
1506		- interrupt-controller;
1507		- #interrupt-cells = <2>;
1508		- };
1509		-
1510		- wcnss_smsm: wcnss@6 {
1511		- reg = <6>;
1512		- interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1513		-
1514		- interrupt-controller;
1515		- #interrupt-cells = <2>;
1516		- };
	1912	+ timer {
	1913	+ compatible = "arm,armv8-timer";
	1914	+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	1915	+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	1916	+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	1917	+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
1517	1918	};
1518	1919	};
1519	1920