forked from ~ljy/RK356X_SDK_RELEASE
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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/arch/arm64/boot/dts/qcom/ipq8074.dtsi
....@@ -108,7 +108,7 @@
108108 				#phy-cells = <0>;
109109 				clocks = <&gcc GCC_USB1_PIPE_CLK>;
110110 				clock-names = "pipe0";
111
-				clock-output-names = "gcc_usb1_pipe_clk_src";
111
+				clock-output-names = "usb3phy_1_cc_pipe_clk";
112112 			};
113113 		};
114114 
....@@ -151,7 +151,7 @@
151151 				#phy-cells = <0>;
152152 				clocks = <&gcc GCC_USB0_PIPE_CLK>;
153153 				clock-names = "pipe0";
154
-				clock-output-names = "gcc_usb0_pipe_clk_src";
154
+				clock-output-names = "usb3phy_0_cc_pipe_clk";
155155 			};
156156 		};
157157 
....@@ -167,34 +167,61 @@
167167 			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
168168 		};
169169 
170
-		pcie_phy0: phy@86000 {
171
-			compatible = "qcom,ipq8074-qmp-pcie-phy";
172
-			reg = <0x00086000 0x1000>;
173
-			#phy-cells = <0>;
174
-			clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
175
-			clock-names = "pipe_clk";
176
-			clock-output-names = "pcie20_phy0_pipe_clk";
170
+		pcie_qmp0: phy@84000 {
171
+			compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
172
+			reg = <0x00084000 0x1bc>;
173
+			#address-cells = <1>;
174
+			#size-cells = <1>;
175
+			ranges;
177176 
177
+			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
178
+				<&gcc GCC_PCIE0_AHB_CLK>;
179
+			clock-names = "aux", "cfg_ahb";
178180 			resets = <&gcc GCC_PCIE0_PHY_BCR>,
179181 				<&gcc GCC_PCIE0PHY_PHY_BCR>;
180182 			reset-names = "phy",
181183 				      "common";
182184 			status = "disabled";
185
+
186
+			pcie_phy0: phy@84200 {
187
+				reg = <0x84200 0x16c>,
188
+				      <0x84400 0x200>,
189
+				      <0x84800 0x1f0>,
190
+				      <0x84c00 0xf4>;
191
+				#phy-cells = <0>;
192
+				#clock-cells = <0>;
193
+				clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
194
+				clock-names = "pipe0";
195
+				clock-output-names = "pcie20_phy0_pipe_clk";
196
+			};
183197 		};
184198 
185
-		pcie_phy1: phy@8e000 {
199
+		pcie_qmp1: phy@8e000 {
186200 			compatible = "qcom,ipq8074-qmp-pcie-phy";
187
-			reg = <0x0008e000 0x1000>;
188
-			#phy-cells = <0>;
189
-			clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
190
-			clock-names = "pipe_clk";
191
-			clock-output-names = "pcie20_phy1_pipe_clk";
201
+			reg = <0x0008e000 0x1c4>;
202
+			#address-cells = <1>;
203
+			#size-cells = <1>;
204
+			ranges;
192205 
206
+			clocks = <&gcc GCC_PCIE1_AUX_CLK>,
207
+				<&gcc GCC_PCIE1_AHB_CLK>;
208
+			clock-names = "aux", "cfg_ahb";
193209 			resets = <&gcc GCC_PCIE1_PHY_BCR>,
194210 				<&gcc GCC_PCIE1PHY_PHY_BCR>;
195211 			reset-names = "phy",
196212 				      "common";
197213 			status = "disabled";
214
+
215
+			pcie_phy1: phy@8e200 {
216
+				reg = <0x8e200 0x130>,
217
+				      <0x8e400 0x200>,
218
+				      <0x8e800 0x1f8>;
219
+				#phy-cells = <0>;
220
+				#clock-cells = <0>;
221
+				clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
222
+				clock-names = "pipe0";
223
+				clock-output-names = "pcie20_phy1_pipe_clk";
224
+			};
198225 		};
199226 
200227 		tlmm: pinctrl@1000000 {
....@@ -580,10 +607,8 @@
580607 			phys = <&pcie_phy1>;
581608 			phy-names = "pciephy";
582609 
583
-			ranges = <0x81000000 0 0x10200000 0x10200000
584
-				  0 0x100000   /* downstream I/O */
585
-				  0x82000000 0 0x10300000 0x10300000
586
-				  0 0xd00000>; /* non-prefetchable memory */
610
+			ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>,   /* I/O */
611
+				 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
587612 
588613 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
589614 			interrupt-names = "msi";
....@@ -626,26 +651,26 @@
626651 		};
627652 
628653 		pcie0: pci@20000000 {
629
-			compatible = "qcom,pcie-ipq8074";
654
+			compatible = "qcom,pcie-ipq8074-gen3";
630655 			reg = <0x20000000 0xf1d>,
631656 			      <0x20000f20 0xa8>,
632
-			      <0x00080000 0x2000>,
657
+			      <0x20001000 0x1000>,
658
+			      <0x00080000 0x4000>,
633659 			      <0x20100000 0x1000>;
634
-			reg-names = "dbi", "elbi", "parf", "config";
660
+			reg-names = "dbi", "elbi", "atu", "parf", "config";
635661 			device_type = "pci";
636662 			linux,pci-domain = <0>;
637663 			bus-range = <0x00 0xff>;
638664 			num-lanes = <1>;
665
+			max-link-speed = <3>;
639666 			#address-cells = <3>;
640667 			#size-cells = <2>;
641668 
642669 			phys = <&pcie_phy0>;
643670 			phy-names = "pciephy";
644671 
645
-			ranges = <0x81000000 0 0x20200000 0x20200000
646
-				  0 0x100000   /* downstream I/O */
647
-				  0x82000000 0 0x20300000 0x20300000
648
-				  0 0xd00000>; /* non-prefetchable memory */
672
+			ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>,   /* I/O */
673
+				 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
649674 
650675 			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
651676 			interrupt-names = "msi";
....@@ -663,28 +688,30 @@
663688 			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
664689 				 <&gcc GCC_PCIE0_AXI_M_CLK>,
665690 				 <&gcc GCC_PCIE0_AXI_S_CLK>,
666
-				 <&gcc GCC_PCIE0_AHB_CLK>,
667
-				 <&gcc GCC_PCIE0_AUX_CLK>;
668
-
691
+				 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
692
+				 <&gcc GCC_PCIE0_RCHNG_CLK>;
669693 			clock-names = "iface",
670694 				      "axi_m",
671695 				      "axi_s",
672
-				      "ahb",
673
-				      "aux";
696
+				      "axi_bridge",
697
+				      "rchng";
698
+
674699 			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
675700 				 <&gcc GCC_PCIE0_SLEEP_ARES>,
676701 				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
677702 				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
678703 				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
679704 				 <&gcc GCC_PCIE0_AHB_ARES>,
680
-				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
705
+				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
706
+				 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
681707 			reset-names = "pipe",
682708 				      "sleep",
683709 				      "sticky",
684710 				      "axi_m",
685711 				      "axi_s",
686712 				      "ahb",
687
-				      "axi_m_sticky";
713
+				      "axi_m_sticky",
714
+				      "axi_s_sticky";
688715 			status = "disabled";
689716 		};
690717 	};