forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/arch/arm64/boot/dts/mediatek/mt8173.dtsi
....@@ -18,6 +18,8 @@
1818 #include <dt-bindings/phy/phy.h>
1919 #include <dt-bindings/power/mt8173-power.h>
2020 #include <dt-bindings/reset/mt8173-resets.h>
21
+#include <dt-bindings/gce/mt8173-gce.h>
22
+#include <dt-bindings/thermal/thermal.h>
2123 #include "mt8173-pinfunc.h"
2224 
2325 / {
....@@ -41,14 +43,18 @@
4143 		dpi0 = &dpi0;
4244 		dsi0 = &dsi0;
4345 		dsi1 = &dsi1;
44
-		mdp_rdma0 = &mdp_rdma0;
45
-		mdp_rdma1 = &mdp_rdma1;
46
-		mdp_rsz0 = &mdp_rsz0;
47
-		mdp_rsz1 = &mdp_rsz1;
48
-		mdp_rsz2 = &mdp_rsz2;
49
-		mdp_wdma0 = &mdp_wdma0;
50
-		mdp_wrot0 = &mdp_wrot0;
51
-		mdp_wrot1 = &mdp_wrot1;
46
+		mdp-rdma0 = &mdp_rdma0;
47
+		mdp-rdma1 = &mdp_rdma1;
48
+		mdp-rsz0 = &mdp_rsz0;
49
+		mdp-rsz1 = &mdp_rsz1;
50
+		mdp-rsz2 = &mdp_rsz2;
51
+		mdp-wdma0 = &mdp_wdma0;
52
+		mdp-wrot0 = &mdp_wrot0;
53
+		mdp-wrot1 = &mdp_wrot1;
54
+		serial0 = &uart0;
55
+		serial1 = &uart1;
56
+		serial2 = &uart2;
57
+		serial3 = &uart3;
5258 	};
5359 
5460 	cluster0_opp: opp_table0 {
....@@ -156,10 +162,12 @@
156162 			enable-method = "psci";
157163 			cpu-idle-states = <&CPU_SLEEP_0>;
158164 			#cooling-cells = <2>;
165
+			dynamic-power-coefficient = <263>;
159166 			clocks = <&infracfg CLK_INFRA_CA53SEL>,
160167 				 <&apmixedsys CLK_APMIXED_MAINPLL>;
161168 			clock-names = "cpu", "intermediate";
162169 			operating-points-v2 = <&cluster0_opp>;
170
+			capacity-dmips-mhz = <740>;
163171 		};
164172 
165173 		cpu1: cpu@1 {
....@@ -169,36 +177,42 @@
169177 			enable-method = "psci";
170178 			cpu-idle-states = <&CPU_SLEEP_0>;
171179 			#cooling-cells = <2>;
180
+			dynamic-power-coefficient = <263>;
172181 			clocks = <&infracfg CLK_INFRA_CA53SEL>,
173182 				 <&apmixedsys CLK_APMIXED_MAINPLL>;
174183 			clock-names = "cpu", "intermediate";
175184 			operating-points-v2 = <&cluster0_opp>;
185
+			capacity-dmips-mhz = <740>;
176186 		};
177187 
178188 		cpu2: cpu@100 {
179189 			device_type = "cpu";
180
-			compatible = "arm,cortex-a57";
190
+			compatible = "arm,cortex-a72";
181191 			reg = <0x100>;
182192 			enable-method = "psci";
183193 			cpu-idle-states = <&CPU_SLEEP_0>;
184194 			#cooling-cells = <2>;
185
-			clocks = <&infracfg CLK_INFRA_CA57SEL>,
195
+			dynamic-power-coefficient = <530>;
196
+			clocks = <&infracfg CLK_INFRA_CA72SEL>,
186197 				 <&apmixedsys CLK_APMIXED_MAINPLL>;
187198 			clock-names = "cpu", "intermediate";
188199 			operating-points-v2 = <&cluster1_opp>;
200
+			capacity-dmips-mhz = <1024>;
189201 		};
190202 
191203 		cpu3: cpu@101 {
192204 			device_type = "cpu";
193
-			compatible = "arm,cortex-a57";
205
+			compatible = "arm,cortex-a72";
194206 			reg = <0x101>;
195207 			enable-method = "psci";
196208 			cpu-idle-states = <&CPU_SLEEP_0>;
197209 			#cooling-cells = <2>;
198
-			clocks = <&infracfg CLK_INFRA_CA57SEL>,
210
+			dynamic-power-coefficient = <530>;
211
+			clocks = <&infracfg CLK_INFRA_CA72SEL>,
199212 				 <&apmixedsys CLK_APMIXED_MAINPLL>;
200213 			clock-names = "cpu", "intermediate";
201214 			operating-points-v2 = <&cluster1_opp>;
215
+			capacity-dmips-mhz = <1024>;
202216 		};
203217 
204218 		idle-states {
....@@ -213,6 +227,20 @@
213227 				arm,psci-suspend-param = <0x0010000>;
214228 			};
215229 		};
230
+	};
231
+
232
+	pmu_a53 {
233
+		compatible = "arm,cortex-a53-pmu";
234
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
235
+			     <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
236
+		interrupt-affinity = <&cpu0>, <&cpu1>;
237
+	};
238
+
239
+	pmu_a72 {
240
+		compatible = "arm,cortex-a72-pmu";
241
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
242
+			     <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
243
+		interrupt-affinity = <&cpu2>, <&cpu3>;
216244 	};
217245 
218246 	psci {
....@@ -275,12 +303,18 @@
275303 			cooling-maps {
276304 				map0 {
277305 					trip = <&target>;
278
-					cooling-device = <&cpu0 0 0>;
306
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT
307
+							  THERMAL_NO_LIMIT>,
308
+							 <&cpu1 THERMAL_NO_LIMIT
309
+							  THERMAL_NO_LIMIT>;
279310 					contribution = <3072>;
280311 				};
281312 				map1 {
282313 					trip = <&target>;
283
-					cooling-device = <&cpu2 0 0>;
314
+					cooling-device = <&cpu2 THERMAL_NO_LIMIT
315
+							  THERMAL_NO_LIMIT>,
316
+							 <&cpu3 THERMAL_NO_LIMIT
317
+							  THERMAL_NO_LIMIT>;
284318 					contribution = <1024>;
285319 				};
286320 			};
....@@ -310,6 +344,7 @@
310344 			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
311345 			     <GIC_PPI 10
312346 			      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
347
+		arm,no-tick-in-suspend;
313348 	};
314349 
315350 	soc {
....@@ -415,7 +450,7 @@
415450 			};
416451 		};
417452 
418
-		scpsys: scpsys@10006000 {
453
+		scpsys: power-controller@10006000 {
419454 			compatible = "mediatek,mt8173-scpsys";
420455 			#power-domain-cells = <1>;
421456 			reg = <0 0x10006000 0 0x1000>;
....@@ -519,6 +554,15 @@
519554 			#clock-cells = <0>;
520555 			#phy-cells = <0>;
521556 			status = "disabled";
557
+		};
558
+
559
+		gce: mailbox@10212000 {
560
+			compatible = "mediatek,mt8173-gce";
561
+			reg = <0 0x10212000 0 0x1000>;
562
+			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
563
+			clocks = <&infracfg CLK_INFRA_GCE>;
564
+			clock-names = "gce";
565
+			#mbox-cells = <2>;
522566 		};
523567 
524568 		mipi_tx0: mipi-dphy@10215000 {
....@@ -878,13 +922,16 @@
878922 			};
879923 		};
880924 
881
-		mmsys: clock-controller@14000000 {
925
+		mmsys: syscon@14000000 {
882926 			compatible = "mediatek,mt8173-mmsys", "syscon";
883927 			reg = <0 0x14000000 0 0x1000>;
884928 			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
885929 			assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
886930 			assigned-clock-rates = <400000000>;
887931 			#clock-cells = <1>;
932
+			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
933
+				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
934
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
888935 		};
889936 
890937 		mdp_rdma0: rdma@14001000 {
....@@ -965,6 +1012,7 @@
9651012 			clocks = <&mmsys CLK_MM_DISP_OVL0>;
9661013 			iommus = <&iommu M4U_PORT_DISP_OVL0>;
9671014 			mediatek,larb = <&larb0>;
1015
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
9681016 		};
9691017 
9701018 		ovl1: ovl@1400d000 {
....@@ -975,6 +1023,7 @@
9751023 			clocks = <&mmsys CLK_MM_DISP_OVL1>;
9761024 			iommus = <&iommu M4U_PORT_DISP_OVL1>;
9771025 			mediatek,larb = <&larb4>;
1026
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
9781027 		};
9791028 
9801029 		rdma0: rdma@1400e000 {
....@@ -985,6 +1034,7 @@
9851034 			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
9861035 			iommus = <&iommu M4U_PORT_DISP_RDMA0>;
9871036 			mediatek,larb = <&larb0>;
1037
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
9881038 		};
9891039 
9901040 		rdma1: rdma@1400f000 {
....@@ -995,6 +1045,7 @@
9951045 			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
9961046 			iommus = <&iommu M4U_PORT_DISP_RDMA1>;
9971047 			mediatek,larb = <&larb4>;
1048
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
9981049 		};
9991050 
10001051 		rdma2: rdma@14010000 {
....@@ -1005,6 +1056,7 @@
10051056 			clocks = <&mmsys CLK_MM_DISP_RDMA2>;
10061057 			iommus = <&iommu M4U_PORT_DISP_RDMA2>;
10071058 			mediatek,larb = <&larb4>;
1059
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
10081060 		};
10091061 
10101062 		wdma0: wdma@14011000 {
....@@ -1015,6 +1067,7 @@
10151067 			clocks = <&mmsys CLK_MM_DISP_WDMA0>;
10161068 			iommus = <&iommu M4U_PORT_DISP_WDMA0>;
10171069 			mediatek,larb = <&larb0>;
1070
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
10181071 		};
10191072 
10201073 		wdma1: wdma@14012000 {
....@@ -1025,6 +1078,7 @@
10251078 			clocks = <&mmsys CLK_MM_DISP_WDMA1>;
10261079 			iommus = <&iommu M4U_PORT_DISP_WDMA1>;
10271080 			mediatek,larb = <&larb4>;
1081
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
10281082 		};
10291083 
10301084 		color0: color@14013000 {
....@@ -1033,6 +1087,7 @@
10331087 			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
10341088 			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
10351089 			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1090
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
10361091 		};
10371092 
10381093 		color1: color@14014000 {
....@@ -1041,6 +1096,7 @@
10411096 			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
10421097 			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
10431098 			clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1099
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
10441100 		};
10451101 
10461102 		aal@14015000 {
....@@ -1049,6 +1105,7 @@
10491105 			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
10501106 			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
10511107 			clocks = <&mmsys CLK_MM_DISP_AAL>;
1108
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
10521109 		};
10531110 
10541111 		gamma@14016000 {
....@@ -1057,6 +1114,7 @@
10571114 			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
10581115 			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
10591116 			clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1117
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
10601118 		};
10611119 
10621120 		merge@14017000 {
....@@ -1162,6 +1220,8 @@
11621220 			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
11631221 			power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
11641222 			clocks = <&mmsys CLK_MM_MUTEX_32K>;
1223
+			mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
1224
+                                              <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
11651225 		};
11661226 
11671227 		larb0: larb@14021000 {
....@@ -1295,6 +1355,15 @@
12951355 				      "vencpll",
12961356 				      "venc_lt_sel",
12971357 				      "vdec_bus_clk_src";
1358
+			assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1359
+					  <&topckgen CLK_TOP_CCI400_SEL>,
1360
+					  <&topckgen CLK_TOP_VDEC_SEL>,
1361
+					  <&apmixedsys CLK_APMIXED_VCODECPLL>,
1362
+					  <&apmixedsys CLK_APMIXED_VENCPLL>;
1363
+			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1364
+						 <&topckgen CLK_TOP_UNIVPLL_D2>,
1365
+						 <&topckgen CLK_TOP_VCODECPLL>;
1366
+			assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
12981367 		};
12991368 
13001369 		larb1: larb@16010000 {
....@@ -1360,6 +1429,24 @@
13601429 				      "venc_sel",
13611430 				      "venc_lt_sel_src",
13621431 				      "venc_lt_sel";
1432
+			assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
1433
+					  <&topckgen CLK_TOP_VENC_LT_SEL>;
1434
+			assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
1435
+						 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1436
+		};
1437
+
1438
+		jpegdec: jpegdec@18004000 {
1439
+			compatible = "mediatek,mt8173-jpgdec";
1440
+			reg = <0 0x18004000 0 0x1000>;
1441
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;
1442
+			clocks = <&vencsys CLK_VENC_CKE0>,
1443
+				 <&vencsys CLK_VENC_CKE3>;
1444
+			clock-names = "jpgdec-smi",
1445
+				      "jpgdec";
1446
+			power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1447
+			mediatek,larb = <&larb3>;
1448
+			iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
1449
+				 <&iommu M4U_PORT_JPGDEC_BSDMA>;
13631450 		};
13641451 
13651452 		vencltsys: clock-controller@19000000 {
....@@ -1379,4 +1466,3 @@
13791466 		};
13801467 	};
13811468 };
1382
-