| .. | .. |
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| 56 | 56 | }; |
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| 57 | 57 | |
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| 58 | 58 | memory { |
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| 59 | | - reg = <0 0x40000000 0 0x3F000000>; |
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| 59 | + reg = <0 0x40000000 0 0x20000000>; |
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| 60 | 60 | }; |
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| 61 | 61 | |
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| 62 | 62 | reg_1p8v: regulator-1p8v { |
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| .. | .. |
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| 83 | 83 | regulator-max-microvolt = <5000000>; |
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| 84 | 84 | regulator-boot-on; |
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| 85 | 85 | regulator-always-on; |
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| 86 | + }; |
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| 87 | +}; |
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| 88 | + |
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| 89 | +&bch { |
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| 90 | + status = "disabled"; |
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| 91 | +}; |
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| 92 | + |
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| 93 | +&btif { |
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| 94 | + status = "okay"; |
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| 95 | +}; |
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| 96 | + |
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| 97 | +&cir { |
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| 98 | + pinctrl-names = "default"; |
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| 99 | + pinctrl-0 = <&irrx_pins>; |
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| 100 | + status = "okay"; |
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| 101 | +}; |
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| 102 | + |
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| 103 | +ð { |
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| 104 | + pinctrl-names = "default"; |
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| 105 | + pinctrl-0 = <ð_pins>; |
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| 106 | + status = "okay"; |
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| 107 | + |
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| 108 | + gmac0: mac@0 { |
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| 109 | + compatible = "mediatek,eth-mac"; |
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| 110 | + reg = <0>; |
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| 111 | + phy-mode = "2500base-x"; |
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| 112 | + |
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| 113 | + fixed-link { |
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| 114 | + speed = <2500>; |
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| 115 | + full-duplex; |
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| 116 | + pause; |
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| 117 | + }; |
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| 118 | + }; |
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| 119 | + |
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| 120 | + mdio-bus { |
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| 121 | + #address-cells = <1>; |
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| 122 | + #size-cells = <0>; |
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| 123 | + |
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| 124 | + switch@0 { |
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| 125 | + compatible = "mediatek,mt7531"; |
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| 126 | + reg = <0>; |
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| 127 | + reset-gpios = <&pio 54 0>; |
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| 128 | + |
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| 129 | + ports { |
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| 130 | + #address-cells = <1>; |
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| 131 | + #size-cells = <0>; |
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| 132 | + |
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| 133 | + port@0 { |
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| 134 | + reg = <0>; |
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| 135 | + label = "lan0"; |
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| 136 | + }; |
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| 137 | + |
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| 138 | + port@1 { |
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| 139 | + reg = <1>; |
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| 140 | + label = "lan1"; |
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| 141 | + }; |
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| 142 | + |
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| 143 | + port@2 { |
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| 144 | + reg = <2>; |
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| 145 | + label = "lan2"; |
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| 146 | + }; |
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| 147 | + |
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| 148 | + port@3 { |
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| 149 | + reg = <3>; |
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| 150 | + label = "lan3"; |
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| 151 | + }; |
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| 152 | + |
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| 153 | + port@4 { |
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| 154 | + reg = <4>; |
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| 155 | + label = "wan"; |
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| 156 | + }; |
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| 157 | + |
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| 158 | + port@6 { |
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| 159 | + reg = <6>; |
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| 160 | + label = "cpu"; |
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| 161 | + ethernet = <&gmac0>; |
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| 162 | + phy-mode = "2500base-x"; |
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| 163 | + |
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| 164 | + fixed-link { |
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| 165 | + speed = <2500>; |
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| 166 | + full-duplex; |
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| 167 | + pause; |
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| 168 | + }; |
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| 169 | + }; |
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| 170 | + }; |
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| 171 | + }; |
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| 172 | + |
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| 173 | + }; |
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| 174 | +}; |
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| 175 | + |
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| 176 | +&i2c1 { |
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| 177 | + pinctrl-names = "default"; |
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| 178 | + pinctrl-0 = <&i2c1_pins>; |
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| 179 | + status = "okay"; |
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| 180 | +}; |
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| 181 | + |
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| 182 | +&i2c2 { |
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| 183 | + pinctrl-names = "default"; |
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| 184 | + pinctrl-0 = <&i2c2_pins>; |
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| 185 | + status = "okay"; |
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| 186 | +}; |
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| 187 | + |
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| 188 | +&mmc0 { |
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| 189 | + pinctrl-names = "default", "state_uhs"; |
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| 190 | + pinctrl-0 = <&emmc_pins_default>; |
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| 191 | + pinctrl-1 = <&emmc_pins_uhs>; |
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| 192 | + status = "okay"; |
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| 193 | + bus-width = <8>; |
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| 194 | + max-frequency = <50000000>; |
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| 195 | + cap-mmc-highspeed; |
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| 196 | + mmc-hs200-1_8v; |
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| 197 | + vmmc-supply = <®_3p3v>; |
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| 198 | + vqmmc-supply = <®_1p8v>; |
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| 199 | + assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; |
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| 200 | + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; |
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| 201 | + non-removable; |
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| 202 | +}; |
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| 203 | + |
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| 204 | +&mmc1 { |
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| 205 | + pinctrl-names = "default", "state_uhs"; |
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| 206 | + pinctrl-0 = <&sd0_pins_default>; |
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| 207 | + pinctrl-1 = <&sd0_pins_uhs>; |
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| 208 | + status = "okay"; |
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| 209 | + bus-width = <4>; |
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| 210 | + max-frequency = <50000000>; |
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| 211 | + cap-sd-highspeed; |
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| 212 | + r_smpl = <1>; |
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| 213 | + cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; |
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| 214 | + vmmc-supply = <®_3p3v>; |
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| 215 | + vqmmc-supply = <®_3p3v>; |
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| 216 | + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; |
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| 217 | + assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; |
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| 218 | +}; |
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| 219 | + |
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| 220 | +&nandc { |
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| 221 | + pinctrl-names = "default"; |
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| 222 | + pinctrl-0 = <¶llel_nand_pins>; |
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| 223 | + status = "disabled"; |
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| 224 | +}; |
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| 225 | + |
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| 226 | +&nor_flash { |
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| 227 | + pinctrl-names = "default"; |
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| 228 | + pinctrl-0 = <&spi_nor_pins>; |
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| 229 | + status = "disabled"; |
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| 230 | + |
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| 231 | + flash@0 { |
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| 232 | + compatible = "jedec,spi-nor"; |
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| 233 | + reg = <0>; |
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| 86 | 234 | }; |
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| 87 | 235 | }; |
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| 88 | 236 | |
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| .. | .. |
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| 349 | 497 | }; |
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| 350 | 498 | }; |
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| 351 | 499 | |
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| 352 | | -&bch { |
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| 353 | | - status = "disabled"; |
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| 354 | | -}; |
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| 355 | | - |
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| 356 | | -&btif { |
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| 357 | | - status = "okay"; |
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| 358 | | -}; |
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| 359 | | - |
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| 360 | | -&cir { |
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| 361 | | - pinctrl-names = "default"; |
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| 362 | | - pinctrl-0 = <&irrx_pins>; |
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| 363 | | - status = "okay"; |
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| 364 | | -}; |
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| 365 | | - |
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| 366 | | -ð { |
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| 367 | | - pinctrl-names = "default"; |
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| 368 | | - pinctrl-0 = <ð_pins>; |
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| 369 | | - status = "okay"; |
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| 370 | | - |
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| 371 | | - gmac1: mac@1 { |
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| 372 | | - compatible = "mediatek,eth-mac"; |
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| 373 | | - reg = <1>; |
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| 374 | | - phy-handle = <&phy5>; |
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| 375 | | - }; |
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| 376 | | - |
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| 377 | | - mdio-bus { |
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| 378 | | - #address-cells = <1>; |
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| 379 | | - #size-cells = <0>; |
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| 380 | | - |
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| 381 | | - phy5: ethernet-phy@5 { |
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| 382 | | - reg = <5>; |
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| 383 | | - phy-mode = "sgmii"; |
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| 384 | | - }; |
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| 385 | | - }; |
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| 386 | | -}; |
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| 387 | | - |
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| 388 | | -&i2c1 { |
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| 389 | | - pinctrl-names = "default"; |
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| 390 | | - pinctrl-0 = <&i2c1_pins>; |
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| 391 | | - status = "okay"; |
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| 392 | | -}; |
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| 393 | | - |
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| 394 | | -&i2c2 { |
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| 395 | | - pinctrl-names = "default"; |
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| 396 | | - pinctrl-0 = <&i2c2_pins>; |
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| 397 | | - status = "okay"; |
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| 398 | | -}; |
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| 399 | | - |
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| 400 | | -&mmc0 { |
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| 401 | | - pinctrl-names = "default", "state_uhs"; |
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| 402 | | - pinctrl-0 = <&emmc_pins_default>; |
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| 403 | | - pinctrl-1 = <&emmc_pins_uhs>; |
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| 404 | | - status = "okay"; |
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| 405 | | - bus-width = <8>; |
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| 406 | | - max-frequency = <50000000>; |
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| 407 | | - cap-mmc-highspeed; |
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| 408 | | - mmc-hs200-1_8v; |
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| 409 | | - vmmc-supply = <®_3p3v>; |
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| 410 | | - vqmmc-supply = <®_1p8v>; |
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| 411 | | - assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>; |
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| 412 | | - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; |
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| 413 | | - non-removable; |
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| 414 | | -}; |
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| 415 | | - |
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| 416 | | -&mmc1 { |
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| 417 | | - pinctrl-names = "default", "state_uhs"; |
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| 418 | | - pinctrl-0 = <&sd0_pins_default>; |
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| 419 | | - pinctrl-1 = <&sd0_pins_uhs>; |
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| 420 | | - status = "okay"; |
|---|
| 421 | | - bus-width = <4>; |
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| 422 | | - max-frequency = <50000000>; |
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| 423 | | - cap-sd-highspeed; |
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| 424 | | - r_smpl = <1>; |
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| 425 | | - cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; |
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| 426 | | - vmmc-supply = <®_3p3v>; |
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| 427 | | - vqmmc-supply = <®_3p3v>; |
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| 428 | | - assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>; |
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| 429 | | - assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>; |
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| 430 | | -}; |
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| 431 | | - |
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| 432 | | -&nandc { |
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| 433 | | - pinctrl-names = "default"; |
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| 434 | | - pinctrl-0 = <¶llel_nand_pins>; |
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| 435 | | - status = "disabled"; |
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| 436 | | -}; |
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| 437 | | - |
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| 438 | | -&nor_flash { |
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| 439 | | - pinctrl-names = "default"; |
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| 440 | | - pinctrl-0 = <&spi_nor_pins>; |
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| 441 | | - status = "disabled"; |
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| 442 | | - |
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| 443 | | - flash@0 { |
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| 444 | | - compatible = "jedec,spi-nor"; |
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| 445 | | - reg = <0>; |
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| 446 | | - }; |
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| 447 | | -}; |
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| 448 | | - |
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| 449 | 500 | &pwm { |
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| 450 | 501 | pinctrl-names = "default"; |
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| 451 | 502 | pinctrl-0 = <&pwm7_pins>; |
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| .. | .. |
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| 506 | 557 | pinctrl-0 = <&watchdog_pins>; |
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| 507 | 558 | status = "okay"; |
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| 508 | 559 | }; |
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| 560 | + |
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| 561 | +&wmac { |
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| 562 | + status = "okay"; |
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| 563 | +}; |
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