修改4g拨号为QMI,需要在系统里后台执行quectel-CM

hc

2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5

 kernel/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
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@@ -3,6 +3,7 @@
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  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
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  *
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  * Copyright 2014-2015 Freescale Semiconductor, Inc.
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+ * Copyright 2018 NXP
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  *
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  * Mingkai Hu <Mingkai.hu@freescale.com>
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  */
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@@ -12,9 +13,9 @@
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 / {
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 	model = "LS1043A RDB Board";
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+	compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
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 	aliases {
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-		crypto = &crypto;
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 		serial0 = &duart0;
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 		serial1 = &duart1;
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 		serial2 = &duart2;
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@@ -65,6 +66,7 @@
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 			#address-cells = <1>;
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 			#size-cells = <1>;
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 			reg = <0x0 0x0 0x8000000>;
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+			big-endian;
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 			bank-width = <2>;
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 			device-width = <1>;
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 		};
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@@ -92,6 +94,22 @@
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 		compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
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 		reg = <0>;
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 		spi-max-frequency = <1000000>; /* input clock */
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+	};
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+
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+	slic@2 {
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+		compatible = "maxim,ds26522";
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+		reg = <2>;
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+		spi-max-frequency = <2000000>;
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+		fsl,spi-cs-sck-delay = <100>;
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+		fsl,spi-sck-cs-delay = <50>;
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+	};
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+
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+	slic@3 {
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+		compatible = "maxim,ds26522";
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+		reg = <3>;
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+		spi-max-frequency = <2000000>;
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+		fsl,spi-cs-sck-delay = <100>;
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+		fsl,spi-sck-cs-delay = <50>;
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 	};
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 };
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@@ -175,3 +193,27 @@
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 		};
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 	};
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 };
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+
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+&uqe {
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+	ucc_hdlc: ucc@2000 {
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+		compatible = "fsl,ucc-hdlc";
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+		rx-clock-name = "clk8";
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+		tx-clock-name = "clk9";
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+		fsl,rx-sync-clock = "rsync_pin";
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+		fsl,tx-sync-clock = "tsync_pin";
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+		fsl,tx-timeslot-mask = <0xfffffffe>;
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+		fsl,rx-timeslot-mask = <0xfffffffe>;
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+		fsl,tdm-framer-type = "e1";
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+		fsl,tdm-id = <0>;
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+		fsl,siram-entry-id = <0>;
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+		fsl,tdm-interface;
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+	};
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+};
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+
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+&usb0 {
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+	status = "okay";
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+};
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+
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+&usb1 {
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+	status = "okay";
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+};