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2024-10-22 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 
 kernel/arch/arm64/boot/dts/exynos/exynos7.dtsi
....@@ -1,6 +1,6 @@
11 // SPDX-License-Identifier: GPL-2.0
22 /*
3
- * SAMSUNG EXYNOS7 SoC device tree source
3
+ * Samsung Exynos7 SoC device tree source
44  *
55  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
66  *		http://www.samsung.com
....@@ -28,34 +28,51 @@
2828 		tmuctrl0 = &tmuctrl_0;
2929 	};
3030 
31
+	arm-pmu {
32
+		compatible = "arm,cortex-a57-pmu";
33
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
34
+			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
35
+			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
36
+			     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
37
+		interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
38
+				     <&cpu_atlas2>, <&cpu_atlas3>;
39
+	};
40
+
41
+	fin_pll: clock {
42
+		/* XXTI */
43
+		compatible = "fixed-clock";
44
+		clock-output-names = "fin_pll";
45
+		#clock-cells = <0>;
46
+	};
47
+
3148 	cpus {
3249 		#address-cells = <1>;
3350 		#size-cells = <0>;
3451 
3552 		cpu_atlas0: cpu@0 {
3653 			device_type = "cpu";
37
-			compatible = "arm,cortex-a57", "arm,armv8";
54
+			compatible = "arm,cortex-a57";
3855 			reg = <0x0>;
3956 			enable-method = "psci";
4057 		};
4158 
4259 		cpu_atlas1: cpu@1 {
4360 			device_type = "cpu";
44
-			compatible = "arm,cortex-a57", "arm,armv8";
61
+			compatible = "arm,cortex-a57";
4562 			reg = <0x1>;
4663 			enable-method = "psci";
4764 		};
4865 
4966 		cpu_atlas2: cpu@2 {
5067 			device_type = "cpu";
51
-			compatible = "arm,cortex-a57", "arm,armv8";
68
+			compatible = "arm,cortex-a57";
5269 			reg = <0x2>;
5370 			enable-method = "psci";
5471 		};
5572 
5673 		cpu_atlas3: cpu@3 {
5774 			device_type = "cpu";
58
-			compatible = "arm,cortex-a57", "arm,armv8";
75
+			compatible = "arm,cortex-a57";
5976 			reg = <0x3>;
6077 			enable-method = "psci";
6178 		};
....@@ -68,7 +85,7 @@
6885 		cpu_on = <0xC4000003>;
6986 	};
7087 
71
-	soc: soc {
88
+	soc: soc@0 {
7289 		compatible = "simple-bus";
7390 		#address-cells = <1>;
7491 		#size-cells = <1>;
....@@ -77,12 +94,6 @@
7794 		chipid@10000000 {
7895 			compatible = "samsung,exynos4210-chipid";
7996 			reg = <0x10000000 0x100>;
80
-		};
81
-
82
-		fin_pll: xxti {
83
-			compatible = "fixed-clock";
84
-			clock-output-names = "fin_pll";
85
-			#clock-cells = <0>;
8697 		};
8798 
8899 		gic: interrupt-controller@11001000 {
....@@ -96,33 +107,26 @@
96107 				<0x11006000 0x2000>;
97108 		};
98109 
99
-		amba {
100
-			compatible = "simple-bus";
101
-			#address-cells = <1>;
102
-			#size-cells = <1>;
103
-			ranges;
110
+		pdma0: pdma@10e10000 {
111
+			compatible = "arm,pl330", "arm,primecell";
112
+			reg = <0x10E10000 0x1000>;
113
+			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
114
+			clocks = <&clock_fsys0 ACLK_PDMA0>;
115
+			clock-names = "apb_pclk";
116
+			#dma-cells = <1>;
117
+			#dma-channels = <8>;
118
+			#dma-requests = <32>;
119
+		};
104120 
105
-			pdma0: pdma@10e10000 {
106
-				compatible = "arm,pl330", "arm,primecell";
107
-				reg = <0x10E10000 0x1000>;
108
-				interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
109
-				clocks = <&clock_fsys0 ACLK_PDMA0>;
110
-				clock-names = "apb_pclk";
111
-				#dma-cells = <1>;
112
-				#dma-channels = <8>;
113
-				#dma-requests = <32>;
114
-			};
115
-
116
-			pdma1: pdma@10eb0000 {
117
-				compatible = "arm,pl330", "arm,primecell";
118
-				reg = <0x10EB0000 0x1000>;
119
-				interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
120
-				clocks = <&clock_fsys0 ACLK_PDMA1>;
121
-				clock-names = "apb_pclk";
122
-				#dma-cells = <1>;
123
-				#dma-channels = <8>;
124
-				#dma-requests = <32>;
125
-			};
121
+		pdma1: pdma@10eb0000 {
122
+			compatible = "arm,pl330", "arm,primecell";
123
+			reg = <0x10EB0000 0x1000>;
124
+			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
125
+			clocks = <&clock_fsys0 ACLK_PDMA1>;
126
+			clock-names = "apb_pclk";
127
+			#dma-cells = <1>;
128
+			#dma-channels = <8>;
129
+			#dma-requests = <32>;
126130 		};
127131 
128132 		clock_topc: clock-controller@10570000 {
....@@ -211,9 +215,14 @@
211215 			#clock-cells = <1>;
212216 			clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
213217 				 <&clock_top1 DOUT_SCLK_MMC0>,
214
-				 <&clock_top1 DOUT_SCLK_MMC1>;
218
+				 <&clock_top1 DOUT_SCLK_MMC1>,
219
+				 <&clock_top1 DOUT_SCLK_UFSUNIPRO20>,
220
+				 <&clock_top1 DOUT_SCLK_PHY_FSYS1>,
221
+				 <&clock_top1 DOUT_SCLK_PHY_FSYS1_26M>;
215222 			clock-names = "fin_pll", "dout_aclk_fsys1_200",
216
-				      "dout_sclk_mmc0", "dout_sclk_mmc1";
223
+				      "dout_sclk_mmc0", "dout_sclk_mmc1",
224
+				      "dout_sclk_ufsunipro20", "dout_sclk_phy_fsys1",
225
+				      "dout_sclk_phy_fsys1_26m";
217226 		};
218227 
219228 		serial_0: serial@13630000 {
....@@ -471,28 +480,6 @@
471480 			status = "disabled";
472481 		};
473482 
474
-		arm-pmu {
475
-			compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
476
-			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
477
-				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
478
-				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
479
-				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
480
-			interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
481
-					     <&cpu_atlas2>, <&cpu_atlas3>;
482
-		};
483
-
484
-		timer {
485
-			compatible = "arm,armv8-timer";
486
-			interrupts = <GIC_PPI 13
487
-					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
488
-				     <GIC_PPI 14
489
-					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
490
-				     <GIC_PPI 11
491
-					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
492
-				     <GIC_PPI 10
493
-					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
494
-		};
495
-
496483 		pmu_system_controller: system-controller@105c0000 {
497484 			compatible = "samsung,exynos7-pmu", "syscon";
498485 			reg = <0x105c0000 0x5000>;
....@@ -516,6 +503,17 @@
516503 			clock-names = "watchdog";
517504 			samsung,syscon-phandle = <&pmu_system_controller>;
518505 			status = "disabled";
506
+		};
507
+
508
+		gpu: gpu@14ac0000 {
509
+			compatible = "samsung,exynos5433-mali", "arm,mali-t760";
510
+			reg = <0x14ac0000 0x5000>;
511
+			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
512
+				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
513
+				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
514
+			interrupt-names = "job", "mmu", "gpu";
515
+			status = "disabled";
516
+			/* TODO: operating points for DVFS, cooling device */
519517 		};
520518 
521519 		mmc_0: mmc@15740000 {
....@@ -571,6 +569,11 @@
571569 		pwm: pwm@136c0000 {
572570 			compatible = "samsung,exynos4210-pwm";
573571 			reg = <0x136c0000 0x100>;
572
+			interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
573
+				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
574
+				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
575
+				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
576
+				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
574577 			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
575578 			#pwm-cells = <3>;
576579 			clocks = <&clock_peric0 PCLK_PWM>;
....@@ -587,13 +590,38 @@
587590 			#thermal-sensor-cells = <0>;
588591 		};
589592 
590
-		thermal-zones {
591
-			atlas_thermal: cluster0-thermal {
592
-				polling-delay-passive = <0>; /* milliseconds */
593
-				polling-delay = <0>; /* milliseconds */
594
-				thermal-sensors = <&tmuctrl_0>;
595
-				#include "exynos7-trip-points.dtsi"
596
-			};
593
+		ufs: ufs@15570000 {
594
+			compatible = "samsung,exynos7-ufs";
595
+			reg = <0x15570000 0x100>,  /* 0: HCI standard */
596
+				<0x15570100 0x100>,  /* 1: Vendor specificed */
597
+				<0x15571000 0x200>,  /* 2: UNIPRO */
598
+				<0x15572000 0x300>;  /* 3: UFS protector */
599
+			reg-names = "hci", "vs_hci", "unipro", "ufsp";
600
+			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
601
+			clocks = <&clock_fsys1 ACLK_UFS20_LINK>,
602
+				<&clock_fsys1 SCLK_UFSUNIPRO20_USER>;
603
+			clock-names = "core_clk", "sclk_unipro_main";
604
+			freq-table-hz = <0 0>, <0 0>;
605
+			pinctrl-names = "default";
606
+			pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
607
+			phys = <&ufs_phy>;
608
+			phy-names = "ufs-phy";
609
+			status = "disabled";
610
+		};
611
+
612
+		ufs_phy: ufs-phy@15571800 {
613
+			compatible = "samsung,exynos7-ufs-phy";
614
+			reg = <0x15571800 0x240>;
615
+			reg-names = "phy-pma";
616
+			samsung,pmu-syscon = <&pmu_system_controller>;
617
+			#phy-cells = <0>;
618
+			clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
619
+				 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
620
+				 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
621
+				 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
622
+			clock-names = "ref_clk", "rx1_symbol_clk",
623
+				      "rx0_symbol_clk",
624
+				      "tx0_symbol_clk";
597625 		};
598626 
599627 		usbdrd_phy: phy@15500000 {
....@@ -630,6 +658,27 @@
630658 			};
631659 		};
632660 	};
661
+
662
+	thermal-zones {
663
+		atlas_thermal: cluster0-thermal {
664
+			polling-delay-passive = <0>; /* milliseconds */
665
+			polling-delay = <0>; /* milliseconds */
666
+			thermal-sensors = <&tmuctrl_0>;
667
+			#include "exynos7-trip-points.dtsi"
668
+		};
669
+	};
670
+
671
+	timer {
672
+		compatible = "arm,armv8-timer";
673
+		interrupts = <GIC_PPI 13
674
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
675
+			     <GIC_PPI 14
676
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
677
+			     <GIC_PPI 11
678
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
679
+			     <GIC_PPI 10
680
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
681
+	};
633682 };
634683 
635684 #include "exynos7-pinctrl.dtsi"